M24256-BFDW6G/K [STMICROELECTRONICS]
32KX8 I2C/2-WIRE SERIAL EEPROM, PDSO8, ROHS COMPLIANT, TSSOP-8;
| 型号： | M24256-BFDW6G/K |
| 厂家： | 
ST |
| 描述： | 32KX8 I2C/2-WIRE SERIAL EEPROM, PDSO8, ROHS COMPLIANT, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总41页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24256-BF M24256-BR M24256-BW
M24256-DR
256 Kbit serial I²C bus EEPROM
with three Chip Enable lines
Features
2
■ Compatible with all I C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■ Memory array:
SO8 (MN)
150 mils width
– 256 Kb (32 Kbytes) of EEPROM
– Page size: 64 bytes
■ M24xxx- DR: additional Write lockable Page
(Identification page)
■ Single supply voltage:
– 1.7 V to 5.5 V
TSSOP8 (DW)
WLCSP (CS)
– 1.8 V to 5.5 V
– 2.5 V to 5.5 V
■ Noise suppression
– Schmitt trigger inputs
– Input noise filter
■ Write
– Byte write within 5 ms
– Page write within 5 ms
■ Random and sequential read modes
■ Write protect of the whole memory array
■ Enhanced ESD/latch-up protection
■ More than 1 million write cycles
■ More than 40-year data retention
■ Packages
UFDFPN8 (MB)
2 × 3 mm (MLP)
2®
– ECOPACK (RoHS compliant and
halogen-free)
July 2011
Doc ID 6757 Rev 24
1/41
www.st.com
1
Contents
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
2.6.2
2.6.3
2.6.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Lock Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 16
3.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
3.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Random Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 19
3.15 Current Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.17 Reading the Identification Page (M24256-D only) . . . . . . . . . . . . . . . . . . 20
2/41
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M24256-BF, M24256-BR, M24256-BW, M24256-DR
Contents
3.18 Reading the lock status (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
5
6
7
8
9
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 6757 Rev 24
3/41
List of tables
M24256-BF, M24256-BR, M24256-BW, M24256-DR
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device select code (for memory array). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC characteristics (voltage range W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC characteristics (voltage range W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 31
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WLCSP 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22.
Table 23.
Table 24.
4/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
I C Fast mode (f = 400 kHz): maximum R
value versus
C
bus
bus parasitic capacitance (C ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
bus
2
Figure 6.
I C Fast mode Plus (f = 1 MHz): maximum R
value versus
C
bus
bus parasitic capacitance (C ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
bus
2
Figure 7.
Figure 8.
Figure 9.
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31
Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 6757 Rev 24
5/41
Description
M24256-BF, M24256-BR, M24256-BW, M24256-DR
1
Description
2
The M24256-Bx devices are I C-compatible electrically erasable programmable memories
(EEPROM). They are organized as 32 K × 8 bits.
2
The M24256-DR is also an I C-compatible EEPROM organized as 32 K × 8 bits, but it offers
an additional page, named the Identification Page (64 bytes). The Identification Page can be
used to store sensitive application parameters which can be (later) permanently locked in
read-only mode.
Figure 1.
Logic diagram
6
##
ꢅ
%ꢀꢆ%ꢁ
3$!
-ꢁꢄXXX
3#,
7#
6
33
!)ꢀꢁꢁꢂꢃG
Table 1.
Signal names
Signal name
Function
Direction
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Inputs
I/O
SCL
Input
Input
WC
Write Control
Supply voltage
Ground
VCC
VSS
Figure 2.
Package connections
E0
1
2
3
4
8
7
6
5
V
CC
WC
E1
E2
SCL
SDA
V
SS
AI04035e
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
6/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Description
Figure 3. WLCSP connections (top view, marking side, with balls on the underside)
VCC
E1
E0
WC
E2
SDA
VSS
SCL
ai14712
Caution:
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UVlight.
Doc ID 6757 Rev 24
7/41
Signal description
M24256-BF, M24256-BR, M24256-BW, M24256-DR
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V . (Figure 6 indicates how the value of the pull-up resistor can be calculated). In
CC
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
2.3
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V . (Figure 6 indicates how
CC
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to V
CC
or V , to establish the device select code. When not connected (left floating), these inputs
SS
are read as Low (0,0,0).
Figure 4.
Device select code
V
V
CC
CC
M24xxx
M24xxx
E
E
i
i
V
V
SS
SS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as V , and
IL
Write operations are allowed.
When Write Control (WC) is driven High, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Signal description
2.5
VSS ground
V
is the reference for the V supply voltage.
CC
SS
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 7, Table 8 and
CC
CC
Table 9). In order to secure a stable DC supply voltage, it is recommended to decouple the
V
V
line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
CC
/V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t ).
W
2.6.2
2.6.3
Power-up conditions
V
has to rise continuously from 0 V up to V (min) (see Table 7, Table 8 and Table 9),
CC
CC
and the rise time must not vary faster than 1 V/µs.
Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until V
CC
reaches an internal reset threshold voltage. This threshold is lower than the minimum V
CC
operating voltage defined in Table 7, Table 8 and Table 9.
When V passes over the POR threshold, the device is reset and enters the Standby
CC
Power mode. However, the device must not be accessed until V reaches a valid and
CC
stable V voltage within the specified [V (min), V (max)] range.
CC
CC
CC
In a similar way, during power-down (continuous decrease in V ), as soon as V drops
CC
CC
below the power on reset threshold voltage, the device stops responding to any instruction
sent to it.
2.6.4
Power-down conditions
During power-down (where V decreases continuously), the device must be in the Standby
CC
Power mode (mode reached after decoding a Stop condition, assuming that there is no
internal Write cycle in progress).
Doc ID 6757 Rev 24
9/41
Signal description
Figure 5.
M24256-BF, M24256-BR, M24256-BW, M24256-DR
I C Fast mode (f = 400 kHz): maximum R value versus
2
C
bus
bus parasitic capacitance (C
)
bus
100
When t
LOW
= 1.3 µs (min value for
× C
f
= 400 kHz), the R
C
bus
bus
V
CC
time constant must be below the
400 ns time constant line
represented on the left.
10
R
bus
Here R
bus
× C = 120 ns
bus
4 kΩ
SCL
SDA
I²C bus
master
M24xxx
1
30 pF
C
bus
10
100
Bus line capacitor (pF)
1000
ai14796b
2
Figure 6.
I C Fast mode Plus (f = 1 MHz): maximum R
value versus
bus
C
bus parasitic capacitance (C
)
bus
V
100
CC
When t
= 700 ns
LOW
(max possible value for
= 1 MHz), the R × C
bus
time constant must be below
the 270 ns time constant line
represented on the left.
f
C
bus
R
bus
SCL
SDA
I²C bus
master
10
5
M24xxx
When t
= 400 ns
LOW
(min value for f = 1 MHz),
Here,
C
R
× C
= 150 ns
the R
× C time constant
bus
bus
bus bus
C
bus
must be below the 100 ns
time constant line represented
on the left.
1
10
30
Bus line capacitor (pF)
100
ai14795d
10/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Signal description
2
Figure 7.
SCL
I C bus protocol
SDA
SDA
Input
SDA
Change
Start
condition
Stop
condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
Start
condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
Stop
condition
AI00792c
Table 2.
Most significant address byte
b14 b13 b12
b15
b11
b3
b10
b2
b9
b8
b0
Table 3.
Least significant address byte
b6 b5 b4
b7
b1
Doc ID 6757 Rev 24
11/41
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3
Device operation
2
The device supports the I C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always slave in all
communications.
3.1
3.2
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal Write cycle.
3.3
3.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
th
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
12/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
3.5
Addressing the memory array
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 4 (on Serial Data (SDA), most significant bit first).
The 4-bit device type identifier 1010b selects the memory array, the 4-bit device type
identifier 1011b selects the Identification page. A device select code handling a value
different than 1010b or 1011b is not acknowledged by the device.
Table 4.
Device select code (for memory array)
Device type identifier(1)
Chip Enable address(2)
RW
b0
b7
b6
b5
b4
b3
b2
b1
Device select code
when addressing the
memory array
1
0
1
0
E2
E1
E0
RW
RW
Device select code
when accessing the
Identification page
1
0
1
1
E2
E1
E0
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
2
Up to eight memory devices can be connected on a single I C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5.
Mode
Operating modes
RW bit WC(1)
Bytes
Initial sequence
Current Address
Read
1
X
1
Start, device select, RW = 1
0
1
X
X
Start, device select, RW = 0, Address
re-Start, device select, RW = 1
Random Address
Read
1
Similar to Current or Random Address
Read
Sequential Read
1
X
≥ 1
Byte Write
0
0
VIL
VIL
1
Start, device select, RW = 0
Start, device select, RW = 0
Page Write
≤ 64
1. X = VIH or VIL.
Doc ID 6757 Rev 24
13/41
Device operation
Figure 8.
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
Byte Write
Dev sel
Byte addr
Byte addr
Data in
R/W
WC
ACK
ACK
ACK
NO ACK
Data in 2
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write
(cont'd)
Data in N
AI01120d
14/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
3.6
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte (Table 2) is sent first, followed by the least significant byte (Table 3). Bits b15 to b0 form
the address of the byte in memory.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay t , and the successful completion of a Write operation,
W
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
3.7
3.8
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
Page Write (memory array)
The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b15-b6) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 7 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
Doc ID 6757 Rev 24
15/41
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.9
Write Identification Page (M24256-D only)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. The identification page is written by issuing a Write
Identification Page instruction. This instruction uses the same protocol and format as Page
Write (into memory array), except for the following differences:
●
Device Type Identifier = 1011b
●
MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A5/A0 define the byte address inside the identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
3.10
Lock Identification Page (M24256-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
●
●
●
Device Type Identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care.
If the Identification Page is locked, the data bytes transferred during the ID Write instruction
are not acknowledged (NoAck).
3.11
ECC (error correction code) and write cycling
The M24256-Bx and M24256-D devices offer an ECC (error correction code) logic which
compares each 4-byte word with its six associated ECC EEPROM bits. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write data by word (4 bytes) at address
4*N (where N is an integer) in order to benefit from the larger amount of Write cycles.
The M24256-Bx and M24256-DR devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device by multiples of 4-bytes.
16/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
Figure 9.
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
ACK
ACK
Byte Write
Dev sel
Byte addr
Byte addr
Data in
R/W
WC
ACK
ACK
ACK
ACK
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
ACK
Page Write
(cont'd)
Data in N
AI01106d
Doc ID 6757 Rev 24
17/41
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
ACK
NO
Returned
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
operation is
addressing the
memory
NO
YES
Send Address
and Receive ACK
ReStart
Start
NO
YES
Stop
condition
Data for the
Write operation
Device select
with RW = 1
Continue the
Continue the
Random Read operation
Write operation
AI01847d
3.12
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in tables17 and 18, but the typical time is shorter. To make use of this, a polling
sequence can be used by the bus master.
The sequence, as shown in Figure 10, is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
18/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
3.13
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Figure 11. Read mode sequences
ACK
NO ACK
Current
Address
Read
Dev sel
Data out
R/W
ACK
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out
R/W
R/W
ACK
ACK
ACK
NO ACK
Data out N
Sequential
Current
Read
Dev sel
Data out 1
R/W
ACK
R/W
ACK
ACK
ACK
R/W
ACK
Sequential
Random
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out 1
ACK
NO ACK
Data out N
AI01105d
3.14
Random Address Read (in memory array)
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
Doc ID 6757 Rev 24
19/41
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.15
Current Address Read (in memory array)
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the byte.
3.16
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.17
Reading the Identification Page (M24256-D only)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing a Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A17/A6 are don't
care, the LSB address bits A5/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data will be read (e.g.: when reading the Identification Page from location 10d,
the number of bytes should be less than or equal to 54, as the ID page boundary is
64 bytes).
20/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
3.18
Reading the lock status (M24256-D only)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device will return an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
●
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
●
Stop: the device is then set back into Standby mode by the Stop condition.
3.19
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
th
during the 9 bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Standby mode.
Doc ID 6757 Rev 24
21/41
Initial delivery state
M24256-BF, M24256-BR, M24256-BW, M24256-DR
4
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
Ambient Temperature with power applied
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VIO
Lead temperature during soldering
Input or output range
See note (1)
–0.50
–0.50
6.5
6.5
5
VCC
Supply voltage
V
IOL
DC output current (SDA = 0)
Electrostatic pulse voltage (Human Body Model) (2)
mA
V
VESD
3000
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on the restriction of the use of certain hazardous
substances in electrical and electronic equipment (RoHS) 2002/95/EC.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)
22/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
DC and AC parameters
6
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 7.
Symbol
Operating conditions (voltage range W)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
2.5
–40
–40
5.5
85
V
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)
°C
°C
125
Table 8.
Symbol
Operating conditions (voltage range R)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.8
5.5
85
V
Ambient operating temperature
–40
°C
Table 9.
Symbol
Operating conditions (voltage range F)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.7
5.5
85
V
Ambient operating temperature
–40
°C
Table 10. AC test measurement conditions
Symbol
Parameter
Load capacitance
Min.
Max.
Unit
Cbus
100
pF
SCL input rise/fall time
SDA input fall time
50
ns
Input levels
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
V
V
Input and output timing reference levels
Figure 12. AC test measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
0.2V
CC
CC
0.7V
CC
0.3V
CC
AI00825B
Doc ID 6757 Rev 24
23/41
DC and AC parameters
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 11. Input parameters
Symbol
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
CIN
Input capacitance (SDA)
8
6
pF
pF
Input capacitance (other pins)
Input impedance
(E2, E1, E0, WC)
(2)
ZL
VIN < 0.3VCC
30
kΩ
kΩ
Input impedance
(E2, E1, E0, WC)
(2)
ZH
VIN > 0.7VCC
500
1. Sampled only, not 100% tested.
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 12. Memory cell characteristics
Symbol
Parameter
Test condition
Min.
Max.
Unit
Write cycle
Ncycle
Endurance
TA = 25°C, 1.8V < Vcc < 5.5V
1,000,000
-
Note:
This parameter is not tested but established by characterization and qualification. To
estimate endurance in a specific application, please refer to AN2014.
Table 13. DC characteristics (voltage range W, device grade 3)
Test conditions (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 7 and Table 10)
VIN = VSS or VCC
Input leakage current
(SCL, SDA, E0, E1, E2)
ILI
2
2
µA
µA
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
ICC
Supply current (Read)
Supply current (Write)
fc = 400 kHz
During tW
2
mA
mA
ICC0
5(1)
Device not selected(2), VIN = VSS
or VCC
ICC1
VIL
Standby supply current
5
µA
V
Input low voltage
(SCL, SDA, WC)
–0.45
0.3 VCC
6.5
Input high voltage
(SCL, SDA)
0.7VCC
V
VIH
Input high voltage
(WC, E0, E1, E2)
0.7VCC VCC+0.6
V
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
VOL
Output low voltage
0.4
V
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
24/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
DC and AC parameters
Table 14. DC characteristics (voltage range W, device grade 6)
Test conditions (see Table 7 and
Symbol
Parameter
Min.
Max.
Unit
Table 10)
Input leakage
current
(SCL, SDA, E0, E1,
E2)
VIN = VSS or VCC
ILI
2
µA
device in Standby mode
Output leakage
current
SDA in Hi-Z, external voltage applied on
SDA: VSS or VCC
ILO
2
1
µA
mA
mA
mA
mA
VCC = 2.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
Supply current
(Read)
VCC = 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
ICC
2
2.5 V < VCC < 5.5 V, fc = 1 MHz(1)
(rise/fall time < 50 ns)
2.5
2(2)
Supply current
(Write)
ICC0
During tW, 2.5 V < VCC < 5.5 V
Device not selected(3), VIN = VSS or VCC
VCC = 2.5 V
,
2
3
µA
µA
V
Standby supply
current
ICC1
Device not selected(3), VIN = VSS or VCC
VCC = 5.5 V
,
Input low voltage
(SCL, SDA, WC)
VIL
VIH
VOL
–0.45 0.3VCC
0.7VCC 6.5
Input high voltage
(SCL, SDA)
V
V
Input high voltage
(WC, E0, E1, E2)
0.7VCC VCC+0.6
0.4
I
OL = 2.1 mA, VCC = 2.5 V or
Output low voltage
IOL = 3 mA, VCC = 5.5 V
1. Only for devices operating at fC max = 1 MHz (see Table 18).
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 6757 Rev 24
25/41
DC and AC parameters
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 15. DC characteristics (voltage range R)
Test conditions(1) (in addition
to those in Table 8 and
Table 10)
Symbol
Parameter
Min.
Max.
Unit
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
2
2
µA
µA
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
VCC = 1.8 V, fc= 400 kHz
0.8
mA
ICC
Supply current (Read)
fc= 1 MHz
2.5
2(2)
1
mA
mA
µA
ICC0
ICC1
Supply current (Write)
Standby supply current
During tW, 1.8 V < VCC < 2.5 V
Device not selected(3)
VIN = VSS or VCC, VCC = 1.8 V
,
Input low voltage
(SCL, SDA, WC)
VIL
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
6.5
V
V
Input high voltage
(SCL, SDA)
1.8 V ≤ VCC < 2.5 V
0.75VCC
VIH
Input high voltage
(WC, E0, E1, E2)
1.8 V ≤ VCC < 2.5 V
0.75VCC VCC+0.6
0.2
V
V
VOL
Output low voltage
IOL = 1 mA, VCC = 1.8 V
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 14 instead of this table.
2. Characterized value, not tested in production
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
26/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 16. DC characteristics (voltage range F)
DC and AC parameters
Test conditions (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in tables 9 and 10)(1)
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
2
2
µA
µA
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
VCC = 1.7 V, fc= 400 kHz
0.8
mA
ICC
Supply current (Read)
fc= 1 MHz
2.5
2(2)
1
mA
mA
µA
ICC0 Supply current (Write)
ICC1 Standby supply current
During tW, 1.7 V < VCC < 2.5 V
Device not selected(3)
VIN = VSS or VCC, VCC = 1.7 V
,
Input low voltage
VIL
1.7 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
6.5
V
V
(SCL, SDA, WC)
Input high voltage
1.7 V ≤ VCC < 2.5 V
0.75VCC
(SCL, SDA)
Input high voltage
VIH
1.7 V ≤ VCC < 2.5 V
0.75VCC VCC+0.6
0.2
V
V
(WC, E0, E1, E2)
VOL Output low voltage
IOL = 1 mA, VCC = 1.7 V
1. If the application uses the voltage range F device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 14 instead of this table.
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 6757 Rev 24
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DC and AC parameters
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 17. 400 kHz AC characteristics
Test conditions specified in tables 7, 8, 9 and 10
Min.(1)
Symbol
fC
tCHCL
tCLCH
Alt.
fSCL
Parameter
Max.(1)
400
Unit
kHz
Clock frequency
tHIGH
tLOW
tF
Clock pulse width high
Clock pulse width low
SDA (out) fall time
Input signal rise time
Input signal fall time
Data in set up time
Data in hold time
600
ns
ns
ns
ns
ns
ns
ns
ns
1300
(2)
20(3)
tQL1QL2
120
(4)
(4)
tXH1XH2
tXL1XL2
tDXCX
tR
(4)
(4)
tF
tSU:DAT
tHD:DAT
tDH
100
0
tCLDX
(5)
tCLQX
Data out hold time
100
(6)
tAA
tCLQV
Clock low to next data valid (access time)
Start condition setup time
900
ns
ns
ns
ns
tCHDL
tDLCL
tCHDH
tSU:STA
tHD:STA
tSU:STO
600
600
600
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
tDHDL
tW
tBUF
tWR
1300
ns
ms
ns
Write time
5
Pulse width ignored (input filter on SCL and
SDA)
(7)
tNS
80
1. All values are referred to VIL(max) and VIH(min).
2. Characterized only, not tested in production.
3. With Cbus = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C-bus specification that the input signal rise and fall times be more than 20 ns and less than 300 ns
when fC < 400 kHz.
5. The I²C-bus specification does not define a min value of the data hold time (tHD;DAT). The min value of
tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region of the
falling edge SCL.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.
7. Characterized only, not tested in production.
28/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
DC and AC parameters
(1)
Table 18. 1 MHz AC characteristics
Test conditions specified in tables 7, 8, 9 and 10
Min.(2)
0
Max.(2)
Symbol
Alt.
fSCL
Parameter
Clock frequency
Unit
fC
1
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tHIGH
tLOW
tR
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time(5)
300
tCLCH
400
-
(3)
(3)
tXH1XH2
(3)
(3)
tXL1XL2
tF
(4)
tQL1QL2
tDXCX
tCLDX
tF
20
80
0
120
tSU:DAT Data in setup time
tHD:DAT Data in hold time
-
-
(6)
tCLQX
tDH
tAA
Data out hold time
50
-
(7)
tCLQV
Clock low to next data valid (access time)
500
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
250
250
250
-
-
-
Time between Stop condition and next
Start condition
tDHDL
tW
tBUF
tWR
500
-
ns
ms
ns
Write time
-
-
5
Pulse width ignored (input filter on SCL and
SDA)
(4)
tNS
50
1. Only new devices identified by the process letter K are qualified at 1 MHz (refer to TN0440 for more).
2. All values are referred to VIL(max) and VIH(min).
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C-bus specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
4. Characterized only, not tested in production.
5. With CL = 10 pF.
6. The I²C-bus specification does not define a min value of the data hold time (tHD;DAT). The min value of
tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region of the
falling edge SCL.
7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 6.
Doc ID 6757 Rev 24
29/41
DC and AC parameters
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 13. AC waveforms
T8,ꢈ8,ꢁ
T8(ꢈ8(ꢁ
T#(#,
T#,#(
3#,
T$,#,
T8,ꢈ8,ꢁ
3$! )N
T#($,
3TART
CONDITION
T#,$8
T$8#(
3$!
#HANGE
T8(ꢈ8(ꢁ
T#($( T$($,
3TOP
3TART
3$!
)NPUT
CONDITION
CONDITION
3#,
3$! )N
T7
7RITE CYCLE
T#($(
T#($,
3TOP
CONDITION
3TART
CONDITION
T#(#,
3#,
T#,16
T#,18
$ATA VALID
T1,ꢈ1,ꢁ
$ATA VALID
3$! /UT
!)ꢀꢀꢂꢇꢃF
30/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 14. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package
mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.75
0.25
0.0689
0.0098
0.1
0.0039
0.0492
0.011
1.25
0.28
0.17
0.48
0.23
0.1
5
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
0.0067
ccc
D
4.9
6
4.8
5.8
3.8
-
0.1929
0.2362
0.1535
0.05
0.1890
0.2283
0.1496
-
E
6.2
4
E1
e
3.9
1.27
-
h
0.25
0°
0.5
8°
0.0098
0°
0.0197
8°
k
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 6757 Rev 24
31/41
Package mechanical data
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 15. TSSOP8 – 8-lead thin shrink small outline, package outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8
8°
0°
8
8°
N
1. Values in inches are converted from mm and rounded to four decimal digits.
32/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Package mechanical data
Figure 16. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline
e
b
D
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be
allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering
process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 21. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
b
0.55
0.02
0.25
2
0.45
0
0.6
0.05
0.3
2.1
1.7
3.1
0.3
-
0.0217
0.0008
0.0098
0.0787
0.063
0.0177
0
0.0236
0.002
0.0118
0.0827
0.0669
0.122
0.0118
-
0.2
1.9
1.5
2.9
0.1
-
0.0079
0.0748
0.0591
0.1142
0.0039
-
D
D2
E
1.6
3
0.1181
0.0079
0.0197
0.0177
E2
e
0.2
0.5
0.45
L
0.4
0.5
0.15
0.0157
0.0197
0.0059
L1
L3
ddd(2)
0.3
0.0118
0.08
0.08
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
Doc ID 6757 Rev 24
33/41
Package mechanical data
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 17. WLCSP, 0.5 mm pitch, package outline
Orientation reference
D
2
3
1
A
B
e2
G
e
C
D
E
B
E
e3
e1
F
A2
A1
A
1. Drawing is not to scale.
(1)
Table 22. WLCSP 0.5 mm pitch, package mechanical data
Millimeters
Symbol
Inches(2)
Min
Typ
Min
Max
0.65
Typ
0.0236
Max
0.0256
A
0.60
0.55
0.0217
A1
A2
B
0.245
0.355
0.22
0.27
0.0096
0.0140
0.0087
0.0130
0.0106
0.0150
0.330
0.380
Ø 0.311
Ø 0.0122
D
1.97
1.95
1.99
0.0776
0.0703
0.0197
0.0341
0.0098
0.0170
0.0217
0.0154
0.0768
0.0695
0.0783
0.0711
E
1.785
0.5
1.765
1.805
e
e1
e2
e3
F
0.866
0.25
0.433
0.552
0.392
0.502
0.342
0.602
0.442
0.0198
0.0135
0.0237
0.0174
G
N(3)
8
8
1. Preliminary data.
2. Values in inches are converted from mm and rounded to four decimal digits.
3. N is the total number of terminals.
34/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Part numbering
8
Part numbering
Table 23. Ordering information scheme
Example:
M24256–B
W
MW
6
T
P
/AB
Device type
M24 = I2C serial access EEPROM
Device function
256– = 256 Kbit (32 Kb × 8)
Device family
B: Without Identification page
D: With additional Identification page
Operating voltage
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
F = VCC = 1.7 to 5.5 V
Package
MN = SO8 (150 mils body width)
DW = TSSOP8
MB = UFDFPN8 (MLP8)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow
3 = Automotive: device tested with high reliability certified flow(1)
over –40 to 125 °C
Option
blank = standard packing
T = tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process
/A = F8L process (for WLCSP package ordering only)
/AB = F8L process (for device grade 3 ordering only)
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High
Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a
copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 6757 Rev 24
35/41
Revision history
M24256-BF, M24256-BR, M24256-BW, M24256-DR
9
Revision history
Table 24. Document revision history
Date
Revision
Changes
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
29-Jan-2001
1.1
References to PSDIP8 changed to PDIP8, and Package Mechanical data
updated
LGA8 Package Mechanical data and illustration updated
SO16 package removed
10-Apr-2001
1.2
16-Jul-2001
02-Oct-2001
1.3
1.4
LGA8 Package given the designator “LA”
LGA8 Package mechanical data updated
Document becomes Preliminary Data
13-Dec-2001
1.5
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
12-Jun-2001
22-Oct-2003
1.6
2.0
Document promoted to Full Datasheet
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to –0.45V.
LGA8 package is Not for New Design. 5V and -S supply ranges, and
Device Grade 5 removed. Absolute Maximum Ratings for VIO(min) and
VCC(min) changed. Soldering temperature information clarified for RoHS
compliant devices. Device grade information clarified. AEC-Q100-002
compliance. VIL specification unified for SDA, SCL and WC
02-Sep-2004
3.0
Initial delivery state is FFh (not necessarily the same as Erased).
LGA package removed, TSSOP8 and SO8N packages added (see
Package mechanical data section and Table 23: Ordering information
scheme).
Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.
ZL Test Conditions modified in Table 11: Input parameters and Note 2
added.
22-Feb-2005
4.0
ICC and ICC1 values for VCC = 5.5V added to Table 13: DC characteristics
(voltage range W).
Note added to Table 13: DC characteristics (voltage range W).
Power On Reset paragraph specified.
tW max value modified in Table 16: 400 kHz AC characteristics and note 4
added. Plating technology changed in Table 23: Ordering information
scheme.
Resistance and capacitance renamed in Figure 6.
36/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 24. Document revision history (continued)
Revision history
Date
Revision
Changes
Power On Reset paragraph replaced by Section 2.6: Supply voltage
(VCC). Figure 4: Device select code added.
ECC (error correction code) and write cycling added and specified at 1
Million cycles.
05-May-2006
5
ICC0 added and ICC1 specified over the whole voltage range in Table 13
and Table 14.
PDIP8 package removed. Packages are ECOPACK® compliant. Small
text changes.
M24256-BW and M24256-BR part numbers added.
Section 3.11: ECC (error correction code) and write cycling updated.
ICC and ICC1 modified in Table 14: DC characteristics (voltage range R).
tW modified in Table 16: 400 kHz AC characteristics.
16-Oct-2006
6
SO8Narrow package specifications updated (see Table 19 and
Figure 14). Blank option removed from below Plating technology in
Table 23: Ordering information scheme.
Section 2.6: Supply voltage (VCC) modified.
Section 3.11: ECC (error correction code) and write cycling modified.
JEDEC standard and European directive references corrected below
Table 6: Absolute maximum ratings.
Rise/fall time conditions modified for ICC and VIH max modified in
Table 13: DC characteristics (voltage range W) and Table 14: DC
characteristics (voltage range R)
02-Jul-2007
7
Note 1 removed from Table 13: DC characteristics (voltage range W).
SO8W package specifications modified in Section 7: Package mechanical
data.
Table 25: Available M24256-BR, M24256-BW, M24256-BF products
(package, voltage range, temperature grade) and Table 26: Available
M24512-x products (package, voltage range, temperature grade) added.
Section 2.5: VSS ground added. Small text changes.
VIO max changed and Note 1 updated to latest standard revision in
Table 6: Absolute maximum ratings.
Note removed from Table 11: Input parameters.
VIH min and VIL max modified in Table 14: DC characteristics (voltage
range R).
16-Oct-2007
8
Removed tCH1CH2, tCL1CL2 and tDH1DH2, and added tXL1XL2, tDL1DL2 and
Note 3 in Table 16: 400 kHz AC characteristics.
tXH1XH2, tXL1XL2 and Note 2 added to Table 17: 1 MHz AC characteristics.
Figure 13: AC waveforms modified.
Package mechanical data inch values calculated from mm and rounded to
4 decimal digits (see Section 7: Package mechanical data).
Doc ID 6757 Rev 24
37/41
Revision history
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 24. Document revision history (continued)
Date
Revision
Changes
1 MHz frequency introduced (M24512-HR root part number).
Section 2.6.3: Device reset modified.
Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus
parasitic capacitance (Cbus) modified, Figure 6: I2C Fast mode Plus (fC
=
1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus
added.
)
14-Dec-2007
9
tNS moved from Table 11 to Table 16. ILO test conditions modified in
Table 13.
Table 14: DC characteristics (voltage range R) and Table 17: 1 MHz AC
characteristics modified. Small text changes.
Small text changes. M24256-BHR root part number added.
Section 2.6.3: Device reset on page 9 updated.
Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) on page 10 updated.
27-Mar-2008
10
Caution removed in Section 3.11: ECC (error correction code) and write
cycling.
M24512-W and M24256-BW offered in the device grade 3 option
(automotive temperature range):
– Table 7: Operating conditions (voltage range W),
– Table 13: DC characteristics (voltage range W),
– /AB Process letters added to Table 23: Ordering information scheme,
22-Apr-2008
11
– Table 25: Available M24256-BR, M24256-BW, M24256-BF products
(package, voltage range, temperature grade) and
– Table 26: Available M24512-x products (package, voltage range,
temperature grade) updated accordingly).
Small text changes.
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 7: Package
mechanical data).
22-Dec-2008
21-Jan-2009
12
13
M24256-BF part number added (VCC = 1.7 V to 5.5 V voltage range
added, see Table 9, Table 15, Table 16 and Table 25).
ICC1 test conditions modified in Table 13: DC characteristics (voltage
range W), Table 14: DC characteristics (voltage range R) and Table 15:
DC characteristics (voltage range F).
M24512-DR part number and Identification page feature added.
Command replaced by instruction in the whole document.
UFDFPN8 added.
Figure 6 updated.
Section 2.6.2: Power-up conditions and Section 2.6.3: Device reset
updated.
05-Jun-2009
14
tCLQX and tCLQV updated in Table 16, Note 5 and Note 8 added.
tCLQX and tCLQV updated in Table 17, Note 6 and Note 9 added.
Section 8: Part numbering updated.
Reference to the SURE program removed in Section 5: Maximum rating.
Previous 1 MHz M24512-HR and M24512-BHR devices replaced by new
M24512-R and M24256-BR (process letter K).
38/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 24. Document revision history (continued)
Revision history
Date
Revision
Changes
16-Jun-2009
15
Part numbers updated in cover page header.
IOL added to Table 7: Operating conditions (voltage range W).
20-Aug-2009
16
Note 1and ICC modified in Table 13: DC characteristics (voltage range W);
Note and ICC modified in Table 14: DC characteristics (voltage range R);
Datasheet split to leave only devices with 256 Kbit capacity.
M24256-DR part number added (see Table 26: Available M24256-DR
products (package, voltage range, temperature grade).
Figure 4: Device select code and Figure 5: I2C Fast mode (fC = 400 kHz):
maximum Rbus value versus bus parasitic capacitance (Cbus) updated.
VIO max modified in Table 6: Absolute maximum ratings.
VIH modified in Table 13: DC characteristics (voltage range W), Table 14:
DC characteristics (voltage range R) and Table 15: DC characteristics
(voltage range F).
13-Oct-2009
17
In Table 16: 400 kHz AC characteristics and Table 17: 1 MHz AC
characteristics:
– tDL1DL2 changed to tQL1QL2
– tCHDX changed to tCHDL
– tXH1XH2 and tXL1XL2 values removed
– Notes modified
Figure 13: AC waveforms modified.
Section 3.9: Write Identification Page (M24256-D only)
corrected.Section 3.17: Reading the Identification Page (M24256-D only)
clarified.
05-Nov-2009
10-Dec-2009
18
19
UFDFPN8 package is now offered (see Section 7: Package mechanical
data, Table 23: Ordering information scheme and Table 25: Available
M24256-BR, M24256-BW, M24256-BF products (package, voltage
range, temperature grade).
19-Jan-2010
04-Mar-2010
20
21
Revision number corrected at bottom of pages.
Process description corrected in Table 23: Ordering information scheme.
Updated text in:
Features, Section 1: Description, Section 3.1: Start condition, Section 3.6:
Write operations, Section 3.9: Write Identification Page (M24256-D only),
Section 3.10: Lock Identification Page (M24256-D only), Section 3.11:
ECC (error correction code) and write cycling, Section 3.17: Reading the
Identification Page (M24256-D only), Section 3.18: Reading the lock
status (M24256-D only), Table 10: AC test measurement conditions,
Section 8: Part numbering.
21-Dec-2010
22
Updated the following according to the I²C_bus specification:
Table 17: 400 kHz AC characteristics, Table 18: 1 MHz AC characteristics,
Figure 13: AC waveforms.
Doc ID 6757 Rev 24
39/41
Revision history
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Table 24. Document revision history (continued)
Date
Revision
Changes
Added caution under Figure 3: WLCSP connections (top view, marking
side, with balls on the underside).
Updated:
– Description
– Section 3.5: Addressing the memory array
– Section 3.17: Reading the Identification Page (M24256-D only)
– Section 3.18: Reading the lock status (M24256-D only)
– Table 2: Most significant address byte
– Table 6: Absolute maximum ratings
– Table 17: 400 kHz AC characteristics
– Table 18: 1 MHz AC characteristics
Moved:
14-Feb-2011
23
– Table 2: Most significant address byte from Section 2.6.4 to Section 3.5
Deleted:
– Table 3: Device select code to access the Identification page (M24256-
DR only)
– Table 25: Available M24256-BR, M24256-BW, M24256-BF products
(package, voltage range, temperature grade)
– Table 26: Available M24256-DR products (package, voltage range,
temperature grade)
Added Table 12: Memory cell characteristics.
Updated:
– Section 1: Description
– Table 6: Absolute maximum ratings
05-Jul-2011
24
– ICC0 maximum value in Table 14: DC characteristics (voltage range W,
device grade 6), Table 15: DC characteristics (voltage range R) and
Table 16: DC characteristics (voltage range F)
Deleted all references to package SO8 (MW) 208 mils width.
40/41
Doc ID 6757 Rev 24
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
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Doc ID 6757 Rev 24
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