M24256-B [STMICROELECTRONICS]
256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines; 一百二十八分之二百五十六千位串行I2C总线的EEPROM采用三片选线
| 型号： | M24256-B |
| 厂家： | 
ST |
| 描述： | 256/128 Kbit Serial I C Bus EEPROM With Three Chip Enable Lines |
| 文件： | 总19页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24256-B
M24128-B
C Bus EEPROM
256/128 Kbit Serial
I
With Three Chip Enable Lines
PRELIMINARY DATA
2
■ Compatible with I C Extended Addressing
2
■ Two Wire I C Serial Interface
Supports 400 kHz Protocol
■ Single Supply Voltage:
14
– 4.5V to 5.5V for M24xxx-B
8
– 2.5V to 5.5V for M24xxx-BW
– 1.8V to 3.6V for M24xxx-BR
1
1
■ Hardware Write Control
TSSOP14 (DL)
169 mil width
PSDIP8 (BN)
0.25 mm frame
■ BYTE and PAGE WRITE (up to 64 Bytes)
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing
■ Enhanced ESD/Latch-Up Behavior
■ 100000 Erase/Write Cycles (minimum)
■ 40 Year Data Retention (minimum)
8
8
1
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
DESCRIPTION
2
These I C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256-B) and 16Kx8 bits
(M24128-B).
Figure 1. Logic Diagram
These memory devices are compatible with the
2
I C extended memory standard. This is a two wire
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
V
CC
2
accordance with the I C bus definition.
3
E0-E2
SCL
WC
SDA
Table 1. Signal Names
M24256-B
M24128-B
E0, E1, E2
SDA
Chip Enable Inputs
Serial Data/Address Input/
Output
SCL
WC
Serial Clock
Write Control
Supply Voltage
Ground
V
SS
AI02809
V
V
CC
SS
February 2000
1/19
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M24256-B, M24128-B
Figure 2C. TSSOP14 Connections
Figure 2A. PSDIP8 Connections
M24256-B
M24128-B
M24256-B
M24128-B
E0
E1
1
2
3
4
5
6
7
14
13
V
CC
WC
E0
E1
E2
1
2
3
4
8
V
CC
WC
NC
NC
NC
E2
12
NC
7
6
11
NC
SCL
SDA
10
NC
V
5
SS
9
SCL
SDA
AI02810
V
8
SS
AI02812
Note: 1. NC = Not Connected
2
Figure 2B. SO8 and TSSOP8 Connections
The memory behaves as a slave device in the I C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
M24256-B
M24128-B
E0
E1
E2
1
2
3
4
8
V
CC
WC
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9 bit time,
th
7
6
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
SCL
SDA
V
5
SS
AI02811
Power On Reset: V Lock-Out Write Protect
CC
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
TA
Ambient Operating Temperature
-40 to 125
-65 to 150
TSTG
Storage Temperature
°C
PSDIP8: 10 seconds
SO8: 40 seconds
TSSOP8: 40 seconds
TSSOP14: 40 seconds
260
215
215
215
TLEAD
Lead Temperature during Soldering
°C
VIO
VCC
VESD
Input or Output range
Supply Voltage
-0.6 to 6.5
-0.3 to 6.5
V
V
2
4000
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
2/19
M24256-B, M24128-B
set (POR) circuit is included. The internal reset is
held active until the V voltage has reached the
establish the device select code. When uncon-
nected, the E2, E1 and E0 inputs are internally
CC
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
read as V (see Table 7 and Table 8)
IL
Write Control (WC)
mand. In the same way, when V drops from the
CC
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid V
CC
used to enable (WC=V ) or disable (WC=V )
IL
IH
must be applied before applying any logic signal.
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
SIGNAL DESCRIPTION
Serial Clock (SCL)
V , and write operations are allowed.
IL
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
the SCL line to V . (Figure 3 indicates how the
CC
DEVICE OPERATION
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
2
The memory device supports the I C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to V . (Figure 3 indicates how the value of the
CC
pull-up resistor can be calculated).
Start Condition
Chip Enable (E2, E1, E0)
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
These chip enable inputs are used to set the value
that isto be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code.
These inputs must be tied directly to V or V to
CC
SS
2
Figure 3. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
SCL
C
BUS
8
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
3/19
M24256-B, M24128-B
2
Figure 4. I C Bus Protocol
SCL
SDA
START
SDA
SDA
STOP
CONDITION
INPUT CHANGE
CONDITION
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
CONDITION
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
CONDITION
AI00792
Data Input
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, theSDA signal
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between thememory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit DeviceSelect Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into:a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (E2, E1, E0).
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
th
sending eight bits of data. During the 9 clock
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
4/19
M24256-B, M24128-B
1
Table 3. Device Select Code
Device Type Identifier
Chip Enable
RW
b0
b7
b6
0
b5
1
b4
0
b3
E2
b2
E1
b1
E0
Device Select Code
1
RW
Note: 1. The most significant bit, b7, is sent first.
Up to eight memory devices can be connected on
a single I C bus. Each one is given a unique 3-bit
Table 4. Most Significant Byte
2
b15
b14
b13
b12
b11
b10 b9
b8
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the mem-
ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
Note: 1. b15 is treated as Don’t Care on the M24256-B series.
b15 and b14 are Don’t Care on the M24128-B series.
Table 5. Least Significant Byte
th
The 8 bit is the RW bit. This is set to ‘1’ for read
b7
b6
b5
b4
b3
b2
b1
b0
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
th
ing the 9 bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4) is sent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256-B memory. Bits b15 and
b14 are treated as Don’t Care bits on the M24128-
B memory.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown inTable 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
Table 6. Operating Modes
1
Mode
RW bit
Data Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = ‘1’
X
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 64
START, Device Select, RW = ‘0’
Note: 1. X = VIH or VIL.
5/19
M24256-B, M24128-B
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
DATA IN
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC
ACK
ACK
ACK
NO ACK
DATA IN 1 DATA IN 2
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
R/W
WC (cont’d)
NO ACK
NO ACK
PAGE WRITE
(cont’d)
DATA IN N
AI01120B
that is the most significant memory address bits
(b14-b6 for the M24256-B and b13-b6 for the
M24128-B) are the same. If more bytes are sent
than will fit up to the end of the row, a condition
known as ‘roll-over’ occurs. Data starts to become
overwritten (in a way not formally specified in this
data sheet).
A STOP condition at any other time does not trig-
ger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
th
mediately after the Ack bit (in the “10 bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
6/19
M24256-B, M24128-B
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
BYTE ADDR
DATA IN 1
DATA IN 2
R/W
WC (cont’d)
ACK
ACK
PAGE WRITE
(cont’d)
DATA IN N
AI01106B
Minimizing System Delays by Polling On ACK
Read Operations
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
Read operations are performed independently of
the state of the WC pin.
Random Address Read
mum write time (t ) is shown in Table 9, but the
w
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the mas-
ter sends another START condition, and repeats
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is:
– Initial condition: a Write is in progress.
– Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction).
– Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
minated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
7/19
M24256-B, M24128-B
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by M24xxx
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send
Byte Address
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
AI01847
internal address counter. The counter is then in-
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8, with-
out acknowledging the byte output.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
th
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
8/19
M24256-B, M24128-B
Figure 8. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
DATA OUT N
R/W
ACK
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01105C
st
th
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 4 bytes) must be identical.
9/19
M24256-B, M24128-B
Table 7. DC Characteristics
(T = –40 to 85 °C; V = 4.5 to 5.5 V or 2.5 to 5.5 V)
A
CC
(T = –20 to 85 °C; V = 1.8 to 3.6 V)
A
CC
Symbol
Parameter
Test Condition
0 V ≤ VIN ≤ VCC
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
± 2
µA
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
± 2
2
µA
mA
mA
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
c
-W series:
1
ICC
Supply Current
1
VCC =1.8V, f =100kHz (rise/fall time < 30ns)
-R series:
mA
µA
µA
c
0.5
V
IN = VSS or VCC , VCC = 5 V
10
2
Supply Current
(Stand-by)
-W series:
-R series:
VIN = VSS or VCC , VCC = 2.5 V
ICC1
1
VIN = VSS or VCC , VCC = 1.8 V
µA
1
VIL
VIH
0.3VCC
VCC+1
Input Low Voltage (SCL, SDA)
Input High Voltage (SCL, SDA)
–0.3
V
V
0.7VCC
Input Low Voltage
(E0-E2, WC)
VIL
VIH
–0.3
0.5
V
V
Input High Voltage
(E0-E2, WC)
0.7VCC
VCC+1
I
OL = 3 mA, VCC = 5 V
0.4
0.4
V
V
Output Low
-W series:
I
I
OL = 2.1 mA, VCC = 2.5 V
OL = 0.7 mA, VCC = 1.8 V
VOL
Voltage
1
-R series:
V
0.2
Note: 1. This is preliminary data.
1
Table 8. Input Parameters (T = 25 °C, f = 400 kHz)
A
Symbol
CIN
Parameter
Test Condition
Min.
Max.
Unit
Input Capacitance (SDA)
8
6
pF
pF
kΩ
kΩ
CIN
Input Capacitance (other pins)
Input Impedance (E0-E2, WC)
Input Impedance (E0-E2, WC)
Z
Z
VIN ≤ 0.5 V
50
L
V
IN ≥ 0.7VCC
500
H
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
Single glitch
100
ns
Note: 1. Sampled only, not 100% tested.
10/19
M24256-B, M24128-B
Table 9. AC Characteristics
M24256-B / M24128-B
V =1.8 to 3.6 V
CC
V
=4.5 to 5.5 V
V
=2.5 to 5.5 V
CC
CC
Symbol
Alt.
Parameter
Unit
4
T =–40 to 85°C T =–40 to 85°C
A
A
T =–20 to 85°C
A
Min
Max
300
300
300
300
Min
Max
300
300
300
300
Min
Max
300
300
300
300
tR
tF
tR
tF
Clock Rise Time
ns
ns
ns
ns
tCH1CH2
tCL1CL2
Clock Fall Time
SDA Rise Time
SDA Fall Time
2
20
20
20
20
20
20
tDH1DH2
2
tDL1DL2
1
tSU:STA Clock High to Input Transition
tHIGH Clock Pulse Width High
600
600
600
0
600
600
600
0
600
600
600
0
ns
ns
ns
µs
µs
tCHDX
tCHCL
tDLCL
tCLDX
tCLCH
tHD:STA Input Low to Clock Low (START)
tHD:DAT Clock Low to Input Transition
tLOW
tSU:DAT
tSU:STO
tBUF
Clock Pulse Width Low
1.3
1.3
1.3
Input Transition to Clock
Transition
tDXCX
tCHDH
tDHDL
100
600
1.3
100
600
1.3
100
600
1.3
ns
ns
µs
ns
ns
Clock High to Input High (STOP)
Input High to Input Low (Bus
Free)
3
tAA
Clock Low to Data Out Valid
200
200
900
200
200
900
200
200
900
tCLQV
Data Out Hold Time After Clock
Low
tCLQX
tDH
fC
fSCL
tWR
Clock Frequency
Write Time
400
10
400
10
400
10
kHz
ms
tW
Note: 1. For a reSTART condition, or following a write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data.
Figure 9. AC Testing Input Output Waveforms
Table 10. AC Measurement Conditions
0.8V
Input Rise and Fall Times
Input Pulse Voltages
≤ 50 ns
CC
0.7V
0.3V
CC
CC
0.2V to 0.8V
CC
CC
0.2V
CC
Input and Output Timing
Reference Voltages
0.3V to 0.7V
CC
CC
AI00825
11/19
M24256-B, M24128-B
Figure 10. AC Waveforms
tCHCL
tDLCL
tCLCH
SCL
tDXCX
tCHDH
SDA IN
tCHDX
tCLDX
SDA
tDHDL
START
CONDITION
SDA
STOP &
BUS FREE
INPUT CHANGE
SCL
tCLQV
tCLQX
DATA VALID
SDA OUT
DATA OUTPUT
SCL
tW
SDA IN
tCHDH
tCHDX
STOP
WRITE CYCLE
START
CONDITION
CONDITION
AI00795B
12/19
M24256-B, M24128-B
Table 11. Ordering Information Scheme
Example:
M24256
– B
W
MN
6
T
Memory Capacity
Option
256
128
256 Kbit (32K x 8)
128 Kbit (16K x 8)
T
Tape and Reel Packing
Temperature Range
–40 °C to 85 °C
6
5
–20 °C to 85 °C
Operating Voltage
Package
1
4.5 V to 5.5 V
2.5 V to 5.5 V
1.8 V to 3.6 V
BN PSDIP8 (0.25 mm frame)
MN SO8 (150 mil width)
blank
W
R
DW TSSOP8 (169 mil width)
DL
TSSOP14 (169 mil width)
Note: 1. Available only on request.
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact your
nearest ST Sales Office.
13/19
M24256-B, M24128-B
Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm
inches
Min.
0.154
0.019
0.130
0.014
0.045
0.008
0.362
–
Symb.
Typ.
Min.
3.90
0.49
3.30
0.36
1.15
0.20
9.20
–
Max.
5.90
–
Typ.
Max.
0.232
–
A
A1
A2
B
5.30
0.56
1.65
0.36
9.90
–
0.209
0.022
0.065
0.014
0.390
–
B1
C
D
E
7.62
2.54
0.300
0.100
E1
e1
eA
eB
L
6.00
–
6.70
–
0.236
–
0.264
–
7.80
–
0.307
–
10.00
3.80
0.394
0.150
3.00
8
0.118
8
N
Figure 11. PSDIP8 (BN)
A2
A
L
A1
e1
B
C
eA
eB
B1
D
N
1
E1
E
PSDIP-a
Note: 1. Drawing is not to scale.
14/19
M24256-B, M24128-B
Table 13. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm
inches
Symb.
Typ.
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
Figure 12. SO8 narrow (MN)
h x 45°
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-a
Note: 1. Drawing is not to scale.
15/19
M24256-B, M24128-B
Table 14. TSSOP8 - 8 lead Thin Shrink Small Outline
mm
inches
Min.
Symb.
Typ.
Min.
Max.
1.10
0.15
0.95
0.30
0.20
3.10
6.50
4.50
–
Typ.
Max.
0.043
0.006
0.037
0.012
0.008
0.122
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
2.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.114
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
8
8
CP
0.08
0.003
Figure 13. TSSOP8 (DW)
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Note: 1. Drawing is not to scale.
16/19
M24256-B, M24128-B
Table 15. TSSOP14 - 14 lead Thin Shrink Small Outline
mm
inches
Symb.
Typ.
Min.
Max.
1.10
0.15
0.95
0.30
0.20
5.10
6.50
4.50
–
Typ.
Min.
Max.
0.043
0.006
0.037
0.012
0.008
0.197
0.256
0.177
–
A
A1
A2
B
0.05
0.85
0.19
0.09
4.90
6.25
4.30
–
0.002
0.033
0.007
0.004
0.193
0.246
0.169
–
C
D
E
E1
e
0.65
0.026
L
0.50
0°
0.70
8°
0.020
0°
0.028
8°
α
N
14
14
CP
0.08
0.003
Figure 14. TSSOP14 (DL)
D
DIE
N
C
E1
E
1
N/2
α
A1
L
A
A2
B
e
CP
TSSOP
Note: 1. Drawing is not to scale.
17/19
M24256-B, M24128-B
Table 16. Revision History
Date
Description of Revision
28-Dec-1999
24-Feb-2000
TSSOP8 package added (pp 1, 2, OrderingInfo, PackageMechData).
E2, E1, E0 must be tied to Vcc or Vss, on page 3
Low Pass Filter Time Constant changed to Glitch Filter in Table 8
18/19
M24256-B, M24128-B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringement of patents or other rights of third parties which may result from its use. No license isgranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.
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19/19
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