M24C16-WDS6T/W [STMICROELECTRONICS]
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM; 16Kbit的， 8Kbit ， 4k位， 2Kbit和1K位，串行I²C总线EEPROM
| 型号： | M24C16-WDS6T/W |
| 厂家： | 
ST |
| 描述： | 16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM |
| 文件： | 总29页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24C16, M24C08
M24C04, M24C02, M24C01
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
2
■
Two Wire I C Serial Interface
Supports 400kHz Protocol
Figure 1. Packages
■
Single Supply Voltage:
–
–
–
4.5 to 5.5V for M24Cxx
2.5 to 5.5V for M24Cxx-W
1.8 to 5.5V for M24Cxx-R
8
■
■
■
■
■
■
■
■
Write Control Input
BYTE and PAGE WRITE (up to 16 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Behavior
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
UFDFPN8 (MB)
2x3mm² (MLP)
March 2004
1/29
M24C16, M24C08, M24C04, M24C02, M24C01
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/29
M24C16, M24C08, M24C04, M24C02, M24C01
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Operating Conditions (M24Cxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Operating Conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Operating Conditions (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. DC Characteristics (M24Cxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11. DC Characteristics (M24Cxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. DC Characteristics (M24Cxx-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. DC Characteristics (M24Cxx-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. DC Characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. AC Characteristics (M24Cxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 16. AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3) . . . . . 18
Table 17. AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 21
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 21
Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 22
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
22
Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline
23
Table 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.
23
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24
Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 24
Figure 16.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
25
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 23. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 24. How to Identify Current and New Products by the Process Identification Letter . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTION
2
These I C-compatible electrically erasable pro-
When writing data to the memory, the device in-
serts an acknowledge bit during the 9 bit time,
th
grammable memory (EEPROM) devices are orga-
nized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02, M24C01).
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 2. Logic Diagram
V
CC
Table 1. Signal Names
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
3
E0-E2
SDA
SCL
M24Cxx
SCL
WC
WC
V
CC
SS
V
Power On Reset: V Lock-Out Write Protect
CC
V
SS
AI02033
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V has reached
the POR threshold value, and all operations are
disabled – the device will not respond to any com-
CC
2
I C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
mand. In the same way, when V drops from the
CC
2
(1010) in accordance with the I C bus definition.
The device behaves as a slave in the I C protocol,
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command.
2
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2.),
terminated by an acknowledge bit.
A stable and valid V (as defined in Table 6. and
CC
Table 7.) must be applied before applying any log-
ic signal.
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View)
M24Cxx
16Kb/8Kb/4Kb/2Kb
NC/ NC/ NC/ E0
NC/ NC/ E1/ E1
NC/ E2/ E2/ E2
/1Kb
/ E0
/ E1
/ E2
1
2
3
4
8
7
6
5
V
CC
WC
SCL
SDA
V
SS
AI02034E
Note: 1. NC = Not Connected
2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
4/29
M24C16, M24C08, M24C04, M24C02, M24C01
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor can be connected from Serial
rial Data (SDA) to V . (Figure 4. indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
CC
Clock (SCL) to V . (Figure 4. indicates how the
CC
to V
or V , to establish the Device Select
CC
SS
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
Code.
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as V , and
IL
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
2
Figure 4. Maximum R Value versus Bus Capacitance (C
) for an I C Bus
L
BUS
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
fc = 400kHz
C
BUS
0
10
100
(pF)
1000
C
BUS
AI01665
5/29
M24C16, M24C08, M24C04, M24C02, M24C01
2
Figure 5. I C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 2. Device Select Code
1
2,3
RW
Device Type Identifier
Chip Enable
b7
b6
0
b5
1
b4
b3
E2
b2
E1
E1
E1
A9
A9
b1
E0
E0
A8
A8
A8
b0
M24C01 Select Code
M24C02 Select Code
M24C04 Select Code
M24C08 Select Code
M24C16 Select Code
1
1
1
1
1
0
0
0
0
0
RW
RW
RW
RW
RW
0
1
E2
0
1
E2
0
1
E2
0
1
A10
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.
6/29
M24C16, M24C08, M24C04, M24C02, M24C01
DEVICE OPERATION
The device supports the I C protocol. This is sum-
2
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
marized in Figure 5.. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave de-
vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24Cxx device is always
a slave in all communication.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Each device is given a unique 3-bit code on the
Chip Enable (E0, E1, E2) inputs. When the Device
Select Code is received, the device only responds
if the Chip Enable Address is the same as the val-
ue on the Chip Enable (E0, E1, E2) inputs. How-
ever, those devices with larger memory capacities
(the M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for use on devices
that need to use address line A8; E1 is not avail-
able for devices that need to use address line A9,
and E2 is not available for devices that need to use
address line A10 (see Figure 3. and Table 2. for
details). Using the E0, E1 and E2 inputs, up to
eight M24C02 (or M24C01), four M24C04, two
M24C08 or one M24C16 devices can be connect-
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
2
ed to one I C bus. In each case, and in the hybrid
Acknowledge Bit (ACK)
cases, this gives a total memory capacity of
16 Kbits, 2 KBytes (except where M24C01 devic-
es are used).
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
th
The 8 bit is the Read/Write bit (RW). This bit is
(SDA) after sending eight bits of data. During the
th
set to 1 for Read and 0 for Write operations.
9
clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9 bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
th
Table 3. Operating Modes
1
Mode
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = 1
X
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 16
START, Device Select, RW = 0
Note: 1. X = VIH or VIL.
7/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
ACK
NO ACK
DATA IN
Byte Write
DEV SEL
BYTE ADDR
R/W
WC
ACK
ACK
NO ACK
NO ACK
DATA IN 3
Page Write
DEV SEL
BYTE ADDR
DATA IN 1 DATA IN 2
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write
(cont'd)
DATA IN N
AI02803C
Write Operations
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in Figure 6., and the location is
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminates the transfer by gener-
ating a Stop condition, as shown in Figure 7..
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7., and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
Page Write
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10 bit” time
th
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is Write-protected, by Write Control (WC) be-
ing driven High (during the period from the Start
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Write-protected, by Write Con-
trol (WC) being driven High (during the period from
8/29
M24C16, M24C08, M24C04, M24C02, M24C01
condition until the end of the address byte), the de-
vice replies to the data bytes with NoAck, as
shown in Figure 6., and the locations are not mod-
ified. After each byte is transferred, the internal
byte address counter (the 4 least significant ad-
dress bits only) is incremented. The transfer is ter-
minated by the bus master generating a Stop
condition.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
WC
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
ACK
ACK
ACK
ACK
PAGE WRITE
DEV SEL
BYTE ADDR
DATA IN 1
DATA IN 2
DATA IN 3
R/W
WC (cont'd)
ACK
ACK
PAGE WRITE
(cont'd)
DATA IN N
AI02804B
9/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
Minimizing System Delays by Polling On ACK
–
–
Initial condition: a Write cycle is in progress.
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
The maximum Write time (t ) is shown in Table
w
–
Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
15. to Table 17., but the typical time is shorter. To
make use of this, a polling sequence can be used
by the bus master.
The sequence, as shown in Figure 8., is:
10/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9. Read Mode Sequences
ACK
NO ACK
CURRENT
ADDRESS
READ
DEV SEL
DATA OUT
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
DATA OUT N
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
st
rd
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
master must not acknowledge the byte, and termi-
nates the transfer with a Stop condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 9.) but without sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the RW bit
set to 1. The device acknowledges this, and out-
puts the contents of the addressed byte. The bus
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 9., without acknowledging the
byte.
11/29
M24C16, M24C08, M24C04, M24C02, M24C01
Sequential Read
Acknowledge in Read Mode
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9..
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9 bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
th
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh).
12/29
M24C16, M24C08, M24C04, M24C02, M24C01
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
°C
°C
V
TSTG
Storage Temperature
–65
150
1
TLEAD
VIO
Lead Temperature during Soldering
Input or Output range
See note
–0.50
–0.50
–4000
6.5
6.5
VCC
Supply Voltage
V
2
VESD
4000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
13/29
M24C16, M24C08, M24C04, M24C02, M24C01
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 5. Operating Conditions (M24Cxx)
Symbol
Parameter
Min.
4.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
Table 6. Operating Conditions (M24Cxx-W)
Symbol
Parameter
Min.
2.5
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature (Device Grade 6)
Ambient Operating Temperature (Device Grade 3)
–40
–40
85
°C
°C
TA
125
Table 7. Operating Conditions (M24Cxx-R)
Symbol
Parameter
Min.
1.8
Max.
5.5
Unit
V
V
CC
Supply Voltage
Ambient Operating Temperature
TA
–40
85
°C
14/29
M24C16, M24C08, M24C04, M24C02, M24C01
Table 8. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
Input Levels
50
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Levels
V
CC
Figure 10. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
Table 9. Input Parameters
1,2
Symbol
CIN
Test Condition
Min.
Max.
8
Unit
pF
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
WC Input Impedance
CIN
6
pF
ZWCL
ZWCH
VIN < 0.5 V
5
70
kΩ
kΩ
WC Input Impedance
VIN > 0.7VCC
500
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
Single glitch
100
ns
Note: 1. T = 25°C, f = 400kHz
A
2. Sampled only, not 100% tested.
Table 10. DC Characteristics (M24Cxx, Device Grade 6)
Test Condition
(in addition to those in Table 5.)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
± 2
2
µA
mA
µA
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
ICC1
VIN = VSS or VCC , VCC = 5 V
Stand-by Supply Current
1
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.45
–0.45
0.3VCC
0.5
V
V
V
V
VIL
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.4
VOL
Output Low Voltage
IOL = 3 mA, VCC = 5 V
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx6 range.
15/29
M24C16, M24C08, M24C04, M24C02, M24C01
Table 11. DC Characteristics (M24Cxx, Device Grade 3)
Test Condition
(in addition to those in Table 5.)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
± 2
3
µA
mA
µA
V
CC=5V, f =400kHz (rise/fall time < 30ns)
c
ICC1
VIN = VSS or VCC , VCC = 5 V
Stand-by Supply Current
5
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.45
–0.45
0.3VCC
0.5
V
V
V
V
VIL
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.4
VOL
Output Low Voltage
IOL = 3 mA, VCC = 5 V
Note: 1. This range is Not for New Design, and will soon be replaced by the M24Cxx-Wxx3 range.
Table 12. DC Characteristics (M24Cxx-W, Device Grade 6)
Test Condition
Symbol
Parameter
Min.
Max.
Unit
(in addition to those in Table 6.)
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
ICC
VOUT = VSS or VCC, SDA in Hi-Z
Output Leakage Current
Supply Current
± 2
1
µA
mA
µA
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
c
ICC1
Stand-by Supply Current
VIN = VSS or VCC , VCC = 2.5 V
0.5
Input Low Voltage
(E2, E1, E0, SCL, SDA)
0.3VCC
0.5
–0.45
–0.45
V
V
V
V
VIL
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.4
VOL
IOL = 2.1 mA, VCC = 2.5 V
Output Low Voltage
16/29
M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. DC Characteristics (M24Cxx-W, Device Grade 3)
Test Condition
(in addition to those in Table 6.)
1
1
Symbol
Parameter
Unit
Min.
Max.
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
± 2
3
µA
mA
µA
V
CC =2.5V, f =400kHz (rise/fall time < 30ns)
c
ICC1
V
IN = VSS or VCC , VCC = 2.5 V
Stand-by Supply Current
2
Input Low Voltage
(E2, E1, E0, SCL, SDA)
–0.45
–0.45
0.3VCC
0.5
V
V
V
V
VIL
Input Low Voltage (WC)
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.4
VOL
Output Low Voltage
IOL = 2.1 mA, VCC = 2.5 V
Note: 1. This is preliminary data.
Table 14. DC Characteristics (M24Cxx-R)
Test Condition
(in addition to those in Table 7.)
Symbol
Parameter
Min.
Max.
Unit
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
µA
ILO
ICC
VOUT = VSS or VCC, SDA in Hi-Z
Output Leakage Current
Supply Current
± 2
0.8
µA
mA
µA
V
V
CC =1.8V, f =400kHz (rise/fall time < 30ns)
c
ICC1
Stand-by Supply Current
VIN = VSS or VCC , VCC = 1.8 V
2.5 V ≤ VCC
0.3
–0.45
–0.45
–0.45
0.3 VCC
0.25 VCC
0.5
Input Low Voltage
(E2, E1, E0, SCL, SDA)
VIL
1.8 V ≤ VCC < 2.5 V
V
Input Low Voltage (WC)
V
Input High Voltage
(E2, E1, E0, SCL, SDA, WC)
VIH
0.7VCC
VCC+1
0.2
V
V
VOL
Output Low Voltage
IOL = 0.7 mA, VCC = 1.8 V
17/29
M24C16, M24C08, M24C04, M24C02, M24C01
Table 15. AC Characteristics (M24Cxx, Device Grade 6)
Test conditions specified in Table 8. and Table 5.
4
4
Symbol
fC
Alt.
fSCL
Parameter
Unit
kHz
ns
Min.
Max.
Clock Frequency
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
600
1300
20
ns
2
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
100
0
ns
ns
200
200
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
Start Condition Set Up Time
Start Condition Hold Time
600
600
ns
ns
ns
ns
ms
tCHDX
tDLCL
tCHDH
tDHDL
tW
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
600
1300
tWR
5
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary data for M24Cxx-Wxx3.
Table 16. AC Characteristics (M24Cxx, Device Grade 3; M24Cxx-W, Device Grade 6 or 3)
Test conditions specified in Table 8. and Table 5. or Table 6.
Symbol
fC
Alt.
fSCL
Parameter
Min.
Max.
Unit
kHz
ns
Clock Frequency
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
600
1300
20
ns
2
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
100
0
ns
ns
200
200
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
Start Condition Set Up Time
Start Condition Hold Time
600
600
ns
ns
ns
ns
ms
tCHDX
tDLCL
tCHDH
tDHDL
tW
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
600
1300
4
tWR
10 or 5
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. 10ms write time is offered on the standard device. 5ms write time is offered on new products bearing the Process Identification letter
“W” or “G” on the package, as described in Table 24..
18/29
M24C16, M24C08, M24C04, M24C02, M24C01
Table 17. AC Characteristics (M24Cxx-R)
Test conditions specified in Table 8. and Table 7.
4
4
Symbol
fC
Alt.
fSCL
Parameter
Clock Frequency
Min.
Max.
Unit
kHz
ns
Min.
Max.
100
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
4000
4700
20
600
1300
20
ns
2
300
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
250
0
100
0
ns
ns
200
200
ns
Clock Low to Next Data Valid (Access
Time)
3
tAA
200
3500
200
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
4700
4000
4000
600
600
600
ns
ns
ns
tCHDX
tDLCL
tCHDH
Time between Stop Condition and
Next Start Condition
tDHDL
tW
tBUF
tWR
4700
1300
ns
Write Time
10
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. 100kHz clock frequency is offered on the standard device. 400kHz clock frequency is offered on new products bearing the Process
Identification letter “W” or “G” on the package, as described in Table 24..
19/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 11. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
tCHDX
START
Condition
tW
Write Cycle
STOP
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
20/29
M24C16, M24C08, M24C04, M24C02, M24C01
PACKAGE MECHANICAL
Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
E
b2
A2
A1
A
L
c
b
e
eA
eB
D
8
1
E1
PDIP-B
Note: Drawing is not to scale.
Table 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
mm
inches
Min.
Symb.
Typ.
Min.
Max.
Typ.
Max.
A
A1
A2
b
5.33
0.210
0.38
2.92
0.36
1.14
0.20
9.02
7.62
6.10
–
0.015
0.115
0.014
0.045
0.008
0.355
0.300
0.240
–
3.30
0.46
1.52
0.25
9.27
7.87
6.35
2.54
7.62
4.95
0.56
1.78
0.36
10.16
8.26
7.11
–
0.130
0.018
0.060
0.010
0.365
0.310
0.250
0.100
0.300
0.195
0.022
0.070
0.014
0.400
0.325
0.280
–
b2
c
D
E
E1
e
eA
eB
L
–
–
–
–
10.92
3.81
0.430
0.150
3.30
2.92
0.130
0.115
21/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 13. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A
C
B
CP
e
D
N
E
H
1
A1
α
L
SO-a
Note: Drawing is not to scale.
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm
Min.
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min.
0.053
0.004
0.013
0.007
0.189
0.150
–
Symb.
Typ.
Max.
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ.
Max.
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
22/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline
e
b
D
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V . It must not be allowed to be connected to
SS
any other voltage or signal line on the PCB, for example during the soldering process.
Table 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data
mm
Min.
0.50
0.00
0.20
inches
Min.
Symbol
Typ.
Max.
0.60
0.05
0.30
Typ.
Max.
0.024
0.002
0.012
A
A1
b
0.55
0.022
0.020
0.000
0.008
0.25
2.00
0.010
0.079
D
D2
ddd
E
1.55
1.65
0.05
0.061
0.065
0.002
3.00
0.118
E2
e
0.15
–
0.25
–
0.006
–
0.010
–
0.50
0.45
0.020
0.018
L
0.40
0.50
0.15
0.016
0.020
0.006
L1
L3
N
0.30
0.012
8
8
23/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Note: Drawing is not to scale.
Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
24/29
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 16. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
D
8
1
5
4
c
E1
E
α
A1
L
A
A2
L1
CP
b
e
TSSOP8BM
Note: Drawing is not to scale.
Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
mm
inches
Min.
Symbol
Typ.
Min.
Max.
1.100
0.150
0.950
0.400
0.230
3.100
5.150
3.100
–
Typ.
Max.
0.0433
0.0059
0.0374
0.0157
0.0091
0.1220
0.2028
0.1220
–
A
A1
A2
b
0.050
0.750
0.250
0.130
2.900
4.650
2.900
–
0.0020
0.0295
0.0098
0.0051
0.1142
0.1831
0.1142
–
0.850
0.0335
c
D
3.000
4.900
3.000
0.650
0.1181
0.1929
0.1181
0.0256
E
E1
e
CP
L
0.100
0.700
0.0039
0.0276
0.550
0.950
0.400
0°
0.0217
0.0374
0.0157
0°
L1
α
6°
6°
25/29
M24C16, M24C08, M24C04, M24C02, M24C01
PART NUMBERING
Table 23. Ordering Information Scheme
Example:
M24C08
–
W DW
6
T
P
/W
Device Type
2
M24 = I C serial access EEPROM
Device Function
16 = 16 Kbit (2048 x 8)
08 = 8 Kbit (1024 x 8)
04 = 4 Kbit (512 x 8)
02 = 2 Kbit (256 x 8)
01 = 1 Kbit (128 x 8)
Operating Voltage
4
blank = V = 4.5 to 5.5V (400kHz)
CC
2
W
= V = 2.5 to 5.5V (400kHz)
CC
R = V = 1.8 to 5.5V (400kHz)
CC
Package
BN = PDIP8
MN = SO8 (150 mil width)
MB = UDFDFPN8 (MLP8)
DW = TSSOP8 (169 mil width)
DS = TSSOP8 (3x3mm² body size, MSOP8)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
1
3 = Automotive: device tested with High Reliability Certified Flow over –40 to 125 °C
Option
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free
2
3
3
Process
blank = F6SP20%
/W = F6SP36%
/G = F6SP36%
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. 2.5 to 5.5V devices bearing the process letter “W” or “G” in the package marking (on the top side of the package, on the right side,
see Table 24.), guarantee a maximum write time of 5ms, instead of the standard 10ms. For more information about these devices,
and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/EE/0061 and 0062
(PCEE0061 and PCEE0062).
3. Used only for Device Grade 3
4. This range is Not for New Design, and will soon be replaced by the M24Cxx-W range.
26/29
M24C16, M24C08, M24C04, M24C02, M24C01
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
Table 24. How to Identify Current and New Products by the Process Identification Letter
1
1
Markings on Current Products
Markings on New Products
24CxxW6
24CxxW6
24CxxW6
ST xxxxL
ST xxxxW
ST xxxxG
Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST
Sales Office for Process Change Notices PCN MPG/EE/0061 and 0062 (PCEE0061 and PCEE0062).
27/29
M24C16, M24C08, M24C04, M24C02, M24C01
REVISION HISTORY
Table 25. Document Revision History
Date
Version
Description of Revision
TSSOP8 Turned-Die package removed (p 2 and order information)
Lead temperature added for TSSOP8 in table 2
10-Dec-1999
2.4
18-Apr-2000
05-May-2000
2.5
2.6
Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13
Extra labelling to Fig-2D
SBGA package information removed to an annex document
-R range changed to being the -S range, and the new -R range added
23-Nov-2000
3.0
SBGA package information put back in this document
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data updated
Wording brought in to line with standard glossary
19-Feb-2001
3.1
20-Apr-2001
08-Oct-2001
3.2
3.3
Revision of DC and AC characteristics for the -S series
Ball numbers added to the SBGA connections and package mechanical illustrations
Specification of Test Condition for Leakage Currents in the DC Characteristics table
improved
09-Nov-2001
3.4
Document reformatted using new template. SBGA5 package removed
TSSOP8 (3x3mm² body size) package (MSOP8) added. -L voltage range added
30-Jul-2002
04-Feb-2003
3.5
3.6
Document title spelt out more fully. “W”-marked devices with tw=5ms added.
-R voltage range upgraded to 400kHz working, and no longer preliminary data.
5V voltage range at temperature range 3 (-xx3) no longer preliminary data.
-S voltage range removed. -Wxx3 voltage+temp ranged added as preliminary data.
05-May-2003
07-Oct-2003
3.7
4.0
Table of contents, and Pb-free options added. Minor wording changes in Summary
Description, Power-On Reset, Memory Addressing, Read Operations. V (min) improved to
IL
-0.45V. t (max) value for -R voltage range corrected.
W
MLP package added. Absolute Maximum Ratings for V (min) and V (min) changed.
IO
CC
Soldering temperature information clarified for RoHS compliant devices. Device grade
information clarified. Process identification letter “G” information added. 2.2-5.5V range is
removed, and 4.5-5.5V range is now Not for New Design
17-Mar-2004
5.0
28/29
M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -
Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -
Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
29/29
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