M24M01-DFCT6P/B [STMICROELECTRONICS]
I2C/2-WIRE SERIAL EEPROM;
| 型号： | M24M01-DFCT6P/B |
| 厂家： | 
ST |
| 描述： | I2C/2-WIRE SERIAL EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总41页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24M01-R M24M01-DF
1-Mbit serial I²C bus EEPROM
Datasheet −production data
Features
2
■ Compatible with all I C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■ Memory array:
SO8 (MN)
150 mil width
– 1 Mbit (128 Kbytes) of EEPROM
– Page size: 256 bytes
– Additional Write lockable page
(M24M01-D order codes)
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
TSSOP8 (DW)
WLCSP (CS)
■ Single supply voltage: 1.7 V to 5.5 V
■ Operating temperature range: from -40 °C up
to +85 °C
■ Random and sequential Read modes
■ Write protect of the whole memory array
■ Enhanced ESD/Latch-Up protection
■ More than 4 million Write cycles
■ More than 200-year data retention
■ Packages
– RoHS compliant and halogen-free
®
(ECOPACK )
April 2012
Doc ID 12943 Rev 9
1/41
This is information on a product in full production.
www.st.com
1
Contents
M24M01-R M24M01-DF
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
2.2
2.3
2.4
2.5
2.6
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6.1
2.6.2
2.6.3
2.6.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
4.5
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 18
Lock Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . 18
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 19
Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 20
5.2
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.1
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Contents
5.2.2
5.2.3
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3
5.4
Read Identification Page (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . 22
Read the lock status (M24M01-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.4.1
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7
8
9
10
11
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List of tables
M24M01-R M24M01-DF
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics (voltage range R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (voltage range F, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33
SO8N – 8 lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 34
WLCSP8 – Wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . 35
WLCSP – Wafer level chip size package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4/41
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M24M01-R M24M01-DF
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections for die identified by process letter A (bump side view) . . . . . . . . . . . . 7
WLCSP connections for die identified by process letter K (bump side view) . . . . . . . . . . . . 8
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
Figure 10. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Maximum R
value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C
Figure 14. Maximum R
value versus bus parasitic capacitance C ) for
bus
bus
2
an I C bus at maximum frequency f = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C
Figure 15. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34
Figure 18. Standard WLCSP8 – Wafer level chip scale package outline (for die
identified by process letter A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. Thin WLCSP – Wafer level chip size package outline (for die identified
by process letter K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 12943 Rev 9
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Description
M24M01-R M24M01-DF
1
Description
2
The M24M01 is a 1 Mb I C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 128 K × 8 bits.
The M24M01-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24M01-DF
can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of
-40 °C / +85 °C.
The M24M01-D offers an additional page, named the Identification Page (256 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1.
Logic diagram
6
##
ꢀ
%ꢁꢂ%ꢀ
3$!
-ꢀꢃXXX
3#,
7#
6
33
.4ꢀꢁꢂꢂꢀ7ꢃ
Table 1.
Signal names
Signal name
Function
Direction
E1, E2
SDA
SCL
WC
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
Input
I/O
Input
Input
VCC
VSS
6/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Figure 2.
Description
8-pin package connections
-ꢀꢃ-ꢊꢁ
$5
%ꢁ
%ꢀ
ꢁ
ꢇ
ꢅ
ꢈ
ꢉ
6
##
ꢀ
ꢆ
ꢃ
7#
3#,
3$!
6
33
-3ꢁꢄꢅꢅꢆ6ꢁ
1. DU: Don't Use (if connected, must be connected to VSS
)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Figure 3.
WLCSP connections for die identified by process letter A (bump side
view)
)NDEX
6
3#,
3$!
##
6
7#
$5
33
%ꢁ
%ꢀ
-3ꢁꢄꢅꢅꢀ6ꢁ
1. DU: Don't Use (if connected, must be connected to VSS
)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Doc ID 12943 Rev 9
7/41
Description
M24M01-R M24M01-DF
Figure 4.
WLCSP connections for die identified by process letter K (bump side
view)
SCL
VCC
W
SDA
VSS
DU
E1
E2
MS30220V1
1. DU: Don't Use (if connected, must be connected to VSS
)
2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1.
Caution:
As EEPROM cells lose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form by STMicroelectronics must never be
exposed to UV light.
8/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Signal description
2
Signal description
2.1
Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2
2.3
Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open
drain output that may be wire-OR’ed with other open drain or open collector signals on the
bus. A pull up resistor must be connected (Figure 13 indicates how to calculate the value of
the pull-up resistor).
Chip Enable (E1, E2)
These input signals are used to set the value that is to be looked for on the two bits (b3, b2)
of the 7-bit device select code. These inputs must be tied to V or V , to establish the
CC
SS
device select code as shown in Figure 5. When not connected (left floating), these inputs
are read as low (0,0).
Figure 5.
Device select code
V
V
CC
CC
M24xxx
M24xxx
E
E
i
i
V
V
SS
SS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
Doc ID 12943 Rev 9
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Signal description
M24M01-R M24M01-DF
2.5
VSS (ground)
V
is the reference for the V supply voltage.
CC
SS
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Operating conditions
CC
CC
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the V line with a suitable capacitor (usually of the order of 10
CC
nF to 100 nF) close to the V /V package pins.
CC SS
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (t ).
W
2.6.2
2.6.3
Power-up conditions
The V voltage has to rise continuously from 0 V up to the minimum V operating voltage
CC
CC
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until V has reached the
CC
internal reset threshold voltage. This threshold is lower than the minimum V operating
CC
voltage (see Operating conditions in Section 8: DC and AC parameters). When V passes
CC
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until V reaches a valid and stable DC voltage within the
CC
specified [V (min), V (max)] range (see Operating conditions in Section 8: DC and AC
CC
CC
parameters).
In a similar way, during power-down (continuous decrease in V ), the device must not be
CC
accessed when V drops below V (min). When V drops below the internal reset
CC
CC
CC
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in V ), the device must be in the Standby Power
CC
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
10/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Memory organization
3
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
7#
%ꢀ
%ꢁ
(IGH VOLTAGE
GENERATOR
#ONTROL LOGIC
3#,
3$!
)ꢋ/ SHIFT REGISTER
$ATA
REGISTER
!DDRESS REGISTER
AND COUNTER
ꢁ PAGE
)DENTIFICATION PAGE
8 DECODER
-3ꢁꢄꢅꢄꢄ6ꢁ
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Device operation
M24M01-R M24M01-DF
4
Device operation
2
The device supports the I C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
2
Figure 7.
I C bus protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
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M24M01-R M24M01-DF
Device operation
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3
4.4
4.5
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to
th
acknowledge the receipt of the eight data bits.
Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 7 (on Serial Data (SDA), most significant bit first).
Table 2.
Device select code
Device type identifier(1)
Chip Enable
address(2)
Address bits
RW
b7
1
b6
0
b5
1
b4
0
b3
E2
b2
b1
b0
When accessing
the memory
E1
A16
RW
When accessing
the Identification
page
1
0
1
1
E2
E1
A16
RW
1. The most significant bit, b7, is sent first.
2. E2,E1 are compared against the external pin on the memory device.
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Device operation
M24M01-R M24M01-DF
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1 inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
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Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Instructions
5
Instructions
5.1
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Table 3.
Most significant address byte
A14 A13 A12
A15
A11
A3
A10
A2
A9
A1
A8
A0
Table 4.
Least significant address byte
A6 A5 A4
A7
The 128 Kbytes (1 Mb) are addressed with 17 address bits, the 16 lower address bits being
defined by the two address bytes and the most significant address bit (A16) being included
in the Device Select code (see Table 2).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
th
the “10 bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t is triggered. A Stop condition at any other time slot does not trigger the internal
W
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t ), the
W
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 9.
Doc ID 12943 Rev 9
15/41
Instructions
M24M01-R M24M01-DF
5.1.1
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 8.
Figure 8.
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
ACK
ACK
Byte Write
Dev sel
Byte addr
Byte addr
Data in
R/W
WC
ACK
ACK
ACK
ACK
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
ACK
Page Write (cont'd)
Data in N
AI01106d
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Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Instructions
5.1.2
Page Write
The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, b16-b8, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 9. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 9.
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
Byte Write
Dev sel
Byte addr
Byte addr
Data in
R/W
WC
ACK
ACK
ACK
NO ACK
Data in 2
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write (cont'd)
Data in N
AI01120d
Doc ID 12943 Rev 9
17/41
Instructions
M24M01-R M24M01-DF
5.1.3
Write Identification Page (M24M01-D only)
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences:
●
Device type identifier = 1011b
●
MSB address bits A16/A8 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A7/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4
Lock Identification Page (M24M01-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
●
●
●
Device type identifier = 1011b
Address bit A10 must be ‘1’; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
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M24M01-R M24M01-DF
Instructions
5.1.5
ECC (Error Correction Code) and Write cycling
The Error Correction Code (ECC) is an internal logic function which is transparent for the
2
I C communication protocol.
(a)
The ECC logic is implemented on each group of four EEPROM bytes . Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
(a)
other bytes located in the same group . As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 9: Cycling performance by groups of four bytes.
a. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an
integer.
Doc ID 12943 Rev 9
19/41
Instructions
M24M01-R M24M01-DF
5.1.6
Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 10, is:
●
Initial condition: a Write cycle is in progress.
●
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
ACK
NO
returned
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
addressing the
memory
NO
YES
Send Address
and Receive ACK
ReStart
NO
YES
Stop
StartCondition
Data for the
Write cperation
Device select
with RW = 1
Continue the
Continue the
Random Read operation
Write operation
AI01847de
1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
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Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Instructions
5.2
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Figure 11. Read mode sequences
ACK
NO ACK
Current
Address
Read
Dev sel
Data out
R/W
ACK
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out
R/W
R/W
ACK
ACK
ACK
NO ACK
Data out N
Sequential
Current
Read
Dev sel
Data out 1
R/W
ACK
R/W
ACK
ACK
ACK
R/W
ACK
Sequention
Random
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out1
ACK
NO ACK
Data out N
AI01105d
5.2.1
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
Doc ID 12943 Rev 9
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Instructions
M24M01-R M24M01-DF
5.2.2
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the byte.
5.2.3
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
5.3
Read Identification Page (M24M01-D only)
The Identification Page (256 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A16/A8 are don't
care, the LSB address bits A7/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 100d, the number of bytes should be less than
or equal to 156, as the ID page boundary is 256 bytes).
5.4
Read the lock status (M24M01-D only)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
●
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
●
Stop: the device is then set back into Standby mode by the Stop condition.
5.4.1
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
th
during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
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Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Initial delivery state
6
Initial delivery state
The device is delivered with all bits set to 1 (both in the memory array and in the
Identification page - that is, each byte contains FFh).
Doc ID 12943 Rev 9
23/41
Maximum rating
M24M01-R M24M01-DF
7
Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VIO
Lead temperature during soldering
Input or output range
see note (1)
–0.50
VCC+0.6
5
IOL
DC output current (SDA = 0)
Supply voltage
-
–0.50
-
mA
V
VCC
6.5
VESD
Electrostatic pulse (Human Body model)(2)
4000(3)
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with JEDEC Std
JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).
3. 3000 V for previous devices (process letter A or B).
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M24M01-R M24M01-DF
DC and AC parameters
8
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6.
Symbol
Operating conditions (voltage range R)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.8
–40
-
5.5
85
1
V
Ambient operating temperature
Operating clock frequency
°C
fC
MHz
Table 7.
Symbol
Operating conditions (voltage range F)
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.7
–40
-
5.5
85
1
V
Ambient operating temperature
Operating clock frequency
°C
fC
MHz
Table 8.
Symbol
AC measurement conditions
Parameter
Min.
Max.
Unit
Cbus
Load capacitance
100
pF
ns
V
SCL input rise/fall time, SDA input fall time
Input levels
50
0.2 VCC to 0.8 VCC
0.3 VCC to 0.7 VCC
Input and output timing reference levels
V
Figure 12. AC measurement I/O waveform
)NPUT VOLTAGE LEVELS
)NPUT AND OUTPUT
4IMING REFERENCE LEVELS
ꢊꢌꢇ6
##
ꢊꢌꢅ6
##
ꢊꢌꢆ6
##
ꢊꢌꢀ6
##
-3ꢁꢄꢅꢅꢃ6ꢁ
Doc ID 12943 Rev 9
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DC and AC parameters
M24M01-R M24M01-DF
Table 9.
Symbol
Cycling performance by groups of four bytes
Parameter
Test condition(1)
Max.
Unit
TA ≤ 25 °C, 1.8 V < VCC < 5.5 V
4,000,000
1,200,000
Write cycle
Write
Ncycle
endurance(2)
cycle(3)
TA = 85 °C, 1.8 V < VCC < 5.5 V
1. Cycling performance for products identified by process letter K.
2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1,
4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by characterization and
qualification.
3. A Write cycle is executed when either a Page Write, a Byte Write, a Write Identification Page or a Lock
Identification Page instruction is decoded. When using the Byte Write, the Page Write or the Write
Identification Page, refer also to Section 5.1.5: ECC (Error Correction Code) and Write cycling.
Table 10. Memory cell data retention
Parameter
Data retention(1)
Test condition
TA = 55 °C
Min.
Unit
200
Year
1. For products identified by process letter K. The data retention is not tested in production but defined from
characterization and qualification results.
Table 11. Input parameters
Symbol
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
CIN
ZL
Input capacitance (SDA)
8
6
pF
pF
kΩ
kΩ
Input capacitance (other pins)
VIN < 0.3 VCC
VIN > 0.7 VCC
30
Input impedance (WC)
ZH
400
1. Sampled only, not 100% tested.
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M24M01-R M24M01-DF
DC and AC parameters
.
Table 12. DC characteristics (voltage range R, device grade 6)
Test conditions (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 6)
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
2
2
µA
µA
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
Supply current (Read)
VCC = 1.8 V, fc= 400 kHz
VCC = 2.5 V, fc =400 kHz
VCC = 5.5 V, fc =400 kHz
1(1)
1
mA
mA
mA
ICC
1.5(2)
fc= 1 MHz
During tW
1.5(3)
2(4)(5)
3(6)
mA
mA
µA
ICC0
Supply current (Write)
Standby supply current
Device not selected,
VIN = VSS or VCC, VCC = 1.8 V
Device not selected,
ICC1
3(7)
5(8)
µA
µA
VIN = VSS or VCC, VCC = 2.5 V
Device not selected,
VIN = VSS or VCC, VCC = 5.5 V
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
1.8 V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
–0.45
–0.45
0.25 VCC
0.30 VCC
V
V
v
Input low voltage
(SCL, SDA, WC)
VIL
VIH
0.75 VCC VCC+1
Input high voltage
(SCL, SDA)
0.70 VCC 0 VCC+1
v
I
OL = 1.0 mA, VCC = 1.8 V
0.2
0.4
0.4
V
V
V
VOL
Output low voltage
IOL = 2.1 mA, VCC = 2.5 V
IOL = 3.0 mA, VCC = 5.5 V
1. Devices identified by process letter A or B offer ICC = 0.8 mA
2. The previous product identified by process letter A or B was specified with Icc(max) = 2 mA.
3. Devices identified by process letter A or B offer ICC = 2.5 mA.
4. Characterized only, not tested in production.
5. The previous product identified by process letter A or B was characterized with Icc0(max) = 5 mA.
6. Devices identified by process letter A or B offer ICC1 = 1 µA.
7. Devices identified by process letter A or B offer ICC1 = 2 µA.
8. Devices identified by process letter A or B offer ICC1 = 3 µA.
Doc ID 12943 Rev 9
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DC and AC parameters
M24M01-R M24M01-DF
Table 13. DC characteristics (voltage range F, device grade 6)
Test conditions (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 6)
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
2
2
µA
µA
device in Standby mode
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
ILO
Output leakage current
Supply current (Read)
VCC = 1.7 V, fc= 400 kHz
VCC = 2.5 V, fc =400 kHz
VCC = 5.5 V, fc =400 kHz
1
mA
mA
mA
1
ICC
1.5
fc= 1 MHz
During tW
1.5
2(1)
3
mA
mA
µA
ICC0
Supply current (Write)
Standby supply current
Device not selected,
VIN = VSS or VCC, VCC = 1.7 V
Device not selected,
ICC1
3
5
µA
µA
VIN = VSS or VCC, VCC = 2.5 V
Device not selected,
VIN = VSS or VCC, VCC = 5.5 V
1.7 V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
1.7 V ≤ VCC < 2.5 V
2.5 V ≤ VCC < 5.5 V
IOL = 1.0 mA, VCC = 1.7 V
–0.45
–0.45
0.25 VCC
0.30 VCC
V
V
v
Input low voltage
(SCL, SDA, WC)
VIL
VIH
0.75 VCC VCC+1
Input high voltage
(SCL, SDA)
0.70 VCC 0 VCC+1
v
0.2
0.4
0.4
V
V
V
VOL
Output low voltage
I
OL = 2.1 mA, VCC = 2.5 V
IOL = 3.0 mA, VCC = 5.5 V
1. Characterized only, not tested in production.
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M24M01-R M24M01-DF
DC and AC parameters
Table 14. 400 kHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tF
Clock frequency
-
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
Clock pulse width high
Clock pulse width low
SDA (out) fall time
600
1300
-
-
20(2)
300
(1)
tQL1QL2
tXH1XH2
tXL1XL2
tDXCH
(3)
(3)
tR
Input signal rise time
Input signal fall time
(3)
(3)
tF
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
-
tCLDX
-
(4)
tCLQX
tDH
tAA
Data out hold time
100(5)
-
(6)
tCLQV
Clock low to next data valid (access time)
-
900
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
600
600
600
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tBUF
1300
-
ns
(7)(2)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
-
-
µs
µs
(8)(2)
tDHWH
tW
tWR
Internal Write cycle duration
5
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
80(9)
ns
(2)
tNS
-
1. Characterized only, not tested in production.
2. With CL = 10 pF.
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C < 400 kHz.
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. The previous product identified by process letter A was specified with tCLQX = 200 ns (min).
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 13.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
9. The previous product identified by process letter A or B was specified with tNS = 100 ns (max).
Doc ID 12943 Rev 9
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DC and AC parameters
M24M01-R M24M01-DF
Table 15. 1 MHz AC characteristics
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
Clock frequency
0
1
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tHIGH Clock pulse width high
tLOW Clock pulse width low
300
tCLCH
400
-
(1)
(1)
tXH1XH2
tXL1XL2
tR
tF
tF
Input signal rise time
Input signal fall time
SDA (out) fall time
(1)
(1)
(8)
tQL1QL2
tDXCX
tCLDX
-
120
tSU:DAT Data in setup time
tHD:DAT Data in hold time
80
0
-
-
(2)
tCLQX
tDH
tAA
Data out hold time
50
-
-
(3)
tCLQV
Clock low to next data valid (access time)
500
tCHDL
tDLCL
tCHDH
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
250
250
250
-
-
-
Time between Stop condition and next Start
condition
tDHDL
tBUF
500
-
ns
(4)(8)
tWLDL
tSU:WC WC set up time (before the Start condition)
tHD:WC WC hold time (after the Stop condition)
0
1
-
-
-
µs
µs
(5)(8)
tDHWH
tW
tWR
Write time
5
ms
Pulse width ignored (input filter on SCL and
SDA)
80(7)
ns
(6)
tNS
-
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when
fC < 1 MHz.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 14.
4. WC=0 set up time condition to enable the execution of a WRITE command.
5. WC=0 hold time condition to enable the execution of a WRITE command.
6. Characterized only, not tested in production.
7. The previous product identified by process letter A or B was specified with tNS = 50 ns (max).
30/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Figure 13. Maximum R
DC and AC parameters
value versus bus parasitic capacitance (C ) for
bus
bus
2
an I C bus at maximum frequency f = 400 kHz
C
ꢁꢊꢊ
4HE 2
X # TIME CONSTANT
BUS
BUS
MUST BE BELOW THE ꢃꢊꢊ NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFTꢌ
6
##
ꢁꢊ
2
BUS
(ERE 2
BUS
§ # ꢏ ꢁꢀꢊ NS
BUS
ꢃ K½
3#,
3$!
)£# BUS
MASTER
-ꢀꢃXXX
ꢁ
ꢆꢊ P&
#
BUS
ꢁꢊ
ꢁꢊꢊ
"US LINE CAPACITOR ꢍP&ꢎ
ꢁꢊꢊꢊ
AIꢁꢃꢅꢄꢈB
Figure 14. Maximum R
value versus bus parasitic capacitance C ) for
bus
bus
2
an I C bus at maximum frequency f = 1MHz
C
6
ꢁꢊꢊ
##
2
BUS
4HE 2
§ #
TIME CONSTANT
BUS
BUS
MUST BE BELOW THE ꢁꢉꢊ NS
TIME CONSTANT LINE REPRESENTED
ON THE LEFTꢌ
3#,
3$!
)£# BUS
MASTER
ꢁꢊ
ꢃ
-ꢀꢃXXX
(EREꢐ
#
§
BUS
ꢏ ꢁꢀꢊ NS
#
2
BUS
BUS
ꢁ
ꢁꢊ
ꢆꢊ
"US LINE CAPACITOR ꢍP&ꢎ
ꢁꢊꢊ
-3ꢁꢄꢅꢃꢉ6ꢁ
Doc ID 12943 Rev 9
31/41
DC and AC parameters
M24M01-R M24M01-DF
Figure 15. AC waveforms
3TART
CONDITION
3TART
CONDITION
3TOP
CONDITION
T8,ꢁ8,ꢀ
T#(#,
T8(ꢁ8(ꢀ
3#,
T#,#(
T$,#,
T8,ꢁ8,ꢀ
3$! )N
7#
3$!
)NPUT
T#($,
T7,$,
T#,$8
T$8#(
3$!
#HANGE
T8(ꢁ8(ꢀ
T#($(
T$($,
T$(7(
3TOP
CONDITION
3TART
CONDITION
3#,
3$! )N
T7
7RITE CYCLE
T#($(
T#($,
3#,
T#,16
T#,18
$ATA VALID
T1,ꢁ1,ꢀ
$ATA VALID
3$! /UT
!)ꢊꢊꢅꢄꢉG
32/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters
Min.
inches(1)
Symbol
Typ.
Max.
Typ.
Min.
Max.
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8°
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 12943 Rev 9
33/41
Package mechanical data
M24M01-R M24M01-DF
Figure 17. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 17. SO8N – 8 lead plastic small outline, 150 mils body width, package data
millimeters
inches (1)
Symbol
Typ
Min
Max
Typ
Min
Max
A
1.750
0.250
0.0689
0.0098
A1
A2
b
0.100
1.250
0.280
0.170
0.0039
0.0492
0.0110
0.0067
0.480
0.230
0.100
5.000
6.200
4.000
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
c
ccc
D
4.900
6.000
3.900
1.270
4.800
5.800
3.800
0.1929
0.2362
0.1535
0.0500
0.1890
0.2283
0.1496
E
E1
e
h
0.250
0°
0.500
8°
0.0098
0°
0.0197
8°
k
L
0.400
1.270
0.0157
0.0500
L1
1.040
0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.
34/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Package mechanical data
Figure 18. Standard WLCSP8 – Wafer level chip scale package outline (for die
identified by process letter A)
e1
D
e2
e
Detail A
e2
E
Orientation
reference
aaa
(4X)
G
A2
F
Orientation reference
A
Wafer back side
Side view
Bump side
Bump
A1
eee Z
(2)
Z
b(8X)
(3)
Seating plane
Note 4
Detail A rotated by 90°
E1_ME_b
1
2
3
4
Drawing is not to scale and corresponds to preliminary data.
The dimension is measured at the maximum bump diameter parallel to primary datum Z.
The primary datum Z and seating plane are defined by the spherical crowns of the bump.
Bump position designation per JESD 95-1, SPP-010.
(1)
Table 18. WLCSP8 – Wafer level chip scale package mechanical data
millimeters
inches(2)
Symbol
Typ
0.580
Min
Max
0.605
Typ
Min
Max
A
0.555
0.0228
0.0091
0.0138
0.0127
0.1406
0.0807
0.0236
0.0945
0.0472
0.0230
0.0167
0.0043
0.0043
0.0043
0.0024
0.0024
0.0219
0.0238
A1
A2
b
0.230
0.350
0.322
3.570
2.050
0.600
2.400
1.200
0.585
0.424
0.110
0.110
0.110
0.060
0.060
D
3.685
2.165
0.1451
0.0852
E
e
e1
e2
F
G
aaa
bbb
ccc
ddd
eee
N (number of bumps) 8
1. Preliminary data.
2. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 12943 Rev 9
35/41
Package mechanical data
M24M01-R M24M01-DF
Figure 19. Thin WLCSP – Wafer level chip size package outline (for die identified
by process letter K)
6$$ BALL MARKING
$
Eꢀ
Eꢆ
%
E
E
Eꢁ
"UMP SIDE
7AFER BACK SIDE
"UMP
$ETAIL !
!ꢁ
!
!ꢀ
$ETAIL ꢁ
ROTATED ꢄꢊ
-3ꢆꢊꢀꢁꢇ6ꢁ
Table 19. WLCSP – Wafer level chip size package mechanical data
millimeters
inches(1)
Symbol
Typ.
Min.
Max.
Typ.
Min.
Max.
A
A1
A2
b
0.300
0.100
0.200
0.126
2.560
1.698
1.000
1.200
1.100
0.500
0.280
0.320
0.0118
0.0039
0.0079
0.0050
0.1008
0.0669
0.0394
0.0472
0.0433
0.0197
0.0110
0.0126
D
E
1.823
0.0676
e
e1
e2
e3
1. Values in inches are converted from mm and rounded to four decimal digits.
36/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Part numbering
10
Part numbering
Table 20. Ordering information scheme
Example:
M24M01-D
R
MN 6
T
P /K
Device type
M24 = I2C serial access EEPROM
Device function
M01 = 1 Mbit (128 Kb × 8 bits)
Device family
Blank: Without Identification page
-D: With additional Identification page
Operating voltage
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
Package
MN = SO8 (150 mil width)(1)
DW = TSSOP8 (169 mil width)(1)
CS = standard WLCSP
CT = thin WLCSP
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P = ECOPACK® (RoHS compliant)
Process(2)
/A, /B or /K= Manufacturing technology code
1. RoHS-compliant and halogen-free (ECOPACK2®)
2. The process letter applies to WLCSP devices only.
For a list of available options (speed, package, etc.) or for further information on any aspect
of the devices, please contact your nearest ST sales office.
Doc ID 12943 Rev 9
37/41
Revision history
M24M01-R M24M01-DF
11
Revision history
Table 21. Document revision history
Date
Revision
Changes
07-Dec-2006
1
Initial release.
Document status promoted from Preliminary Data to full Datasheet.
Section 2.6: Supply voltage (VCC) updated.
Note 1 updated to latest standard revision below Table 5: Absolute
maximum ratings.
02-Oct-2007
2
VIL, VIH modified and, rise/fall time corrected in Test conditions in
Table 11: DC characteristics (M24M01-R and M24M01-HR).
Package values in inches calculated from mm and rounded to 4
decimal digits (note added below package mechanical data tables in
Section 7: Package mechanical data.
1 MHz maximum clock frequency added:
– Figure 6: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz
– Table 14: AC characteristics at 1 MHz (M24M01-HR) added.
tNS moved from Table 8: Input parameters to Table 13: AC
characteristics at 400 kHz (M24M01-R and M24M01-W). Note
removed below Table 8. In Table 13, tCH1CH2, tCL1CL2 and tDL1DL2
removed, tXH1XH2, tXL1XL2 added, tDL1DL2 max modified, notes
modified.
26-Nov-2007
3
Figure 5: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 400 kHz modified.
Figure 13: AC waveforms modified. Small text changes.
M24M01-HR root part number added. Small text changes.
Figure 6: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz modified.
Most significant address bits modified in Section 3.8: Page Write on
page 15.
18-Mar-2008
4
Test conditions modified for ILI, ICC and VOL in Table 11: DC
characteristics (M24M01-R and M24M01-HR).
TW and TNS values corrected in Table 13: AC characteristics at
400 kHz (M24M01-R and M24M01-W).
Cross-reference corrected in Note 5 below Table 14: AC
characteristics at 1 MHz (M24M01-HR).
38/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Table 21. Document revision history (continued)
Revision history
Date
Revision
Changes
Added: M24M01-W part number in device grade 3 temperature range
(see Table 8: Operating conditions (M24M01-W), Table 12: DC
characteristics (M24M01-W) and Table 17: Ordering information
scheme (M24M01-x products sold in packages)).
M24M01-R offered as a bare die (see Section 8: Part numbering and
Table 18: Ordering information scheme (M24M01-R sold as bare
dice)).
In Table 13: AC characteristics at 400 kHz (M24M01-R and M24M01-
W), Note 1 modified, Note 2 added, tXH1XH2, tXL1XL2 and tDL1DL2
values modified.
02-Sep-2008
5
In Table 14: AC characteristics at 1 MHz (M24M01-HR), Note 1
modified, Note 3 added, tXH1XH2, tXL1XL2 and tDL1DL2 values modified.
tCHDX, tDL1DL2 and tDXCX changed to tCHDL, tQL1QL2 and tDXCH
,
respectively (see Table 13, Table 14 and Figure 13).
Table 19: Available M24M01-x products (package, voltage range,
frequency, temperature grade) added.
Small text changes.
WLCSP8 package added (see Figure 3: WLCSP8 connections
(bumps side view) and Section 7: Package mechanical data).
Section 2.6: Supply voltage (VCC) updated.
12-Mar-2009
6
IOL added to Table 5: Absolute maximum ratings.
VRES added to Table 11: DC characteristics (M24M01-R and
M24M01-HR) and Table 12: DC characteristics (M24M01-W).
ECOPACK text updated.
Section : Features updated.
NC pin changed to DU in Figure 2: SO connections.
Device select code Chip enable address bits updated in Section 2.3.
Internal reset threshold modified in Section 2.6.3: Device reset.
Figure 6: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz updated.
VRES removed, and ICC1 conditions modified in Table 11: DC
characteristics (M24M01-R and M24M01-HR), and Table 12: DC
characteristics (M24M01-W). VRES removed from Table 12: DC
characteristics (M24M01-W).
26-Jun-2009
7
tXH1XH2 updated in Table 13: AC characteristics at 400 kHz (M24M01-
R and M24M01-W). tXH1XH2 updated, and Note 5 updated in Table 14:
AC characteristics at 1 MHz (M24M01-HR).
Command replaced by instruction in the whole document.
Doc ID 12943 Rev 9
39/41
Revision history
Table 21. Document revision history (continued)
M24M01-R M24M01-DF
Date
Revision
Changes
Updated Features on page 1.
Updated Figure 3: WLCSP8 connections (bumps side view), Figure 5:
Maximum Rbus value versus bus parasitic capacitance (Cbus) for an
I2C bus at maximum frequency fC = 400 kHz and Figure 6: Maximum
Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at
maximum frequency fC = 1MHz.
Updated Table 10: DC characteristics (M24M01-R and M24M01-HR).
02-May-2011
8
Updated footnote 5 of Table 14: AC characteristics at 1 MHz
(M24M01-HR).
Modified description of Write Control in Section 3.6: Write operations.
Replaced CL with Cbus in Table 7: AC measurement conditions.
Changed note 4 about tCLQV in Table 13: AC characteristics at
400 kHz (M24M01-R and M24M01-W).
Datasheet split into:
– M24M01-R, M24M01-DF (this datasheet) for standard products
(range 6),
23-Apr-2012
9
– M24M01-125 datasheet for automotive products (range 3).
40/41
Doc ID 12943 Rev 9
M24M01-R M24M01-DF
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
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GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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Doc ID 12943 Rev 9
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