M24M01-DF [STMICROELECTRONICS]
1 Mbit串行I2C总线EEPROM;
| 型号： | M24M01-DF |
| 厂家： | 
ST |
| 描述： | 1 Mbit串行I2C总线EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总30页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M24M01-R
1 Mbit serial I²C bus EEPROM
Features
2
■ Compatible with I C extended addressing
2
■ Two-wire I C serial interface
supports 1 MHz protocol
■ Single supply voltage:
– 1.8 V to 5.5 V
SO8 (MN)
150 mils width
■ Hardware write control
■ Byte and Page Write (up to 256 bytes)
■ Random and Sequential Read modes
■ Self-timed programming cycle
■ Automatic address incrementing
■ Enhanced ESD/Latch-Up protection
■ More than 1 million Write cycles
■ More than 40-year data retention
SO8 (MW)
208 mils width
■ Packages
– ECOPACK® (RoHS compliant)
November 2007
Rev 3
1/30
www.st.com
1
Contents
M24M01-R
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
2.6.2
2.6.3
2.6.4
Operating supply voltage V
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . . . 16
3.10 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
3.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/30
M24M01-R
Contents
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
6
7
8
9
3/30
List of tables
M24M01-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC characteristics at 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC characteristics at 1 MHz (preliminary data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO8W – 8 lead plastic small outline, 208 mils body width, package
Table 14.
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15.
Table 16.
4/30
M24M01-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Maximum R
value versus bus parasitic capacitance (C ) for an I C
bus
bus
bus at maximum frequency f = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
C
2
Figure 5.
Maximum R
value versus bus parasitic capacitance (C ) for an I C
bus bus
bus at maximum frequency f = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
C
2
Figure 6.
Figure 7.
Figure 8.
Figure 9.
I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 26
Figure 14. SO8W – 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 27
5/30
Description
M24M01-R
1
Description
2
The M24M01-R is an I C-compatible electrically erasable programmable memory
(EEPROM) device organized as 128 Kb × 8 bits.
2
The I C bus is a two-wire serial interface, comprising a bidirectional data line and a clock
line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with
2
the I C bus definition.
2
The M24M01-R behaves as a slave in the I C protocol, with all memory operations
synchronized by the serial clock. Read and Write operations are generated by the bus
master and initiated by a Start condition, followed by the device select code, address bytes
and data bytes. Data transfers are terminated by a Stop condition after an Ack for Write, and
after a NoAck for Read.
th
When writing data to the memory, the device inserts an acknowledge bit during the 9 bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way.
In order to meet environmental requirements, ST offers the M24M01-R in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
V
CC
2
E1-E2
SDA
M24M01-R
SCL
WC
V
SS
AI13415b
Table 1.
Signal names
Signal name
Function
Direction
E1, E2
SDA
SCL
WC
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
Input
I/O
Input
Input
VCC
VSS
6/30
M24M01-R
Description
Figure 2.
SO connections
M24M01-R
NC
E1
E2
1
2
3
4
8
7
6
5
V
CC
WC
SCL
SDA
V
SS
AI13416b
1. See Section 7: Package mechanical for package dimensions, and how to identify pin-1.
2. NC = Not Connected internally.
7/30
Signal description
M24M01-R
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to V . (Figure 5 indicates how the value of the pull-up resistor can be calculated). In
CC
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
2.3
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to V . (Figure 5 indicates how
CC
the value of the pull-up resistor can be calculated).
Chip Enable (E1, E2)
These input signals are used to set the value that is to be looked for on the two bits (b2, b1)
of the 7-bit device select code. These inputs must be tied to V or V , to establish the
CC
SS
device select code as shown in Figure 3. When not connected (left floating), these inputs
are read as low (0,0).
Figure 3.
Device select code
V
V
CC
CC
M24xxx
M24xxx
E
E
i
i
V
V
SS
SS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. When unconnected, the signal is internally read as V , and
IL
Write operations are allowed.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/30
M24M01-R
Signal description
2.5
VSS ground
V
is the reference for the V supply voltage.
CC
SS
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage V
CC
Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage
CC
within the specified [V (min), V (max)] range must be applied (see Table 7). In order to
CC
CC
secure a stable DC supply voltage, it is recommended to decouple the V line with a
CC
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the V /V package
CC SS
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (t ).
W
2.6.2
2.6.3
Power-up conditions
When the power supply is turned on, V rises from V to V . The V rise time must not
vary faster than 1 V/µs.
CC
SS
CC
CC
Device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of V ), the device does not respond to any
CC
instruction until V has reached the power on reset threshold voltage (this threshold is
CC
lower than the minimum V operating voltage defined in Table 7). When V passes over
CC
CC
the POR threshold, the device is reset and is in Standby Power mode.
In a similar way, during power-down (continuous decrease in V ), as soon as V drops
CC
CC
below the Power On Reset threshold voltage, the device stops responding to any instruction
sent to it.
2.6.4
Power-down conditions
During power-down (continuous decrease in V ), the device must be in the Standby Power
CC
mode (mode reached after decoding a Stop condition, assuming that is there is no internal
Write cycle in progress).
9/30
Signal description
M24M01-R
2
Figure 4.
Maximum R
value versus bus parasitic capacitance (C ) for an I C
bus
bus
bus at maximum frequency f = 400 kHz
C
100
10
1
f
= 400 kHz, t
= 1.3 µs
C
LOW
Rbus x Cbus time
constant must be less than
500 ns
V
CC
R
bus
SCL
SDA
I²C bus
master
M24xxx
C
bus
10
100
1000
Bus line capacitor (pF)
ai14796
2
Figure 5.
Maximum R
value versus bus parasitic capacitance (C ) for an I C
bus
bus
bus at maximum frequency f = 1MHz
C
V
100
CC
f
= 1 MHz, t
LOW
= 500 ns,
x C
C
time constant R
must be less than 150 ns
bus
bus
R
bus
SCL
SDA
I²C bus
master
10
M24xxx
f
= 1 MHz, t
LOW
= 700 ns,
x C
C
time constant R
must be less than 270 ns
bus
bus
C
bus
1
10
100
Bus line capacitor (pF)
ai14795
10/30
M24M01-R
Signal description
2
Figure 6.
I C bus protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 2.
Device select code
Device type identifier(1)
Chip Enable
address(2)
A16
RW
b7
1
b6
0
b5
1
b4
0
b3
b2
b1
b0
Device select code
E2
E1
A16
RW
1. The most significant bit, b7, is sent first.
2. E1 and E2 are compared against the respective external pins on the memory device.
Table 3.
Most significant address byte
b14 b13 b12
b15
b11
b3
b10
b2
b9
b1
b8
b0
Table 4.
Least significant address byte
b6 b5 b4
b7
11/30
Device operation
M24M01-R
3
Device operation
2
The device supports the I C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24M01-R device is always a slave in
all communication.
3.1
3.2
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal EEPROM Write cycle.
3.3
3.4
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
th
of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
12/30
M24M01-R
Device operation
3.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 2-bit Chip Enable
“Address” (E2, E1). To address the memory array, the 4-bit device type identifier is 1010b.
2
Up to four memory devices can be connected on a single I C bus. Each one is given a
unique 2-bit code on the Chip Enable (E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E1, E2) inputs.
th
The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
th
acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5.
Operating modes
Mode
RW bit WC(1) Bytes
Initial sequence
Current Address Read
Random Address Read
1
0
1
1
0
0
X
X
1
1
Start, device select, RW = 1
Start, device select, RW = 0, Address
reStart, device select, RW = 1
X
Sequential Read
Byte Write
X
≥ 1
Similar to Current or Random Address Read
Start, device select, RW = 0
VIL
VIL
1
Page Write
≤256 Start, device select, RW = 0
1. X = V or V .
IH
IL
13/30
Device operation
M24M01-R
Figure 7.
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
ACK
ACK
NO ACK
Byte Write
Dev sel
Byte addr
Byte addr
Data in
R/W
WC
ACK
ACK
ACK
NO ACK
Data in 2
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
R/W
WC (cont'd)
NO ACK
NO ACK
Page Write (cont'd)
Data in N
AI01120d
14/30
M24M01-R
Device operation
3.6
Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write
instruction with Write Control (WC) driven high (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 7.
Each data byte in the memory has a 17-bit address (the most significant bit b16 is in the
device select code and the Least Significant Bits b15-b0 are defined in two address bytes).
The most significant byte (Table 3) is sent first, followed by the least significant byte
(Table 4).
th
When the bus master generates a Stop condition immediately after the Ack bit (in the “10
bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay t , and the successful completion of a Write operation,
W
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
3.7
3.8
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 8.
Page Write
The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided
that they are all located in the same ’row’ in the memory: that is, the most significant
memory address bits, b15-b6, are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 6 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
15/30
Device operation
M24M01-R
Figure 8.
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
ACK
ACK
Byte Write
Dev sel
Byte addr
Byte addr
Data in
R/W
WC
ACK
ACK
ACK
ACK
Page Write
Dev sel
Byte addr
Byte addr
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
ACK
Page Write (cont'd)
Data in N
AI01106d
3.9
ECC (error correction code) and Write cycling
The M24M01-R device offers an ECC (error correction code) logic which compares each 4-
byte word with its six associated EEPROM ECC bits. As a result, if a single bit out of 4 bytes
of data happens to be erroneous during a Read operation, the ECC detects it and replaces
it by the correct value. The read reliability is therefore much improved by the use of this
feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC word), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by packets of 4 bytes in order to
benefit from the larger amount of Write cycles.
The M24M01-R device is qualified at 1 million (1 000 000) Write cycles, using a cycling
routine that writes to the device by multiples of 4-byte words.
16/30
M24M01-R
Device operation
Figure 9.
Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
ACK
returned
NO
First byte of instruction
YES
with RW = 0 already
decoded by the device
Next
Operation is
addressing the
memory
NO
YES
Send Address
and Receive ACK
ReStart
StartCondition
NO
YES
Stop
Data for the
Write cperation
Ddevice select
with RW = 1
Continue the
Continue the
Random Read operation
Write operation
AI01847d
17/30
Device operation
M24M01-R
3.10
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 11, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 9, is:
■
■
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
■
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Figure 10. Read mode sequences
ACK
NO ACK
Current
Address
Read
Dev sel
Data out
R/W
ACK
ACK
ACK
ACK
NO ACK
Random
Address
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out
R/W
R/W
ACK
ACK
ACK
NO ACK
Data out N
Sequential
Current
Read
Dev sel
Data out 1
R/W
ACK
ACK
ACK
ACK
R/W
ACK
Sequention
Random
Read
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out1
R/W
ACK
NO ACK
Data out N
AI01105d
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
18/30
M24M01-R
Device operation
3.11
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
3.12
3.13
3.14
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.15
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
th
during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
19/30
Initial delivery state
M24M01-R
4
Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TA
Ambient operating temperature
Storage temperature
–40
–65
130
150
°C
°C
°C
V
TSTG
TLEAD
VIO
Lead temperature during soldering
Input or output range
see note (1)
–0.50
VCC + 0.6
6.5
VCC
Supply voltage
–0.50
V
VESD
Electrostatic discharge voltage (Human Body model)(2) –3000
3000
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
20/30
M24M01-R
DC and AC parameters
6
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 7.
Symbol
Operating conditions
Parameter
Min.
Max.
Unit
VCC
TA
Supply voltage
1.8
5.5
85
V
Ambient operating temperature
–40
°C
Table 8.
Symbol
AC measurement conditions
Parameter
Min.
Max.
Unit
CL
Load capacitance
100
pF
ns
V
Input rise and fall times
Input levels
50
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and output timing reference levels
V
Figure 11. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
Table 9.
Symbol
Input parameters
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
CIN
ZL
Input capacitance (SDA)
8
6
pF
pF
kΩ
kΩ
Input capacitance (other pins)
VIN < 0.3 VCC
VIN > 0.7VCC
30
Input impedance (WC)
ZH
400
1. Sampled only, not 100% tested.
21/30
DC and AC parameters
M24M01-R
Table 10. DC characteristics
Test condition (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 7)
VIN = VSS or VCC
Input leakage current
(E1, E2, SCL, SDA)
ILI
± 2
± 2
0.8
µA
µA
device in Standby mode
ILO
Output leakage current
VOUT = VSS or VCC, SDA in Hi-Z
VCC = 1.8 V, fc= 400 kHz
(rise/fall time < 50 ns)
mA
VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns)
1
2
mA
mA
ICC
Supply current (Read)
VCC = 5.0 V, fc= 400 kHz
(rise/fall time < 50 ns)
1.8 V < VCC < 5.5 V, fc= 1 MHz
(rise/fall time < 50 ns)
2.5
5(1)
1
mA
mA
µA
ICC0
Supply current (Write)
Standby supply current
During tW, 1.8V < VCC < 5.5V
VIN = VSS or VCC
,
VCC = 1.8 V
VIN = VSS or VCC
,
ICC1
2
3
µA
VCC = 2.5 V
VIN = VSS or VCC
,
µA
V
VCC = 5.5 V
1.8 V ≤VCC < 2.5 V
2.5 V ≤VCC ≤5.5 V
–0.45
–0.45
0.25 VCC
0.3 VCC
VCC+1
VCC+1
0.2
Input low voltage
(SCL, SDA, WC)
VIL
VIH
1.8 V ≤VCC < 2.5 V
2.5 V ≤VCC ≤5.5 V
0.75VCC
0.7VCC
V
Input high voltage
(SCL, SDA, WC)
I
OL = 0.7 mA, VCC = 1.8 V
V
V
V
VOL
Output low voltage
IOL = 2.1 mA, VCC = 2.5 V
OL = 3.0 mA, VCC = 5.5 V
0.4
I
0.4
1. Characterized value, not tested in production.
22/30
M24M01-R
DC and AC parameters
Table 11. AC characteristics at 400 kHz
Test conditions specified in Table 7
Symbol
Alt.
Parameter
Min.
Max.
Unit
fC
fSCL
tHIGH
tLOW
tR
Clock frequency
400
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
600
1300
20
(1)
tXH1XH2
300
300
100
(1)
tXL1XL2
tDL1DL2
tDXCX
tF
20
tF
20
tSU:DAT Data in set up time
tHD:DAT Data in hold time
100
0
tCLDX
tCLQX
tDH
tAA
Data out hold time
200
200
600
600
600
(2)(3)
tCLQV
tCHDX
tDLCL
tCHDH
Clock low to next data valid (access time)
900
(4)
tSU:STA Start condition set up time
tHD:STA Start condition hold time
tSU:STO Stop condition set up time
Time between Stop condition and next Start
condition
tDHDL
tW
tBUF
1300
ns
Pulse width ignored (input filter on SCL and
SDA)
100
5
ns
(5)
tNS
tWR
Write time 1.8 V < VCC < 5.5 V
ms
1. Values recommended by the I²C-bus Fast-Mode specification.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a
compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus
× Cbus time constant is less than 500 ns (as specified in Figure 4).
4. For a reStart condition, or following a Write cycle.
5. Characterized only, not tested in production.
23/30
DC and AC parameters
Table 12.
M24M01-R
AC characteristics at 1 MHz (preliminary data)
Test conditions specified in Table 7
Symbol
Alt.
fSCL
Parameter
Clock frequency
Min.
Max.
Unit
fC
0
1
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHCL
tCLCH
tHIGH
tLOW
tR
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
300
400
20
-
(1)
tXH1XH2
300
(1)
tXL1XL2
tF
20
300
(2)
tDL1DL2
tF
20
100
tDXCX
tCLDX
tCLQX
tSU:DAT Data in setup time
tHD:DAT Data in hold time
80
-
0
-
tDH
tAA
Data out hold time
50
-
(3)(4)
tCLQV
Clock low to next data valid (access time)
50
500
(5)
tCHDX
tSU:STA Start condition setup time
tHD:STA Start condition hold time
tSU:STO Stop condition setup time
250
250
250
-
-
-
tDLCL
tCHDH
Time between Stop condition and next
Start condition
tDHDL
tW
tBUF
tWR
500
-
ns
ms
ns
Write time
-
-
5
Pulse width ignored (input filter on SCL
and SDA)
(2)
tNS
50
1. Values recommended by the I²C-bus Fast-Mode specification.
2. Characterized only, not tested in production.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC, assuming
that the Rbus × Cbus time constant is less than 150 ns (as specified in Figure 4).
5. For a reStart condition, or following a Write cycle.
24/30
M24M01-R
DC and AC parameters
Figure 12. AC waveforms
tXL1XL2
tXH1XH2
tCHCL
tCLCH
SCL
tDLCL
tXL1XL2
SDA In
tCHDX
Start
condition
tCLDX
tDXCX
SDA
Change
tXH1XH2
tCHDH tDHDL
Start
SDA
Input
Stop
condition
condition
SCL
SDA In
tW
Write cycle
tCHDH
tCHDX
Stop
condition
Start
condition
tCHCL
SCL
tCLQV
tCLQX
Data valid
tDL1DL2
Data valid
SDA Out
AI00795e
25/30
Package mechanical
M24M01-R
7
Package mechanical
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
1.75
0.25
0.0689
0.0098
0.1
0.0039
0.0492
0.011
1.25
0.28
0.17
0.48
0.23
0.1
5
0.0189
0.0091
0.0039
0.1969
0.2441
0.1575
-
c
0.0067
ccc
D
4.9
6
4.8
5.8
3.8
-
0.1929
0.2362
0.1535
0.05
0.189
0.2283
0.1496
-
E
6.2
4
E1
e
3.9
1.27
-
h
0.25
0°
0.5
8°
0.0098
0°
0.0197
8°
k
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
26/30
M24M01-R
Package mechanical
Figure 14. SO8W – 8 lead plastic small outline, 208 mils body width, package outline
A2
A
c
b
CP
e
D
N
1
E E1
A1
k
L
6L_ME
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1 and the ‘N’ indicates the total
number of pins.
Table 14. SO8W – 8 lead plastic small outline, 208 mils body width, package
mechanical data
millimeters
Min
inches(1)
Symbol
Typ
Max
Typ
Min
Max
A
A1
A2
b
2.5
0.25
2
0.0984
0.0098
0.0787
0.0201
0.0138
0.0039
0.2382
0.2449
0.35
0
0
1.51
0.35
0.1
0.0594
0.0138
0.0039
0.4
0.2
0.51
0.35
0.1
0.0157
0.0079
c
CP
D
6.05
6.22
8.89
-
E
5.02
7.62
-
0.1976
E1
e
0.3
1.27
0.05
-
0°
-
k
0°
10°
0.8
10°
L
0.5
8
0.0197
8
0.0315
N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
27/30
Part numbering
M24M01-R
8
Part numbering
Table 15. Ordering information scheme
Example:
M24M01
–
H R MN 6
T
P
Device type
M24 = I2C serial access EEPROM
Device function
M01 = 1 Mbit (256 Kb × 8 bits)
Clock frequency
Blank: fC max = 400 kHz
H: fC max = 1 MHz
Operating voltage
R = VCC = 1.8 V to 5.5 V
Package
MN = SO8 (150 mils width)
MW = SO8 (208 mils width)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
The category of second-level interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
28/30
M24M01-R
Revision history
9
Revision history
Table 16. Document revision history
Date
Revision
Changes
07-Dec-2006
1
Initial release.
Document status promoted from Preliminary Data to full Datasheet.
Section 2.6: Supply voltage (VCC) updated.
Note 1 updated to latest standard revision below Table 6: Absolute
maximum ratings.
02-Oct-2007
2
VIL, VIH modified and, rise/fall time corrected in Test conditions in
Table 10: DC characteristics.
Package values in inches calculated from mm and rounded to 4
decimal digits (note added below package mechanical data tables in
Section 7: Package mechanical.
1 MHz maximum clock frequency added:
– Figure 5: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 1MHz
– Table 12: AC characteristics at 1 MHz (preliminary data) added.
tNS moved from Table 9: Input parameters to Table 11: AC
characteristics at 400 kHz. Note removed below Table 9. In Table 11,
tCH1CH2, tCL1CL2 and tDL1DL2 removed, tXH1XH2, tXL1XL2 added,
tDL1DL2 max modified, notes modified.
26-Nov-2007
3
Figure 4: Maximum Rbus value versus bus parasitic capacitance
(Cbus) for an I2C bus at maximum frequency fC = 400 kHz modified.
Figure 12: AC waveforms modified. Small text changes.
29/30
M24M01-R
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