M25P20-VMN1TP/X_技术文档

M25P20

2 Mbit, low voltage, Serial Flash memory

with 50MHz SPI bus interface

Feature summary

■ 2 Mbit of Flash Memory

■ Page Program (up to 256 Bytes) in 1.4ms

(typical)

■ Sector Erase (512 Kbit) in 1s (typical)

■ Bulk Erase (2 Mbit) in 3s (typical)

■ 2.7 to 3.6V Single Supply Voltage

■ SPI Bus Compatible Serial Interface

■ 50MHz Clock Rate (maximum)

■ Deep Power-down Mode 1µA (typical)

■ Electronic Signatures

SO8 (MN)

150 mil width

– JEDEC Standard two-Byte Signature

(2012h)

VFQFPN8 (MP)

(MLP8)

– RES Instruction, One-Byte, Signature

(11h), for backward compatibility

■ Packages

– ECOPACK® (RoHS compliant)

June 2006

Rev 10

1/50

www.st.com

1

Contents

M25P20

Contents

1

2

Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

2.5

2.6

Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3

4

SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . 11

Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . 11

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5

6

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1

6.2

6.3

6.4

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4.1

6.4.2

6.4.3

6.4.4

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.5

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/50

M25P20

Contents

6.6

6.7

6.8

6.9

Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 25

Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 31

7

Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8

9

10

11

12

13

3/50

List of tables

M25P20

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DC Characteristics (Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DC Characteristics (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Instruction Times (Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Instruction Times (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AC Characteristics (25MHz Operation, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . 40

AC Characteristics (40MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 41

AC Characteristics (50MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

Table 22.

6x5mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 23.

Table 24.

4/50

M25P20

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SO and VFQFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Bus Master and memory devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . 19

Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . . . 21

Figure 11. Write Status Register (WRSR) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 24

Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence

and Data-Out Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 15. Sector Erase (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 16. Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 17. Deep Power-down (DP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction

Sequence and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19. Release from Deep Power-down (RES) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . 32

Figure 20. Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 21. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 22. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1. . . . . . . . . . . . . . . . . 43

Figure 24. Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 25. Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . . . 45

Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6x5mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5/50

Summary description

M25P20

1

Summary description

The M25P20 is a 2 Mbit (256K x 8) Serial Flash Memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program

instruction.

The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144

bytes.

The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,

using the Sector Erase instruction.

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages.

ECOPACK® packages are Lead-free and RoHS compliant.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 1.

Logic Diagram

V

CC

D

C

S

Q

M25P20

W

HOLD

V

SS

AI04080

Figure 2.

SO and VFQFPN Connections

M25P20

S

Q

1

8

V

CC

HOLD

2

3

4

7

W

6

5

C

D

V

SS

AI04081B

1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to V_SS

and must not be allowed to be connected to any other voltage or signal line on the PCB.

,

2. See Package mechanical section for package dimensions, and how to identify pin-1.

6/50

M25P20

Summary description

Table 1.

Signal Names

Serial Clock

C

D

Serial Data Input

Serial Data Output

Chip Select

Write Protect

Hold

Q

S

W

HOLD

V_CC

V_SS

Supply Voltage

Ground

7/50

Signal description

M25P20

2

Signal description

2.1

Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (C).

2.2

2.3

2.4

Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

Chip Select (S)

When this input signal is High, the device is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,

the device will be in the Standby mode (this is not the Deep Power-down mode). Driving

Chip Select (S) Low selects the device, placing it in the Active Power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

2.5

2.6

Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is

protected against program or erase instructions (as specified by the values in the BP1 and

BP0 bits of the Status Register).

8/50

M25P20

SPI modes

3

SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two following modes:

■

CPOL=0, CPHA=0

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

■

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

Figure 3.

Bus Master and memory devices on the SPI Bus

V_SS

V_CC

R⁽²⁾

SDO

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SDI

SCK

V_CC

C

Q

D

C

Q

D

C Q D

V_SS

SPI Bus Master

R⁽²⁾

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

CS3 CS2 CS1

S

W

HOLD

W

HOLD

W

AI12836

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-

impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time

(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all

inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become

High at the same time, and so, that the t_SHCHrequirement is met).

9/50

SPI modes

M25P20

Figure 4.

SPI modes supported

CPOL CPHA

C

0

1

0

1

C

D

MSB

Q

MSB

AI01438B

10/50

M25P20

Operating features

4

Operating features

4.1

Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one

byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is

followed by the internal Program cycle (of duration t ).

PP

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few Bytes (see Page Program (PP),

Instruction Times (Device Grade 6) and Table 16: Instruction Times (Device Grade 3)).

4.2

Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be

achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the

entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of

duration t or t ).

SE

BE

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

4.3

4.4

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase

(SE or BE) can be achieved by not waiting for the worst case delay (t , t , t , or t ). The

W

PP SE

BE

Write In Progress (WIP) bit is provided in the Status Register so that the application program

can monitor its value, polling it to establish when the previous Write cycle, Program cycle or

Erase cycle is complete.

Active Power, Standby Power and Deep Power-Down Modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode.

When Chip Select (S) is High, the device is deselected, but could remain in the Active Power

mode until all internal cycles have completed (Program, Erase, Write Status Register). The

device then goes in to the Standby Power mode. The device consumption drops to I

.

CC1

The Deep Power-down mode is entered when the specific instruction (the Deep Power-

down (DP) instruction) is executed. The device consumption drops further to I . The

CC2

device remains in this mode until another specific instruction (the Release from Deep

Power-down and Read Electronic Signature (RES) instruction) is executed.

All other instructions are ignored while the device is in the Deep Power-down mode. This

can be used as an extra software protection mechanism, when the device is not in active

use, to protect the device from inadvertent Write, Program or Erase instructions.

11/50

Operating features

M25P20

4.5

Status Register

The Status Register contains a number of status and control bits, as shown in Table 6, that

can be read or set (as appropriate) by specific instructions. For a detailed description of the

Status Register bits, see Section 6.4: Read Status Register (RDSR).

4.6

Protection Modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M25P20 features the following data protection mechanisms:

■

Power On Reset and an internal timer (t

) can provide protection against inadvertant

PUW

changes while the power supply is outside the operating specification.

■

Program, Erase and Write Status Register instructions are checked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for

execution.

■

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Page Program (PP) instruction completion

Sector Erase (SE) instruction completion

Bulk Erase (BE) instruction completion

■

The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-

only. This is the Software Protected Mode (SPM).

The Write Protect (W) signal, in co-operation with the Status Register Write Disable

(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable

(SRWD) bit to be write-protected. This is the Hardware Protected Mode (HPM).

■

In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection from inadvertant Write, Program and Erase instructions, as all

instructions are ignored except one particular instruction (the Release from Deep

Power-down instruction).

12/50

M25P20

Operating features

Table 2.

Protected Area Sizes

Status Register

Content

Memory Content

BP1 Bit BP0 Bit

Protected Area

Unprotected Area

0

1

none

All sectors⁽¹⁾(four sectors: 0, 1, 2 and 3)

Lower three-quarters (three sectors: 0

to 2)

Upper quarter (Sector 3)

1

0

1

Upper half (two sectors: 2 and 3)

Lower half (Sectors 0 and 1)

All sectors (four sectors: 0, 1, 2 and 3) none

1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.

4.7

Hold Condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence. However, taking this signal Low does not terminate any

Write Status Register, Program or Erase cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (S) Low.

The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low (as shown in Figure 5).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes

Low. (This is shown in Figure 5).

During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration

of the Hold condition. This is to ensure that the state of the internal logic remains unchanged

from the moment of entering the Hold condition.

If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the Hold condition.

13/50

Operating features

Figure 5.

M25P20

Hold Condition Activation

C

HOLD

Hold

Condition

(standard use)

(non-standard use)

AI02029D

14/50

M25P20

Memory organization

5

Memory organization

The memory is organized as:

■

262,144 bytes (8 bits each)

4 sectors (512 Kbits, 65536 bytes each)

1024 pages (256 bytes each).

Each page can be individually programmed (bits are programmed from 1 to 0). The device is

Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.

Table 3.

Memory Organization

Sector

Address Range

3

2

1

0

30000h

20000h

10000h

00000h

3FFFFh

2FFFFh

1FFFFh

0FFFFh

Figure 6.

Block Diagram

HOLD

W

High Voltage

Generator

Control Logic

S

C

D

Q

I/O Shift Register

Status

Register

Address Register

and Counter

256 Byte

Data Buffer

3FFFFh

30000h

Size of the

read-only

memory area

20000h

10000h

00000h

000FFh

256 Bytes (Page Size)

X Decoder

AI04079

15/50

Instructions

M25P20

6

Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select

(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most

significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 4.

Every instruction sequence starts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data bytes, or by both or none.

Chip Select (S) must be driven High after the last bit of the instruction sequence has been

shifted in.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),

Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power-

down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence

is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the

data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status

Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)

instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the

instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when

the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of

eight.

All attempts to access the memory array during a Write Status Register cycle, Program

cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program

cycle or Erase cycle continues unaffected.

16/50

M25P20

Instructions

Table 4.

Instruction Set

Description

One-byte Instruction Address Dummy Data

Instruction

Code

Bytes

WREN

WRDI

Write Enable

0000 0110

0000 0100

1001 1111

0000 0101

0000 0001

0000 0011

06h

04h

9Fh

05h

01h

03h

0

3

0

Write Disable

0

RDID⁽¹⁾

RDSR

WRSR

READ

Read Identification

Read Status Register

Write Status Register

Read Data Bytes

1 to 3

1 to ∞

1

1 to ∞

Read Data Bytes at Higher

Speed

FAST_READ

0000 1011

0Bh

3

1

1 to ∞

PP

SE

BE

DP

Page Program

Sector Erase

Bulk Erase

0000 0010

1101 1000

1100 0111

1011 1001

02h

D8h

C7h

B9h

3

0

1 to 256

0

Deep Power-down

Release from Deep Power-

down, and Read Electronic

Signature

0

3

0

1 to ∞

RES

1010 1011

ABh

Release from Deep Power-

down

0

1. The Read Identification (RDID) instruction is available only in products with Process Technology code X

(see Application Note AN1995).

6.1

Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector

Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figure 7.

Write Enable (WREN) Instruction Sequence

S

0

1

2

3

4

5

6

7

C

D

Q

Instruction

High Impedance

AI02281E

17/50

Instructions

M25P20

6.2

Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

■

Power-up

■

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Page Program (PP) instruction completion

Sector Erase (SE) instruction completion

Bulk Erase (BE) instruction completion

Figure 8.

Write Disable (WRDI) Instruction Sequence

S

0

1

2

3

4

5

6

7

C

D

Q

Instruction

High Impedance

AI03750D

18/50

M25P20

Instructions

6.3

Read Identification (RDID)

The Read Identification (RDID) instruction is available in products with Process Technology

code X only.

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be

read, followed by two bytes of device identification. The manufacturer identification is

assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification

is assigned by the device manufacturer, and indicates the memory type in the first byte

(20h), and the memory capacity of the device in the second byte (12h).

Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is

not decoded, and has no effect on the cycle that is in progress.

The Read Identification (RDID) instruction should not be issued while the device is in Deep

Power-down mode.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. This is followed by the 24-bit device identification, stored in

the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during

the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 9.

The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the Stand-by Power mode. Once in

the Stand-by Power mode, the device waits to be selected, so that it can receive, decode

and execute instructions.

Table 5.

Read Identification (RDID) Data-Out Sequence

Device Identification

Manufacturer Identification

Memory Type

Memory Capacity

20h

12h

Figure 9.

Read Identification (RDID) Instruction Sequence and Data-Out Sequence

S

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

28 29 30 31

C

D

Instruction

Manufacturer Identification

Device Identification

High Impedance

Q

15 14 13

MSB

3

2

1

0

MSB

AI06809b

19/50

Instructions

M25P20

6.4

Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write Status

Register cycle is in progress. When one of these cycles is in progress, it is recommended to

check the Write In Progress (WIP) bit before sending a new instruction to the device. It is

also possible to read the Status Register continuously, as shown in Figure 10.

Table 6.

Status Register Format

b7

b0

SRWD

0

BP1

BP0

WEL

WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

The status and control bits of the Status Register are as follows:

6.4.1

6.4.2

6.4.3

WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to

0 no such cycle is in progress.

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable

Latch is reset and no Write Status Register, Program or Erase instruction is accepted.

BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Program and Erase instructions. These bits are written with the

Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1,

BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected

against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1,

BP0) bits can be written provided that the Hardware Protected mode has not been set. The

Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are

0.

6.4.4

SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware Protected mode (when the Status Register

Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the

non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the

Write Status Register (WRSR) instruction is no longer accepted for execution.

20/50

M25P20

Instructions

Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out

Sequence

S

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

C

D

Instruction

Status Register Out

High Impedance

Q

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

AI02031E

21/50

Instructions

M25P20

6.5

Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

Register. Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN) instruction has been decoded and

executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 11.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the

Status Register. b6, b5 and b4 are always read as 0.

Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.

If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed Write Status Register cycle (whose duration is t ) is

W

initiated. While the Write Status Register cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)

bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the

Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-

only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the

user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the

Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect

(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write

Status Register (WRSR) instruction is not executed once the Hardware Protected Mode

(HPM) is entered.

Figure 11. Write Status Register (WRSR) Instruction Sequence

S

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

C

Instruction

Status

Register In

7

6

5

4

3

2

0

1

D

Q

High Impedance

MSB

AI02282D

22/50

M25P20

Instructions

Table 7.

Protection Modes

Memory Content

W

Signal

SRWD

Bit

Write Protection of the

Mode

Unprotected

Status Register

Protected Area⁽¹⁾

Area⁽¹⁾

1

0

Status Register is Writable

(if the WREN instruction

has set the WEL bit)

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program and

Sector Erase

Software

Protected

(SPM)

The values in the SRWD,

BP1 and BP0 bits can be

changed

instructions

1

Status Register is

Hardware write protected

Protected against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept

Page Program and

Sector Erase

Hardware

Protected

(HPM)

0

1

The values in the SRWD,

BP1 and BP0 bits cannot

be changed

instructions

1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.

The protection features of the device are summarized in Table 7.

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect (W) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

■

If Write Protect (W) is driven High, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

■

If Write Protect (W) is driven Low, it is not possible to write to the Status Register even

if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)

instruction. (Attempts to write to the Status Register are rejected, and are not accepted

for execution). As a consequence, all the data bytes in the memory area that are

software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register,

are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be

entered:

■

by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

Low

■

or by driving Write Protect (W) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can

never be activated, and only the Software Protected Mode (SPM), using the Block Protect

(BP1, BP0) bits of the Status Register, can be used.

23/50

Instructions

M25P20

6.6

Read Data Bytes (READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum

frequency f , during the falling edge of Serial Clock (C).

R

The instruction sequence is shown in Figure 12.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

C

Instruction

24-Bit Address

23 22 21

MSB

3

2

1

0

D

Q

Data Out 1

High Impedance

2

7

6

5

4

3

1

7

0

MSB

AI03748D

1. Address bits A23 to A18 are Don’t Care.

24/50

M25P20

Instructions

6.7

Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read

Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each

bit being shifted out, at a maximum frequency f , during the falling edge of Serial Clock (C).

C

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)

instruction. When the highest address is reached, the address counter rolls over to

000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any

Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.

Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence

and Data-Out Sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

C

Instruction

24 BIT ADDRESS

23 22 21

3

2

1

0

D

Q

S

C

High Impedance

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Dummy Byte

7

6

5

4

3

2

0

1

D

Q

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

MSB

AI04006

1. Address bits A23 to A18 are Don’t Care.

25/50

Instructions

M25P20

6.8

Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable (WREN) instruction has been

decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, three address bytes and at least one data byte on Serial Data Input (D).

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes

beyond the end of the current page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 data bytes are guaranteed to be programmed correctly within the same page. If less

than 256 Data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few Bytes (see Instruction Times

(Device Grade 6) and Table 16: Instruction Times (Device Grade 3)).

Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is t ) is initiated. While the Page Program cycle is in progress, the Status Register

PP

may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is

reset.

A Page Program (PP) instruction applied to a page which is protected by the Block Protect

(BP1, BP0) bits (see Table 3 and Table 2) is not executed.

26/50

M25P20

Instructions

Figure 14. Page Program (PP) Instruction Sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

C

D

Instruction

24-Bit Address

Data Byte 1

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

MSB

S

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

C

D

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

MSB

AI04082B

1. Address bits A23 to A18 are Don’t Care.

27/50

Instructions

M25P20

6.9

Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write

Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data Input (D). Any address inside the

Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is t ) is

SE

initiated. While the Sector Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified

time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect

(BP1, BP0) bits (see Table 3 and Table 2) is not executed.

Figure 15. Sector Erase (SE) Instruction Sequence

S

0

1

2

3

4

5

6

7

8

9

29 30 31

C

D

Instruction

24 Bit Address

23 22

MSB

2

0

1

AI03751D

1. Address bits A23 to A18 are Don’t Care.

28/50

M25P20

Instructions

6.10

Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write

Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)

is driven High, the self-timed Bulk Erase cycle (whose duration is t ) is initiated. While the

BE

Bulk Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk

Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0.

The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.

Figure 16. Bulk Erase (BE) Instruction Sequence

S

0

1

2

3

4

5

6

7

C

D

Instruction

AI03752D

29/50

Instructions

M25P20

6.11

Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the Deep Power-down mode). It can also be used as an extra

software protection mechanism, while the device is not in active use, since in this mode, the

device ignores all Write, Program and Erase instructions.

Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode

(if there is no internal cycle currently in progress). But this mode is not the Deep Power-

down mode. The Deep Power-down mode can only be entered by executing the Deep

Power-down (DP) instruction, subsequently reducing the standby current (from I

to I

,

CC1

CC2

as specified in Table 13).

Once the device has entered the Deep Power-down mode, all instructions are ignored

except the Release from Deep Power-down and Read Electronic Signature (RES)

instruction. This releases the device from this mode.

The Release from Deep Power-down and Read Electronic Signature (RES) instruction and

the Read Identification (RDID) instruction also allow the Electronic Signature of the device to

be output on Serial Data Output (Q).

The Deep Power-down mode automatically stops at Power-down, and the device always

Powers-up in the Standby mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of t before the supply current is reduced

DP

to I

and the Deep Power-down mode is entered.

CC2

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Deep Power-down (DP) Instruction Sequence

S

t_DP

0

1

2

3

4

5

6

7

C

D

Instruction

Stand-by Mode

Deep Power-down Mode

AI03753D

30/50

M25P20

Instructions

6.12

Release from Deep Power-down and Read Electronic

Signature (RES)

Once the device has entered the Deep Power-down mode, all instructions are ignored

except the Release from Deep Power-down and Read Electronic Signature (RES)

instruction. Executing this instruction takes the device out of the Deep Power-down mode.

The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic

Signature, whose value for the M25P20 is 11h.

Except while an Erase, Program or Write Status Register cycle is in progress, the Release

from Deep Power-down and Read Electronic Signature (RES) instruction always provides

access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep

Power-down mode has not been entered.

Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while

an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no

effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. The instruction code is followed

by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge

of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out

on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock

(C).

The instruction sequence is shown in Figure 18.

The Release from Deep Power-down and Read Electronic Signature (RES) instruction is

terminated by driving Chip Select (S) High after the Electronic Signature has been read at

least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is

driven Low, cause the Electronic Signature to be output repeatedly.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the

device was not previously in the Deep Power-down mode, the transition to the Standby

Power mode is immediate. If the device was previously in the Deep Power-down mode,

though, the transition to the Standby Power mode is delayed by t

, and Chip Select (S)

RES2

must remain High for at least t

(max), as specified in Table 18. Once in the Standby

RES2

Power mode, the device waits to be selected, so that it can receive, decode and execute

instructions.

31/50

Instructions

M25P20

Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction

Sequence and Data-Out Sequence

S

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

C

t_RES2

Instruction

3 Dummy Bytes

23 22 21

MSB

3

2

1

0

D

Q

Electronic Signature Out

High Impedance

7

6

5

4

3

2

0

1

MSB

Deep Power-down Mode

Stand-by Mode

AI04047C

1. The value of the 8-bit Electronic Signature, for the M25P20, is 11h.

Figure 19. Release from Deep Power-down (RES) Instruction Sequence

S

t_RES1

0

1

2

3

4

5

6

7

C

D

Instruction

High Impedance

Q

Deep Power-down Mode

Stand-by Mode

AI04078B

Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,

but before the whole of the 8-bit Electronic Signature has been transmitted for the first time

(as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the

device was not previously in the Deep Power-down mode, the transition to the Standby

Power mode is immediate. If the device was previously in the Deep Power-down mode,

though, the transition to the Standby Power mode is delayed by t

, and Chip Select (S)

RES1

must remain High for at least t

(max), as specified in Table 18. Once in the Standby

RES1

Power mode, the device waits to be selected, so that it can receive, decode and execute

instructions.

32/50

M25P20

Power-up and Power-down

7

Power-up and Power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on V ) until V reaches the correct value:

CC

■

V

(min) at Power-up, and then for a further delay of t

at Power-down

CC

SS

VSL

Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper

Power-up and Power-down.

To avoid data corruption and inadvertent write operations during power up, a Power On

Reset (POR) circuit is included. The logic inside the device is held reset while V is less

CC

than the Power On Reset (POR) threshold voltage, V – all operations are disabled, and

WI

the device does not respond to any instruction.

Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of

t

has elapsed after the moment that V rises above the V threshold. However, the

PUW

CC WI

correct operation of the device is not guaranteed if, by this time, V is still below V (min).

CC

No Write Status Register, Program or Erase instructions should be sent until the later of:

■

t

after V passed the V threshold

CC WI

PUW

VSL

after V passed the V (min) level

CC

These values are specified in Table 8.

If the delay, t

, has elapsed, after V has risen above V (min), the device can be

VSL

CC

selected for READ instructions even if the t

delay is not yet fully elapsed.

PUW

At Power-up, the device is in the following state:

■

The device is in the Standby mode (not the Deep Power-down mode).

The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the V supply.

CC

Each device in a system should have the V rail decoupled by a suitable capacitor close to

CC

the package pins. (Generally, this capacitor is of the order of 0.1µF).

At Power-down, when V drops from the operating voltage, to below the Power On Reset

CC

(POR) threshold voltage, V , all operations are disabled and the device does not respond

WI

to any instruction. (The designer needs to be aware that if a Power-down occurs while a

Write, Program or Erase cycle is in progress, some data corruption can result.)

33/50

Power-up and Power-down

M25P20

Figure 20. Power-up Timing

V

CC

V

(max)

CC

Program, Erase and Write Commands are Rejected by the Device

Chip Selection Not Allowed

V

(min)

CC

tVSL

Read Access allowed

Device fully

accessible

Reset State

of the

Device

V

WI

tPUW

time

AI04009C

Table 8.

Symbol

Power-Up Timing and V Threshold

WI

Parameter

Min.

Max.

Unit

(1)

t_VSL

V_CC(min) to S low

10

1

µs

ms

V

(1)

t_PUW

Time delay to Write instruction

Write Inhibit Voltage (Device grade 6)

Write Inhibit Voltage (Device grade 3)

10

2

1

(1)

V_WI

1

2.2

V

1. These parameters are characterized only.

34/50

M25P20

Initial delivery state

8

Initial delivery state

The device is delivered with the memory array erased: all bits are set to 1 (each byte

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

9

Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings" table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 9.

Symbol

Absolute Maximum Ratings

Parameter

Min.

Max.

Unit

T_STG

V_IO

Storage Temperature

–65

–0.6

150

4.0

°C

V

Input and Output Voltage (with respect to Ground)

V_CC

V_ESD

Supply Voltage

–0.6

4.0

V

Electrostatic Discharge Voltage (Human Body model) ⁽¹⁾

–2000

2000

V

1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω).

35/50

DC and AC parameters

M25P20

10

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC Characteristic tables that

follow are derived from tests performed under the Measurement Conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

Table 10. Operating Conditions

Symbol

Parameter

Min.

Max.

Unit

V_CC

Supply Voltage

2.7

–40

3.6

85

V

Ambient Operating Temperature (Device Grade 6)

Ambient Operating Temperature (Device Grade 3)

T_A

°C

125

Table 11. Data Retention and Endurance

Parameter

Condition

Device Grade 6

Min.

Max.

Unit

100,000

10,000

20

Erase/Program

Cycles

cycles per

sector

Device Grade 3

at 55°C

Data Retention

years

Table 12. Capacitance

Symbol

Parameter

Test Condition

Min.

Max.

Unit

C_OUT

C_IN

Output Capacitance (Q)

V_OUT= 0V

V_IN= 0V

8

6

pF

Input Capacitance (other pins)

1. Sampled only, not 100% tested, at T_A=25°C and a frequency of 20MHz.

36/50

M25P20

DC and AC parameters

Table 13. DC Characteristics (Device Grade 6)

Test Condition (in addition to

Symbol

Parameter

Min.

Max.

Unit

those in Table 10)

I_LI

Input Leakage Current

Output Leakage Current

Standby Current

± 2

50

5

µA

I_LO

I_CC1

I_CC2

S = V_CC, V_IN= V_SSor V_CC

Deep Power-down Current

C = 0.1V_CC/ 0.9.V_CCat

40MHz and 50MHz, Q = open

8

4

mA

I_CC3

Operating Current (READ)

C = 0.1V_CC/ 0.9.V_CCat

20MHz, Q = open

I_CC4

I_CC5

I_CC6

I_CC7

V_IL

Operating Current (PP)

Operating Current (WRSR)

Operating Current (SE)

Operating Current (BE)

Input Low Voltage

S = V_CC

15

mA

V

15

– 0.5

0.3V_CC

V_IH

Input High Voltage

0.7V_CCV_CC+0.4

0.4

V

V_OL

V_OH

Output Low Voltage

I_OL= 1.6 mA

V

Output High Voltage

I_OH= –100 µA

V_CC–0.2

V

37/50

DC and AC parameters

M25P20

Table 14. DC Characteristics (Device Grade 3)

Test Condition (in addition to

Symbol

Parameter

Min.⁽¹⁾Max.⁽¹⁾Unit

those in Table 10)

I_LI

Input Leakage Current

Output Leakage Current

Standby Current

± 2

100

50

µA

I_LO

I_CC1

I_CC2

S = V_CC, V_IN= V_SSor V_CC

Deep Power-down Current

C = 0.1V_CC/ 0.9.V_CCat 25MHz,

Q = open

8

4

mA

I_CC3

Operating Current (READ)

C = 0.1V_CC/ 0.9.V_CCat 20MHz,

Q = open

I_CC4

I_CC5

I_CC6

I_CC7

V_IL

Operating Current (PP)

Operating Current (WRSR)

Operating Current (SE)

Operating Current (BE)

Input Low Voltage

S = V_CC

15

mA

V

15

– 0.5

0.3V_CC

V_IH

Input High Voltage

0.7V_CCV_CC+0.4

0.4

V

V_OL

Output Low Voltage

I_OL= 1.6 mA

V

V_CC

0.2

–

V_OH

Output High Voltage

I_OH= –100 µA

V

2. This is preliminary data

Table 15. Instruction Times (Device Grade 6)

Test conditions specified in Table 10 and Table 17

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

t_W

Write Status Register Cycle Time

5

15

ms

Page Program Cycle Time (256 Bytes)

1.4

(1)

t_PP

5

ms

0.4+

n*1/256

Page Program Cycle Time (n Bytes)

t_SE

t_BE

Sector Erase Cycle Time

Bulk Erase Cycle Time

0.8

2.5

3

6

s

1. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are

obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤

256)

38/50

M25P20

DC and AC parameters

Table 16. Instruction Times (Device Grade 3)

Test conditions specified in Table 10 and Table 17

Symbol

Alt.

Parameter

Min.

Typ^{(1) (2)}Max⁽²⁾Unit

t_W

Write Status Register Cycle Time

8

15

ms

Page Program Cycle Time (256 Bytes)

1.5

(3)

t_PP

5

ms

0.4+

n*1.1/256

Page Program Cycle Time (n Bytes)

t_SE

t_BE

Sector Erase Cycle Time

Bulk Erase Cycle Time

1

3

6

s

2.8

1. At 85°C

2. Preliminary data.

3. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are

obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤

256)

Table 17. AC Measurement Conditions

Symbol

Parameter

Load Capacitance

Min.

Max.

Unit

C_L

30

pF

ns

V

Input Rise and Fall Times

5

Input Pulse Voltages

0.2V_CCto 0.8V_CC

0.3V_CCto 0.7V_CC

V_CC/ 2

Input Timing Reference Voltages

Output Timing Reference Voltages

V

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 21. AC Measurement I/O Waveform

Input Levels

Input and Output

Timing Reference Levels

0.8V

CC

0.7V

0.5V

0.3V

CC

0.2V

CC

AI07455

39/50

DC and AC parameters

M25P20

Table 18. AC Characteristics (25MHz Operation, Device Grade 6 or 3)

Test conditions specified in Table 10 and Table 17

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following

f_C

f_R

f_C

instructions: FAST_READ, PP, SE, BE,

DP, RES, WREN, WRDI, RDSR, WRSR

D.C.

25

20

MHz

Clock Frequency for READ instructions

Clock High Time

D.C.

18

0.1

10

5

MHz

ns

(1)

t_CH

t_CLH

t_CLL

(1)

t_CL

Clock Low Time

ns

(2)

t_CLCH

Clock Rise Time⁽³⁾(peak to peak)

Clock Fall Time⁽³⁾(peak to peak)

S Active Setup Time (relative to C)

S Not Active Hold Time (relative to C)

Data In Setup Time

V/ns

ns

(2)

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_SHSL

t_CSS

ns

t_DSU

t_DH

ns

Data In Hold Time

5

ns

S Active Hold Time (relative to C)

S Not Active Setup Time (relative to C)

S Deselect Time

10

100

ns

t_CSH

t_DIS

t_V

ns

(2)

t_SHQZ

Output Disable Time

15

ns

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

Clock Low to Output Valid

Output Hold Time

ns

t_HO

0

ns

HOLD Setup Time (relative to C)

HOLD Hold Time (relative to C)

HOLD Setup Time (relative to C)

HOLD Hold Time (relative to C)

HOLD to Output Low-Z

10

ns

(2)

t_HHQX

t_LZ

15

20

ns

(2)

t_HLQZ

t_HZ

HOLD to Output High-Z

ns

(4)

t_WHSL

Write Protect Setup Time

Write Protect Hold Time

20

ns

(4)

t_SHWL

100

ns

(2)

t_DP

S High to Deep Power-down Mode

3

µs

S High to Standby Mode without

Electronic Signature Read

(2)

t_RES1

3 or 30⁽⁵⁾

µs

S High to Standby Mode with Electronic

Signature Read

1.8 or 30⁽⁵⁾

µs

(2)

t_RES2

1. t_CH+ t_CLmust be greater than or equal to 1/ f_C

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. It is 30µs in devices produced with the “X” process technology (grade 3 devices are only produced using

the “X” process technology). Details of how to find the process letter on the device marking are given in the

Application note AN1995.

40/50

M25P20

DC and AC parameters

Table 19. AC Characteristics (40MHz Operation, Device Grade 6)

40MHz available for products marked since week 20 of 2004, only⁽¹⁾

Test conditions specified in Table 10 and Table 17

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following

f_C

f_R

f_C

instructions: FAST_READ, PP, SE, BE,

DP, RES, WREN, WRDI, RDSR, WRSR

D.C.

40

20

MHz

Clock Frequency for READ instructions

Clock High Time

D.C.

11

0.1

5

MHz

ns

(2)

t_CH

t_CLH

t_CLL

(2)

t_CL

Clock Low Time

ns

(3)

t_CLCH

Clock Rise Time⁽⁴⁾(peak to peak)

Clock Fall Time⁽⁴⁾(peak to peak)

S Active Setup Time (relative to C)

S Not Active Hold Time (relative to C)

Data In Setup Time

V/ns

ns

(3)

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_SHSL

t_CSS

5

ns

t_DSU

t_DH

2

ns

Data In Hold Time

5

ns

S Active Hold Time (relative to C)

S Not Active Setup Time (relative to C)

S Deselect Time

5

ns

5

ns

t_CSH

t_DIS

t_V

100

ns

(3)

t_SHQZ

Output Disable Time

9

ns

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

Clock Low to Output Valid

Output Hold Time

ns

t_HO

0

5

ns

HOLD Setup Time (relative to C)

HOLD Hold Time (relative to C)

HOLD Setup Time (relative to C)

HOLD Hold Time (relative to C)

HOLD to Output Low-Z

ns

(3)

t_HHQX

t_LZ

9

ns

(3)

t_HLQZ

t_HZ

HOLD to Output High-Z

ns

(5)

t_WHSL

Write Protect Setup Time

Write Protect Hold Time

20

ns

(5)

t_SHWL

100

ns

(3)

t_DP

S High to Deep Power-down Mode

3

µs

S High to Standby Mode without

Electronic Signature Read

(3)

t_RES1

3 or 30⁽⁶⁾

µs

S High to Standby Mode with Electronic

Signature Read

(3)

t_RES2

1.8 or 30⁽⁶⁾

1. Details of how to find the date of marking are given in Application Note, AN1995.

2. t_CH+ t_CLmust be greater than or equal to 1/ f_C

3. Value guaranteed by characterization, not 100% tested in production.

4. Expressed as a slew-rate.

5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

6. It is 30µs in devices produced with the “X” process technology. Details of how to find the process letter on

the device marking are given in the Application note AN1995.

41/50

DC and AC parameters

M25P20

Table 20. AC Characteristics (50MHz Operation, Device Grade 6)

50MHz available only in products with Process Technology code X⁽¹⁾

Test conditions specified in Table 10 and Table 17

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following

f_C

f_R

f_C

instructions: FAST_READ, PP, SE, BE, DP,

RES, WREN, RDID, WRDI, RDSR, WRSR

D.C.

50

20

MHz

Clock Frequency for READ instructions

Clock High Time

D.C.

9

MHz

ns

(2)

t_CH

t_CLH

t_CLL

(2)

t_CL

Clock Low Time

9

ns

(3)

t_CLCH

Clock Rise Time⁽⁴⁾(peak to peak)

Clock Fall Time⁽⁴⁾(peak to peak)

S Active Setup Time (relative to C)

S Not Active Hold Time (relative to C)

Data In Setup Time

0.1

5

V/ns

ns

(3)

t_CHCL

t_SLCH

t_CHSL

t_DVCH

t_CHDX

t_CHSH

t_SHCH

t_SHSL

t_CSS

5

ns

t_DSU

t_DH

2

ns

Data In Hold Time

5

ns

S Active Hold Time (relative to C)

S Not Active Setup Time (relative to C)

S Deselect Time

5

ns

5

ns

t_CSH

t_DIS

t_V

100

ns

(3)

t_SHQZ

Output Disable Time

8

ns

t_CLQV

t_CLQX

t_HLCH

t_CHHH

t_HHCH

t_CHHL

Clock Low to Output Valid

Output Hold Time

ns

t_HO

0

5

ns

HOLD Setup Time (relative to C)

HOLD Hold Time (relative to C)

HOLD Setup Time (relative to C)

HOLD Hold Time (relative to C)

HOLD to Output Low-Z

ns

(3)

t_HHQX

t_LZ

8

ns

(3)

t_HLQZ

t_HZ

HOLD to Output High-Z

ns

(5)

t_WHSL

Write Protect Setup Time

Write Protect Hold Time

20

ns

(5)

t_SHWL

100

ns

(3)

t_DP

S High to Deep Power-down Mode

3

µs

S High to Standby Power mode without

Electronic Signature Read

(3)

t_RES1

30

µs

S High to Standby Power mode with

Electronic Signature Read

(3)

t_RES2

30

1. Details of how to find the date of marking are given in Application Note, AN1995.

2. t_CH+ t_CLmust be greater than or equal to 1/ f_C

3. Value guaranteed by characterization, not 100% tested in production.

4. Expressed as a slew-rate.

5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

42/50

M25P20

DC and AC parameters

Figure 22. Serial Input Timing

tSHSL

S

tCHSL

tSLCH

tCHSH

tSHCH

C

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

D

Q

High Impedance

AI01447C

Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1

W

tSHWL

tWHSL

S

C

D

High Impedance

Q

AI07439

43/50

DC and AC parameters

M25P20

Figure 24. Hold Timing

S

C

tHLCH

tCHHH

tCHHL

tHLQZ

tHHCH

tHHQX

Q

D

HOLD

AI02032

tSHQZ

AI01449e

Figure 25. Output Timing

S

tCH

C

tCLQV

tCL

tCLQX

Q

tCLQX

LSB OUT

tQLQH

tQHQL

ADDR.

LSB IN

D

44/50

M25P20

Package mechanical

11

Package mechanical

Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package

Outline

h x 45˚

A2

A

c

ccc

b

e

0.25 mm

D

GAUGE PLANE

k

8

1

E1

E

L

A1

L1

SO-A

1. Drawing is not to scale.

2. The ‘1’ that appears in the top view of the package shows the position of pin 1.

Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,

package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.75

0.25

0.069

0.010

0.10

1.25

0.28

0.17

0.004

0.049

0.011

0.007

0.48

0.23

0.10

5.00

6.20

4.00

–

0.019

0.009

0.004

0.197

0.244

0.157

–

c

ccc

D

4.90

6.00

3.90

1.27

4.80

5.80

3.80

–

0.193

0.236

0.154

0.050

0.189

0.228

0.150

–

E

E1

e

h

0.25

0°

0.50

8°

0.010

0°

0.020

8°

k

L

0.40

1.27

0.016

0.050

L1

1.04

0.041

45/50

Package mechanical

M25P20

Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6x5mm, Package Outline

D

D1

E

E1

E2

e

b

D2

θ

A

A2

L

A1 A3

VFQFPN-01

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 22. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6x5mm, Package Mechanical Data

millimeters

Min.

inches

Min.

Symbol

Typ.

Max.

Typ.

Max.

A

A1

A2

A3

b

0.85

1.00

0.05

0.0335

0.0394

0.0020

0.00

0.35

3.20

0.0000

0.0138

0.1260

0.65

0.20

0.40

6.00

5.75

3.40

5.00

4.75

4.00

1.27

0.60

0.0256

0.0079

0.0157

0.2362

0.2264

0.1339

0.1969

0.1870

0.1575

0.0500

0.0236

0.48

3.60

4.20

0.0189

0.1417

0.1654

D

D1

D2

E

E1

E2

e

3.80

0.50

0.1496

0.0197

L

0.75

12°

0.0295

12°

θ

46/50

M25P20

Part numbering

12

Part numbering

Table 23. Ordering Information Scheme

Example:

M25P20

–

V

MN 6

T

P /X

Device Type

M25P = Serial Flash Memory for Code Storage

Device Function

20 = 2 Mbit (256K x 8)

Operating Voltage

V = V_CC= 2.7 to 3.6V

Package

MN = SO8 (150 mil width)

MP = VFQFPN8 6x5mm (MLP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3

⁽¹⁾= Device tested with High Reliability Certified Flow⁽²⁾

.

Automotive temperature range (–40 to 125 °C)

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

P or G = ECOPACK® (RoHS compliant)

Process⁽³⁾

/X = T7Y

1. Device grade 3 available in SO8 ECOPACK® (RoHS compliant) package.

2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your

nearest ST sales office for a copy.

3. The process letter (/X) is specified in the ordering information of Grade 3 devices only.

For Grade 6 devices, the process letter does not appear in the Ordering Information, it only appears on the

device package (marking) and on the shipment box. Please contact your nearest ST Sales Office.

For more information on how to identify products by the Process Identification Letter, please refer to

AN1995: Serial Flash Memory Device Marking.

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST Sales Office.

The category of Second-Level Interconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standard JESD97. The maximum ratings related to

soldering conditions are also marked on the inner box label.

47/50

Revision history

M25P20

13

Revision history

Table 24. Document revision history

Date

Revision

Changes

12-Apr-2001

25-May-2001

1.0

1.1

Document written

Serial Paged Flash Memory renamed as Serial Flash Memory

Changes to text: Signal Description/Chip Select; Hold Condition/1st para;

Protection modes; Release from Power-down and Read Electronic

Signature (RES); Power-up

Repositioning of several tables and illustrations without changing their

contents

11-Sep-2001

16-Jan-2002

1.2

1.3

Power-up timing illustration; SO8W package removed

Changes to tables: Abs Max Ratings/V_IO; DC Characteristics/V_IL

FAST_READ instruction added. Document revised with new timings, V_WI

I_CC3and clock slew rate. Descriptions of Polling, Hold Condition, Page

Programming, Release for Deep Power-down made more precise. Value

of t_W(max) modified.

,

Clarification of descriptions of entering Standby Power mode from Deep

Power-down mode, and of terminating an instruction sequence or data-

out sequence.

16-May-2002

12-Sep-2002

1.4

1.5

VFQFPN8 package (MLP8) added. Document promoted to full datasheet.

Typical Page Program time improved. Write Protect setup and hold times

specified, for applications that switch Write Protect to exit the Hardware

Protection mode immediately before a WRSR, and to enter the Hardware

Protection mode again immediately after.

13-Dec-2002

24-Nov-2003

1.6

2.0

Table of contents, warning about exposed paddle on MLP8, and Pb-free

options added.

40MHz AC Characteristics table included as well as 25MHz. I_CC3(max),

t_SE(typ) and t_BE(typ) values improved. Change of naming for VDFPN8

package

Automotive range added. Soldering temperature information clarified for

RoHS compliant devices. Device Grade clarified

26-Apr-2004

05-Aug-2004

21-Dec-2004

3.0

4.0

5.0

Device Grade information clarified. Data-retention measurement

temperature corrected. Details of how to find the date of marking added.

2 Notes removed from Table 23: Ordering Information Scheme. Small text

changes. End timing line of t_SHQZmodified in Figure 25: Output Timing.

Updated Page Program (PP) instructions in Page Programming, Page

Program (PP), Instruction Times (Device Grade 6) and Instruction Times

(Device Grade 3).

01-Aug-2005

6.0

48/50

M25P20

Revision history

Table 24. Document revision history (continued)

Date

Revision

Changes

50MHz operation added (see Table 20: AC Characteristics (50MHz

Operation, Device Grade 6)). All packages are ECOPACK®. Blank option

removed from under Plating Technology in Table 23: Ordering Information

Scheme. MLP package renamed as VFQFPN, silhouette and package

mechanical drawing updated (see package silhouette on page 1 and

Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat

Package No lead, 6x5mm, Package Outline. Note added to <Blue>Figure

26. and Figure 27 Read Identification (RDID) instruction added.

01-Dec-2005

7.0

t_RES1and t_RES2modified in Table 20: AC Characteristics (50MHz

Operation, Device Grade 6). Titles of Figure 27 and Table 22 corrected.

22-Dec-2005

8.0

The data contained in Table 11, Table 16 and Table 18 is no longer

preliminary data.

Figure 3: Bus Master and memory devices on the SPI Bus modified and

Note 2 added.

40MHz frequency condition modified for I_CC3in Table 14: DC

Characteristics (Device Grade 3).

Table 16: Instruction Times (Device Grade 3) shows preliminary data.

14-Apr-2006

9

Device Grade distinction removed, Condition changed for the Data

Retention parameter in Table 11: Data Retention and Endurance.

V_WIparameter for Device Grade 3 added to Table 8: Power-Up Timing

and VWI Threshold.

SO8 package specifications updated (see Figure 26 and Table 21).

/X Process added to Table 23: Ordering Information Scheme.

t_RES1and t_RES2parameter timings changed for devices produced with the

“X” process technology in Table 18 and Table 19.

05-Jun-2006

10

SO8 Narrow package specifications updated (see Figure 26 and

Table 21).

49/50

M25P20

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50/50


型号：	M25P20-VMN1TP/X
厂家：	ST
描述：	2 Mbit, Low Voltage, Serial Flash Memory With 40MHz SPI Bus Interface 2兆位，低电压，串行闪存的40MHz SPI总线接口闪存
文件：	总50页 (文件大小：396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M25P20-VMN1TP/X [STMICROELECTRONICS]

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