M27C1024-70XF7X [STMICROELECTRONICS]
1 Mbit 64Kb x16 UV EPROM and OTP EPROM; 1兆位64Kb的X16 UV EPROM和OTP EPROM
| 型号： | M27C1024-70XF7X |
| 厂家： | 
ST |
| 描述： | 1 Mbit 64Kb x16 UV EPROM and OTP EPROM |
| 文件： | 总15页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27C1024
1 Mbit (64Kb x16) UV EPROM and OTP EPROM
5V ± 10% SUPPLYVOLTAGEin READ
OPERATION
FASTACCESS TIME: 35ns
LOW POWER CONSUMPTION:
– Active Current 35mA at 5MHz
– StandbyCurrent 100µA
40
40
1
1
PROGRAMMING VOLTAGE: 12.75V ± 0.25V
PROGRAMMING TIME: 100µs/byte (typical)
ELECTRONIC SIGNATURE
– ManufacturerCode: 0020h
– Device Code: 008Ch
FDIP40W (F)
PDIP40 (B)
DESCRIPTION
PLCC44 (C)
TSOP40 (N)
10 x 14mm
The M27C1024 is a 1 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processorsystems requiringlargedata or program
storage and is organized as 65,536 words of 16
bits.
Figure 1. Logic Diagram
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
V
V
PP
CC
For application where the content is programmed
only one time and erasure is not required, the
M27C1024 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14mm) packages.
16
16
A0-A15
Q0-Q15
Table 1. Signal Names
P
E
M27C1024
A0-A15
Q0-Q15
E
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program
G
G
P
V
SS
VPP
VCC
VSS
Program Supply
Supply Voltage
Ground
AI00702B
September 1998
1/15
M27C1024
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
V
1
2
3
4
5
6
7
8
9
40
39
V
P
PP
E
CC
Q15
Q14
Q13
Q12
Q11
Q10
Q9
38 NC
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
1 44
Q12
A13
A12
A11
A10
A9
Q11
Q10
Q9
Q8
Q8 10
M27C1024
V
12
M27C1024
34
V
SS
SS
V
SS
11
30
V
SS
NC
Q7
Q6
Q5
Q4
NC
A8
A7
A6
A5
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
23
AI00704
G
20
AI00703
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
DEVICE OPERATION
The modes of operations of the M27C1024 are
listedin the OperatingModes table. Asingle power
supply is required in the read mode. All inputs are
TTL levels except for Vpp and 12V on A9 for
ElectronicSignature.
A9
A10
A11
A12
A13
A14
A15
NC
1
40
V
SS
A8
A7
A6
Read Mode
A5
The M27C1024 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
OutputEnable(G) is the outputcontrol and should
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable, the address access time
(tAVQV)is equalto thedelayfrom Etooutput(tELQV).
Data is available at the output after a delay of tOE
from the falling edge of G, assuming that E has
been low and the addresses have been stable for
A4
A3
A2
P
A1
V
CC
10 M27C1024
31
30
A0
(Normal)
V
PP
E
11
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
at least tAVQV-tGLQV
.
Standby Mode
The M27C1024 has a standby mode which re-
duces the active current from 35mAto 100µA.
DQ8
20
21
V
SS
The M27C1024 is placed in the standby mode by
applyinga TTL high signal to the E input. When in
thestandby mode, theoutputs are in a high imped-
ance state, independentof the G input.
AI01582
Warning: NC = Not Connected.
2/15
M27C1024
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Ambient Operating Temperature (3)
Temperature Under Bias
Storage Temperature
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
TBIAS
TSTG
C
°
°C
V
(2)
VIO
Input or Output Voltages (except A9)
Supply Voltage
VCC
–2 to 7
V
(2)
VA9
A9 Voltage
–2 to 13.5
–2 to 14
V
VPP
Program Supply Voltage
V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0Vfor a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
E
G
VIL
VIH
X
P
A9
X
VPP
VCC or VSS
VCC or VSS
VPP
Q0 - Q15
Data Output
Hi-Z
Read
VIL
VIL
VIL
VIL
VIH
VIH
VIL
VIH
Output Disable
Program
X
X
VIL Pulse
X
Data Input
Data Output
Hi-Z
Verify
VIL
X
VIH
X
X
VPP
Program Inhibit
Standby
X
VPP
X
X
X
VCC or VSS
VCC
Hi-Z
Electronic Signature
VIL
VIH
VID
Codes
Note: X = VIH or VIL, VID = 12V ±0.5V
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
VIL
VIH
Q7
0
Q6
Q5
1
Q4
0
Q3
0
Q2
0
Q1
0
Q0
Hex Data
20h
0
0
0
0
1
0
0
1
1
0
8Ch
Note: Outputs Q8-Q15 are set to ’0’.
3/15
M27C1024
Table 5. AC Measurement Conditions
High Speed
10ns
Standard
20ns
Input Rise and Fall Times
≤
≤
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Two Line Output Control
controlbus. This ensures that all deselectedmem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
BecauseEPROMsare usuallyused in largermem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
SystemConsiderations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer :
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. Themagnitudeof
transientcurrentpeaksisdependentonthe capaci-
tive and inductive loading of the device at the
output.
a. the lowest possible memory power dissipation,
b. completeassurancethat output bus contention
will not occur.
Forthe mostefficientuse of thesetwo controllines,
E should be decoded and used as the primary
device selecting function,while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
4/15
M27C1024
Table 7. Read Mode DC Characteristics(1)
(TA = 0 to 70 °C, –40 to 85 °C; –40 to 105 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
Symbol
ILI
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±10
µA
ILO
0V
V
OUT
V
CC
10
±
A
µ
≤
≤
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz
ICC
Supply Current
35
mA
ICC1
ICC2
IPP
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
E = VIH
E > VCC – 0.2V
VPP = VCC
1
100
mA
µA
100
A
µ
VIL
Input Low Voltage
–0.3
2
0.8
V
(2)
VIH
Input High Voltage
VCC + 1
0.4
V
V
V
V
VOL
VOH
Output Low Voltage
IOL = 2.1mA
Output High Voltage TTL
Output High Voltage CMOS
IOH = –400 A
2.4
µ
IOH = –100 A
VCC – 0.7
µ
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or afterVPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C, –40 to 85 °C; –40 to 105 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
M27C1024
Symbol
Alt
Parameter
Test Condition
Unit
-35 (3)
-45 (3)
-55 (3)
Min Max Min Max Min Max
tAVQV
tELQV
tGLQV
tACC Address Valid to Output Valid
tCE Chip Enable Low to Output Valid
tOE Output Enable Low to Output Valid
tDF Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
E = VIL, G = VIL
G = VIL
35
35
20
30
30
45
45
25
30
30
55
55
30
30
30
ns
ns
ns
ns
ns
E = VIL
(2)
tEHQZ
G = VIL
0
0
0
0
0
0
(2)
tGHQZ
E = VIL
Address Transition to Output
Transition
tAXQX
tOH
E = VIL, G = VIL
0
0
0
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or afterVPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurementconditions.
5/15
M27C1024
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C, –40 to 85 °C; –40 to 105 °C or –40 to 125 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC
)
M27C1024
Symbol
Alt
Parameter
Test Condition
Unit
-10/-12/
-15/-20
-70
-80/-90
Min Max Min Max Min Max
tAVQV
tELQV
tGLQV
tACC Address Valid to Output Valid
tCE Chip Enable Low to Output Valid
tOE Output Enable Low to Output Valid
tDF Chip Enable High to Output Hi-Z
tDF Output Enable High to Output Hi-Z
E = VIL, G = VIL
G = VIL
70
70
35
30
30
80
80
40
30
30
100
100
50
ns
ns
ns
ns
ns
E = VIL
(2)
tEHQZ
G = VIL
0
0
0
0
0
0
30
(2)
tGHQZ
E = VIL
30
Address Transition to Output
Transition
tAXQX
tOH
E = VIL, G = VIL
0
0
0
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or afterVPP.
2. Sampled only, not 100% tested.
Figure 5. Read Mode AC Waveforms
VALID
tAVQV
VALID
A0-A15
E
tAXQX
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q15
AI00705B
6/15
M27C1024
Table 9. ProgrammingMode DC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V;VPP = 12.75V ± 0.25V)
Symbol
ILI
Parameter
Input Leakage Current
Supply Current
Test Condition
Min
Max
10
Unit
0
V
IN
V
IH
A
µ
≤
≤
±
ICC
50
mA
mA
V
IPP
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
E = VIL
50
0.8
VIL
–0.3
2
VIH
VCC + 0.5
0.4
V
VOL
VOH
VID
IOL = 2.1mA
IOH = –400 A
V
2.4
V
µ
11.5
12.5
V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or afterVPP
.
Table 10. ProgrammingMode AC Characteristics(1)
(TA = 25 °C; VCC = 6.25V ± 0.25V;VPP = 12.75V ± 0.25V)
Symbol
tAVPL
Alt
tAS
Parameter
Test Condition
Min
2
Max
Unit
Address Valid to Program Low
Input Valid to Program Low
VPP High to Program Low
VCC High to Program Low
Chip Enable Low to Program Low
Program Pulse Width
s
s
s
s
s
s
s
µ
µ
µ
µ
µ
µ
µ
tQVPL
tDS
2
tVPHPL
tVCHPL
tELPL
tVPS
tVCS
tCES
tPW
tDH
2
2
2
tPLPH
95
2
105
tPHQX
Program High to Input Transition
Input Transition to Output Enable
Low
tQXGL
tGLQV
tOES
2
s
µ
tOE
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
100
130
ns
ns
(2)
tGHQZ
tDFP
0
0
Output Enable High to Address
Transition
tGHAX
tAH
ns
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or afterVPP
.
2. Sampled only, not 100% tested.
7/15
M27C1024
Figure 6. Programmingand Verify Modes AC Waveforms
VALID
A0-A15
Q0-Q15
tAVPL
tQVPL
DATA IN
DATA OUT
tPHQX
V
PP
tVPHPL
tVCHPL
tGLQV
tGHQZ
tGHAX
V
CC
E
tELPL
tPLPH
P
tQXGL
G
PROGRAM
VERIFY
AI00706
DEVICE OPERATION
(cont’d)
be present in the data word. The only way to
changea ’0’ to a ’1’is by die exposureto ultraviolet
light (UV EPROM). The M27C1024 is in the pro-
gramming mode when VPP input is at 12.75V,E is
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
andVSS. Thisshouldbe a highfrequencycapacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between Vcc and VSS for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
at VIL and P is pulsed to V . The data to be
IL
programmed is applied to 16 bits in parallel to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25V ± 0.25V.
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows pro-
gramming of the whole array with a guaranteed
margin, in a typical time of 6.5 seconds.Program-
ming with PRESTO II consists of applying a se-
quenceof 100µs programpulsestoeach worduntil
a correct verify occurs (see Figure 7). During pro-
gramming and verify operation, a MARGIN MODE
circuit is automaticallyactivatedin orderto guaran-
tee that each cell is programmed with enough
margin. No overprogrampulse is appliedsincethe
verify in MARGIN MODE provides necessarymar-
gin to each programmedcell.
Programming
Whendelivered (and aftereach ’1’s erasureforUV
EPROM), all bits of the M27C1024 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed,both ’1’s and’0’s can
8/15
M27C1024
Figure 7. ProgrammingFlowchart
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
withits correspondingprogrammingalgorithm.The
ES mode is functional in the 25°C ± 5°C ambient
temperaturerange that is required when program-
ming the M27C1024.To activatethe ESmode, the
programmingequipmentmustforce11.5Vto 12.5V
V
= 6.25V, V = 12.75V
PP
CC
n = 0
P = 100µs Pulse
NO
on address line A9 of the M27C1024 with VPP
=
NO
++n
= 25
VERIFY
YES
++ Addr
VCC = 5V. Two identifier bytes may then be se-
quenced from the device outputs by toggling ad-
YES
dresslineA0 from VIL to V . All otheraddresslines
IH
must be held at VIL during Electronic Signature
mode. Byte 0 (A0=V ) represents the manufac-
Last
Addr
NO
IL
FAIL
turercode and byte 1 (A0=V ) the deviceidentifier
IH
code. For the STMicroelectronics M27C1024,
these two iden-tifier bytes are given in Table 4 and
can be read-out on outputsQ0 to Q7.
YES
CHECK ALL WORDS
1st: V
2nd: V
= 6V
= 4.2V
CC
CC
ERASUREOPERATION (applies to UV EPROM)
The erasure characteristics of the M27C1024 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately4000Å. It shouldbe notedthatsunlight
and some type of fluorescent lamps have wave-
lengthsin the3000-4000Årange.Researchshows
that constant exposure to room level fluorescent
lightingcould erase a typicalM27C1024 in about 3
years, while it would take approximately1 week to
cause erasure when exposed to direct sunlight. If
the M27C1024 is to be exposed to these types of
lighting conditions for extended periods of time, it
is suggested that opaque labels be put over the
M27C1024 window to prevent unintentional era-
sure.The recommendederasure procedurefor the
M27C1024 is exposure to short wave ultraviolet
light whichhas wavelength2537 Å. Theintegrated
dose(i.e. UVintensityx exposuretime)for erasure
should be a minimum of 15 W-sec/cm2. The era-
sure time with this dosage is approximately 15 to
20 minutes using an ultraviolet lamp with
12000 µW/cm2 power rating. The M27C1024
shouldbe placedwithin 2.5 cm (1 inch) of thelamp
tubesduring the erasure.Some lamps have a filter
on their tubes which should be removed before
erasure.
AI00707C
Program Inhibit
Programming of multiple M27C1024s in parallel
with different data is also easily accomplished.
Except for E, all like inputs including G of the
parallel M27C1024 may be common. A TTL low
level pulse applied to a M27C1024’s P input, with
E low and VPP at 12.75V, will program that
M27C1024. A high level E input inhibits the other
M27C1024sfrom being programmed.
Program Verify
A verify (read) should be performed on the pro-
grammedbitsto determinethatthey werecorrectly
programmed. The verify is accomplished with E
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.
On-Board Programming
TheM27C1024 can be directlyprogrammed in the
application circuit. See the relevant Application
Note AN620.
9/15
M27C1024
ORDERING INFORMATION SCHEME
Example:
M27C1024 -12 X
C
1
X
Speed
35ns
V
CC Tolerance
Package
FDIP40W
PDIP40
Temperature Range
Option
-35 (1)
-45 (1)
-55 (1)
-70
blank
X
10%
5%
F
B
C
N
1
6
7
3
0 to 70 C
X
Additional
Burn-in
±
±
°
45ns
55ns
–40 to 85 C
°
TR
Tape & Reel
Packing
PLCC44
–40 to 105 °C
–40 to 125 °C
70ns
TSOP40
10 x 14mm
-80
80ns
-90
90ns
-10
100ns
120ns
150ns
200ns
100ns
-12
-15
-20
-10
Note: 1. High Speed, see AC Characteristics section for furtherinformation.
Fora list ofavailableoptions(Speed, Package,etc...)or for furtherinformationon anyaspect of thisdevice,
please contact the STMicroelectronics Sales Office nearest to you.
10/15
M27C1024
FDIP40W - 40 pin Ceramic Frit-seal DIP, with window
mm
Min
inches
Min
Symb
Typ
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
51.79
–
0.30
52.60
–
0.009
2.039
–
0.012
2.071
–
D
D2
E
48.26
15.24
1.900
0.600
–
–
–
–
E1
e
13.06
–
13.36
–
0.514
–
0.526
–
2.54
0.100
1.900
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
0.637
0.125
0.060
–
0.710
S
2.49
–
0.098
–
8.13
0.320
α
4°
11°
4°
11°
N
40
40
A2
A3
A1
A
L
α
B1
B
e
C
eA
eB
D2
D
S
N
1
E1
E
FDIPW-a
Drawing is not to scale.
11/15
M27C1024
PDIP40 - 40 pin Plastic DIP, 600 mils width
mm
Min
–
inches
Symb
Typ
4.45
0.64
Max
–
Typ
Min
–
Max
–
A
A1
A2
B
0.175
0.025
0.38
3.56
0.38
1.14
0.20
51.78
–
–
0.015
0.140
0.015
0.045
0.008
2.039
–
–
3.91
0.53
1.78
0.31
52.58
–
0.154
0.021
0.070
0.012
2.070
–
B1
C
D
D2
E
48.26
1.900
14.80
13.46
–
16.26
13.99
–
0.583
0.530
–
0.640
0.551
–
E1
e1
eA
eB
L
2.54
0.100
0.600
15.24
–
–
–
15.24
3.05
1.52
17.78
3.81
2.29
0.600
0.120
0.060
0É
0.700
0.150
0.090
S
0
°
15
°
15
°
α
N
40
40
A2
A
L
A1
e1
α
C
B1
B
D2
eA
eB
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
12/15
M27C1024
PLCC44 - 44 lead Plastic Leaded Chip Carrier, square
mm
Min
4.20
2.29
0.33
0.66
17.40
16.51
14.99
17.40
16.51
14.99
–
inches
Min
Symb
Typ
Max
4.70
3.04
0.53
0.81
17.65
16.66
16.00
17.65
16.66
16.00
–
Typ
Max
0.185
0.120
0.021
0.032
0.695
0.656
0.630
0.695
0.656
0.630
–
A
A1
B
0.165
0.090
0.013
0.026
0.685
0.650
0.590
0.685
0.650
0.590
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
j
–
–
–
–
N
44
44
CP
0.10
0.004
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
13/15
M27C1024
TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
14.20
12.50
10.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.559
0.492
0.398
–
A
A1
A2
B
0.05
0.95
0.17
0.10
13.80
12.30
9.90
–
0.002
0.037
0.007
0.004
0.543
0.484
0.390
–
C
D
D1
E
e
0.50
0.020
L
0.50
0.70
0.020
0.028
0
°
5
°
0
°
5
°
α
N
40
40
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
14/15
M27C1024
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1998 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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15/15
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