M27C1024-80XK3 [STMICROELECTRONICS]

64KX16 OTPROM, 80ns, PQCC44, PLASTIC, LCC-44;


型号：	M27C1024-80XK3
厂家：	ST
描述：	64KX16 OTPROM, 80ns, PQCC44, PLASTIC, LCC-44 可编程只读存储器
文件：	总16页 (文件大小：110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M27C1024

1 Mbit (64Kb x16) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION

■ ACCESS TIME: 35ns

■ LOW POWER CONSUMPTION:

– Active Current 35mA at 5MHz

– Standby Current 100µA

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 100µs/word

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

FDIP40W (F)

PDIP40 (B)

– Device Code: 8Ch

DESCRIPTION

The M27C1024 is a 1 Mbit EPROM offered in the

two ranges UV (ultra violet erase) and OTP (one

time programmable). It is ideally suited for micro-

processor systems requiring large data or program

storage and is organized as 65,536 words of 16

bits.

PLCC44 (K)

TSOP40 (N)

10 x 14 mm

Figure 1. Logic Diagram

The FDIP40W (window ceramic frit-seal package)

has a transparent lid which allows the user to ex-

pose the chip to ultraviolet light to erase the bit pat-

tern. A new pattern can then be written to the

device by following the programming procedure.

For application where the content is programmed

only one time and erasure is not required, the

M27C1024 is offered in PDIP40, PLCC44 and

TSOP40 (10 x 14 mm) packages.

A0-A15

Q0-Q15

M27C1024

AI00702B

September 2000

1/16

M27C1024

Figure 2A. DIP Connections

Figure 2B. LCC Connections

Q15

Q14

Q13

Q12

Q11

Q10

38 NC

37 A15

36 A14

35 A13

34 A12

33 A11

32 A10

31 A9

1 44

Q12

A13

A12

A11

A10

Q11

Q10

Q8 10

M27C1024

Q7 12

Q6 13

Q5 14

Q4 15

Q3 16

Q2 17

Q1 18

Q0 19

29 A8

28 A7

27 A6

26 A5

25 A4

24 A3

23 A2

22 A1

21 A0

AI00704

AI00703

Figure 2C. TSOP Connections

Table 1. Signal Names

A0-A15

Address Inputs

A10

A11

A12

A13

A14

A15

Q0-Q15

Data Outputs

Chip Enable

Output Enable

Program

Program Supply

Supply Voltage

Ground

10 M27C1024 31

(Normal)

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

Not Connected Internally

DQ8

AI01582

2/16

M27C1024

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

–40 to 125

–50 to 125

–65 to 150

–2 to 7

Unit

°C

(3)

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage (except A9)

Supply Voltage

BIAS

STG

(2)

–2 to 7

(2)

A9 Voltage

–2 to 13.5

–2 to 14

Program Supply Voltage

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

3. Depends on range.

+0.5V with possible overshoot to V +2V for a period less than 20ns.

Table 3. Operating Modes

Mode

Q15-Q0

Data Output

Hi-Z

or V

Read

Output Disable

Program

Pulse

Data Input

Data Output

Hi-Z

Verify

Program Inhibit

Standby

or V

CC SS

Hi-Z

Electronic Signature

Codes

Note: X = V or V , V = 12V ± 0.5V.

IH IL ID

Table 4. Electronic Signature

Identifier

Manufacturer’s Code

Device Code

Hex Data

20h

8Ch

Note: Outputs Q15-Q8 are set to ’0’.

3/16

M27C1024

Table 5. AC Measurement Conditions

High Speed

≤ 10ns

Standard

≤ 20ns

Input Rise and Fall Times

Input Pulse Voltages

0 to 3V

1.5V

0.4V to 2.4V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

1.3V

High Speed

1N914

1.5V

3.3kΩ

DEVICE

UNDER

TEST

OUT

Standard

2.4V

2.0V

0.8V

0.4V

= 30pF for High Speed

= 100pF for Standard

includes JIG capacitance

AI01822

AI01823B

(1)

Table 6. Capacitance

Symbol

(T = 25 °C, f = 1 MHz)

Parameter

Test Condition

Min

Max

Unit

= 0V

Input Capacitance

Output Capacitance

OUT

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

dent of device selection. Assuming that the ad-

dresses are stable, the address access time

The modes of operations of the M27C1024 are

listed in the Operating Modes table. A single pow-

er supply is required in the read mode. All inputs

are TTL levels except for V and 12V on A9 for

Electronic Signature.

) is equal to the delay from E to output

). Data is available at the output after a delay

AVQV

ELQV

of t from the falling edge of G, assuming that E

has been low and the addresses have been stable

for at least t

-t

AVQV GLQV

Read Mode

Standby Mode

The M27C1024 has a standby mode which reduc-

es the active current from 35mA to 100µA.

The M27C1024 is placed in the standby mode by

applying a TTL high signal to the E input. When in

the standby mode, the outputs are in a high imped-

ance state, independent of the G input.

The M27C1024 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (E) is the power

control and should be used for device selection.

Output Enable(G) is the output control and should

be used to gate data to the output pins, indepen-

4/16

M27C1024

(1)

Table 7. Read Mode DC Characteristics

(T = 0 to 70 °C, –40 to 85 °C; –40 to 105 °C or –40 to 125 °C; V = 5V ± 5% or 5V ± 10%; V = V

)

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Max

±10

Unit

µA

0V ≤ V ≤ V

OUT CC

E = V , G = V ,

Supply Current

= 0mA, f = 5MHz

OUT

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Program Current

E = V

µA

CC1

E > V – 0.2V

100

0.8

CC2

= V

PP CC

Input Low Voltage

–0.3

(2)

+ 1

Input High Voltage

= 2.1mA

= –400µA

= –100µA

Output Low Voltage

0.4

Output High Voltage TTL

Output High Voltage CMOS

2.4

– 0.7V

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Maximum DC voltage on Output is V +0.5V.

(1)

Table 8A. Read Mode AC Characteristics

(T = 0 to 70 °C, –40 to 85 °C; –40 to 105 °C or –40 to 125 °C; V = 5V ± 5% or 5V ± 10%; V = V

)

M27C1024

(3)

Symbol

Alt

Parameter

Test Condition

Unit

-35

-45

-55

Min Max Min Max Min Max

Address Valid to Output Valid

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

E = V , G = V

AVQV

ACC

G = V

ELQV

E = V

GLQV

(2)

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

G = V

EHQZ

(2)

E = V

GHQZ

Address Transition to Output

Transition

E = V , G = V

IL IL

AXQX

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

Two Line Output Control

For the most efficient use of these two control

lines, Eshould be decoded and used as the prima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

Because EPROMs are usually used in larger

memory arrays, this product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

5/16

M27C1024

(1)

Table 8B. Read Mode AC Characteristics

(T = 0 to 70 °C, –40 to 85 °C; –40 to 105 °C or –40 to 125 °C; V = 5V ± 5% or 5V ± 10%; V = V

)

M27C1024

-10/-12

-15/-20

Symbol

Alt

Parameter

Test Condition

-70

-80/-90

Unit

Min Max Min Max Min Max

Address Valid to Output Valid

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

E = V , G = V

100

AVQV

ELQV

GLQV

ACC

G = V

E = V

(2)

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

G = V

E = V

EHQZ

GHQZ

Address Transition to Output

Transition

E = V , G = V

AXQX

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V

2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

VALID

tGLQV

VALID

A0-A15

tAVQV

tAXQX

tEHQZ

tGHQZ

tELQV

Hi-Z

Q0-Q15

AI00705B

System Considerations

The power switching characteristics of Advanced

CMOS EPROMs requirecareful decoupling of the

output control and by properly selected decoupling

capacitors. It is recommended that a 0.1µF ceram-

ic capacitor be used on every device between V

and V . This should be a high frequency capaci-

devices. The supply current, I , has three seg-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-

tion, a 4.7µF bulk electrolytic capacitor should be

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

transient current peaks is dependent on the ca-

pacitive and inductive loading of the device at the

output. The associated transient voltage peaks

can be suppressed by complying with the two line

used between V and V for every eight devic-

es. The bulk capacitor should be located near the

power supply connection point.The purpose of the

bulk capacitor is to overcome the voltage drop

caused by the inductive effects of PCB traces.

6/16

M27C1024

(1)

Table 9. Programming Mode AC Characteristics

(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)

Symbol

Parameter

Test Condition

Min

Max

±10

Unit

µA

Input Leakage Current

Supply Current

0 ≤ V ≤ V

E = V

Program Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage TTL

A9 Voltage

–0.3

0.8

+ 0.5

= 2.1mA

0.4

= –400µA

2.4

11.5

12.5

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

(1)

Table 10. Programming Mode AC Characteristics

(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)

Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

µs

Address Valid to Program Low

Input Valid to Program Low

AVPL

QVPL

High to Program Low

VPHPL

VPS

VCS

CES

VCHPL

Chip Enable Low to Program Low

Program Pulse Width

ELPL

105

PLPH

Program High to Input Transition

Input Transition to Output Enable Low

Output Enable Low to Output Valid

PHQX

QXGL

GLQV

OES

100

130

(2)

Output Enable High to Output Hi-Z

DFP

GHQZ

Output Enable High to Address

Transition

GHAX

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Sampled only, not 100% tested.

Programming

light (UV EPROM). The M27C1024 is in the pro-

gramming mode when V input is at 12.75V, E is

When delivered (and after each ’1’s erasure for UV

EPROM), all bits of the M27C1024 are in the ’1’

state. Data is introduced by selectively program-

ming ’0’s into the desired bit locations. Although

only ’0’s will be programmed, both ’1’s and ’0’s can

be present in the data word. The only way to

change a ’0’ to a ’1’ is by die exposure to ultraviolet

at V and P is pulsed to V . The data to be pro-

grammed is applied to 16 bits in parallel to the data

output pins. The levels required for the address

and data inputs are TTL. V

is specified to be

6.25V ± 0.25V.

7/16

M27C1024

Figure 6. Programming and Verify Modes AC Waveforms

VALID

A0-A15

Q0-Q15

tAVPL

tQVPL

DATA IN

DATA OUT

tPHQX

tVPHPL

tVCHPL

tGLQV

tGHQZ

tGHAX

tELPL

tPLPH

tQXGL

PROGRAM

VERIFY

AI00706

Figure 7. Programming Flowchart

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows pro-

gramming of the whole array with a guaranteed

margin, in a typical time of 6.5 seconds. Program-

ming with PRESTO II consists of applying a se-

quence of 100µs program pulses to each word

until a correct verify occurs (see Figure 7). During

programming and verify operation, a MARGIN

MODE circuit is automatically activated in order to

guarantee that each cell is programmed with

enough margin. No overprogram pulse is applied

since the verify in MARGIN MODE provides nec-

essary margin to each programmed cell.

= 6.25V, V

= 12.75V

n = 0

P = 100µs Pulse

Program Inhibit

++n

= 25

VERIFY

YES

++ Addr

Programming of multiple M27C1024s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs including G of the parallel

M27C1024 may be common. A TTL low level

pulse applied to a M27C1024’s P input, with E low

YES

Last

FAIL

Addr

and V at 12.75V, will program that M27C1024.

YES

A high level E input inhibits the other M27C1024s

from being programmed.

CHECK ALL WORDS

1st: V

2nd: V

Program Verify

= 6V

= 4.2V

A verify (read) should be performed on the pro-

grammed bits to determine that they were correct-

ly programmed. The verify is accomplished with E

AI00707C

and G at V , P at V , V at 12.75V and V at

6.25V.

8/16

M27C1024

Electronic Signature

ERASURE OPERATION (applies to UV EPROM)

The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that

will identify its manufacturer and type. This mode

is intended for use by programming equipment to

automatically match the device to be programmed

with its corresponding programming algorithm.

The ES mode is functional in the 25°C ± 5°C am-

bient temperature range that is required when pro-

gramming the M27C1024. To activate the ES

mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the

The erasure characteristics of the M27C1024 is

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000 Å. It should be noted that

sunlight and some type of fluorescent lamps have

wavelengths in the 3000-4000 Å range. Research

shows that constant exposure to room level fluo-

rescent lighting could erase atypical M27C1024 in

about 3 years, while it would take approximately 1

week to cause erasure when exposed to direct

sunlight. If the M27C1024 is to be exposed to

these types of lighting conditions for extended pe-

riods of time, it is suggested that opaque labels be

put over the M27C1024 window to prevent unin-

tentional erasure. The recommended erasure pro-

cedure for the M27C1024 is exposure to short

wave ultraviolet light which has wavelength 2537

Å. The integrated dose (i.e. UV intensity x expo-

sure time) for erasure should be a minimum of 15

M27C1024 with V

= V

= 5V. Two identifier

bytes maythen be sequenced from the device out-

puts by toggling address line A0 from V to V . All

other address lines must be held at V during

Electronic Signature mode. Byte 0 (A0 = V ) rep-

resents the manufacturer code and byte 1

(A0 = V ) the device identifier code. For the

STMicroelectronics M27C1024, these two identifi-

er bytes are given in Table 4 and can be read-out

on outputs Q7 to Q0.

W-sec/cm . The erasure time with this dosage is

approximately 15 to 20 minutes using an ultravio-

let lamp with 12000µW/cm power rating. The

M27C1024 should be placed within 2.5 cm (1 inch)

of the lamp tubes during the erasure. Some lamps

have a filter on their tubes which should be re-

moved before erasure.

9/16

M27C1024

Table 11. Ordering Information Scheme

Example:

M27C1024

-12

Device Type

M27

Supply Voltage

C = 5V

Device Function

1024 = 1 Mbit (64Kb x16)

Speed

(1)

-35

-45

-55

= 35 ns

= 45 ns

= 55 ns

(1)

-70 = 70 ns

-80 = 80 ns

-90 = 90 ns

-10 = 100 ns

-12 = 120 ns

-15 = 150 ns

-20 = 200 ns

Tolerance

blank = ± 10%

X = ± 5%

Package

F = FDIP40W

B = PDIP40

K = PLCC44

N = TSOP40: 10 x 14 mm

Temperature Range

1 = 0 to 70 °C

3 = –40 to 125 °C

6 = –40 to 85 °C

7 = –40 to 105 °C

Options

X = Additional Burn-in

TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

10/16

M27C1024

Table 12. Revision History

Date

Revision Details

September 1998 First Issue

09/20/00

AN620 Reference removed

11/16

M27C1024

Table 13. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Mechanical Data

inches

Symb

Typ

Min

Max

5.72

1.40

4.57

4.50

0.56

–

Typ

Min

Max

0.225

0.055

0.180

0.177

0.022

–

0.51

3.91

3.89

0.41

–

0.020

0.154

0.153

0.016

–

1.45

0.057

0.23

51.79

–

0.30

52.60

–

0.009

2.039

–

0.012

2.071

–

48.26

15.24

1.900

0.600

–

13.06

–

13.36

–

0.514

–

0.526

–

2.54

0.100

0.590

14.99

–

16.18

3.18

1.52

–

18.03

–

0.637

0.125

0.060

–

0.710

–

2.49

–

0.098

–

8.13

0.320

4°

11°

4°

11°

Figure 8. FDIP40W - 40 pin Ceramic Frit-seal DIP with window, Package Outline

FDIPW-a

Drawing is not to scale.

12/16

M27C1024

Table 14. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data

Min

–

inches

Min

Symb

Typ

4.45

0.64

Max

–

Typ

Max

–

0.175

0.025

–

0.38

3.56

0.38

1.14

0.20

51.78

–

0.015

0.140

0.015

0.045

0.008

2.039

–

3.91

0.53

1.78

0.31

52.58

–

0.154

0.021

0.070

0.012

2.070

–

48.26

1.900

14.80

13.46

–

16.26

13.99

–

0.583

0.530

–

0.640

0.551

–

2.54

0.100

0.600

15.24

–

15.24

3.05

1.52

0°

17.78

3.81

2.29

15°

0.600

0.120

0.060

0°

0.700

0.150

0.090

15°

Figure 9. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Outline

PDIP

Drawing is not to scale.

13/16

M27C1024

Table 15. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data

Min

4.20

2.29

–

inches

Min

Symbol

Typ

Max

4.70

3.04

0.51

0.53

0.81

17.65

16.66

16.00

17.65

16.66

16.00

–

Typ

Max

0.185

0.120

0.020

0.021

0.032

0.695

0.656

0.630

0.695

0.656

0.630

–

0.165

0.090

–

0.33

0.66

17.40

16.51

14.99

17.40

16.51

14.99

–

0.013

0.026

0.685

0.650

0.590

0.685

0.650

0.590

–

1.27

0.89

0.050

0.035

0.00

–

0.25

–

0.000

–

0.010

–

0.10

0.004

Figure 10. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline

1 N

E1 E

D2/E2

0.51 (.020)

1.14 (.045)

PLCC

Drawing is not to scale.

14/16

M27C1024

Table 16. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Mechanical Data

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

14.20

12.50

10.10

–

Typ

Max

0.047

0.006

0.041

0.011

0.008

0.559

0.492

0.398

–

0.05

0.95

0.17

0.10

13.80

12.30

9.90

–

0.002

0.037

0.007

0.004

0.543

0.484

0.390

–

0.50

0.020

0.50

0°

0.70

5°

0.020

0°

0.028

5°

0.10

0.004

Figure 11. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 14 mm, Package Outline

N/2

DIE

TSOP-a

Drawing is not to scale.

15/16

M27C1024

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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http://www.st.com

16/16

M27C1024-80XK3 [STMICROELECTRONICS]

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