M27C800-100XK6 [STMICROELECTRONICS]
512KX16 OTPROM, 100ns, PQCC44, PLASTIC, LCC-44;型号: | M27C800-100XK6 |
厂家: | ST |
描述: | 512KX16 OTPROM, 100ns, PQCC44, PLASTIC, LCC-44 可编程只读存储器 OTP只读存储器 内存集成电路 |
文件: | 总17页 (文件大小:115K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M27C800
8 Mbit (1Mb x8 or 512Kb x16) UV EPROM and OTP EPROM
■ 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 50ns
■ BYTE-WIDE or WORD-WIDE
CONFIGURABLE
42
42
■ 8 Mbit MASK ROM REPLACEMENT
■ LOW POWER CONSUMPTION
– Active Current 70mA at 8MHz
– Stand-by Current 50µA
1
1
FDIP42W (F)
PDIP42 (B)
■ PROGRAMMING VOLTAGE: 12.5V ± 0.25V
■ PROGRAMMING TIME: 50µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
44
1
PLCC44 (K)
SO44 (M)
– Device Code: B2h
DESCRIPTION
The M27C800 is an 8 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large data or program
storage. It is organised as either 1 Mwords of 8 bit
or 512 Kwords of 16 bit. The pin-out is compatible
with the most common 8 Mbit Mask ROM.
Figure 1. Logic Diagram
V
CC
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern.
A new patterncan then be written rapidly to the de-
vice by following the programming procedure.
19
Q15A–1
A0-A18
15
Q0-Q14
E
M27C800
For applications where the content is programmed
only one time and erasure is not required, the
M27C800 is offered in PDIP42, PLCC44 and
SO44 packages.
G
BYTEV
PP
V
SS
AI01593
January 2000
1/17
M27C800
Figure 2A. DIP Connections
Figure 2B. LCC Connections
A18
A17
A7
1
2
3
4
5
6
7
8
9
42 NC
41 A8
40 A9
A6
39 A10
38 A11
37 A12
36 A13
35 A14
34 A15
33 A16
32 BYTEV
A5
1 44
A4
A4
A12
A13
A3
A3
A2
A1
A0
A2
A14
A1
A15
A0 10
A16
M27C800
E
11
12
13
PP
E
12
M27C800
34 BYTEV
PP
V
31
V
SS
G
SS
V
V
SS
Q15A–1
SS
G
30 Q15A–1
29 Q7
Q0 14
Q8 15
Q1 16
Q9 17
Q2 18
Q0
Q8
Q1
Q7
28 Q14
27 Q6
Q14
Q6
23
26 Q13
25 Q5
Q10 19
Q3 20
24 Q12
23 Q4
AI02042
Q11 21
22
V
CC
AI01594
Figure 2C. SO Connections
Table 1. Signal Names
A0-A18
Q0-Q7
Q8-Q14
Q15A–1
E
Address Inputs
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
Data Outputs
Data Outputs
2
NC
3
A8
4
A9
5
A10
A11
A12
A13
A14
A15
A16
BYTEV
Data Output / Address Input
Chip Enable
6
7
8
9
G
Output Enable
10
11
12
13
14
15
16
17
18
19
20
21
22
BYTEV
Byte Mode / Program Supply
Supply Voltage
PP
M27C800
PP
V
V
V
V
CC
SS
SS
G
SS
Q15A–1
Q7
Ground
Q0
Q8
Q14
Q6
NC
Not Connected Internally
Q1
Q9
Q13
Q5
Q2
Q10
Q3
Q12
Q4
Q11
V
CC
AI01595
2/17
M27C800
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
(3)
T
A
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
BIAS
T
STG
(2)
V
IO
V
–2 to 7
V
CC
(2)
A9 Voltage
–2 to 13.5
–2 to 14
V
V
A9
V
Program Supply Voltage
V
PP
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V +2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
BYTEV
E
G
A9
X
Q15A–1
Q14-Q8
Data Out
Hi-Z
Q7-Q0
Data Out
Data Out
Data Out
Hi-Z
PP
V
V
V
Read Word-wide
Data Out
IL
IL
IL
IL
IL
IL
IH
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
V
V
V
V
V
V
V
X
V
IH
IL
IL
V
X
Hi-Z
IL
IL
V
V
X
X
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
IH
IH
V
Pulse
V
V
V
Program
X
Data In
Data Out
Hi-Z
Data In
Data Out
Hi-Z
IL
PP
PP
PP
V
V
V
Verify
X
IH
IH
IH
IL
V
V
Program Inhibit
Standby
X
IH
X
X
X
Hi-Z
Hi-Z
Hi-Z
V
V
V
V
Electronic Signature
Code
Codes
Codes
IL
IL
IH
ID
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Q15
and
Q7
Q14
and
Q6
Q13
and
Q5
Q12
and
Q4
Q11
and
Q3
Q10
and
Q2
Q9
and
Q1
Q8
and
Q0
Identifier
A0
Hex Data
V
Manufacturer’s Code
Device Code
0
1
0
0
1
1
0
1
0
0
0
0
0
1
0
0
20h
B2h
IL
V
IH
3/17
M27C800
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
DEVICE OPERATION
lower 8 bits of the 16 bit data are selected and with
A–1 at V the upper 8 bits of the 16 bit data are
IH
The operating modes of the M27C800 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V and 12V on A9 for the
Electronic Signature.
selected.
The M27C800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte- wide organisation must be selected.
PP
Read Mode
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
The M27C800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV pin. When BYTEV
PP
PP
is at V the Word-wide organisation is selected
IH
and the Q15A–1 pin is used for Q15 Data Output.
dress access time (t
) is equal to the delay
AVQV
When the BYTEV pin is at V the Byte-wide or-
PP
IL
from E to output (t
). Data is available at the
ELQV
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
output after a delay of t
from the falling edge
GLQV
of G, assuming that E has been low and the ad-
dresses have been stable for at least t -t
.
AVQV GLQV
Byte-wide organisation, then with A–1 at V the
IL
4/17
M27C800
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Test Condition
Min
Max
10
Unit
pF
Input Capacitance (except BYTEV
)
V
V
= 0V
= 0V
= 0V
PP
IN
IN
C
IN
Input Capacitance (BYTEV
)
120
12
pF
PP
C
OUT
V
OUT
Output Capacitance
pF
Note: 1. Sampled only, not 100% tested.
(1)
Table 7. Read Mode DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 5V ± 5% or 5V ± 10%; V = V
)
CC
A
CC
PP
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
Unit
µA
I
±1
0V ≤ V ≤ V
LI
IN
CC
I
0V ≤ V
≤ V
OUT CC
±10
µA
LO
E = V , G = V ,
IL
IL
70
50
mA
mA
I
= 0mA, f = 8MHz
OUT
I
Supply Current
CC
E = V , G = V ,
IL
IL
I
= 0mA, f = 5MHz
OUT
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC1
IH
I
E > V – 0.2V
CC
50
10
0.8
CC2
I
V
= V
PP CC
PP
V
Input Low Voltage
–0.3
2
IL
(2)
V
+ 1
Input High Voltage
V
V
V
V
CC
IH
V
I
= 2.1mA
Output Low Voltage
0.4
OL
OL
V
I
= –400µA
OH
Output High Voltage TTL
2.4
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V + 0.5V.
CC
Standby Mode
The M27C800 has a standby mode which reduces
the supply current from 50mA to 100µA. The
M27C800 is placed in the standby mode by apply-
ing aCMOS high signal to the Einput. When in the
standby mode, the outputs are in a high imped-
ance state, independent of the G input.
5/17
M27C800
(1)
Table 8A. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 5V ± 5% or 5V ± 10%; V = V
)
CC
A
CC
PP
M27C800
(3)
Symbol
Alt
Parameter
Test Condition
-70
-90
Unit
-50
Min Max
Min
Max Min
Max
Address Valid to Output
Valid
t
t
E = V , G = V
50
70
90
ns
ns
ns
AVQV
ACC
IL
IL
IL
BYTE High to Output
Valid
t
t
t
E = V , G = V
50
50
70
70
90
90
BHQV
ST
IL
Chip Enable Low to
Output Valid
t
G = V
ELQV
GLQV
CE
OE
IL
Output Enable Low to
Output Valid
t
t
E = V
30
30
35
30
45
30
30
ns
ns
ns
IL
(2)
(2)
t
E = V , G = V
BYTE Low to Output Hi-Z
t
STD
IL
IL
BLQZ
Chip Enable High to
Output Hi-Z
t
G = V
0
0
5
5
30
30
0
0
5
5
30
30
0
0
5
5
t
DF
IL
EHQZ
Output Enable High to
Output Hi-Z
(2)
t
E = V
30
ns
ns
ns
t
DF
IL
GHQZ
Address Transition to
Output Transition
t
t
E = V , G = V
AXQX
OH
OH
IL
IL
IL
BYTE Low to Output
Transition
t
t
E = V , G = V
BLQX
IL
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
PP.
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
(1)
Table 8B. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 5V ± 5% or 5V ± 10%; V = V )
A
CC
PP
CC
M27C800
-100 -120/150
Min Max Min Max
Symbol
Alt
Parameter
Test Condition
Unit
t
t
Address Valid to Output Valid
BYTE High to Output Valid
E = V , G = V
100
100
100
50
120
120
120
60
ns
ns
ns
ns
AVQV
ACC
IL
IL
IL
t
t
E = V , G = V
BHQV
ST
IL
t
t
G = V
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
ELQV
CE
IL
t
t
E = V
GLQV
OE
IL
(2)
(2)
(2)
t
E = V , G = V
BYTE Low to Output Hi-Z
40
40
40
50
50
50
ns
ns
t
STD
IL
IL
BLQZ
t
G = V
Chip Enable High to Output Hi-Z
0
0
t
DF
IL
EHQZ
GHQZ
t
E = V
Output Enable High to Output Hi-Z
Address Transition to Output Transition
BYTE Low to Output Transition
0
5
5
0
5
5
ns
ns
ns
t
DF
IL
t
t
E = V , G = V
AXQX
OH
OH
IL
IL
IL
t
t
E = V , G = V
BLQX
IL
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
PP.
CC
PP
2. Sampled only, not 100% tested.
6/17
M27C800
Figure 5. Word-Wide Read Mode AC Waveforms
VALID
VALID
A0-A18
tAVQV
tAXQX
E
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q15
AI01596B
Note: BYTEV = V
.
IH
PP
Two Line Output Control
System Considerations
Because EPROMs are usually used in larger
memory arrays, this product features a 2-line con-
trol function which accommodates the use of mul-
tiple memory connection. The two-line control
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I
CC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E.
function
allows:
a. the lowest possible memory power dissipation
b. complete assurance that output bus contention
will not occur.
The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading
of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control and by properly se-
lected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor is used on every
For the most efficient use of these two control
lines, Eshould be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
device between V and V
.
CC
SS
This should be a high frequency type of low inher-
ent inductance and should be placed as close as
possible to the device. In addition, a 4.7µF electro-
lytic capacitor should be used between V
SS
and
CC
V
for every eight devices. This capacitor should
be mounted near the power supply connection
point. The purpose of this capacitor is to overcome
the voltage drop caused by the inductive effects of
PCB traces.
7/17
M27C800
Figure 6. Byte-Wide Read Mode AC Waveforms
VALID
tAVQV
A–1,A0-A18
E
VALID
tAXQX
tEHQZ
tGHQZ
tGLQV
G
tELQV
Hi-Z
Q0-Q7
AI01597B
Note: BYTEV = V
PP
IL.
Figure 7. BYTE Transition AC Waveforms
A0-A18
VALID
A–1
VALID
tAVQV
tAXQX
BYTEV
PP
tBHQV
Q0-Q7
tBLQX
Q8-Q15
tBLQZ
DATA OUT
Hi-Z
DATA OUT
AI01598C
Note: Chip Enable (E) and Output Enable (G) = V .
IL
8/17
M27C800
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.5V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±1
Unit
µA
mA
mA
V
I
0 ≤ V ≤ V
Input Leakage Current
Supply Current
LI
IN
CC
I
50
CC
I
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
PP
IL
V
–0.3
2.4
0.8
IL
V
V
V
+ 0.5
CC
V
IH
I
= 2.1mA
OL
0.4
V
OL
V
OH
I
= –2.5mA
OH
3.5
V
V
11.5
12.5
V
ID
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12.5V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
Max
Unit
µs
µs
µs
µs
µs
µs
µs
ns
t
t
t
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
2
2
AVEL
AS
t
QVEL
DS
t
t
V
V
High to Address Valid
High to Address Valid
2
VPHAV
VPS
VCS
PP
CC
t
t
2
VCHAV
t
t
Chip Enable Program Pulse Width
Chip Enable High to Input Transition
Input Transition to Output Enable Low
Output Enable Low to Output Valid
45
2
55
ELEH
PW
t
t
EHQX
DH
OES
t
t
t
2
QXGL
GLQV
t
120
130
OE
(2)
t
Output Enable High to Output Hi-Z
0
0
ns
ns
t
DFP
GHQZ
Output Enable High to Address
Transition
t
t
GHAX
AH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Programming
change a ’0’ to a ’1’ is by die exposition to ultravio-
let light (UVEPROM). The M27C800 is in the pro-
When delivered (and after each erasure for UV
EPROM), all bits of the M27C800 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed, both ’1’s and ’0’s can
be present in the data word. The only way to
gramming mode when V input is at 12.5V, G is
PP
at V and E is pulsed to V . The data to be pro-
IH
IL
grammed is applied to 16 bits in parallel to the data
output pins. The levels required for the address
and data inputs are TTL. V
6.25V ± 0.25V.
is specified to be
CC
9/17
M27C800
Figure 8. Programming and Verify Modes AC Waveforms
A0-A18
Q0-Q15
BYTEV
VALID
tAVEL
DATA IN
tQVEL
DATA OUT
tEHQX
PP
tVPHAV
tVCHAV
tGLQV
tGHQZ
tGHAX
V
E
CC
tELEH
tQXGL
G
PROGRAM
VERIFY
AI01599
Figure 9. Programming Flowchart
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 26 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 9). During
programing and verify operation a MARGIN
MODE circuit is automatically activated to guaran-
tee that each cell is programed with enough mar-
gin. No overprogram pulse is applied since the
verify in MARGIN MODE provides the necessary
margin to each programmed cell.
V
= 6.25V, V = 12.5V
PP
CC
n = 0
E = 50µs Pulse
NO
NO
++n
= 25
VERIFY
YES
++ Addr
Program Inhibit
YES
Programming of multiple M27C800s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C800 may be common. A TTL low level pulse
Last
NO
FAIL
Addr
applied to a M27C800’s E input and V at 12.5V,
PP
YES
will program that M27C800. A high level Einput in-
hibits the other M27C800s from being pro-
grammed.
CHECK ALL WORDS
BYTEV
1st: V
=V
PP IH
Program Verify
= 6V
CC
2nd: V
= 4.2V
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
CC
AI01044B
at V and G at V , V
at 12.5V and V
at
IH
6.25V.
IL
PP
CC
10/17
M27C800
On-Board Programming
ERASURE OPERATION (applies to UV EPROM)
The M27C800 can be directly programmed in the The erasure characteristics of the M27C800 is
application circuit. See the relevant Application such that erasure begins when the cells are ex-
Note AN620.
Electronic Signature
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27C800 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C800 is to be exposed to these
types of lighting conditions for extended periods of
time, itis suggested that opaque labels beput over
the M27C800 window to prevent unintentional era-
sure. The recommended erasure procedure for
M27C800 is exposure to short wave ultraviolet
light which has a wavelength of 2537 Å. The inte-
grated dose (i.e. UV intensity x exposure time) for
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27C800. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C800, with V = V
bytes maythen be sequenced from the device out-
puts by toggling address line A0 from V to V . All
other address lines must be held at V during
Electronic Signature mode.
Byte 0 (A0 = V ) represents the manufacturer
code and byte 1 (A0 = V ) the device identifier
= 5V. Two identifier
PP
CC
2
IL
IH
erasure should be a minimum of 30 W-sec/cm .
IL
The erasure time with this dosage is approximate-
ly 30 to 40 minutes using an ultraviolet lamp with
2
IL
12000 µW/cm power rating. The M27C800
IH
should be placed within 2.5cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.
code. Forthe STMicroelectronics M27C800, these
two identifier bytes are given inTable 4 and can be
read-out on outputs Q7 to Q0.
11/17
M27C800
Table 11. Ordering Information Scheme
Example:
M27C800
-50
X
M
1
TR
Device Type
M27
Supply Voltage
C = 5V
Device Function
800 = 8 Mbit (1Mb x8 or 512Kb x16)
Speed
(1)
-50
= 50 ns
-70 = 70 ns
-90 = 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
V
Tolerance
CC
blank = ± 10%
X = ± 5%
Package
F = FDIP40W
B = PDIP40
K = PLCC44
M = SO44
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Options
TR = Tape & Reel Packing
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 1. Revision History
Date
Revision Details
March 1999
First Issue
50ns speed class addes (Tables8A and 11)
Electronic Signature change (Table 4)
FDIP42W Package Dimension, L Max added (Table 12)
01/25/00
12/17
M27C800
Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
54.41
–
0.30
54.86
–
0.009
2.142
–
0.012
2.160
–
D
D2
E
50.80
15.24
2.000
0.600
–
–
–
–
E1
e
14.50
–
14.90
–
0.571
–
0.587
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
4.10
2.49
–
0.637
0.125
0.060
–
0.710
0.161
0.098
–
S
K
9.40
0.370
0.450
K1
α
11.43
–
–
–
–
4°
11°
4°
11°
N
42
42
Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline
A2
A3
A
L
A1
e1
α
B1
B
C
eA
eB
D2
D
S
N
1
K
E1
E
K1
FDIPW-b
Drawing is not to scale.
13/17
M27C800
Table 13. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
mm
Min
–
inches
Min
–
Symb
Typ
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.25
3.56
0.38
1.27
0.20
52.20
–
0.010
0.140
0.015
0.050
0.008
2.055
–
4.06
0.53
1.65
0.36
52.71
–
0.160
0.021
0.065
0.014
2.075
–
B1
C
D
D2
E
50.80
15.24
2.000
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.590
14.99
–
–
–
–
15.24
3.18
0.86
0°
17.78
3.43
1.37
10°
0.600
0.125
0.034
0°
0.700
0.135
0.054
10°
S
α
N
42
42
Figure 11. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Drawing is not to scale.
14/17
M27C800
Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Mechanical Data
mm
Min
4.20
2.29
–
inches
Min
Symb
Typ
Max
4.70
3.04
0.51
0.53
0.81
17.65
16.66
16.00
17.65
16.66
16.00
–
Typ
Max
0.185
0.120
0.020
0.021
0.032
0.695
0.656
0.630
0.695
0.656
0.630
–
A
A1
A2
B
0.165
0.090
–
0.33
0.66
17.40
16.51
14.99
17.40
16.51
14.99
–
0.013
0.026
0.685
0.650
0.590
0.685
0.650
0.590
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
44
44
CP
0.10
0.004
Figure 12. PLCC44 - 44 lead Plastic Leaded Chip Carrier, Package Outline
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
15/17
M27C800
Table 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
Symb
mm
Min
2.42
0.22
2.25
inches
Min
Typ
Max
2.62
0.23
2.35
0.50
0.25
28.30
13.40
–
Typ
Max
0.103
0.010
0.093
0.020
0.010
1.114
0.528
–
A
A1
A2
B
0.095
0.009
0.089
C
0.10
28.10
13.20
–
0.004
1.106
0.520
–
D
E
e
1.27
0.050
H
15.90
–
16.10
–
0.626
–
0.634
–
L
0.80
0.031
α
3°
–
–
3°
–
–
N
44
44
CP
0.10
0.004
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Drawing is not to scale.
16/17
M27C800
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
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