M27V322-120S1 [STMICROELECTRONICS]
32 Mbit (2Mb 】16) low-voltage UV EPROM and OTP EPROM; 32兆位（2MB × 16 ）低电压UV EPROM和OTP EPROM
| 型号： | M27V322-120S1 |
| 厂家： | 
ST |
| 描述： | 32 Mbit (2Mb 】16) low-voltage UV EPROM and OTP EPROM |
| 文件： | 总23页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27V322
32 Mbit (2Mb ×16) low-voltage UV EPROM and OTP EPROM
Feature summary
■ 3.3V ± 10% supply voltage in Read operation
■ Read access time
– 100ns at V = 3.0V to 3.6V
CC
42
■ Pin compatible with M27C322
■ Word-wide configurable
1
■ 32 Mbit Mask ROM replacement
FDIP42W (F)
■ Low power consumption
– Active Current 30mA at 5MHz
– Stand-by Current 60µA
■ Programming voltage: 12V ± 0.25V
■ Programming time: 50µs/word
■ Electronic signature
42
– Manufacturer Code: 0020h
– Device Code: 0034h
1
■ ECOPACK® packages available
PDIP42 (B)
42
1
SDIP42 (S)
May 2006
Rev 3
1/23
www.st.com
1
Contents
M27V322
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Two Line Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PRESTO III programming algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Program Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
On-Board programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.10 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11 Erasure operation (applies to UV EPROM) . . . . . . . . . . . . . . . . . . . . . . . 10
3
4
5
6
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
M27V322
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read mode DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Programming mode DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Margin mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programming mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FDIP42W - 42 pin Ceramic Frit-seal DIP, with window (0.315" × 0.630"),
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PDIP42 - 42 pin Plastic DIP, 600 mils width, package mechanical data . . . . . . . . . . . . . . 19
SDIP42 - 42 lead Shrink Plastic DIP, 600 mils width, package mechanical data . . . . . . . . 20
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13.
Table 14.
Table 15.
Table 16.
3/23
List of figures
M27V322
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Programming flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
AC testing input output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Margin mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programming and Verify modes AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FDIP42W - 42 pin Ceramic Frit-seal DIP, with window (0.315" × 0.630"),
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. PDIP42 - 42 pin Plastic DIP, 600 mils width, package outline . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, package outline. . . . . . . . . . . . . . . . . 20
4/23
M27V322
Summary description
1
Summary description
The M27V322 is a 32 Mbit EPROM offered in the UV range (ultra violet erase) and OTP
range. It is ideally suited for microprocessor systems requiring large data or program
storage. It is organised as 2 MWords of 16 bit. The pin-out is compatible with a 32 Mbit Mask
ROM.
The FDIP42W (window ceramic frit-seal package) has a transparent lid which allows the
user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be
written rapidly to the device by following the programming procedure.
For applications where the content is programmed only one time and erasure is not
required, the M27V322 is offered in PDIP42 and SDIP42 packages.
In order to meet environmental requirements, ST offers the M27V322 in ECOPACK®
packages.
ECOPACK packages are Lead-free. The category of second Level Interconnect is marked
on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
V
CC
21
16
A0-A20
Q0-Q15
E
M27V322
GV
PP
V
SS
AI03050
Table 1.
Signal names
A0-A20
Address Inputs
Data Outputs
Chip Enable
Q0-Q15
E
GVPP
VCC
Output Enable / Program Supply
Supply Voltage
VSS
Ground
5/23
Summary description
Figure 2.
M27V322
DIP connections
A18
A17
A7
1
2
3
4
5
6
7
8
9
42 A19
41 A8
40 A9
A6
39 A10
38 A11
37 A12
36 A13
35 A14
34 A15
33 A16
32 A20
A5
A4
A3
A2
A1
A0 10
M27V322
E
11
12
13
V
31
V
SS
SS
PP
GV
30 Q15
29 Q7
28 Q14
27 Q6
26 Q13
25 Q5
24 Q12
23 Q4
Q0 14
Q8 15
Q1 16
Q9 17
Q2 18
Q10 19
Q3 20
Q11 21
22
V
CC
AI03051
6/23
M27V322
Device operation
2
Device operation
The operating modes of the M27V322 are listed in the Operating Modes Table. A single
power supply is required in the read mode. All inputs are TTL compatible except for V and
PP
12V on A9 for the Electronic Signature.
2.1
Read mode
The M27V322 has a word-wide organization. Chip Enable (E) is the power control and
should be used for device selection. Output Enable (G) is the output control and should be
used to gate data to the output pins independent of device selection. Assuming that the
addresses are stable, the address access time (t
) is equal to the delay from E to output
AVQV
(t
). Data is available at the output after a delay of t
from the falling edge of GV ,
ELQV
GLQV PP
assuming that E has been low and the addresses have been stable for at least t
-t
.
AVQV GLQV
2.2
2.3
Standby mode
The M27V322 has a standby mode which reduces the supply current from 30mA to 30µA.
The M27V322 is placed in the standby mode by applying a CMOS high signal to the E
input.When in the standby mode, the outputs are in a high impedance state, independent of
the GV input.
PP
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, this product features a 2 line
control function which accommodates the use of multiple memory connection. The two line
control function allows:
■
■
the lowest possible memory power dissipation,
complete assurance that output bus contention will not occur.
For the most efficient use of these two control lines, E should be decoded and used as the
primary device selecting function, while GV should be made a common connection to all
PP
devices in the array and connected to the READ line from the system control bus. This
ensures that all deselected memory devices are in their low power standby mode and that
the output pins are only active when data is required from a particular memory device.
7/23
Device operation
M27V322
2.4
System considerations
The power switching characteristics of Advanced CMOS EPROMs require careful
decoupling of the supplies to the devices. The supply current ICC has three segments of
importance to the system designer: the standby current, the active current and the transient
peaks that are produced by the falling and rising edges of E. The magnitude of the transient
current peaks is dependent on the capacitive and inductive loading of the device outputs.
The associated transient voltage peaks can be suppressed by complying with the two line
output control and by properly selected decoupling capacitors. It is recommended that a
0.1µF ceramic capacitor is used on every device between V and V . This should be a
CC
SS
high frequency type of low inherent inductance and should be placed as close as possible to
the device. In addition, a 4.7µF electrolytic capacitor should be used between V and V
CC
SS
for every eight devices. This capacitor should be mounted near the power supply connection
point. The purpose of this capacitor is to overcome the voltage drop caused by the inductive
effects of PCB traces.
2.5
Programming
When delivered (and after each erasure for UV EPROM), all bits of the M27V322 are in the
"1" state. Data is introduced by selectively programming "0"s into the desired bit locations.
Although only "0"s will be programmed, both "1"s and "0"s can be present in the data word.
The only way to change a "0" to a "1" is by die exposition to ultraviolet light (UV EPROM).
The M27V322 is in the programming mode when V input is at 12.V, GV is at V and E
PP
PP
IH
is pulsed to V . The data to be programmed is applied to 16 bits in parallel to the data
IL
output pins. The levels required for the address and data inputs are TTL. V is specified to
CC
be 6.25V ± 0.25V.
2.6
PRESTO III programming algorithm
The PRESTO III Programming Algorithm allows the whole array to be programed with a
guaranteed margin in a typical time of 100 seconds. Programming with PRESTO III consists
of applying a sequence of 50µs program pulses to each word until a correct verify occurs
(see Figure 3). During programing and verify operation a MARGIN MODE circuit must be
activated to guarantee that each cell is programed with enough margin. No overprogram
pulse is applied since the verify in MARGIN MODE provides the necessary margin to each
programmed cell.
8/23
M27V322
Device operation
Figure 3.
Programming flowchart
V
= 6.25V, V = 12V
PP
CC
SET MARGIN MODE
n = 0
E = 50µs Pulse
NO
NO
++n
= 25
VERIFY
++ Addr
YES
YES
Last
Addr
NO
FAIL
YES
RESET MARGIN MODE
CHECK ALL WORDS
1st: V
2nd: V
= 5V
= 3V
CC
CC
AI03059B
2.7
Program Inhibit
Programming of multiple M27V322s in parallel with different data is also easily
accomplished. Except for E, all like inputs including GV of the parallel M27V322 may be
PP
common. A TTL low level pulse applied to a M27V322's E input and V at 12V, will program
PP
that M27V322. A high level E input inhibits the other M27V322s from being programmed.
2.8
2.9
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were
correctly programmed. The verify is accomplished with GV at V . Data should be verified
PP
IL
with t
after the falling edge of E.
ELQV
On-Board programming
The M27V322 can be directly programmed in the application circuit. See the relevant
Application Note AN620.
9/23
Device operation
M27V322
2.10
Electronic Signature
The Electronic Signature (ES) mode allows the reading out of a binary code from an
EPROM that will identify its manufacturer and type. This mode is intended for use by
programming equipment to automatically match the device to be programmed with its
corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C
ambient temperature range that is required when programming the M27V322. To activate
the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of
the M27V322, with V = V = 5V. Two identifier bytes may then be sequenced from the
PP
CC
device outputs by toggling address line A0 from V to V . All other address lines must be
IL
IH
held at V during Electronic Signature mode.
IL
Byte 0 (A0 = V ) represents the manufacturer code and byte 1 (A0 = V ) the device
IL
IH
identifier code. For the STMicroelectronics M27V322, these two identifier bytes are given in
Table 3 and can be read-out on outputs Q0 to Q7.
2.11
Erasure operation (applies to UV EPROM)
The erasure characteristics of the M27V322 is such that erasure begins when the cells are
exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted
that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å
range. Research shows that constant exposure to room level fluorescent lighting could
erase a typical M27V322 in about 3 years, while it would take approximately 1 week to
cause erasure when exposed to direct sunlight. If the M27V322 is to be exposed to these
types of lighting conditions for extended periods of time, it is suggested that opaque labels
be put over the M27V322 window to prevent unintentional erasure. The recommended
erasure procedure for M27V322 is exposure to short wave ultraviolet light which has a
wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure
2
should be a minimum of 30 W-sec/cm . The erasure time with this dosage is approximately
2
30 to 40 minutes using an ultraviolet lamp with 12000 µW/cm power rating. The M27V322
should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. Some lamps
have a filter on their tubes which should be removed before erasure.
(1)
Table 2.
Operating modes
Mode
E
GVPP
A9
Q15-Q0
Read
VIL
VIL
VIL
VIH
VPP
VPP
X
X
X
Data Out
Hi-Z
Output Disable
Program
VIL Pulse
VIH
X
Data In
Hi-Z
Program Inhibit
Standby
X
VIH
X
Hi-Z
Electronic Signature
1. X = VIH or VIL, VID = 12V ± 0.5V.
VIL
VIL
VID
Codes
(1)
Table 3.
Electronic signature
Identifier
A0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Hex Data
Manufacturer’s Code
Device Code
VIL
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
20h
34h
VIH
1. Outputs Q15-Q8 are set to '0'.
10/23
M27V322
Maximum rating
3
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient Operating Temperature(1)
Temperature Under Bias
Storage Temperature
–40 to 125
–50 to 125
–65 to 150
–2 to 7
°C
°C
°C
V
TBIAS
TSTG
(2)
VIO
Input or Output Voltage (except A9)
Supply Voltage
VCC
–2 to 7
V
(2)
VA9
A9 Voltage
–2 to 13.5
–2 to 14
V
VPP
Program Supply Voltage
V
1. Depends on range.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than
20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less
than 20ns.
11/23
DC and AC parameters
M27V322
4
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 5.
AC measurement conditions
High Speed
Standard
Input Rise and Fall Times
≤10ns
0 to 3V
1.5V
≤20ns
Input Pulse Voltages
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 4.
AC testing input output waveform
High Speed
3V
1.5V
0V
Standard
2.4V
2.0V
0.8V
0.4V
AI01822
12/23
M27V322
DC and AC parameters
Figure 5.
AC testing load circuit
1.3V
1N914
3.3kΩ
DEVICE
UNDER
TEST
OUT
C
L
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01823B
(1) (2)
Table 6.
Symbol
Capacitance
Parameter
Test Condition
Min
Max
Unit
CIN
Input Capacitance
Output Capacitance
VIN = 0V
10
12
pF
pF
COUT
VOUT = 0V
1. TA = 25 °C, f = 1 MHz
2. Sampled only, not 100% tested.
13/23
DC and AC parameters
M27V322
Unit
(1) (2)
Table 7.
Symbol
Read mode DC characteristics
Parameter
Test Condition
Min
Max
ILI
Input Leakage Current
Output Leakage Current
0V ≤VIN ≤VCC
±1
µA
µA
ILO
0V ≤VOUT ≤VCC
±10
E = VIL, GVPP = VIL,
IOUT = 0mA, f = 5MHz
ICC
ICC1
ICC2
Supply Current
30
1
mA
mA
µA
Supply Current (Standby)
TTL
E = VIH
Supply Current (Standby)
CMOS
E > VCC – 0.2V
VPP = VCC
60
IPP
VIL
Program Current
10
µA
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
–0.6
0.2VCC
(3)
VIH
0.7VCC
VCC + 0.5
0.4
V
V
V
VOL
VOH
IOL = 2.1mA
IOH = –400µA
2.4
1.
TA = –40 to 85 °C or 0 to 70 °C; VCC = 3.3V ± 10%; VPP = VCC
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
3. Maximum DC voltage on Output is VCC +0.5V.
.
(1) (2)
Table 8.
Symbol
Programming mode DC characteristics
Parameter
Test Condition
Min
Max
Unit
ILI
ICC
IPP
Input Leakage Current
Supply Current
V
IL ≤VIN ≤VIH
±10
50
µA
mA
mA
V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
E = VIL
50
VIL
–0.3
2.4
0.8
VIH
VOL
VOH
VID
VCC + 0.5
0.4
V
IOL = 2.1mA
V
IOH = –2.5mA
3.5
V
11.5
12.5
V
1. TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
14/23
M27V322
DC and AC parameters
Figure 6. Read mode AC waveforms
VALID
VALID
tEHQZ
A0-A20
tAVQV
tAXQX
E
tGLQV
GV
PP
tGHQZ
tELQV
Hi-Z
Q0-Q15
AI02207
(1) (2)
Test
Table 9.
Read mode AC characteristics
M27V322
Symbol Alt
Parameter
-100(3)
-120
-150
Unit
Condition
Min Max Min Max Min Max
Address Valid to Output
Valid
E = VIL,
G = VIL
tAVQV tACC
100
100
50
120
120
60
150 ns
150 ns
60 ns
50 ns
50 ns
ns
Chip Enable Low to Output
Valid
tELQV
tCE
G = VIL
E = VIL
G = VIL
E = VIL
Output Enable Low to
Output Valid
tGLQV tOE
Chip Enable High to Output
Hi-Z
(4)
tEHQZ
tDF
tDF
tAXQX tOH
0
0
5
45
0
0
5
50
0
0
5
Output Enable High to
Output Hi-Z
(4)
tGHQZ
45
50
Address Transition to
Output Transition
E = VIL,
G = VIL
1.
TA = –40 to 85 °C or 0 to 70 °C; VCC = 3.3V ± 10%; VPP = VCC
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
3. Speed obtained with High Speed measurement conditions.
4. Sampled only, not 100% tested.
15/23
DC and AC parameters
Figure 7.
M27V322
Margin mode AC waveforms
V
CC
A8
A9
tA9HVPH
tVPXA9X
GV
PP
tVPHEL
tEXVPX
E
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
1. A8 High level = 5V; A9 High level = 12V.
(1) (2)
Table 10. Margin mode AC characteristics
Test
Condition
Symbol
Alt
Parameter
Min
Max
Unit
tA9HVPH tAS9 VA9 High to VPP High
tVPHEL tVPS VPP High to Chip Enable Low
2
2
1
1
1
2
2
µs
µs
µs
µs
µs
µs
µs
tA10HEH tAS10 VA10 High to Chip Enable High (Set)
tA10LEH tAS10 VA10 Low to Chip Enable High (Reset)
tEXA10X tAH10 Chip Enable Transition to VA10 Transition
tEXVPX
tVPH Chip Enable Transition to VPP Transition
tVPXA9X tAH9 VPP Transition to VA9 Transition
1. TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
.
16/23
M27V322
DC and AC parameters
Figure 8.
Programming and Verify modes AC waveforms
VALID
A0-A20
tAVEL
tEHAX
Q0-Q15
DATA IN
DATA OUT
tQVEL
tVCHEL
tVPHEL
tEHQX
tEHQZ
V
CC
tEHVPX
tELQV
GV
PP
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI02205
1. BYTE = VIH
.
(1) (2)
Table 11. Programming mode AC characteristics
Test
Condition
Symbol
Alt
Parameter
Min
Max
Unit
tAVEL
tQVEL
tAS
tDS
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
1
1
µs
µs
µs
µs
ns
tVCHEL
tVPHEL
tVPLVPH
tVCS VCC High to Chip Enable Low
tOES VPP High to Chip Enable Low
tPRT VPP Rise Time
2
1
50
Chip Enable Program Pulse Width
(Initial)
tELEH
tPW
45
55
µs
tEHQX
tEHVPX
tVPLEL
tELQV
tDH
Chip Enable High to Input Transition
2
2
1
µs
µs
µs
µs
ns
ns
tOEH Chip Enable High to VPP Transition
tVR
tDV
VPP Low to Chip Enable Low
Chip Enable Low to Output Valid
1
(3)
tEHQZ
tDFP Chip Enable High to Output Hi-Z
tAH Chip Enable High to Address Transition
0
0
130
tEHAX
1.
TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V
2. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP
3. Sampled only, not 100% tested.
.
17/23
Package mechanical
M27V322
5
Package mechanical
Figure 9.
FDIP42W - 42 pin Ceramic Frit-seal DIP, with window (0.315" × 0.630"),
package outline
A2
A3
A
L
A1
e1
α
B1
B
C
eA
eB
D2
D
S
N
K
E1
E
1
K1
FDIPW-b
1. Drawing is not to scale.
Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window (0.315" × 0.630"),
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
A3
B
5.72
1.40
4.57
4.50
0.56
–
0.225
0.055
0.180
0.177
0.022
–
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
54.41
–
0.30
54.86
–
0.009
2.142
–
0.012
2.160
–
D
D2
E
50.80
15.24
2.000
0.600
–
–
–
–
E1
e
14.50
–
14.90
–
0.571
–
0.587
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
4.10
2.49
–
0.637
0.125
0.060
–
0.710
0.161
0.098
–
S
K
8.00
0.315
0.630
K1
α
16.00
–
–
–
–
4°
11°
4°
11°
N
42
42
18/23
M27V322
Package mechanical
Figure 10. PDIP42 - 42 pin Plastic DIP, 600 mils width, package outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
1. Drawing is not to scale.
Table 13. PDIP42 - 42 pin Plastic DIP, 600 mils width, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
–
0.25
3.56
0.38
1.27
0.20
52.20
–
5.08
–
–
0.200
–
0.010
0.140
0.015
0.050
0.008
2.055
–
4.06
0.53
1.65
0.36
52.71
–
0.160
0.021
0.065
0.014
2.075
–
B1
C
D
D2
E
50.80
15.24
2.000
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.590
14.99
–
–
–
–
15.24
3.18
0.86
0°
17.78
3.43
1.37
10°
0.600
0.125
0.034
0°
0.700
0.135
0.054
10°
S
α
N
42
42
19/23
Package mechanical
M27V322
Figure 11. SDIP42 - 42 pin Shrink Plastic DIP, 600 mils width, package outline
A2
A1
A
L
c
b2
b
e
eA
eB
D2
D
S
N
1
E1
E
SDIP
1. Drawing is not to scale.
Table 14. SDIP42 - 42 lead Shrink Plastic DIP, 600 mils width, package mechanical
data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
5.08
0.200
0.51
3.05
0.38
0.89
0.23
36.58
–
0.020
0.120
0.015
0.035
0.009
1.440
–
3.81
0.46
4.57
0.56
1.14
0.38
37.08
–
0.150
0.018
0.040
0.010
1.450
1.402
0.070
0.180
0.022
0.045
0.015
1.460
–
b2
c
1.02
0.25
D
36.83
35.60
1.78
D2
e
–
–
–
–
E
15.24
12.70
16.00
14.48
0.600
0.500
0.630
0.570
E1
eA
eB
L
13.72
15.24
0.540
0.600
18.54
3.56
0.730
0.140
3.30
0.64
2.54
42
0.130
0.025
0.100
42
S
N
20/23
M27V322
Part numbering
6
Part numbering
Table 15. Ordering information scheme
Example:
M27V322
-100 X
F
1
Device Type
M27
Supply Voltage
V = 3.3V ±10%
Device Function
322 = 32 Mbit (2Mb x16)
Speed
-100 = 100 ns(1)
-120 = 120 ns
-150 = 150 ns
VCC Tolerance
blank = 3.3V ±10%
X = 3.3V ±5%
Package
F = FDIP42W
B = PDIP42
S = SDIP42
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.
21/23
Revision history
M27V322
7
Revision history
Table 16. Document revision history
Date
Revision
Revision Details
July 1999
0.1
First Issue
Programming Flowchart changed (Figure 3)
02/09/00
03/01/01
1
2
PRESTO III Programming Algorithm paragraph changed
FDIP42W Package Dimension, L Max added (Table 12)
SDIP42 Package added (Figure 11, Table 14)
Document converted to new template (sections added, information
moved).
Packages are ECOPACK® compliant. SDIP42 package specifications
updated (see Table 14 and Figure 11).
22-May-2006
3
22/23
M27V322
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23/23
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