M27V401-200N6 [STMICROELECTRONICS]

512KX8 OTPROM, 200ns, PDSO32, 8 X 20 MM, PLASTIC, TSOP-32;


型号：	M27V401-200N6
厂家：	ST
描述：	512KX8 OTPROM, 200ns, PDSO32, 8 X 20 MM, PLASTIC, TSOP-32 可编程只读存储器 OTP只读存储器光电二极管内存集成电路
文件：	总15页 (文件大小：103K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M27V401

4 Mbit (512Kb x 8) Low Voltage UV EPROM and OTP EPROM

NOT FOR NEW DESIGN

■ M27V401 is replaced by the M27W401

■ 3V to 3.6V LOW VOLTAGE in READ

OPERATION

■ ACCESS TIME: 120ns

■ LOW POWER CONSUMPTION:

– Active Current 15mA at 5MHz

– Standby Current 20µA

FDIP32W (F)

PDIP32 (B)

■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■ PROGRAMMING TIME: 100µs/word

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 41h

PLCC32 (K)

TSOP32 (N)

8 x 20 mm

DESCRIPTION

The M27V401 is a low voltage 4 Mbit EPROM of-

fered in the two range UV (ultra violet erase) and

OTP (one time programmable). It is ideally suited

for microprocessor systems requiring large data or

program storage and is organised as 524,288 by 8

bits.

Figure 1. Logic Diagram

The M27V401 operates in the read mode with a

supply voltage as low as 3V. The decrease in op-

erating power allows either a reduction of the size

of the battery or an increase in the time between

battery recharges.

The FDIP32W (window ceramic frit-seal package)

has a transparent lid which allow the user to ex-

pose the chip to ultraviolet light to erase the bit pat-

tern. A new pattern can then be written to the

device by following the programming procedure.

A0-A18

Q0-Q7

M27V401

For applications where the content is programmed

only one time and erasure is not required, the

M27V401 is offered in PDIP32, PLCC32 and

TSOP32 (8 x 20 mm) packages.

AI00695B

July 2000

1/15

This is information on a product still in production but not recommended for new designs.

M27V401

Figure 2A. DIP Connections

Figure 2B. LCC Connections

A16

A15

A12

31 A18

30 A17

29 A14

28 A13

27 A8

1 32

A14

A13

26 A9

25 A11

M27V401

25 A11

23 A10

A2 10

A1 11

A0 12

Q0 13

Q1 14

Q2 15

A10

21 Q7

20 Q6

19 Q5

18 Q4

17 Q3

AI00696

AI01861

Figure 2C. TSOP Connections

Table 1. Signal Names

A0-A18

Q0-Q7

Address Inputs

Data Outputs

Chip Enable

Output Enable

A11

A10

A13

A14

A17

A18

Program Supply

Supply Voltage

Ground

M27V401

(Normal)

A16

A15

A12

AI01156B

2/15

M27V401

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

–40 to 125

–50 to 125

–65 to 150

–2 to 7

Unit

°C

(3)

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage (except A9)

Supply Voltage

BIAS

STG

(2)

–2 to 7

(2)

A9 Voltage

–2 to 13.5

–2 to 14

Program Supply Voltage

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

3. Depends on range.

+0.5V with possible overshoot to V +2V for a period less than 20ns.

Table 3. Operating Modes

Mode

Q7-Q0

Data Out

Hi-Z

or V

Read

Output Disable

Program

or V

Pulse

Data In

Data Out

Hi-Z

Verify

Program Inhibit

Standby

or V

Hi-Z

Electronic Signature

Codes

Note: X = V or V , V = 12V ± 0.5V.

IH IL ID

Table 4. Electronic Signature

Identifier

Manufacturer’s Code

Device Code

Hex Data

20h

41h

3/15

M27V401

Table 5. AC Measurement Conditions

High Speed

≤ 10ns

Standard

≤ 20ns

Input Rise and Fall Times

Input Pulse Voltages

0 to 3V

1.5V

0.4V to 2.4V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

1.3V

High Speed

1N914

1.5V

3.3kΩ

DEVICE

UNDER

TEST

OUT

Standard

2.4V

2.0V

0.8V

0.4V

= 30pF for High Speed

= 100pF for Standard

includes JIG capacitance

AI01822

AI01823B

(1)

Table 6. Capacitance

Symbol

(T = 25 °C, f = 1 MHz)

Parameter

Test Condition

Min

Max

Unit

= 0V

Input Capacitance

Output Capacitance

OUT

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

) is equal to the delay from E to output

). Data is available at the output after a delay

GLQV

AVQV

ELQV

of t

The operating modes of the M27V401 are listed in

the Operating Modes table. A single power supply

is required in the read mode. All inputs are TTL

from the falling edge of G, assuming that

E has been low and the addresses have been sta-

ble for at least t

-t

AVQV GLQV

levels except for V and 12V on A9 for Electronic

Signature.

Standby Mode

Read Mode

The M27V401 has a standby mode which reduces

the supply current from 15mA to 20µA with low

The M27V401 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (E) is the power

control and should be used for device selection.

Output Enable(G) is the output control and should

be used to gate data to the output pins, indepen-

dent of device selection. Assuming that the ad-

dresses are stable, the address access time

voltage operation V ≤ 3.6V, see Read Mode DC

Characteristics Table for details. The M27V401 is

placed in the standby mode by applying a CMOS

high signal to the E input. When in the standby

mode, the outputs are in a high impedance state,

independent of the G input.

4/15

M27V401

(1)

Table 7. Read Mode DC Characteristics

(T = 0 to 70 °C or –40 to 85°C; V = 3.3V ± 10%; V = V

)

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Max

±10

Unit

µA

0V ≤ V ≤ V

0V ≤ V

≤ V

OUT CC

µA

E = V , G = V , I

= 0mA,

IL OUT

Supply Current

f = 5MHz, V ≤ 3.6V

E = V

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

Program Current

µA

CC1

0.8

E > V – 0.2V, V ≤ 3.6V

CC2

= V

PP CC

Input Low Voltage

–0.3

(2)

+ 1

Input High Voltage

= 2.1mA

= –400µA

= –100µA

Output Low Voltage

0.4

Output High Voltage TTL

Output High Voltage CMOS

2.4

–0.7V

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Maximum DC voltage on Output is V +0.5V.

(1)

Table 8A. Read Mode AC Characteristics

(T = 0 to 70 °C or –40 to 85°C; V = 3.3V ± 10%; V = V )

M27V401

Symbol

Alt

Parameter

Test Condition

-120

-150

Unit

Min Max Min

Max

150

E = V , G = V

Address Valid to Output Valid

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

120

AVQV

ACC

G = V

ELQV

E = V

GLQV

(2)

G = V

EHQZ

E = V

Output Enable High to Output Hi-Z

GHQZ

Address Transition to Output

Transition

E = V , G = V

IL IL

AXQX

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Sampled only, not 100% tested.

Two Line Output Control

For the most efficient use of these two control

lines, Eshould be decoded and used as the prima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

Because EPROMs are usually used in larger

memory arrays, this product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

5/15

M27V401

(1)

Table 8B. Read Mode AC Characteristics

(T = 0 to 70°C or –40 to 85°C; V = 3.3V ± 10%; V = V

M27V401

Unit

Symbol

Alt

Parameter

Test Condition

-180

Max

-200

Min

Max

200

100

E = V , G = V

Address Valid to Output Valid

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

180

AVQV

ACC

G = V

ELQV

E = V

GLQV

(2)

G = V

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

EHQZ

E = V

GHQZ

Address Transition to Output

Transition

E = V , G = V

IL IL

AXQX

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

VALID

tGLQV

VALID

A0-A18

tAVQV

tAXQX

tEHQZ

tGHQZ

tELQV

Hi-Z

Q0-Q7

AI00724B

System Considerations

output control and by properly selected decoupling

capacitors. It is recommended that a 0.1µF ceram-

The power switching characteristics of Advanced

CMOS EPROMs requirecareful decoupling of the

devices. The supply current, I , has three seg-

ic capacitor be used on every device between V

and V . This should be a high frequency capaci-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-

tion, a 4.7µF bulk electrolytic capacitor should be

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

capacitive and inductive loading of the device at

the output. The associated transient voltage peaks

can be suppressed by complying with the two line

used between V and V for every eight devic-

es. The bulk capacitor should be located near the

power supply connection point. The purpose of the

bulk capacitor is to overcome the voltage drop

caused by the inductive effects of PCB traces.

6/15

M27V401

(1)

Table 9. Programming Mode DC Characteristics

(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)

Parameter

Symbol

Test Condition

Min

Max

±10

Unit

µA

≤ V ≤ V

Input Leakage Current

Supply Current

E = V

Program Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage TTL

A9 Voltage

–0.3

0.8

+ 0.5

= 2.1mA

0.4

= –400µA

2.4

11.5

12.5

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

(1)

Table 10. Programming Mode AC Characteristics

(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)

Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

µs

Address Valid to Program Low

Input Valid to Program Low

AVPL

QVPL

High to Program Low

VPHPL

VPS

VCS

CES

VCHPL

Chip Enable Low to Program Low

Program Pulse Width

ELPL

105

PLPH

Program High to Input Transition

Input Transition to Output Enable Low

Output Enable Low to Output Valid

PHQX

QXGL

GLQV

OES

100

130

(2)

Output Enable High to Output Hi-Z

DFP

GHQZ

Output Enable High to Address

Transition

GHAX

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Sampled only, not 100% tested.

Programming

Although only ’0’s will be programmed, both ’1’s

and ’0’s can be present in the data word. The only

way to change a ’0’ to a ’1’ is by die exposure to ul-

traviolet light (UV EPROM). The M27V401 is in the

The M27V401 has been designed to be fully com-

patible withthe M27C4001 and hasthe same elec-

tronic signature. As a result the M27V401 can be

programmed as the M27C4001 on the same pro-

gramming equipments applying 12.75V on V

and 6.25V on V by the use of the same PRES-

TO II algorithm. When delivered (and after each

erasure for UV EPROM), all bits of the M27V401

are in the ’1’ state. Data is introduced by selective-

ly programming ’0’s into the desired bit locations.

programming mode when V input is at 12.75V,

G at V and E is pulsed to V . The data to be pro-

grammed is applied to 8 bits in parallel to the data

output pins. The levels required for the address

and data inputs are TTL. V

6.25V ± 0.25V.

is specified to be

7/15

M27V401

Figure 6. Programming and Verify Modes AC Waveforms

VALID

A0-A18

tAVPL

Q0-Q7

DATA OUT

DATA IN

tQVEL

tEHQX

tVPHEL

tGLQV

tGHQZ

tGHAX

tVCHEL

tELEH

tQXGL

PROGRAM

VERIFY

AI00725

Figure 7. Programming Flowchart

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the

whole array to be programmed, with a guaranteed

margin, in a typical time of 52.5 seconds. Pro-

gramming with PRESTO II involves in applying a

sequence of 100µs program pulses to each byte

until a correct verify occurs (see Figure 7). During

programming and verify operation, a MARGIN

MODE circuit is automatically activated in order to

guarantee that each cell is programmed with

enough margin. No overprogram pulse is applied

= 6.25V, V

= 12.75V

n = 0

E = 100µs Pulse

since the verify in MARGIN MODE at V

much

higher than 3.6V provides necessary margin to

each programmed cell.

Program Inhibit

++n

= 25

VERIFY

YES

++ Addr

Programming of multiple M27V401s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs including G of the parallel

M27V401 may be common. A TTL low level pulse

YES

Last

FAIL

Addr

applied to a M27V401’s E input with V

YES

12.75V, will program that M27V401. A high level E

input inhibits the other M27V401s from being pro-

grammed.

CHECK ALL BYTES

1st: V

2nd: V

= 6V

= 4.2V

Program Verify

A verify (read) should be performed on the pro-

grammed bits to determine that they were correct-

ly programmed. The verify is accomplished with G

AI00760B

at V , E at V , V at 12.75V and V at 6.25V.

8/15

M27V401

Electronic Signature

ERASURE OPERATION (applies to UV EPROM)

The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that

will identify its manufacturer and type. This mode

is intended for use by programming equipment to

automatically match the device to be programmed

with its corresponding programming algorithm.

The ES mode is functional in the 25°C ± 5°C am-

bient temperature range that is required when pro-

gramming theM27V401. To activate the ES mode,

the programming equipment must force 11.5V to

12.5V on address line A9 of the M27V401, with

The erasure characteristics of the M27V401 is

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000Å. Itshould be noted that sunlight

and some type of fluorescent lamps have wave-

lengths in the 3000-4000Å range. Research

shows that constant exposure to room level fluo-

rescent lighting could erase a typical M27V401 in

about 3 years, while it would take approximately 1

week to cause erasure when exposed to direct

sunlight. If the M27V401 is to be exposed to these

types of lighting conditions for extended periods of

time, it is suggested that opaque labels be put over

the M27V401 window to prevent unintentional era-

sure. The recommended erasure procedure for

the M27V401 is exposure to short wave ultraviolet

light which has a wavelength of 2537Å. The inte-

grated dose (i.e. UV intensity x exposure time) for

= V = 5V. Two identifier bytes may then be

sequenced from the device outputs by toggling ad-

dress line A0 from V to V . All other address

lines must be held at V during Electronic Signa-

ture mode.

Byte 0 (A0 = V ) represents the manufacturer

code and byte 1 (A0 = V ) the device identifier

erasure should be a minimum of 15 W-sec/cm .

code. Forthe STMicroelectronics M27V401, these

two identifier bytes are given inTable 4 and can be

read-out on outputs Q7 to Q0. Note that the

M27V401 and M27C4001 have thesame identifier

bytes.

The erasure time with this dosage is approximate-

ly 15 to 20 minutes using an ultraviolet lamp with

12000µW/cm power rating. The M27V401 should

be placed within 2.5 cm (1 inch) of the lamp tubes

during the erasure. Some lamps have a filter on

their tubes which should be removed before era-

sure.

9/15

M27V401

Table 11. Ordering Information Scheme

Example:

M27V401

-120 K

Device Type

M27

Supply Voltage

V = 3V to 3.6V

Device Function

401 = 4 Mbit (512Kb x 8)

Speed

-120 = 120 ns

-150 = 150 ns

-180 = 180 ns

-200 = 200 ns

Package

F = FDIP32W

B = PDIP32

K = PLCC32

N = TSOP32: 8 x 20 mm

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Options

TR = Tape & Reel Packing

M27V401 is replaced by the M27W401

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

10/15

M27V401

Table 12. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

inches

Symb

Typ

Min

Max

5.72

1.40

4.57

4.50

0.56

–

Typ

Min

Max

0.225

0.055

0.180

0.177

0.022

–

0.51

3.91

3.89

0.41

–

0.020

0.154

0.153

0.016

–

1.45

0.057

0.23

41.73

–

0.30

42.04

–

0.009

1.643

–

0.012

1.655

–

38.10

15.24

1.500

0.600

–

13.06

–

13.36

–

0.514

–

0.526

–

2.54

0.100

0.590

14.99

–

16.18

3.18

1.52

–

18.03

0.637

0.125

0.060

–

0.710

2.49

–

0.098

–

7.11

0.280

4°

11°

4°

11°

Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline

FDIPW-a

Drawing is not to scale.

11/15

M27V401

Table 13. PDIP32 - 32 pin lead Plastic DIP, 600 mils width, Package Mechanical Data

Min

–

inches

Min

–

Symb

Typ

Max

5.08

–

Typ

Max

0.200

–

0.38

3.56

0.38

–

0.015

0.140

0.015

–

4.06

0.51

–

0.160

0.020

–

1.52

0.060

0.20

41.78

–

0.30

42.04

–

0.008

1.645

–

0.012

1.655

–

38.10

15.24

1.500

0.600

–

13.59

–

13.84

–

0.535

–

0.545

–

2.54

0.100

0.600

15.24

–

15.24

3.18

1.78

0°

17.78

3.43

2.03

10°

0.600

0.125

0.070

0°

0.700

0.135

0.080

10°

Figure 9. PDIP32 - 32 pin lead Plastic DIP, 600 mils width, Package Outline

PDIP

Drawing is not to scale.

12/15

M27V401

Table 14. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data

Min

2.54

1.52

0.38

0.33

0.66

12.32

11.35

9.91

14.86

13.89

12.45

–

inches

Symb

Typ

Max

3.56

2.41

–

Typ

Min

Max

0.140

0.095

–

0.100

0.060

0.015

0.013

0.026

0.485

0.447

0.390

0.585

0.547

0.490

–

0.53

0.81

12.57

11.56

10.92

15.11

14.10

13.46

–

0.021

0.032

0.495

0.455

0.430

0.595

0.555

0.530

–

1.27

0.89

0.050

0.035

0.00

–

0.25

–

0.000

–

0.010

–

0.10

0.004

Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline

1 N

E1 E

D2/E2

0.51 (.020)

1.14 (.045)

PLCC

Drawing is not to scale.

13/15

M27V401

Table 15. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

8.10

–

Typ

Max

0.047

0.007

0.041

0.011

0.008

0.795

0.728

0.319

–

0.05

0.95

0.15

0.10

19.80

18.30

7.90

–

0.002

0.037

0.006

0.004

0.780

0.720

0.311

–

0.50

0.020

0.50

0°

0.70

5°

0.020

0°

0.028

5°

0.10

0.004

Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline

N/2

DIE

TSOP-a

Drawing is not to scale

14/15

M27V401

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

15/15

M27V401-200N6 [STMICROELECTRONICS]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E