M27W201-80N6TR [STMICROELECTRONICS]

2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM; 2兆的256Kb ×8低压UV EPROM和OTP EPROM


型号：	M27W201-80N6TR
厂家：	ST
描述：	2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM 2兆的256Kb ×8低压UV EPROM和OTP EPROM 存储内存集成电路光电二极管可编程只读存储器 OTP只读存储器电动程控只读存储器
文件：	总16页 (文件大小：173K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M27W201

2 Mbit (256Kb x 8) Low Voltage UV EPROM and OTP EPROM

■ 2.7V to 3.6V LOW VOLTAGE in READ

OPERATION

■ ACCESS TIME:

– 70ns at V = 3.0V to 3.6V

– 80ns at V = 2.7V to 3.6V

■ PIN COMPATIBLE with M27C2001

■ LOW POWER CONSUMPTION:

– 15µA max Standby Current

FDIP32W (F)

PDIP32 (B)

– 15mA max Active Current at 5MHz

■ PROGRAMMING TIME 100µs/byte

■ HIGH RELIABILITY CMOS TECHNOLOGY

– 2,000V ESD Protection

PLCC32 (K)

TSOP32 (N)

8 x 20 mm

– 200mA Latchup Protection Immunity

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code: 61h

DESCRIPTION

TSOP32 (NZ)

8 x 14 mm

The M27W201 is a low voltage 2 Mbit EPROM of-

fered in the two range UV (ultra violet erase) and

OTP (one time programmable). It is ideally suited

for microprocessor systems requiring large data or

program storage and is organised as 262,144 by 8

bits.

The M27W201 operates in the read mode with a

supply voltage as low as 2.7V at –40 to 85°C tem-

perature range. The decrease in operating power

allows either a reduction of the size of the battery

or an increase in the time between battery re-

charges.

Figure 1. Logic Diagram

A0-A17

Q0-Q7

The FDIP32W (window ceramic frit-seal package)

has a transparent lid which allows the user to ex-

pose the chip to ultraviolet light to erase the bit pat-

tern. A new pattern can then be written to the

device by following the programming procedure.

M27W201

For application where the content is programmed

only one time and erasure is not required, the

M27W201 is offered in PDIP32, PLCC32 and

TSOP32 (8 x 20mm and 8 x 14mm) packages.

AI01359

October 2001

1/16

M27W201

Figure 2A. DIP Connections

Figure 2B. LCC Connections

A16

A15

A12

30 A17

29 A14

28 A13

27 A8

1 32

A14

A13

26 A9

25 A11

M27W201

25 A11

23 A10

A2 10

A1 11

A0 12

Q0 13

Q1 14

Q2 15

A10

21 Q7

20 Q6

19 Q5

18 Q4

17 Q3

AI01360

AI02675

Figure 2C. TSOP Connections

Table 1. Signal Names

A0-A17

Address Inputs

Q0-Q7

Data Outputs

Chip Enable

Output Enable

Program

A11

A10

A13

A14

A17

Program Supply

Supply Voltage

Ground

M27W201

A16

A15

A12

AI01361

2/16

M27W201

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

–40 to 125

–50 to 125

–65 to 150

–2 to 7

Unit

°C

(3)

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltage (except A9)

Supply Voltage

BIAS

STG

(2)

–2 to 7

(2)

A9 Voltage

–2 to 13.5

–2 to 14

Program Supply Voltage

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC

voltage on Output is V

3. Depends on range.

+0.5V with possible overshoot to V

+2V for a period less than 20ns.

Table 3. Operating Modes

Mode

Q7-Q0

Data Out

Hi-Z

or V

Read

Output Disable

Program

Pulse

Data In

Data Out

Hi-Z

Verify

Program Inhibit

Standby

or V

CC SS

Hi-Z

Electronic Signature

Codes

Note: X = V or V , V = 12V ± 0.5V.

IH IL ID

Table 4. Electronic Signature

Identifier

Manufacturer’s Code

Device Code

Hex Data

20h

61h

3/16

M27W201

Table 5. AC Measurement Conditions

High Speed

≤ 10ns

Standard

≤ 20ns

Input Rise and Fall Times

Input Pulse Voltages

0 to 3V

1.5V

0.4V to 2.4V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

1.3V

High Speed

1N914

1.5V

3.3kΩ

DEVICE

UNDER

TEST

OUT

Standard

2.4V

2.0V

0.8V

0.4V

= 30pF for High Speed

= 100pF for Standard

includes JIG capacitance

AI01822

AI01823B

(1)

Table 6. Capacitance

Symbol

(T = 25 °C, f = 1 MHz)

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

Unit

= 0V

OUT

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION

of t

) is equal to the delay from E to output

). Data is available at the output after a delay

AVQV

ELQV

The operating modes of the M27W201 are listed in

the Operating Modes table. A single power supply

is required in the read mode. All inputs are TTL

from the falling edge of G, assuming that

GLQV

E has been low and the addresses have been sta-

ble for at least t

-t

AVQV GLQV

levels except for V and 12V on A9 for Electronic

Signature.

Standby Mode

Read Mode

The M27W201 has a standby mode which reduc-

es the supply current from 15mA to 15µA with low

The M27W201 has two control functions, both of

which must be logically active in order to obtain

data at the outputs. Chip Enable (E) is the power

control and should be used for device selection.

Output Enable (G) is the output control and should

be used to gate data to the output pins, indepen-

dent of device selection. Assuming that the ad-

dresses are stable, the address access time

voltage operation V ≤ 3.6V, see Read Mode DC

Characteristics table for details.The M27W201 is

placed in the standby mode by applying a CMOS

high signal to the E input. When in the standby

mode, the outputs are in a high impedance state,

independent of the G input.

4/16

M27W201

(1)

Table 7. Read Mode DC Characteristics

(T = –40 to 85 °C; V = 2.7V to 3.6V; V = V

)

Symbol

Parameter

Test Condition

Min

Max

Unit

µA

Input Leakage Current

Output Leakage Current

±10

0V ≤ V ≤ V

OUT CC

µA

E = V , G = V ,

= 0mA, f = 5MHz

OUT

Supply Current

≤ 3.6V

E = V

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

µA

E > V – 0.2V

≤ 3.6V

= V

Program Current

µA

0.2 V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage TTL

–0.6

(2)

0.7 V

+ 0.5

= 2.1mA

0.4

= –400µA

2.4

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Maximum DC voltage on Output is V +0.5V.

Two Line Output Control

System Considerations

Because EPROMs are usually used in larger

memory arrays, this product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the prima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupling of the

devices. The supply current, I , has three seg-

ments that are of interest to the system designer:

the standby current level, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

capacitive and inductive loading of the device at

the output.

The associated transient voltage peaks can be

suppressed by complying with the two line output

control and by properly selected decoupling ca-

pacitors. It is recommended that a 0.1µF ceramic

capacitor be used on every device between V

and V . This should be a high frequency capaci-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-

tion, a 4.7µF bulk electrolytic capacitor should be

used between V and V for every eight devic-

es. The bulk capacitor should be located near the

power supply connection point. The purpose of the

bulk capacitor is to overcome the voltage drop

caused by the inductive effects of PCB traces.

5/16

M27W201

(1)

Table 8. Read Mode AC Characteristics

(T = –40 to 85 °C; V = 2.7V to 3.6V; V = V

)

M27W201

-100

(-120/-150/-200)

(3)

-80

Test

Condition

Symbol Alt

Parameter

Unit

= 3.0V to 3.6V V = 2.7V to 3.6V V = 2.7V to 3.6V

CC CC

Min

Max

Min

Max

Min

Max

E = V ,

Address Valid to

Output Valid

ACC

100

AVQV

G = V

Chip Enable Low to

Output Valid

G = V

100

ELQV

Output Enable Low

to Output Valid

E = V

GLQV

Chip Enable High to

Output Hi-Z

(2)

G = V

EHQZ

Output Enable High

to Output Hi-Z

(2)

E = V

GHQZ

E = V ,

Address Transition

to Output Transition

AXQX

G = V

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditions.

Figure 5. Read Mode AC Waveforms

VALID

A0-A17

tAVQV

tAXQX

tEHQZ

tGHQZ

tGLQV

tELQV

Hi-Z

Q0-Q7

AI00719B

6/16

M27W201

(1)

Table 9. Programming Mode DC Characteristics

(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)

Symbol

Parameter

Test Condition

Min

Max

±10

Unit

µA

0 ≤ V ≤ V

Input Leakage Current

Supply Current

E = V

Program Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage TTL

A9 Voltage

–0.3

0.8

+ 0.5

= 2.1mA

0.4

= –400µA

2.4

11.5

12.5

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

(1)

Table 10. Programming Mode AC Characteristics

(T = 25 °C; V = 6.25V ± 0.25V; V = 12.75V ± 0.25V)

Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

µs

Address Valid to Program Low

Input Valid to Program Low

AVPL

QVPL

High to Program Low

VPHPL

VPS

VCS

CES

VCHPL

Chip Enable Low to Program Low

Program Pulse Width

ELPL

105

PLPH

Program High to Input Transition

Input Transition to Output Enable Low

Output Enable Low to Output Valid

Output Enable High to Output Hi-Z

PHQX

QXGL

GLQV

OES

100

130

(2)

DFP

GHQZ

Output Enable High to Address

Transition

GHAX

Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .

2. Sampled only, not 100% tested.

Programming

ming '0's into the desired bit locations. Although

only '0's will be programmed, both '1's and '0's can

be present in the data word. The only way to

change a ‘0’ to a ‘1’ is by die exposure to ultraviolet

light (UV EPROM). The M27W201 is in the pro-

The M27W201 has been designed to be fully com-

patible with the M27C2001 and has the same elec-

tronic signature. As a result the M27W201 can be

programmed as the M27C2001 on the same pro-

gramming mode when V input is at 12.75V, E is

gramming equipment applying 12.75V on V and

at V and P is pulsed to V . The data to be pro-

6.25V on V

algorithm.

by the use of the same PRESTO II

grammed is applied to 8 bits in parallel to the data

output pins. The levels required for the address

When delivered (and after each ‘1’s erasure for UV

EPROM), all bits of the M27W201 are in the '1'

state.Data is introduced by selectively program-

and data inputs are TTL. V

6.25V ± 0.25V.

is specified to be

7/16

M27W201

Figure 6. Programming and Verify Modes AC Waveforms

VALID

A0-A17

tAVPL

Q0-Q7

DATA IN

DATA OUT

tQVPL

tVPHPL

tVCHPL

tELPL

tPHQX

tGLQV

tGHQZ

tGHAX

tPLPH

tQXGL

PROGRAM

VERIFY

AI00720

Figure 7. Programming Flowchart

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the

whole array to be programmed with a guaranteed

margin, in a typical time of 26.5 seconds. Pro-

gramming with PRESTO II consists of applying a

sequence of 100µs program pulses to each byte

until a correct verify occurs (see Figure 7). During

programming and verify operation, a MARGIN

MODE circuit is automatically activated in order to

guarantee that each cell is programmed with

enough margin. No overprogram pulse is applied

= 6.25V, V

= 12.75V

n = 0

P = 100µs Pulse

since the verify in MARGIN MODE at V

much

higher than 3.6V, provides the necessary margin

to each programmed cell.

Program Inhibit

++n

= 25

VERIFY

YES

++ Addr

YES

Programming of multiple M27W201s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs including G of the parallel

M27W201 may be common. A TTL low level pulse

applied to a M27W201's P input, with E low and

Last

Addr

FAIL

YES

at 12.75V, will program that M27W201. A high

CHECK ALL BYTES

level E input inhibits the other M27W201s from be-

ing programmed.

1st: V

= 5V

2nd: V

= 2.7V

Program Verify

A verify (read) should be performed on the pro-

grammed bits to determine that they were correct-

ly programmed. The verify is accomplished with E

AI00715D

and G at V , P at V , V at 12.75V and V at

6.25V.

8/16

M27W201

Electronic Signature

ERASURE OPERATION (applies to UV EPROM)

The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that

will identify its manufacturer and type. This mode

is intended for use by programming equipment to

automatically match the device to be programmed

with its corresponding programming algorithm.

The ES mode is functional in the 25°C ± 5°C am-

bient temperature range that is required when pro-

gramming the M27W201. To activate the ES

mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the

The erasure characteristics of the M27W201 are

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000 Å. It should be noted that

sunlight and some type of fluorescent lamps have

wavelengths in the 3000-4000 Å range. Data

shows that constant exposure to room level fluo-

rescent lighting could erase a typical M27W201 in

about 3 years, while it would take approximately 1

week to cause erasure when exposed to direct

sunlight. If the M27W201 is to be exposed to these

types of lighting conditions for extended periods of

time, it is suggested that opaque labels be put over

the M27W201 window to prevent unintentional

erasure. The recommended erasure procedure for

the M27W201 is exposure to short wave ultraviolet

light which has wavelength of 2537 Å. The inte-

grated dose (i.e. UV intensity x exposure time) for

M27W201 with V = V

= 5V. Two identifier

bytes may then be sequenced from the device out-

puts by toggling address line A0 from V to V . All

other address lines must be held at V during

Electronic Signature mode. Byte 0 (A0 = V )

repres ents the manufacturer code and byte 1

(A0 = V ) the device identifier code. For the ST-

Microelectronics M27W201, these two identifier

bytes are given in Table 4 and can be read-out on

outputs Q7 to Q0. Note that the M27W201 and

M27C2001 have the same identifier byte.

erasure should be a minimum of 15 W-sec/cm .

The erasure time with this dosage is approximate-

ly 15 to 20 minutes using an ultraviolet lamp with

12000 µW/cm power rating. The M27W201

should be placed within 2.5 cm (1 inch) of the lamp

tubes during the erasure. Some lamps have a filter

on their tubes which should be removed before

erasure.

9/16

M27W201

Table 11. Ordering Information Scheme

Example:

M27W201

-80

Device Type

M27

Supply Voltage

W = 2.7V to 3.6V

Device Function

201 = 2 Mbit (256Kb x 8)

Speed

(1,2)

-80

= 80 ns

-100 = 100 ns

(3)

Not For New Design

-120 = 120 ns

-150 = 150 ns

-200 = 200 ns

Package

(4)

F = FDIP32W

B = PDIP32

K = PLCC32

(4)

N = TSOP32: 8 x 20 mm

(4)

NZ = TSOP32: 8 x 14 mm

Temperature Range

6 = –40 to 85 °C

Options

TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

2. This speed also guarantees 70ns access time at V

3. These speeds are replaced by the 100ns.

= 3.0V to 3.6V.

4. Packages option available on request. Please contact STMicroelectronics local Sales Office.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

Table 12. Revision History

Date

July 1999

Version

Revision Details

-01

First Issue

FDIP32W Package Dimension, L Max added (Table 13)

TSOP32 Package Dimension changed (Table 16)

0 to 70°C Temperature Range deleted, Programming Time changed

19-Apr-2000

24-Oct-2001

-02

-03

TSOP32 8x14mm added

10/16

M27W201

Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

5.72

1.40

4.57

4.50

0.56

–

Typ

Max

0.225

0.055

0.180

0.177

0.022

–

0.51

3.91

3.89

0.41

–

0.020

0.154

0.153

0.016

–

1.45

0.057

0.23

41.73

–

0.30

42.04

–

0.009

1.643

–

0.012

1.655

–

38.10

15.24

1.500

0.600

–

13.06

–

13.36

–

0.514

–

0.526

–

2.54

0.100

0.590

14.99

–

16.18

3.18

1.52

–

18.03

4.10

2.49

–

0.637

0.125

0.060

–

0.710

0.161

0.098

–

7.11

0.280

4°

11°

4°

11°

Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline

FDIPW-a

Drawing is not to scale.

11/16

M27W201

Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data

millimeters

inches

Min

–

Symbol

Typ

Min

–

Max

5.08

–

Typ

Max

0.200

–

0.38

3.56

0.38

–

0.015

0.140

0.015

–

4.06

0.51

–

0.160

0.020

–

1.52

0.060

0.20

41.78

–

0.30

42.04

–

0.008

1.645

–

0.012

1.655

–

38.10

15.24

1.500

0.600

–

13.59

–

13.84

–

0.535

–

0.545

–

2.54

0.100

0.600

15.24

–

15.24

3.18

1.78

0°

17.78

3.43

2.03

10°

0.600

0.125

0.070

0°

0.700

0.135

0.080

10°

Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline

PDIP

Drawing is not to scale.

12/16

M27W201

Table 15. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Mechanical Data

millimeters

inches

Symbol

Typ

Min

Max

3.56

2.41

Typ

Min

Max

0.140

0.095

2.54

0.100

0.060

0.015

0.013

0.026

0.485

0.447

0.390

1.52

0.38

0.33

0.53

0.81

0.021

0.032

0.495

0.455

0.430

0.66

12.32

11.35

9.91

12.57

11.56

10.92

1.27

0.89

0.050

0.035

14.86

13.89

12.45

0.00

15.11

14.10

13.46

0.25

0.585

0.547

0.490

0.000

0.595

0.555

0.530

0.010

0.10

0.004

Figure 10. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular, Package Outline

1 N

E1 E

D2/E2

0.51 (.020)

1.14 (.045)

PLCC

Drawing is not to scale.

13/16

M27W201

Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

20.200

18.500

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

–

0.050

0.950

0.150

0.100

19.800

18.300

–

0.0020

0.0374

0.0059

0.0039

0.7795

0.7205

–

0.500

0.0197

7.900

0.500

0°

8.100

0.700

5°

0.3110

0.0197

0°

0.3189

0.0276

5°

0.100

0.0039

Figure 11. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline

N/2

DIE

TSOP-a

Drawing is not to scale.

14/16

M27W201

Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14 mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

14.200

12.500

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.5591

0.4921

–

0.050

0.950

0.170

0.100

13.800

12.300

–

0.0020

0.0374

0.0067

0.0039

0.5433

0.4843

–

0.500

0.0197

7.900

0.500

0°

8.100

0.700

5°

0.3110

0.0197

0°

0.3189

0.0276

5°

0.100

0.0039

Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14 mm, Package Outline

N/2

DIE

TSOP-a

Drawing is not to scale.

15/16

M27W201

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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M27W201-80N6TR [STMICROELECTRONICS]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E