M28C16B-90K6TR [STMICROELECTRONICS]
2KX8 EEPROM 5V, 90ns, PQCC32, PLASTIC, LCC-32;
| 型号： | M28C16B-90K6TR |
| 厂家： | 
ST |
| 描述： | 2KX8 EEPROM 5V, 90ns, PQCC32, PLASTIC, LCC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28C16B
M28C17B
16 Kbit (2K x 8) Parallel EEPROM
With Software Data Protection
NOT FOR NEW DESIGN
■ Fast Access Time: 90 ns at V =5V
CC
■ Single Supply Voltage:
– 4.5 V to 5.5 V for M28CxxB
– 2.7 V to 3.6 V for M28CxxB-W
■ Low Power Consumption
■ Fast BYTE and PAGE WRITE (up to 64 Bytes)
– 3 ms at V =4.5 V
CC
– 5 ms at V =2.7 V
CC
■ Enhanced Write Detection and Monitoring:
– Data Polling
PLCC32 (K)
– Toggle Bit
– Page Load Timer Status
■ JEDEC Approved Bytewide Pin-Out
■ Software Data Protection
■ 100000 Erase/Write Cycles (minimum)
■ Data Retention (minimum): 40 Years
DESCRIPTION
The M28C16B and M28C17B devices consist of
2048x8 bits of low power, parallel EEPROM, fabri-
cated with STMicroelectronics’ proprietary single
polysilicon CMOS technology. The devices offer
fast access time, with low power dissipation, and
require a single voltage supply.
Figure 1. Logic Diagram
V
CC
Table 1. Signal Names
11
8
A0-A10
Address Input
A0-A10
DQ0-DQ7
DQ0-DQ7
Data Input / Output
Write Enable
W
E
W
E
M28C16B
M28C17B
Chip Enable
RB
G
Output Enable
Ready/Busy (M28C17B only)
Supply Voltage
Ground
(M28C17B only)
G
RB
V
CC
V
SS
V
SS
AI02816
April 2001
1/17
This is information on a product still in production but not recommended for new designs.
M28C16B, M28C17B
Figure 2A. PLLC Connections
Figure 2B. PLLC Connections
1 32
1 32
A6
A8
A6
A8
A5
A4
A3
A9
A5
A4
A3
A9
NC
NC
G
NC
NC
G
A2
A1
9
M28C16B
25
A2
A1
9
M28C17B
25
A10
E
A10
E
A0
A0
NC
DQ7
DQ6
NC
DQ7
DQ6
DQ0
DQ0
17
17
AI02817
AI02830
Note: 1. NC = Not Connected
Note: 1. NC = Not Connected
The M28C17B is like the M28C16B in every way,
except that it has an extra ready/busy (RB) output.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V comparator in-
The device has been designed to offer a flexible
microcontroller interface, featuring software hand-
shaking, with Data Polling and Toggle Bit. The de-
vice supports a 64 byte Page Write operation.
Software Data Protection (SDP) is also supported,
using the standard JEDEC algorithm.
CC
hibits the Write operations if the V
voltage is
CC
lower than V (see Table 4A). Once the voltage
WI
applied on the V
pin goes over the V thresh-
CC
WI
old (V >V ), write access to the memory is al-
CC
WI
lowed after a time-out t
4A.
Further protection against data corruption is of-
fered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
, as specified in Table
PUW
SIGNAL DESCRIPTION
The external connections to the device are sum-
marized in Table 1, and their use in Table 3.
Addresses (A0-A10). The address inputs are
used to select one byte from the memory array
during a read or write operation.
Read
Data In/Out (DQ0-DQ7). The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E). The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G). The Output Enable input con-
trols the data output buffers, and is used to initiate
read operations.
Write Enable (W). The Write Enable input controls
whether the addressed location is to be read, from
or written to.
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 11 and Figure 12). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first). Af-
ter a delay, t
, that cannot be shorter than the
WLQ5H
Ready/Busy (RB). Ready/Busy (on the M28C17B
only) is an open drain output that can be used to
detect the end of the internal write cycle.
value specified in Table 10A, the internal write cy-
cle starts. It continues, under internal timing con-
trol, until the write operation is complete. The
commencement of this period can be detected by
reading the Page Load Timer Status on DQ5. The
2/17
M28C16B, M28C17B
1
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
-40 to 125
-65 to 150
-0.3 to 6.5
-0.6 to VCC+0.6
-0.3 to 6.5
4000
Unit
°C
°C
V
TA
TSTG
VCC
VIO
Ambient Operating Temperature
Storage Temperature
Supply Voltage
Input or Output Voltage
Input Voltage
V
VI
V
2
VESD
V
Electrostatic Discharge Voltage (Human Body model)
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
Figure 3. Block Diagram
E
G
W
V
GEN
RESET
CONTROL LOGIC
PP
ADDRESS
LATCH
A6-A10
(Page Address)
16K ARRAY
ADDRESS
LATCH
A0-A5
Y
DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD
TIMER STATUS
TOGGLE BIT
DATA POLLING
DQ0-DQ7
AI02818
3/17
M28C16B, M28C17B
1
Table 3. Operating Modes
Mode
E
1
X
X
0
0
0
G
X
1
W
X
X
1
DQ0-DQ7
Hi-Z
Stand-by
Output Disable
Write Disable
Read
Hi-Z
X
0
Hi-Z
1
Data Out
Data In
Hi-Z
Write
1
0
Chip Erase
V
0
Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V ± 5%.
end of the cycle can be detected by reading the
status of the Data Polling and the Toggle Bit func-
tions on DQ7 and DQ6.
Otherwise, the Page Write operation is not execut-
ed.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Page Write
The Page Write mode allows up to 64 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write op-
erations, no two of which are separated by more
Software Data Protection (SDP)
The device offers a software-controlled write-pro-
tection mechanism that allows the user to inhibit all
write operations to the device. This can be useful
for protecting the memory from inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).
By default, the device is shipped in the “unprotect-
ed” state: the memory contents can be freely
changed by the user. Once the Software Data Pro-
tection Mode is enabled, all write commands are
than the t
value (as specified in Table 10A).
WLQ5H
The page write can be initiated during any byte
write operation. Following the first byte write in-
struction the host may send another address and
data with a minimum data transfer rate of:
1/t
.
WLQ5H
The internal write cycle can start at any instant af-
ter t . Once initiated, the write operation is in-
WLQ5H
ternally timed, and continues, uninterrupted, until
completion.
All bytes must be located on the same page ad-
dress (A10-A6 must be the same for all bytes).
1
Table 4A. Power-Up Timing for M28CxxB (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
Parameter
Time Delay to Read Operation
Symbol
Min.
Max.
1
Unit
µs
t
PUR
t
Time Delay to Write Operation (once VCC ≥ VWI
)
10
ms
V
PUW
VWI
Write Inhibit Threshold
3.0
4.2
Note: 1. Sampled only, not 100% tested.
1
Table 4B. Power-Up Timing for M28CxxB-W (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
Parameter
Time Delay to Read Operation
Symbol
Min.
Max.
1
Unit
µs
t
PUR
t
Time Delay to Write Operation (once VCC ≥ VWI
)
15
ms
V
PUW
VWI
Write Inhibit Threshold
1.5
2.5
Note: 1. Sampled only, not 100% tested.
4/17
M28C16B, M28C17B
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Write AAh in
Write AAh in
Address 555h
Address 555h
Page Write
Timing
(see note 1)
Page Write
Timing
(see note 1)
Write 55h in
Address 2AAh
Write 55h in
Address 2AAh
Write A0h in
Write A0h in
Address 555h
Address 555h
Write
is Enabled
SDP is set
Physical
Page Write
Instruction
Page Write
(1 up to 64 bytes)
SDP Enable Algorithm
Write to Memory
When SDP is SET
AI02819
Note: 1. The most significant address bits (A10 to A6) differ during these specific Page Write operations.
ignored, and have no effect on the memory con-
tents.
The device remains in this mode until a valid Soft-
ware Data Protection disable sequence is re-
ceived. The device reverts to its “unprotected”
state.
ferent locations, as shown in Figure 6. This com-
plex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
The status of the Software Data Protection (en-
abled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.
Figure 6. Software Data Protection Disable
Algorithm
The Software Data Protection Enable command
consists of the writing of three specific data bytes
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the user has to write specific data bytes into six dif-
Write AAh in
Address 555h
Write 55h in
Address 2AAh
Write 80h in
Address 555h
Page Write
Figure 5. Status Bit Assignment
Timing
Write AAh in
Address 555h
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Write 55h in
Address 2AAh
DP
TB
PLTS Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write 20h in
Address 555h
DP
TB
= Data Polling
= Toggle Bit
PLTS = Page Load Timer Status
Hi-Z = High impedance
Unprotected State
AI02815
AI02820
5/17
M28C16B, M28C17B
Figure 7. Chip Erase AC Waveforms
tWHEH
E
G
tGLWH
W
tELWL
tWLWH2
tWHRH
AI01484B
1
Table 5. Chip Erase AC Characteristics
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V or 2.7 to 3.6 V)
A
CC
Symbol
Parameter
Test Condition
G = VCC + 7V
G = VCC + 7V
G = VCC + 7V
G = VCC + 7V
G = VCC + 7V
Min.
Max.
Unit
t
Chip Enable Low to Write Enable Low
Write Enable High to Chip Enable High
Write Enable Low to Write Enable High
Output Enable Low to Write Enable High
Write Enable High to Write Enable Low
1
0
µs
ns
ELWL
t
WHEH
t
10
1
ms
µs
WLWH2
t
GLWH
t
3
ms
WHRH
Note: 1. Sampled only, not 100% tested.
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from inad-
vertent use). The sequence is as shown in Figure
4. This consists of an unlock key, to enable the
write action, at the end of which the SDP continues
to be enabled. This allows the SDP to be enabled,
and data to be written, within a single Write cycle
once a byte or more has been latched into the
memory).
Data Polling bit (DQ7). The internally timed write
cycle starts after t
(defined in Table 10A)
WLQ5H
has elapsed since the previous byte was latched in
to the memory. The value of the DQ7 bit of this last
byte, is used as a signal throughout this write op-
eration: it is inverted while the internal write oper-
ation is underway, and is inverted back to its
original value once the operation is complete.
(t ).
WC
Software Chip Erase
The contents of the entire memory are erased (set
to FFh) by holding Chip Enable (E) low, and hold-
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first
read value being ’0’) on subsequent attempts to
read any byte of the memory. When the internal
write cycle is complete, the toggling is stopped,
and the values read on DQ7-DQ0 are those of the
addressed memory byte. This indicates that the
device is again available for new Read and Write
operations.
ing Output Enable (G) at V +7.0V. The chip is
CC
cleared when a 10 ms low pulse is applied to the
Write Enable (W) signal (see Figure 7 and Table 5
for details).
Status Bits
The devices provide three status bits (DQ7, DQ6
and DQ5), for use during write operations. These
allow the application to use the write time latency
of the device for getting on with other work. These
signals are available on the I/O port bits DQ7, DQ6
and DQ5 (but only during programming cycle,
Page Load Timer Status bit (DQ5). An internal
timer is used to measure the period between suc-
6/17
M28C16B, M28C17B
Table 6A. Read Mode DC Characteristics for M28CxxB (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0 V ≤ VIN ≤ VCC
Min.
Max.
10
10
30
25
1
Unit
µA
ILI
ILO
0 V ≤ VOUT ≤ VCC
µA
Supply Current (TTL inputs)
Supply Current (CMOS inputs)
Supply Current (Stand-by) TTL
E = VIL, G = VIL , f = 5 MHz
E = VIL, G = VIL , f = 5 MHz
mA
mA
mA
1
ICC
1
E = V
IH
ICC1
1
Supply Current (Stand-by) CMOS
Input Low Voltage
E > VCC - 0.3V
100
0.8
µA
V
ICC2
VIL
VIH
-0.3
2
V
CC + 0.5
Input High Voltage
V
VOL
VOH
I
OL = 2.1 mA
Output Low Voltage
0.4
V
I
OH = -400 µA
Output High Voltage
2.4
V
Note: 1. All inputs and outputs open circuit.
Table 6B. Read Mode DC Characteristics for M28CxxB-W (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
0 V ≤ VIN ≤ VCC
Min.
Max.
10
Unit
µA
µA
mA
mA
µA
V
ILI
ILO
0 V ≤ VOUT ≤ VCC
10
E = VIL, G = VIL , f = 5 MHz, VCC = 3.3V
E = VIL, G = VIL , f = 5 MHz, VCC = 3.6V
8
1
Supply Current (CMOS inputs)
ICC
10
1
Supply Current (Stand-by) CMOS
Input Low Voltage
E > VCC - 0.3V
20
ICC2
VIL
VIH
-0.3
2
0.6
Input High Voltage
VCC + 0.5
0.2 VCC
V
VOL
VOH
I
OL = 1.6 mA
Output Low Voltage
V
I
OH = -400 µA
0.8 VCC
Output High Voltage
V
Note: 1. All inputs and outputs open circuit.
cessive Write operations, up to t
(defined in
WLQ5H
Table 10A). The DQ5 line is held low to show
when this timer is running (hence showing that the
device has received one write operation, and is
waiting for the next). The DQ5 line is held high
when the counter has overflowed (hence showing
that the device is now starting the internal write to
the memory array).
7/17
M28C16B, M28C17B
1
Table 7. Input and Output Parameters (T = 25 °C, f = 1 MHz)
A
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min.
Max.
6
Unit
pF
VIN = 0 V
COUT
VOUT = 0 V
12
pF
Note: 1. Sampled only, not 100% tested.
Table 8. AC Measurement Conditions
Input Rise and Fall Times
≤ 20 ns
Input Pulse Voltages
0.4 V to 2.4 V
0.8 V to 2.0 V
Input and Output Timing Reference Voltages
Figure 8. AC Testing Input Output Waveforms
Figure 9. AC Testing Equivalent Load Circuit
I
OL
2.4V
DEVICE
UNDER
TEST
2.0V
0.8V
OUT
0.4V
I
OH
C
= 100pF
L
AI02821
C
includes JIG capacitance
L
AI02102B
8/17
M28C16B, M28C17B
Table 9A. Read Mode AC Characteristics for M28CxxB (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
M28CxxB
Test
Condition
Symbol
Alt.
Parameter
-90
-12
Unit
Min
Max
Min
Max
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
90
120
ns
AVQV
G = V
G = V
E = V
IL
t
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
90
40
40
120
45
ns
ns
ns
ELQV
CE
IL
t
t
GLQV
OE
IL
1
t
DF
G = V
0
0
0
0
45
t
IL
IL
EHQZ
1
t
DF
E = V
Output Enable High to Output Hi-Z
40
45
ns
ns
t
GHQZ
E = V ,
IL
t
t
Address Transition to Output Transition
0
0
AXQX
OH
G = V
IL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 9B. Read Mode AC Characteristics for M28CxxB-W (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
M28CxxB-W
Test
Condition
Symbol
Alt.
Parameter
-12
-15
Unit
Min
Max
Min
Max
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
120
150
ns
AVQV
G = V
G = V
E = V
IL
t
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
120
80
150
80
ns
ns
ns
ELQV
CE
IL
t
t
GLQV
OE
IL
1
t
DF
G = V
0
0
45
0
0
50
t
IL
IL
EHQZ
1
t
DF
E = V
Output Enable High to Output Hi-Z
45
50
ns
ns
t
GHQZ
E = V ,
IL
t
t
Address Transition to Output Transition
0
0
AXQX
OH
G = V
IL
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
9/17
M28C16B, M28C17B
Table 10A. Write Mode AC Characteristics for M28CxxB (5V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 4.5 to 5.5 V)
A
CC
M28C17B
Symbol
Alt.
Parameter
Test Condition
Unit
Min
Max
t
t
E = V , G = V
IH
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Write Enable Low to Input Valid
0
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
AVWL
AS
IL
t
t
G = V , W = V
AVEL
AS
IH
IL
t
t
G = V
0
ELWL
CES
OES
OES
IH
t
t
t
t
E = V
0
GHWL
IL
t
W = V
0
GHEL
IL
t
G = V
0
WLEL
WES
IH
t
t
AH
50
50
WLAX
t
t
AH
ELAX
t
t
E = V , G = V
IH
1
WLDV
DV
IL
t
t
G = V , W = V
IH IL
Chip Enable Low to Input Valid
1
ELDV
DV
t
t
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Time-out After the Last Byte Write
Write Cycle Time
50
0
ELEH
WP
t
t
WHEH
CEH
OEH
OEH
t
t
t
t
0
WHGL
t
0
EHGL
t
0
EHWH
WEH
t
t
0
WHDX
DH
t
t
0
EHDX
DH
t
t
WPH
50
50
100
WHWL
t
t
WLWH
WP
t
t
BLC
WLQ5H
t
t
WC
3
Q5HQ5X
t
t
Data Valid before Write Enable High
Data Valid before Chip Enable High
50
50
DVWH
DS
DS
t
t
DVEH
10/17
M28C16B, M28C17B
Table 10B. Write Mode AC Characteristics for M28CxxB-W (3V range)
(T = 0 to 70 °C or -40 to 85 °C; V = 2.7 to 3.6 V)
A
CC
M28C17B-xxW
Unit
Symbol
Alt.
Parameter
Test Condition
Min
Max
t
t
E = V , G = V
IH
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Write Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Write Enable Low to Chip Enable Low
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Write Enable Low to Input Valid
0
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ns
ns
AVWL
AS
IL
t
t
G = V , W = V
0
AVEL
AS
IH
IL
t
t
G = V
0
ELWL
CES
OES
OES
IH
t
t
t
t
E = V
0
GHWL
IL
t
W = V
0
GHEL
IL
t
G = V
0
WLEL
WES
IH
t
t
AH
100
100
WLAX
t
t
AH
ELAX
t
t
E = V , G = V
IH
1
1
WLDV
DV
IL
t
t
G = V , W = V
IH IL
Chip Enable Low to Input Valid
ELDV
DV
t
t
Chip Enable Low to Chip Enable High
Write Enable High to Chip Enable High
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Time-out after the last byte write
100
0
1000
ELEH
WP
t
t
WHEH
CEH
OEH
OEH
t
t
t
t
0
WHGL
t
0
EHGL
t
0
EHWH
WEH
t
t
0
WHDX
DH
t
t
0
EHDX
DH
t
t
WPH
50
100
100
1000
WHWL
t
t
WLWH
WP
t
t
BLC
WLQ5H
t
t
WC
Write Cycle Time
5
Q5HQ5X
t
t
Data Valid before Write Enable High
Data Valid before Chip Enable High
50
50
DVWH
DS
t
t
DVEH
DS
11/17
M28C16B, M28C17B
Figure 10. Read Mode AC Waveforms (with Write Enable, W, high)
A0-A10
E
VALID
tAVQV
tAXQX
tGLQV
tEHQZ
tGHQZ
G
tELQV
Hi-Z
DQ0-DQ7
DATA OUT
AI02822
Note: 1. Write Enable (W) = V
IH
Figure 11. Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A10
VALID
tAVWL
tELWL
tGHWL
tWLAX
E
tWHEH
G
tWLWH
tWHGL
W
tWLDV
tWHWL
DATA IN
tDVWH
DQ0-DQ7
tWHDX
RB
tWHRL
AI02823
12/17
M28C16B, M28C17B
Figure 12. Write Mode AC Waveforms (Chip Enable, E, controlled)
A0-A10
VALID
tAVEL
tGHEL
tWLEL
tELAX
E
tELEH
G
tEHGL
W
tELDV
tEHWH
DATA IN
tDVEH
DQ0-DQ7
tEHDX
RB
tEHRL
AI02824
Figure 13. Page Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A10
Addr 0
Addr 1
Addr 2
Addr n
E
G
tWHWL
W
tWLWH
Byte 0
Byte 1
Byte 2
Byte n
DQ0-DQ7 (in)
DQ5 (out)
tWHRL
tWLQ5H
tQ5HQ5X
RB
AI02825
13/17
M28C16B, M28C17B
Figure 14. Software Protected Write Cycle Waveforms
G
E
tWLWH
tWHWL
tWHWH
W
tAVEL
tWLAX
2AAh
A0-A5
Byte Address
Page Address
Byte 0
tWHDX
555h
A6-A10
DQ0-DQ7
555h
tDVWH
AAh
55h
A0h
Byte 62
Byte 63
AI02826
Note: 1. A10 to A6 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E
are both low.
Figure 15. Data Polling Sequence Waveforms
A0-A10
Address of the last byte of the Page Write instruction
E
G
W
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
Last WRITE
Internal Write Sequence
Ready
AI02827
14/17
M28C16B, M28C17B
Figure 16. Toggle Bit Sequence Waveforms
A0-A10
E
G
W
DQ6
(1)
Last WRITE
TOGGLE
Internal Write Sequence
Ready
AI02828
Note: 1. The Toggle Bit is first set to ‘0’.
Table 11. Ordering Information Scheme
Example:
M28C16
– 120
W
K
6
TR
Ready/Busy
Option
16
17
Pin 1 = Not Connected
Pin 1 = Ready/Busy
TR Tape and Reel Packing
Speed
Temperature Range
90
90 ns (5V range only)
120 ns
1
6
0 °C to 70 °C
120
150
–40 °C to 85 °C
150 ns (3V range only)
Operating Voltage
Package
blank 4.5 V to 5.5 V
2.7 V to 3.6 V
K
PLCC32
W
ORDERING INFORMATION
Devices are shipped from the factory with the
memory content set at all ‘1’s (FFh).
The notation used for the device number is as
shown in Table 11. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please contact the ST
Sales Office nearest to you.
15/17
M28C16B, M28C17B
Table 12. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
inches
Min.
0.100
0.060
–
Symbol
Typ.
Min.
2.54
1.52
–
Max.
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ.
Max.
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
Figure 17. PLCC (K)
D
A1
D1
A2
1
N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Note: 1. Drawing is not to scale.
16/17
M28C16B, M28C17B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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17/17
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