M28F201-70N6RTR [STMICROELECTRONICS]
256KX8 FLASH 12V PROM, 70ns, PDSO32, 8 X 20 MM, PLASTIC, TSOP-32;
| 型号： | M28F201-70N6RTR |
| 厂家： | 
ST |
| 描述： | 256KX8 FLASH 12V PROM, 70ns, PDSO32, 8 X 20 MM, PLASTIC, TSOP-32 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总21页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28F201
2 Mbit (256Kb x8, Bulk) Flash Memory
5V ± 10% SUPPLYVOLTAGE
12V PROGRAMMING VOLTAGE
FASTACCESS TIME: 70ns
BYTE PROGRAMMING TIME: 10µs typical
ELECTRICAL CHIP ERASE in 1s RANGE
LOW POWER CONSUMPTION
– Active Current: 15mA typical
– Stand-byCurrent: 5µA typical
10,000 PROGRAM/ERASE CYCLES
PLCC32 (K)
TSOP32 (N)
8 x 20 mm
INTEGRATED ERASE/PROGRAM-STOP
TIMER
OTP COMPATIBLE PACKAGES and PINOUT
20 YEARSDATARETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– ManufacturerCode: 20h
Figure 1. Logic Diagram
– Device Code: F4h
DESCRIPTION
The M28F201 Flash memory is a non-volatile
memory that may be erased electricallyat the chip
level and programmed by byte. It is organised as
256K bytes by 8 bits. It uses a command register
architecturetoselecttheoperatingmodesandthus
provide a simple microprocessor interface. The
device is offered in PLCC32 and TSOP32 (8 x
20mm)packages.Bothnormalandreversepinouts
are available for the TSOP32package.
V
V
PP
CC
18
8
A0-A17
DQ0-DQ7
W
E
M28F201
Table 1. Signal Names
G
A0-A17
Address Inputs
Data Inputs / Outputs
Chip Enable
DQ0-DQ7
E
V
SS
AI00637C
G
Output Enable
Write Enable
W
VPP
VCC
VSS
Program Supply
Supply Voltage
Ground
August 1998
1/21
M28F201
Figure 2A. LCC Pin Connections
Figure 2B. TSOP Pin Connections
A11
A9
1
32
G
A10
E
A8
1 32
A13
A14
A17
W
DQ7
DQ6
DQ5
DQ4
DQ3
A7
A14
A13
A8
A6
A5
A4
A9
V
8
9
M28F201
(Normal)
25
24
CC
A3
A2
9
M28F201
25 A11
G
V
PP
V
SS
A16
DQ2
DQ1
DQ0
A0
A1
A10
E
A15
A12
A7
A0
DQ0
DQ7
17
A6
A1
A5
A2
A4
16
17
A3
AI00638C
AI00639C
Figure 2C. TSOP Reverse Pin Connections
DEVICE OPERATION
The M28F201 Flash memory product employs a
technologysimilar to a 2 Mbit EPROM but add to
the device functionalityby providingelectrical era-
sure and programming. These functions are man-
agedby a commandregister.Thefunctionsthatare
addressed via the command register depend on
the voltage applied to the VPP, program voltage,
input. When VPP is less than or equal to 6.5V, the
command register is disabled and the M28F201
functionsas a read only memory providing operat-
ing modes similar to an EPROM (Read, Output
Disable, Electronic Signature Read and Standby).
When VPP is raised to 12V the command register
is enabledand this provides,in addition,Erase and
Programoperations.
G
A10
E
1
32
A11
A9
A8
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
A17
W
8
9
M28F201
(Reverse)
25
24
V
V
CC
PP
V
SS
DQ2
DQ1
DQ0
A0
A16
A15
A12
A7
READ ONLY MODES, VPP ≤ 6.5V
For all Read Only Modes, except Standby Mode,
the Write Enable input W should be High. In the
StandbyMode this input is ’don’t care’.
A1
A6
A2
A5
Read Mode. The M28F201has two enableinputs,
E and G, both of which must be Low in order to
outputdata from the memory. The ChipEnable(E)
is the powercontrol and shouldbe used for device
selection. Output Enable (G) is the output control
and should be used to gate data on to the output,
independantof the device selection.
A3
16
17
A4
AI00640D
2/21
M28F201
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
Parameter
Value
–40 to 125
–65 to 150
–0.6 to VCC + 0.5
–0.6 to 7
Unit
Ambient Operating Temperature (4)
Storage Temperature
Input or Output Voltages
Supply Voltage
°C
TSTG
C
°
(2,3)
VIO
V
VCC
V
V
(2)
VA9
A9 Voltage
–0.6 to 13.5
Program Supply Voltage, during Erase
or Programming
(2)
VPP
–0.6 to 14
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltagemay undershoot to –2V during transitionand for less than 20ns.
3. Maximum Voltagemay overshoot to 7V during transition and for less than 20ns.
4. Depends on range.
(1)
Table 3. Operations
VPP
Operation
Read
E
G
VIL
VIH
X
W
VIH
A9
A9
X
DQ0 - DQ7
Data Output
Hi-Z
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIH
Output Disable
Standby
VIH
Read Only
VPPL
X
X
Hi-Z
Electronic Signature
Read
VIL
VIL
VIH
VIH
X
VIH
VID
A9
A9
X
Codes
VIH
Data Output
Data Input
Hi-Z
Read/Write (2)
VPPH
Write
VIL Pulse
VIH
Output Disable
Standby
X
X
Hi-Z
Notes:
1. X = VIL or VIH.
2. Refer also to the Command table.
Table 4. ElectronicSignature
Identifier
Manufacturer’s Code
Device Code
A0
VIL
VIH
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Hex Data
20h
0
1
0
1
1
1
0
1
0
0
0
1
0
0
0
0
F4h
3/21
M28F201
Table 5. Commands (1)
1st Cycle
A0-A17
X
2nd Cycle
A0-A17
Command
Cycles
Operation
DQ0-DQ7
Operation
DQ0-DQ7
Read
1
2
Write
00h
Read
Read
00000h
00001h
20h
F4h
Electronic
Write
Write
X
X
80h or 90h
20h
Signature (2)
Setup Erase/
Erase
2
Write
Read
X
X
20h
Erase Verify
Setup Program/
Program
2
2
Write
Write
A0-A17
X
A0h
40h
Data Output
Write
Read
Write
A0-A17
Data Input
Data Output
FFh
Program Verify
2
2
Write
Write
X
X
C0h
FFh
X
X
Reset
Notes: 1. X = VIL or VIH.
2. Refer also to the Electronic Signature table.
Standby Mode.
In the Standby Mode the maxi-
data at any location in the memory. Read mode is
set-up with one cycle only and may be followed by
any number of read operations to output data.
ElectronicSignatureRead mode is set-upwith one
cycle and followed by a read cycle to output the
manufactureror device codes.
mum supply current is reduced. The device is
placed in the Standby Mode by applying a High
level to the Chip Enable (E) input. When in the
StandbyMode theoutputsare in a highimpedance
state, independant of the Output Enable (G) input.
Awrite tothecommandregisteris madebybringing
WLowwhileE is Low.ThefallingedgeofW latches
Addresses, while the rising edge latches Data,
which are used for those commands that require
address inputs, command input or provide data
output. The supply voltage VCC and the program
voltageVPP can be appliedin any order. Whenthe
device is powered up or when VPP is ≤ 6.5V the
contentsof the command register defaults to 00h,
thus automatically setting-up Read operations. In
addition a specific command may be used to set
the command registerto 00h for readingthe mem-
ory. The system designer may chose to provide a
constant high VPP and use the register commands
for all operations, or to switch the VPP from low to
high only when needing to erase or program the
memory. All command register access is inhibited
whenVCC fallsbelow the Erase/WriteLockoutVolt-
age (VLKO) of 2.5V.
Output Disable Mode.
(G) is High the outputs are in a high impedance
state.
When the Output Enable
ElectronicSignatureMode.
Thismode allowsthe
read out of two binarycodesfromthe device which
identify the manufacturer and device type. This
mode is intended for use by programming equip-
ment to automaticallyselect the correcterase and
programmingalgorithms. TheElectronicSignature
Mode is active when a high voltage(11.5V to 13V)
is appliedto addresslineA9withEand GLow.With
A0 Low the output data is the manufacturercode,
when A0 is High the output is the device code. All
other address lines should be maintained Low
while reading the codes. The electronic signature
can also be accessed in Read/Writemodes.
READ/WRITE MODES, 11.4V ≤ VPP ≤ 12.6V
If the device is deselected during Erasure, Pro-
gramming or verifying it will draw active supply
currents until the operationsare terminated.
The device is protected against stress caused by
long erase or program times. If the end of Erase or
Programming operations are not terminated by a
Verify cycle within a maximum time permitted, an
internal stop timer automatically stops the opera-
tion.The deviceremains in an inactivestate, ready
to start a Verify or Reset Mode operation.
When VPP is High both read and write operations
may be performed. These are defined by the con-
tents of an internal command register. Commands
may be written to this register to set-up and exe-
cute,Erase,Erase Verify,Program,ProgramVerify
and Reset modes. Each of these modes needs 2
cycles. Each mode starts with a write operation to
set-upthe command, thisis followedby eitherread
or write operations. The device expects the first
cycle to be a write operation and does not corrupt
4/21
M28F201
Table 6. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 10ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.45V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.45V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01275B
AI01276B
Table 7. Capacitance(1)
(TA = 25 °C, f = 1 MHz )
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Test Condition
VIN = 0V
Min
Max
6
Unit
pF
COUT
VOUT = 0V
12
pF
Note: 1. Sampled only, not 100% tested.
Read Mode.
The Read Mode is the default at
codes may be read directly. It is not neccessary to
apply a high voltage to A9 when using the com-
mand register. The Electronic Signature Mode is
set-up by writing 80h or 90h to the command
register. The following read cycles, with address
inputs 00000h or 00001h,output themanufacturer
or device codes. The command is terminated by
writing another valid command to the command
register (for example Reset).
power up or may be set-up by writing 00h to the
command register. Subsequent read operations
outputdata fromthe memory.Thememoryremains
in the Read Mode until a new command is written
to the command register.
ElectronicSignature Mode.
correct erase and programming algorithms for on-
board programming, the manufacturerand device
In orderto select the
5/21
M28F201
Table 8. DC Characteristics
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%)
Symbol
ILI
Parameter
Test Condition
0V
Min
Max
Unit
Input Leakage Current
V
V
1
A
µ
≤
≤
±
IN
CC
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
E = VIL, f = 10MHz
E = VIH
±10
30
µA
mA
mA
µA
ICC
Supply Current (Read)
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Supply Current (Programming)
Supply Current (Program Verify)
Supply Current (Erase)
1
ICC1
E = VCC ± 0.2V
During Programming
During Verify
100
10
(1)
ICC2
mA
mA
mA
mA
µA
(1)
ICC3
20
(1)
ICC4
During Erasure
During Erase Verify
20
(1)
ICC5
Supply Current (Erase Verify)
Program Leakage Current
20
ILPP
IPP
V
PP ≤ VCC
VPP > VCC
VPP
±10
200
µA
Program Current (Read or
Standby)
V
10
±
A
µ
≤
CC
(1)
IPP1
Program Current (Programming)
VPP = VPPH, During Programming
PP = VPPH, During Verify
30
mA
mA
Program Current (Program
Verify)
(1)
IPP2
V
5
(1)
IPP3
Program Current (Erase)
Program Current (Erase Verify)
Input Low Voltage
VPP = VPPH, During Erase
30
5
mA
mA
V
(1)
IPP4
VPP = VPPH, During Erase Verify
VIL
–0.5
2
0.8
Input High Voltage TTL
Input High Voltage CMOS
Output Low Voltage
VCC + 0.5
VCC + 0.5
0.45
V
VIH
0.7 VCC
V
VOL
IOL = 5.8mA
V
IOH = –100 A
VCC – 0.4
0.85 VCC
2.4
V
µ
Output High Voltage CMOS
VOH
I
OH = –2.5mA
V
Output High Voltage TTL
IOH = –2.5mA
V
Program Voltage (Read
Operations)
VPPL
0
6.5
V
Program Voltage (Read/Write
Operations)
VPPH
VID
11.4
11.5
12.6
V
V
A9 Voltage(Electronic Signature)
A9 Current (Electronic Signature)
13
(1)
IID
A9 = VID
200
A
µ
Supply Voltage, Erase/Program
Lock-out
VLKO
2.5
V
Note:
1. Not 100% tested. Characterisation Data available.
6/21
M28F201
Table 9. Read Only Mode AC Characteristics
((TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F201
-120
VCC
-70
-90
-150
VCC
VCC
5V±10%
=
VCC
=
=
=
Symbol
Alt
Parameter
Test Condition
Unit
5V±10%
5V±10%
5V±10%
Standard Standard Standard Standard
Interface Interface Interface Interface
Min Max Min Max Min Max Min Max
Write Enable High to
Output Enable Low
tWHGL
tAVAV
tAVQV
6
6
6
6
µs
ns
ns
tRC
Read Cycle Time
E = VIL, G = VIL
E = VIL, G = VIL
70
90
120
150
Address Valid to
Output Valid
tACC
70
70
90
90
120
120
150
150
Chip Enable Low to
Output Transition
(1)
tELQX
tLZ
tCE
tOLZ
tOE
G = VIL
G = VIL
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
Chip Enable Low to
Output Valid
tELQV
Output Enable Low
to Output Transition
(1)
tGLQX
E = VIL
Output Enable Low
to Output Valid
tGLQV
E = VIL
25
25
25
30
30
30
35
30
30
40
35
35
Chip Enable High to
Output Hi-Z
(1)
tEHQZ
G = VIL
0
0
0
0
0
0
0
0
0
0
0
0
Output Enable High
to Output Hi-Z
(1)
tGHQZ
tDF
tOH
E = VIL
Address Transition
to Output Transition
tAXQX
E = VIL, G = VIL
Note:
1. Sampled only, not 100% tested
Erase and Erase Verify Modes.
The memory is
The following read cycle is made with an internally
generated margin voltage applied; reading FFh
indicatesthat all bitsof theaddressedbyteare fully
erased. The whole contents of the memory are
verified by repeating the Erase Verify Operation,
first writing the set-up code A0h with the address
of the byte to be verifiedand thenreading the byte
contentsin a second read cycle.
As the Erasealgorithmflow chartshows, when the
data read during Erase Verify is not FFh, another
Erase operation is performed and verification con-
tinuesfromtheaddressof thelastverifiedbyte.The
command is terminated by writing another valid
command to the command register (for example
Program or Reset).
erased by first Programming all bytes to 00h, the
Erase command then erases them to FFh. The
Erase Verify command is then used to read the
memory byte-by-byte for a content of FFh. The
Erase Mode is set-up by writing 20h to the com-
mand register. The write cycle is then repeated to
start the erase operation. Erasure starts on the
rising edge of W during this second cycle. Eraseis
followed by an Erase Verify which reads an ad-
dressed byte. Erase Verify Mode is set-up by writ-
ing A0h to the command register and at the same
time supplying the address of the byte to be veri-
fied. The rising edge of W during the set-up of the
first Erase Verify Mode stops the Erase operation.
7/21
M28F201
Figure 5. Read Mode AC Waveforms
tAVAV
A0-A17
E
tAVQV
tELQV
tAXQX
tEHQZ
tELQX
G
tGLQV
tGLQX
tGHQZ
DQ0-DQ7
DATA OUT
AI00642
Figure 6. Read Command Waveforms
V
PP
tVPHEL
VALID
A0-A17
tAVQV
tAXQX
E
tELWL
tWHEH
tELQV
tEHQZ
tGHQZ
G
tGHWL
tWHGL
W
tWLWH
tGLQV
tDVWH
tWHDX
DQ0-DQ7
COMMAND
DATA OUT
READ SET-UP
READ
AI00643
8/21
M28F201
Figure 7. Electronic Signature Command Waveforms
V
PP
tVPHEL
00000h-00001h
A0-A17
tAVQV
tELQV
tAXQX
tEHQZ
tGHQZ
E
tELWL
tWHEH
G
tGHWL
tWHGL
W
tWLWH
tDVWH
tGLQV
tWHDX
DQ0-DQ7
COMMAND
DATA OUT
READ ELECTRONIC
SIGNATURE SET-UP
READ
MANUFACTURER
OR DEVICE
AI00644
Program and Program Verify Modes.
The Pro-
gramming operation. The following read cycle, of
the address already latched during programming,
is made with an internally generated margin volt-
ageapplied,readingvaliddataindicatesthatallbits
have been programmed.
ResetMode. Thiscommandis usedto safelyabort
Erase or Program Modes. The Reset Mode is
set-up and performed by writing FFh two times to
the command register. The command should be
followed by writing a valid command to the the
command register (for example Read).
gramModeis set-upbywriting 40htothecommand
register. This is followed by a second write cycle
which latches the address and data of the byte to
be programmed. The rising edge of W during this
second cycle starts the programming operation.
Programmingis followedby a ProgramVerifyofthe
data written.
ProgramVerify Modeisset-upbywritingC0hto the
commandregister.The rising edgeof W during the
set-up of the Program Verify Mode stops the Pro-
9/21
M28F201
Table 10A. Read/Write Mode AC Characteristics,W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F201
-70
-90
Symbol
Alt
Parameter
Unit
VCC = 5V 10% VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
Max
Min
Max
tVPHEL
tVPHWL
tWHWH3
tEHEH3
tAVWL
tAVEL
VPP High to Chip Enable Low
1
1
1
1
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
ms
ms
ns
ns
ns
ns
µs
VPP High to Write Enable Low
tWC
tWC
tAS
Write Cycle Time (W controlled)
70
70
0
90
90
0
Write Cycle Time (E controlled)
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
0
0
tWLAX
tELAX
tAH
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Write Enable Low
Write Enable Low to Chip Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Input Valid to Write Enable High
30
30
0
45
45
0
tELWL
tCS
tWLEL
tGHWL
tGHEL
tDVWH
tDVEH
tWLWH
tELEH
0
0
0
0
0
0
tDS
tWP
tDH
30
30
30
50
10
10
10
10
9.5
9.5
0
45
45
45
60
10
10
10
10
9.5
9.5
0
Input Valid to Chip Enable High
Write Enable Low to Write Enable High (Write Pulse)
Chip Enable Low to Chip Enable High (Write Pulse)
Write Enable High to Input Transition
Chip Enable High to Input Transition
Duration of Program Operation (W contr.)
Duration of Program Operation (E contr.)
Duration of Erase Operation (W contr.)
Duration of Erase Operation (E contr.)
Write Enable High to Chip Enable High
Chip Enable High to Write Enable High
tWHDX
tEHDX
tWHWH1
tEHEH1
tWHWH2
tEHEH2
tWHEH
tEHWH
tWHWL
tEHEL
tCH
0
0
tWPH Write Enable High to Write Enable Low
Chip Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
tACC Addess Valid to data Output
10
10
6
20
20
6
tWHGL
tEHGL
tAVQV
6
6
s
µ
70
70
90
90
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tELQX
tLZ
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
0
0
0
0
tELQV
tCE
(1)
tGLQX
tOLZ Output Enable Low to Output Transition
tGLQV
tOE
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
25
25
25
30
30
30
(1)
tEHQZ
(1)
tGHQZ
tDF
tOH
tAXQX
0
0
Note:
1. Sampled only, not 100% tested
10/21
M28F201
Table 10B. Read/Write Mode AC Characteristics,W and E Controlled
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)
M28F201
-120
-150
Symbol
Alt
Parameter
Unit
VCC = 5V 10% VCC = 5V 10%
±
±
Standard
Interface
Standard
Interface
Min
Max
Min
Max
tVPHEL
tVPHWL
tWHWH3
tEHEH3
tAVWL
tAVEL
VPP High to Chip Enable Low
1
1
1
1
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
ms
ms
ns
ns
ns
ns
µs
VPP High to Write Enable Low
tWC
tWC
tAS
Write Cycle Time (W controlled)
120
120
0
150
150
0
Write Cycle Time (E controlled)
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
0
0
tWLAX
tELAX
tAH
Write Enable Low to Address Transition
Chip Enable Low to Address Transition
Chip Enable Low to Write Enable Low
Write Enable Low to Chip Enable Low
Output Enable High to Write Enable Low
Output Enable High to Chip Enable Low
Input Valid to Write Enable High
50
60
0
50
80
0
tELWL
tCS
tWLEL
tGHWL
tGHEL
tDVWH
tDVEH
tWLWH
tELEH
0
0
0
0
0
0
tDS
tWP
tDH
50
50
50
70
10
10
10
10
9.5
9.5
0
50
50
60
80
10
10
10
10
9.5
9.5
0
Input Valid to Chip Enable High
Write Enable Low to Write Enable High (Write Pulse)
Chip Enable Low to Chip Enable High (Write Pulse)
Write Enable High to Input Transition
Chip Enable High to Input Transition
Duration of Program Operation (W contr.)
Duration of Program Operation (E contr.)
Duration of Erase Operation (W contr.)
Duration of Erase Operation (E contr.)
Write Enable High to Chip Enable High
Chip Enable High to Write Enable High
tWHDX
tEHDX
tWHWH1
tEHEH1
tWHWH2
tEHEH2
tWHEH
tEHWH
tWHWL
tEHEL
tCH
0
0
tWPH Write Enable High to Write Enable Low
Chip Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Chip Enable High to Output Enable Low
tACC Addess Valid to data Output
20
20
6
20
20
6
tWHGL
tEHGL
tAVQV
6
6
s
µ
120
120
150
150
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tELQX
tLZ
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
0
0
0
0
tELQV
tCE
(1)
tGLQX
tOLZ Output Enable Low to Output Transition
tGLQV
tOE
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
35
30
30
40
35
35
(1)
tEHQZ
(1)
tGHQZ
tDF
tOH
tAXQX
0
0
Note:
1. Sampled only, not 100% tested
11/21
M28F201
Figure 8. Erase Set-up and Erase Verify Commands Waveforms, W Controlled
12/21
M28F201
Figure 9. Erase Set-up and Erase Verify Commands Waveforms, E Controlled
13/21
M28F201
Figure 10. Program Set-up and Program Verify Commands Waveforms - W Controlled
14/21
M28F201
Figure 11. Program Set-up and Program Verify Commands Waveforms - E Controlled
15/21
M28F201
Figure 12. ErasingFlowchart
Figure 13. ProgrammingFlowchart
V
= 12V
PP
V
= 12V
PP
PROGRAM ALL
BYTES TO 00h
n = 0
n=0, Addr=00000h
PROGRAM SET-UP
Latch Addr, Data
ERASE SET-UP
Wait 10ms
Wait 10µs
NO
PROGRAM VERIFY
ERASE VERIFY
Latch Addr.
NO
YES
++n
= 25
Wait 6µs
++n
YES
=
Wait 6µs
1000
READ DATA OUTPUT
V
<
FAIL
6.5V
PP
READ DATA OUTPUT
V
<
FAIL
6.5V
PP
NO
Data
OK
Addr++
NO
Data
OK
Addr++
YES
YES
Last
NO
Addr
Last
NO
Addr
YES
READ COMMAND
YES
READ COMMAND
V
< 6.5V, PASS
PP
AI00677
V
< 6.5V, PASS
PP
AI00649
PRESTO F ERASE ALGORITHM
PRESTO F PROGRAM ALGORITHM
The PRESTO F Erase Algorithm guarantees that
the device will be erased in a reliable way. The
algorithmfirst programs all bytes to 00h in order to
ensure uniform erasure. The programmingfollows
the PRESTO F Programming Algorithm. Erase is
set-up by writing 20h to the command register, the
erasure is started by repeating this write cycle.
Erase Verify is set-up by writing A0h to the com-
mandregistertogetherwith the addressof thebyte
tobe verified.Thesubsequentread cyclereadsthe
datawhichis comparedtoFFh.EraseVerifybegins
ataddress0000hand continuesto the lastaddress
or until the comparison of the data to FFh fails. If
this occurs, the addressof the last byte checkedis
stored and a new Erase operation performed.
EraseVerifythencontinuesfromthe addressofthe
stored location.
The PRESTO F Programming Algorithm applies a
series of 10µs programming pulses to a byte until
a correct verify occurs. Up to 25 programming
operations are allowed for one byte. Program is
set-up by writing 40h to the command register, the
programming is started after the next write cycle
which also latches the address and data to be
programmed. Program Verify is set-up by writing
C0h to the command register, followed by a read
cycle and a compare of the data read to the data
expected.During Program and Program Verify op-
erations a MARGIN MODE circuit is activated to
guaranteethat the cell isprogrammedwith a safety
margin.
16/21
M28F201
ORDERING INFORMATION SCHEME
Example:
M28F201
-70 X
N
1 TR
Operating Voltage
Option
F
5V
R
Reverse
Pinout
TR Tape & Reel
Packing
Speed
Power Supplies
blank VCC ± 10%
CC ± 5%
Package
Temperature Range
-70
-90
70 ns
90 ns
K
N
PLCC32
1
6
3
0 to 70 °C
X
V
TSOP32
8 x 20 mm
–40 to 85 °C
–40 to 125 °C
-120
-150
120 ns
150 ns
Devices are shipped from the factory with the memory content erased (to FFh).
Fora list ofavailableoptions(Speed, Package,etc...)or for furtherinformationon anyaspect of thisdevice,
please contact the STMicroelectronics Sales Office nearest to you.
17/21
M28F201
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
mm
Min
2.54
1.52
–
inches
Min
Symb
Typ
Max
3.56
2.41
0.38
0.53
0.81
12.57
11.56
10.92
15.11
14.10
13.46
–
Typ
Max
0.140
0.095
0.015
0.021
0.032
0.495
0.455
0.430
0.595
0.555
0.530
–
A
A1
A2
B
0.100
0.060
–
0.33
0.66
12.32
11.35
9.91
14.86
13.89
12.45
–
0.013
0.026
0.485
0.447
0.390
0.585
0.547
0.490
–
B1
D
D1
D2
E
E1
E2
e
1.27
0.89
0.050
0.035
F
0.00
–
0.25
–
0.000
–
0.010
–
R
N
32
32
Nd
Ne
CP
7
7
9
9
0.10
0.004
D
A1
D1
A2
1 N
B1
e
Ne
E1 E
D2/E2
F
B
0.51 (.020)
1.14 (.045)
Nd
A
R
CP
PLCC
Drawing is not to scale.
18/21
M28F201
TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ
Max
0.047
0.007
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-a
A1
α
L
Drawing is not to scale.
19/21
M28F201
TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.17
1.05
0.27
0.21
20.20
18.50
8.10
–
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.795
0.728
0.319
–
A
A1
A2
B
0.05
0.95
0.15
0.10
19.80
18.30
7.90
–
0.002
0.037
0.006
0.004
0.780
0.720
0.311
–
C
D
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
32
32
CP
0.10
0.004
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
TSOP-b
A1
α
L
Drawing is not to scale.
20/21
M28F201
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1998 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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21/21
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