M28W320FST70ZA6F [STMICROELECTRONICS]
32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Boot Block, Secure Flash Memories; 32兆（2MB ×16）和64Mbit的（4MB ×16） 3V电源，引导块，安全的闪存产品
| 型号： | M28W320FST70ZA6F |
| 厂家： | 
ST |
| 描述： | 32Mbit (2Mb x16) and 64Mbit (4Mb x16) 3V Supply, Boot Block, Secure Flash Memories |
| 文件： | 总55页 (文件大小：1025K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M28W320FST, M28W320FSB,
M28W640FSB, M28W640FST
32Mbit (2Mb x16) and 64Mbit (4Mb x16)
3V Supply, Boot Block, Secure Flash Memories
FEATURES SUMMARY
■
SUPPLY VOLTAGE
Figure 1. Package
–
–
–
V
V
V
= 2.7V to 3.6V Core Power Supply
DD
= 1.65V to 3.6V for Input/Output
DDQ
= 12V for fast Program (optional)
PP
■
■
ACCESS TIME: 70ns
PROGRAMMING TIME:
BGA
–
–
–
10µs typical
Double Word Programming Option
Quadruple Word Programming Option
TBGA64 (ZA)
10 x 13mm
■
■
COMMON FLASH INTERFACE
MEMORY BLOCKS
–
Parameter Blocks (Top or Bottom
location)
–
Main Blocks
■
■
HARDWARE PROTECTION
Pin for write protect of all blocks
SECURITY FEATURES
–
V
PP
–
–
–
128 bit User-programmable OTP segment
64 bit Unique Device Identifier
KRYPTO Features:
Modify Protection,
Read Protection,
Device Authentication
■
■
■
AUTOMATIC STAND-BY MODE
PROGRAM and ERASE SUSPEND
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
–
–
Manufacturer Code: 20h
Device Codes:
M28W320FST: 880Ah,
M28W320FSB: 880Bh
M28W640FST: 8858h,
M28W640FSB: 8859h
®
■
ECOPACK PACKAGE AVAILABLE
August 2005
1/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. M28W320FS and M28W640FS Memory Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. M28W320FS Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. M28W640FS Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. M28W320FST and M28W320FSB Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. M28W640FST and M28W640FSB Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
V
V
V
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DD
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DDQ
Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PP
SS
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HARDWARE PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
PP
≤V
PPLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SECURITY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Read Protection Register and Protection Register Lock . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
V
PP
Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10.Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13.Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. Power-Up and Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 14.TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline . . . . . . . . 30
3/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 18. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 20. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 21. Top Boot Block Addresses, M28W320FST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Bottom Boot Block Addresses, M28W320FSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. Top Boot Block Addresses, M28W640FST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Bottom Boot Block Addresses, M28W640FSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 26. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 27. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 28. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 29. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 30. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 16.Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 20.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 21.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX D.COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. . . . . . . . 52
Table 31. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 32. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 33. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
SUMMARY DESCRIPTION
The M28W320FS and M28W640FS are 32 Mbit
(2Mbit x 16) and 64 Mbit (4Mbit x 16) Secure Flash
memories. The devices can be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 2.7V to 3.6V V
supply for the circuitry and a 1.65V to 3.6V V
bit segment and a 128 bit segment. The 64 bit seg-
ment contains a unique device number written by
ST, while the second one is one-time-programma-
ble by the user. The user programmable segment
can be permanently protected. Figure 7., shows
the Protection Register Memory Map.
DD
DDQ
supply for the Input/Output pins. An optional 12V
power supply is provided to speed up custom-
er programming.
The M28W320FS and M28W640FS feature
32Mbit and 64 Mbits respectively and have an
asymmetrical block architecture with 4 KWord Pa-
rameter Blocks and 32 KWord Main Blocks. The
M28W320FST and M28W640FST have the Pa-
rameter Blocks at the top of the memory address
The KRYPTO Protection Register is used to man-
age the Modify and Read protection modes. It also
features a Device Authentication mechanism. The
KRYPTO Protection Register is described in a
dedicated Application Note. Please contact STMi-
croelectronics for further details.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
V
PP
space
while
the
M28W320FSB
and
M28W640FSB locate the Parameter Blocks start-
ing from the bottom. Refer to Table 1., Figure 5.
and Figure 6. for a detailed description of the de-
vices memory architecture and map.
All devices are equipped with hardware and soft-
ware block protection features to avoid unwanted
program/erase (modify) or read of the Flash mem-
ory content:
■
Hardware Protection:
–
When V ≤V
all blocks are protected
PPLK
PP
against program or erase.
All the devices are offered in a TBGA64 (10 x
13mm) package.
In order to meet environmental requirements, ST
■
Software Protection thanks to KRYPTO
Security Features:
offers the M28W320FS and M28W640FS in ECO-
–
Modify Protection: volatile and non-
volatile.
®
PACK
packages. ECOPACK packages are
Lead-free. The category of second Level Intercon-
nect is marked on the package and on the inner
box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to solder-
ing conditions are also marked on the inner box la-
bel.
–
Read Protection.
The KRYPTO Security features are described in a
dedicated Application Note. Please contact STMi-
croelectronics for further details.
Two registers are available for protection purpose:
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
All devices are supplied with all the bits erased
(set to ’1’).
■
The Protection Register
The KRYPTO Protection Register.
■
The Protection Register is a 192 bit Protection
Register to increase the protection of a system de-
sign. The Protection Register is divided into a 64
Table 1. M28W320FS and M28W640FS Memory Architecture
Parameter Blocks
Main Blocks
Block Size
Device
No. of
Blocks
(1)
No. of Blocks
Block Size
M28W320FS
8
8
4 KWords
4 KWords
63
32 KWords
32 KWords
M28W640FS
127
Note: 1. Erasable Block size.
5/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 2. M28W320FS Logic Diagram
Figure 3. M28W640FS Logic Diagram
V
V
V
V
V V
DD DDQ PP
DD DDQ PP
21
16
22
16
A0-A20
A0-A21
DQ0-DQ15
DQ0-DQ15
W
E
W
E
M28W320FST
M28W320FSB
M28W640FST
M28W640FSB
G
G
RP
RP
V
V
SS
SS
AI09925
AI09909
Table 2. Signal Names
M28W320FST and
M28W320FSB
M28W640FST and
M28W640FSB
Signal Names
A0-A20
A0-A21
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Reset
DQ0-DQ15
E
G
W
RP
V
Core Power Supply
DD
Power Supply for
Input/Output
V
DDQ
Optional Supply Voltage for
Fast Program & Erase
V
PP
V
SS
Ground
NC
Not Connected Internally
6/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 4. TBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A0
A1
A5
A7
A8
V
A12
A13
V
A17
A18
A21
NC
A20
A16
NC
G
PP
E
DD
V
NC
NC
SS
A2
A6
A9
A11
RP
A14
A19
A3
A4
DQ1
DQ0
NC
A10
DQ9
DQ10
DQ2
NC
NC
A15
DQ8
NC
NC
NC
DQ3
DQ11
DQ4
DQ12
DQ5
DQ13
NC
DQ15
NC
NC
G
H
V
DQ6
DQ14
DQ7
W
DDQ
NC
V
V
V
NC
DD
SSQ
SS
AI09910b
Note: 1. The above figure gives the TBGA connections for M28W640FST and M28W640FSB. On M28W320FST and M28W320FSB devic-
es, A21 is NC.
7/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 5. M28W320FST and M28W320FSB Block Addresses
M28W320FST
Top Boot Block Addresses
M28W320FSB
Bottom Boot Block Addresses
1FFFFF
1FFFFF
4 KWords
32 KWords
32 KWords
1FF000
1F8000
1F7FFF
Total of 8
4 KWord Blocks
1F0000
Total of 63
32 KWord Blocks
1F8FFF
4 KWords
1F8000
1F7FFF
32 KWords
1F0000
00FFFF
32 KWords
4 KWords
008000
007FFF
Total of 63
007000
32 KWord Blocks
Total of 8
00FFFF
4 KWord Blocks
32 KWords
32 KWords
008000
007FFF
000FFF
000000
4 KWords
000000
AI09931
8/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 6. M28W640FST and M28W640FSB Block Addresses
M28W640FST
M28W640FSB
Top Boot Block Addresses
Bottom Boot Block Addresses
3FFFFF
3FFFFF
4 KWords
32 KWords
32 KWords
3FF000
3F8000
3F7FFF
Total of 8
4 KWord Blocks
3F0000
Total of 127
32 KWord Blocks
3F8FFF
4 KWords
3F8000
3F7FFF
32 KWords
3F0000
00FFFF
32 KWords
4 KWords
008000
007FFF
Total of 127
007000
32 KWord Blocks
Total of 8
00FFFF
4 KWord Blocks
32 KWords
32 KWords
008000
007FFF
000FFF
000000
4 KWords
000000
AI09911
Note: Also see APPENDIX A., Tables 23 and 24 for a full listing of the Block Addresses.
Figure 7. Protection Register Memory Map
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
Unique device number
81h
Protection Register Lock
1
0
80h
AI05520b
9/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
SIGNAL DESCRIPTIONS
See Figures 2 and 3, Logic Diagrams and Table
2., Signal Names, for a brief overview of the sig-
nals connected to this device.
Enable or a change of the address is required to
ensure valid data outputs.
Supply Voltage. V
V
provides the power
DD
DD
Address Inputs. The Address Inputs select the
cells in the memory array to access during Bus
Read operations. Address Inputs range from A0 to
A20 for the M28W320FS. The M28W640FS has
an additional A21 address line. During Bus Write
operations they control the commands sent to the
Command Interface of the internal state machine.
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
Supply Voltage. V
provides the power
DDQ
DDQ
supply to the I/O pins and enables all Outputs to
be powered independently from V . V can be
DD DDQ
tied to V or can use a separate supply.
DD
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
V
Program Supply Voltage. V
is both a
PP
PP
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin. The Supply Voltage V
Program Supply Voltage V
any order.
If V is kept in a low voltage range (0V to 3.6V)
and the
DD
can be applied in
PP
PP
V
is seen as a control input. In this case a volt-
PP
at V and Reset is at V the device is in active
IL
IH
age lower than V
against program or erase, while V
ables these functions (see Table 13., DC Charac-
teristics, for the relevant values). V is only
sampled at the beginning of a program or erase; a
change in its value after the operation has started
does not have any effect on Program or Erase.
gives an absolute protection
PPLK
mode. When Chip Enable is at V the memory is
IH
> V
en-
PP
PP1
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable controls
data outputs during the Bus Read operation of the
memory.
PP
If V is set to V
, it acts as a power supply pin.
PPH
PP
Write Enable (W). The Write Enable controls the
Bus Write operation of the memory’s Command
Interface. The data and address inputs are latched
on the rising edge of Chip Enable, E, or Write En-
able, W, whichever occurs first.
In this condition V must be stable until the Pro-
gram/Erase algorithm is completed (see Table 15.
and Table 16.). A Quadruple Word Program com-
PP
mand will be ignored if V is not set to V
while
PP
PPH
a Double Word Program can be performed even if
V
is set to V
PP
DD.
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at V ,
V
Ground. V is the reference for all voltage
SS SS
IL
the memory is in reset mode: the outputs are high
impedance and the current consumption is mini-
mized. After Reset all blocks are in the Locked
measurements.
Note: Each device in a system should have
V
, V
and V decoupled with a 0.1µF ca-
DD DDQ PP
state. When Reset is at V , the device is in normal
IH
pacitor close to the pin. See Figure 9., AC Mea-
operation. Exiting reset mode the device enters
read array mode, but a negative transition of Chip
surement Load Circuit. The PCB track widths
should be sufficient to carry the required V
program and erase currents.
PP
10/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and Re-
set. See Table 3., Bus Operations, for a summary.
Characteristics, for details of the timing require-
ments.
Output Disable. The data outputs are high im-
pedance when the Output Enable is at V .
IH
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Standby. Standby disables most of the internal
circuitry allowing a substantial reduction of the cur-
rent consumption. The memory is in stand-by
Read. Read Bus operations are used to output
the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common
Flash Interface. Both Chip Enable and Output En-
when Chip Enable is at V and the device is in
IH
read mode. The power consumption is reduced to
the stand-by level and the outputs are set to high
impedance, independently from the Output Enable
or Write Enable inputs. If Chip Enable switches to
able must be at V in order to perform a read op-
IL
eration. The Chip Enable input should be used to
enable the device. Output Enable should be used
to gate data onto the output. The data read de-
pends on the previous command written to the
memory (see Command Interface section). See
Figure 10., Read AC Waveforms, and Table
14., Read AC Characteristics, for details of when
the output becomes valid.
V
during a program or erase operation, the de-
IH
vice enters Standby mode when finished.
Automatic Standby. Automatic Standby pro-
vides a low power consumption state during Read
mode. Following a read operation, the device en-
ters Automatic Standby after 150ns of bus inactiv-
ity even if Chip Enable is Low, V , and the supply
current is reduced to I
IL
. The data Inputs/Out-
DD1
Read mode is the default state of the device when
exiting Reset or after power-up.
puts will still output data if a bus Read operation is
in progress.
Write. Bus Write operations write Commands to
the memory or latch Input Data to be programmed.
A write operation is initiated when Chip Enable
Reset. During Reset mode when Output Enable
is Low, V , the memory is deselected and the out-
IL
puts are high impedance. The memory is in Reset
and Write Enable are at V with Output Enable at
mode when Reset is at V . The power consump-
IL
IL
V . Commands, Input Data and Addresses are
latched on the rising edge of Write Enable or Chip
Enable, whichever occurs first.
tion is reduced to the Standby level, independently
from the Chip Enable, Output Enable or Write En-
IH
able inputs. If Reset is pulled to V during a Pro-
SS
gram or Erase, this operation is aborted and the
memory content is no longer valid.
See Figure 11. and Figure 12., Write AC Wave-
forms, and Table 15. and Table 16., Write AC
Table 3. Bus Operations
V
Operation
Bus Read
E
G
W
RP
DQ0-DQ15
Data Output
Data Input
Hi-Z
PP
V
V
V
IH
V
IH
Don't Care
V or V
DD
IL
IL
IL
IL
IH
IH
V
V
V
V
V
V
V
V
IH
Bus Write
Output Disable
Standby
IL
PPH
V
IH
Don't Care
Don't Care
Don't Care
IH
V
IH
X
X
Hi-Z
IH
V
Reset
X
X
X
Hi-Z
IL
Note: X = V or V , V = 12V ± 5%.
PPH
IL
IH
11/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
HARDWARE PROTECTION
All devices feature hardware protection. Refer to
SIGNAL DESCRIPTIONS section for a detailed
description of these signals.
V
≤V
. The VPP pin protects all the blocks.
PP
PPLK
Refer to SIGNAL DESCRIPTIONS section for a
detailed description of these signals.
SECURITY FEATURES
The M28W320FS and M28W640FS are equipped
with KRYPTO Security features performing soft-
ware protection. They allow any block to be pro-
tected from program/erase or read operations:
The KRYPTO features (Modify Protection mode,
Read Protection mode and Device Authentication
mechanism) are not described in this Datasheet.
For further details concerning these additional pro-
tection modes please contact ST Sales Offices.
■
Modify Protection including Volatile Block
Lock/Unlock, Non-Volatile Block Modify
Protection, Non-Volatile Password Modify
Protection and Irreversible Protection.
The devices also feature a 64 bit Unique Device
Identifier and a 128 bit user-programmable OTP
segment (see Figure 7., Protection Register Mem-
ory Map and Protection Register Program Com-
mand).
■
Read Protection.
12/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
dles all timings and verifies the correct execution
of the Program and Erase commands. The Pro-
gram/Erase Controller provides a Status Register
whose output may be read at any time during, to
monitor the progress of the operation, or the Pro-
gram/Erase states. See Table 4., Command
Codes, for a summary of the commands and see
APPENDIX D., Table 31., Write State Machine
Current/Next, sheet 1 of 2., for a summary of the
Command Interface.
Table 4. Command Codes
Hex Code
01h
Command
Block Lock confirm
Program
10h
20h
Erase
30h
Double Word Program
Program
40h
50h
Clear Status Register
Quadruple Word Program
Read Status Register
Read Electronic Signature
Read CFI Query
56h
70h
The Command Interface is reset to Read mode
when power is first applied, when exiting from Re-
90h
set or whenever V
is lower than V
. Com-
DD
LKO
mand sequences must be followed exactly. Any
invalid combination of commands will reset the de-
vice to Read mode. Refer to Table 5., Commands,
in conjunction with the text descriptions below.
98h
B0h
C0h
D0h
FFh
Program/Erase Suspend
Protection Register Program
Program/Erase Resume
Read Memory Array
Read Memory Array Command
The Read command returns the memory to its
Read mode. One Bus Write cycle is required to is-
sue the Read Memory Array command and return
the memory to Read mode. Subsequent read op-
erations will read the addressed location and out-
put the data. When a device Reset occurs, the
memory defaults to Read mode.
Read CFI Query Command
The Read Query Command is used to read data
from the Common Flash Interface (CFI) Memory
Area, allowing programming equipment or appli-
cations to automatically match their interface to
the characteristics of the device. One Bus Write
cycle is required to issue the Read Query Com-
mand. Once the command is issued subsequent
Bus Read operations read from the Common
Flash Interface Memory Area. See APPENDIX
B., COMMON FLASH INTERFACE (CFI), Tables
25, 26, 27, 28, 29 and 30 for details on the infor-
mation contained in the Common Flash Interface
memory area.
Read Status Register Command
The Status Register indicates when a program or
erase operation is complete and the success or
failure of the operation itself. Issue a Read Status
Register command to read the Status Register’s
contents. Subsequent Bus Read operations read
the Status Register at any address, until another
command is issued. See Table 9., Status Register
Bits, for details on the definitions of the bits.
The Read Status Register command may be is-
sued at any time, even during a Program/Erase
operation. Any Read attempt during a Program/
Erase operation will automatically output the con-
tent of the Status Register.
Block Erase Command
The Block Erase command can be used to erase
a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost. If the
block is protected then the Erase operation will
abort, the data in the block will not be changed and
the Status Register will output the error.
Read Electronic Signature Command
The Read Electronic Signature command reads
the Manufacturer and Device Codes, and the Pro-
tection Register.
The Read Electronic Signature command consists
of one write cycle, a subsequent read will output
the Manufacturer Code, the Device Code and the
Protection Register. See Tables 6, and 7 for the
valid address.
Two Bus Write cycles are required to issue the
command.
■
The first bus cycle sets up the Erase
command.
■
The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
13/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See APPENDIX C., Figure 16., Double Word Pro-
gram Flowchart and Pseudo Code for the flow-
chart for using the Double Word Program
command.
Erase aborts if Reset turns to V . As data integrity
IL
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table 8., Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See APPENDIX C., Figure 19., Erase Flowchart
and Pseudo Code, for a suggested flowchart for
using the Erase command.
Quadruple Word Program Command
This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1.
A Quadruple word Program command will be ig-
nored if V is not set to V
.
PP
PPH
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
Program Command
■
■
■
■
■
The first bus cycle sets up the Quadruple
Word Program Command.
The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and
the Data of the second word to be written.
The fourth bus cycle latches the Address and
the Data of the third word to be written.
The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
■
The first bus cycle sets up the Program
command.
■
The second latches the Address and the Data
to be written and starts the Program/Erase
Controller.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in Table 8., Program, Erase
Times and Program/Erase Endurance Cycles.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V . As data integrity
IL
Programming aborts if Reset goes to V . As data
IL
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See APPENDIX C., Figure 17., Quadruple Word
Program Flowchart and Pseudo Code, for the
flowchart for using the Quadruple Word Program
command.
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See APPENDIX C., Figure 15., Program Flow-
chart and Pseudo Code, for the flowchart for using
the Program command.
Clear Status Register Command
Double Word Program Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Three bus write cycles are necessary to issue the
Double Word Program command.
■
■
■
The first bus cycle sets up the Double Word
Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pause the Program/Erase control-
ler.
During Program/Erase Suspend the Command In-
terface will accept the Program/Erase Resume,
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V . As data integrity
IL
cannot be guaranteed when the program opera-
14/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Read Array, Read Status Register, Read Electron-
See APPENDIX C., Figure 18., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 20., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Resume command.
ic Signature and Read CFI Query commands. Ad-
ditionally, if the suspend operation was Erase then
the Program, Double Word Program, Quadruple
Word Program, Block Lock, or Protection Program
commands will also be accepted. The block being
erased may be protected by issuing the Block Pro-
tect, Block Lock or Protection Program com-
mands. When the Program/Erase Resume
command is issued the operation will complete.
Only the blocks not being erased may be read or
programmed correctly.
Protection Register Program Command
The Protection Register Program command is
used to Program the 128 bit user One-Time-Pro-
grammable (OTP) segment of the Protection Reg-
ister. The segment is programmed 16 bits at a
time. When shipped all bits in the segment are set
to ‘1’. The user can only program the bits to ‘0’.
During a Program/Erase Suspend, the device can
be placed in a pseudo-standby mode by taking
Two write cycles are required to issue the Protec-
tion Register Program command.
Chip Enable to V . Program/Erase is aborted if
IH
■
The first bus cycle sets up the Protection
Register Program command.
Reset turns to V .
IL
See APPENDIX C., Figure 18., Program Suspend
& Resume Flowchart and Pseudo Code, and Fig-
ure 20., Erase Suspend & Resume Flowchart and
Pseudo Code, for flowcharts for using the Pro-
gram/Erase Suspend command.
■
The second latches the Address and the Data
to be written to the Protection Register and
starts the Program/Erase Controller.
Read operations output the Status Register con-
tent after the programming has started.
Program/Erase Resume Command
The segment can be protected by programming bit
1 of the Protection Lock Register (see Figure
7., Protection Register Memory Map). Attempting
to program a previously protected Protection Reg-
ister will result in a Status Register error. The pro-
tection of the Protection Register is not reversible.
The Program/Erase Resume command can be
used to restart the Program/Erase Controller after
a Program/Erase Suspend operation has paused
it. One Bus Write cycle is required to issue the
command. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister.
The Protection Register Program cannot be sus-
pended.
15/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 5. Commands
Bus Write Operations
Commands
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data
Read Memory
Array
1+ Write
1+ Write
1+ Write
X
X
X
FFh
RA
X
RD
SRD
IDh
Read
Read Status
Register
70h Read
90h Read
Read Electronic
Signature
(2)
SA
Read CFI Query 1+ Write
X
X
98h Read QA
20h Write BA
QD
Erase
2
2
Write
Write
D0h
40h or
Program
Double Word
X
X
Write PA
10h
PD
3
Write
30h Write PA1 PD1 Write PA2 PD2
(3)
Program
Quadruple Word
5
1
1
1
2
Write
Write
Write
Write
Write
X
X
X
X
X
56h Write PA1 PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4
(4)
Program
Clear Status
Register
50h
Program/Erase
Suspend
B0h
Program/Erase
Resume
D0h
Protection
Register Program
C0h Write PRA PRD
Note: 1. X = Don't Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code),
QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Ad-
dress, PRD=Protection Register Data.
2. The signature addresses are listed in Tables 6 and 7.
3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
Table 6. Read Electronic Signature
A8-A20
Code
Device
E
G
W
A0
A1
A2-A7
DQ0-DQ7
DQ8-DQ15
(2)
A8-A21
Manufacture
Code
V
IL
V
IL
V
IH
V
IL
V
0
Don't Care
20h
00h
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
V
M28W320FST
M28W320FSB
M28W640FST
M28W640FSB
0
0
0
0
Don't Care
Don't Care
Don't Care
Don't Care
0Ah
0Bh
58h
59h
88h
88h
88h
88h
IH
IL
V
V
IH
IL
Device Code
V
V
IH
IL
V
V
IH
IL
Note: 1. RP = V
.
IH
2. Addresses range from A0 to A20 for the M28W320FS and from A0 to A21 for the M29W640FS.
16/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 7. Read Protection Register and Protection Register Lock
(1)
Word
E
G
W
A0-A7
DQ0
DQ1
DQ2
DQ3-DQ7 DQ8-DQ15
A8-A21
OTP Prot.
data
V
IL
V
IL
V
IH
Lock
80h Don't Care
0
0
00h
00h
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
Unique ID 0
Unique ID 1
Unique ID 2
Unique ID 3
OTP 0
81h Don't Care
82h Don't Care
83h Don't Care
84h Don't Care
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
ID data
85h Don't Care OTP data
86h Don't Care OTP data
87h Don't Care OTP data
88h Don't Care OTP data
89h Don't Care OTP data
8Ah Don't Care OTP data
8Bh Don't Care OTP data
8Ch Don't Care OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP data OTP data OTP data
OTP 1
OTP 2
OTP 3
OTP 4
OTP 5
OTP 6
OTP 7
Note: 1. Addresses range from A0 to A20 for the M28W320FS and from A0 to A21 for the M29W640FS.
17/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 8. Program, Erase Times and Program/Erase Endurance Cycles
M28W320FST, M28W320FST
M28W640FST, M28W640FSB
Parameter
Test Conditions
Unit
Min
Typ
10
Max
200
200
200
5
V
= V
DD
Word Program
µs
µs
µs
s
PP
V
V
V
= 12V ±5%
= 12V ±5%
= 12V ±5%
= V
Double Word Program
10
PP
PP
Quadruple Word Program
10
(1)
(1)
PP
0.16/0.08
0.32
Main Block Program
V
5
s
PP
DD
V
V
V
= 12V ±5%
= V
4
s
PP
0.02/0.01
Parameter Block Program
Main Block Erase
V
0.04
1
4
s
PP
DD
= 12V ±5%
= V
10
10
10
10
s
PP
V
1
s
s
PP
DD
= 12V ±5%
= V
0.4
0.4
PP
Parameter Block Erase
V
s
PP
DD
Program/Erase Cycles (per Block)
Data Retention
100,000
20
cycles
years
Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands
respectively.
18/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
The various bits convey information and errors on
the operation. To read the Status register the
Read Status Register command can be issued, re-
fer to Read Status Register Command section. To
output the contents, the Status Register is latched
on the falling edge of the Chip Enable or Output
Enable signals, and can be read until Chip Enable
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly. When the
Erase Status bit is High (set to ‘1’), the Program/
Erase Controller has applied the maximum num-
ber of pulses to the block and still failed to verify
that the block has erased correctly. The Erase Sta-
tus bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
or Output Enable returns to V . Either Chip En-
able or Output Enable must be toggled to update
the latched data.
IH
Bus Read operations from any address always
read the Status Register during Program and
Erase operations.
The bits in the Status Register are summarized in
Table 9., Status Register Bits. Refer to Table 9. in
conjunction with the following text descriptions.
Program/Erase Controller Status (Bit 7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive. When the Program/Erase Controller Sta-
tus bit is Low (set to ‘0’), the Program/Erase Con-
troller is active; when the bit is High (set to ‘1’), the
Program/Erase Controller is inactive, and the de-
vice is ready to process a new command.
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program failure. When the
Program Status bit is High (set to ‘1’), the Pro-
gram/Erase Controller has applied the maximum
number of pulses to the byte and still failed to ver-
ify that it has programmed correctly. The Program
Status bit should be read once the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive).
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new command is issued, otherwise the new
command will appear to fail.
During Program, Erase, operations the Program/
Erase Controller Status bit can be polled to find the
end of the operation. Other bits in the Status Reg-
ister should not be tested until the Program/Erase
Controller completes the operation and the bit is
High.
V
Status (Bit 3). The V
Status bit can be
PP
PP
used to identify an invalid voltage on the V pin
during Program and Erase operations. The V
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can oc-
cur if V becomes invalid during an operation.
PP
PP
PP
After the Program/Erase Controller completes its
When the V Status bit is Low (set to ‘0’), the volt-
PP
operation the Erase Status, Program Status, V
age on the V pin was sampled at a valid voltage;
PP
PP
Status and Block Lock Status bits should be tested
for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended or is going to be suspended.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro-
gram/Erase Resume command.
The Erase Suspend Status should only be consid-
ered valid when the Program/Erase Controller Sta-
tus bit is High (Program/Erase Controller inactive).
Bit 7 is set within 30µs of the Program/Erase Sus-
pend command being issued therefore the memo-
ry may still complete the operation rather than
entering the Suspend mode.
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended. When the Program
Suspend Status bit is High (set to ‘1’), a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Re-
sume command. The Program Suspend Status
should only be considered valid when the Pro-
19/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
gram/Erase Controller Status bit is High (Program/
Erase Controller inactive). Bit 2 is set within 5µs of
the Program/Erase Suspend command being is-
sued therefore the memory may still complete the
operation rather than entering the Suspend mode.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a locked block.
When the Block Protection Status bit is High (set
to ‘1’), a Program or Erase operation has been at-
tempted on a locked block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new command is issued, otherwise
the new command will appear to fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value must be masked.
Note: Refer to APPENDIX C., FLOWCHARTS
AND PSEUDO CODES, for using the Status
Register.
Table 9. Status Register Bits
Bit
Name
Logic Level
Definition
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Ready
7
P/E.C. Status
Busy
Suspended
6
5
4
3
2
Erase Suspend Status
Erase Status
In progress or Completed
Erase Error
Erase Success
Program Error
Program Status
Program Success
V
Invalid, Abort
OK
PP
PP
V
PP
Status
V
Suspended
Program Suspend Status
In Progress or Completed
Program/Erase on protected Block, Abort
No operation to protected blocks
1
0
Block Protection Status
Reserved
Note: Logic level '1' is High, '0' is Low.
20/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 10. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
– 40
– 40
– 55
– 0.6
– 0.6
– 0.6
Max
85
(1)
T
°C
°C
°C
V
A
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
T
125
155
BIAS
T
STG
V
V
+0.6
IO
DDQ
V
, V
DD DDQ
4.1
13
V
V
Program Voltage
V
PP
Note: 1. Depends on range.
21/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment
Conditions
summarized
in
Table
11., Operating and AC Measurement Conditions.
Designers should check that the operating condi-
tions in their circuit match the measurement condi-
tions when relying on the quoted parameters.
Table 11. Operating and AC Measurement Conditions
M28W320FST, M28W320FST, M28W640FST, M28W640FSB
Parameter
70
85
90
10
Units
Min
Max
Min
Max
Min
Max
Min
Max
V
V
Supply Voltage
2.7
3.6
2.7
3.6
2.7
3.6
2.7
3.6
V
V
DD
2.7
3.6
85
2.7
3.6
85
2.7
3.6
85
1.65
–40
3.6
85
Supply Voltage (V
≤V
)
DDQ
DDQ
DD
Ambient Operating Temperature
–40
–40
–40
°C
pF
ns
V
Load Capacitance (C )
50
50
50
50
L
Input Rise and Fall Times
Input Pulse Voltages
5
5
5
5
0 to V
0 to V
0 to V
0 to V
DDQ
DDQ
DDQ
DDQ
Input and Output Timing Ref.
Voltages
V
/2
DDQ
V
/2
DDQ
V
/2
V
/2
DDQ
V
DDQ
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
V
DDQ
V
DDQ
V
/2
DDQ
V
DDQ
V
0V
DD
25kΩ
AI00610
DEVICE
UNDER
TEST
C
L
25kΩ
0.1µF
0.1µF
C
includes JIG capacitance
AI00609C
L
Table 12. Capacitance
Symbol
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
6
Unit
pF
C
V
IN
= 0V
= 0V
IN
C
V
OUT
12
pF
OUT
Note: Sampled only, not 100% tested.
22/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 13. DC Characteristics
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Test Condition
Min
Typ
Max
±1
Unit
µA
I
LI
0V≤V ≤V
DDQ
IN
I
LO
0V≤V
≤V
±10
18
µA
OUT DDQ
I
E = V , G = V , f = 5MHz
9
mA
DD
SS
IH
E = V
RP = V
± 0.2V,
Supply Current (Stand-by or
Automatic Stand-by)
DDQ
I
15
50
50
10
20
20
20
50
400
µA
µA
DD1
± 0.2V
DDQ
Supply Current
(Reset)
I
RP = V ± 0.2V
15
5
DD2
SS
Program in progress
mA
mA
mA
mA
µA
V
PP
= 12V ± 5%
I
Supply Current (Program)
Supply Current (Erase)
DD3
Program in progress
= V
10
5
V
PP
DD
Erase in progress
= 12V ± 5%
V
PP
I
DD4
Erase in progress
= V
10
15
V
PP
DD
E = V
Erase suspended
± 0.2V,
Supply Current
(Program/Erase Suspend)
DDQ
I
DD5
Program Current
(Read or Stand-by)
I
V
> V
DD
µA
PP
PP
Program Current
(Read or Stand-by)
I
V
≤V
DD
1
1
1
5
5
µA
µA
PP1
PP
I
RP = V ± 0.2V
Program Current (Reset)
PP2
SS
Program in progress
10
mA
V
= 12V ± 5%
PP
I
Program Current (Program)
PP3
Program in progress
= V
1
3
1
5
10
5
µA
mA
µA
V
PP
DD
Erase in progress
= 12V ± 5%
V
PP
I
Program Current (Erase)
PP4
Erase in progress
= V
V
PP
DD
–0.5
–0.5
0.4
0.8
V
V
V
V
V
Input Low Voltage
Input High Voltage
IL
V
≥ 2.7V
≥ 2.7V
DDQ
DDQ
V
–0.4
V
V
+0.4
DDQ
DDQ
DDQ
V
IH
V
0.7 V
+0.4
DDQ
I
= 100µA, V = V min,
DD DD
OL
V
Output Low Voltage
Output High Voltage
0.1
V
V
V
OL
V
DDQ
= V
min
DDQ
I
= –100µA, V = V min,
DD DD
OH
V
OH
V
–0.1
DDQ
V
DDQ
= V
min
DDQ
Program Voltage (Program or
Erase operations)
V
PP1
1.65
3.6
Program Voltage
(Program or Erase
operations)
V
11.4
12.6
V
PPH
Program Voltage
(Program and Erase lock-out)
V
1
2
V
V
PPLK
V
Supply Voltage (Program
DD
V
LKO
and Erase lock-out)
23/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 10. Read AC Waveforms
tAVAV
VALID
(1)
A0-A20/A21
E
tAVQV
tAXQX
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQV
tGHQX
tGHQZ
tGLQX
VALID
DQ0-DQ15
OUTPUTS
ENABLED
ADDR. VALID
CHIP ENABLE
DATA VALID
STANDBY
AI09928
Note: 1. Addresses range from A0 to A20 for the M28W320FS and from A0 to A21 for the M29W640FS.
Table 14. Read AC Characteristics
M28W320FST, M28W640FST,
M28W320FST M28W640FSB
Symbol Alt
Parameter
Unit
70
70
70
70
70
70
t
t
RC
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
ns
ns
AVAV
t
t
ACC
Max
AVQV
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(2)
(1)
t
Address Transition to Output Transition
Chip Enable High to Output Transition
Chip Enable High to Output Hi-Z
Min
Min
Max
Max
Min
Min
Max
Max
Min
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
OH
OH
AXQX
t
EHQX
t
t
20
70
0
20
70
0
t
HZ
EHQZ
Chip Enable Low to Output Valid
t
CE
ELQV
ELQX
t
Chip Enable Low to Output Transition
Output Enable High to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
t
LZ
t
0
0
t
t
OH
GHQX
GHQZ
t
20
20
0
20
20
0
DF
t
t
t
OE
GLQV
t
OLZ
GLQX
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t
- t
after the falling edge of E without increasing t
.
ELQV
ELQV GLQV
24/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 11. Write AC Waveforms, Write Enable Controlled
Note: 1. Addresses range from A0 to A20 for the M28W320FS and from A0 to A21 for the M29W640FS.
25/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 15. Write AC Characteristics, Write Enable Controlled
M28W320FST, M28W640FST,
M28W320FST M28W640FSB
Symbol
Alt
Parameter
Unit
70
70
45
45
0
70
70
45
45
0
t
t
WC
Write Cycle Time
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
AVAV
t
t
Address Valid to Write Enable High
Data Valid to Write Enable High
Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
AVWH
AS
DS
CS
t
t
t
DVWH
t
ELWL
t
70
70
ELQV
t
QVVPL
(1,2)
Output Valid to V Low
Min
Min
0
0
ns
ns
PP
t
VPHWH
(1)
t
V
PP
High to Write Enable High
200
200
VPS
t
t
t
Write Enable High to Address Transition
Write Enable High to Data Transition
Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
Min
Min
Min
Min
Min
Min
Min
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
WHAX
AH
t
WHDX
DH
CH
t
t
0
0
WHEH
t
25
20
25
45
25
20
25
45
WHEL
t
WHGL
t
t
WPH
WHWL
t
t
WLWH
WP
Note: 1. Sampled only, not 100% tested.
2. Applicable if V is seen as a logic input (V < 3.6V).
PP
PP
26/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 12. Write AC Waveforms, Chip Enable Controlled
Note: 1. Addresses range from A0 to A20 for the M28W320FS and from A0 to A21 for the M29W640FS.
27/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 16. Write AC Characteristics, Chip Enable Controlled
M28W320FST,
M28W320FST
M28W640FST,
M28W640FSB
Symbol Alt
Parameter
Unit
70
70
45
45
0
70
70
45
45
0
t
t
WC
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
t
Address Valid to Chip Enable High
Data Valid to Chip Enable High
AVEH
AS
DS
AH
DH
t
DVEH
EHAX
t
t
t
t
Chip Enable High to Address Transition
Chip Enable High to Data Transition
Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Write Enable High
Chip Enable Low to Chip Enable High
Chip Enable Low to Output Valid
0
0
EHDX
t
t
CPH
25
25
0
25
25
0
EHEL
t
EHGL
t
t
WH
EHWH
t
t
CP
45
70
45
70
ELEH
ELQV
t
t
QVVPL
(1,2)
Output Valid to V Low
Min
0
0
ns
PP
t
VPHEH
(1)
t
V
High to Chip Enable High
Min
Min
200
0
200
0
ns
ns
VPS
PP
t
t
CS
Write Enable Low to Chip Enable Low
WLEL
Note: 1. Sampled only, not 100% tested.
2. Applicable if V is seen as a logic input (V < 3.6V).
PP
PP
28/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 13. Power-Up and Reset AC Waveforms
W, E, G
tPHWL
tPHEL
tPHGL
tPHWL
tPHEL
tPHGL
RP
tVDHPH
tPLPH
Reset
VDD, VDDQ
Power-Up
AI03537b
Table 17. Power-Up and Reset AC Characteristics
M28W320FST,
M28W320FST,
M28W640FST,
M28W640FSB
Symbol
Parameter
Test Condition
Unit
70
During Program
t
t
PHWL
Min
Min
50
µs
Reset High to Write Enable Low, Chip Enable Low,
Output Enable Low
and Erase
t
PHEL
PHGL
others
30
ns
ns
(1,2)
(3)
Reset Low to Reset High
Min
Min
100
t
PLPH
Supply Voltages High to Reset High
50
µs
t
VDHPH
Note: 1. The device Reset is possible but not guaranteed if t
< 100ns.
PLPH
2. Sampled only, not 100% tested.
3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.
29/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
PACKAGE MECHANICAL
Figure 14. TBGA64 - 10x13 active ball array, 1mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
E
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
Note: Drawing is not to scale.
Table 18. TBGA64 - 10x13 active ball array, 1mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.350
Typ
Max
A
A1
A2
b
0.0472
0.0138
0.300
0.800
0.200
0.0118
0.0315
0.0079
0.350
9.900
–
0.500
0.0138
0.3898
–
0.0197
D
10.000
7.000
10.100
0.3937
0.2756
0.3976
D1
ddd
e
–
–
0.100
0.0039
1.000
13.000
7.000
1.500
3.000
0.500
0.500
–
–
0.0394
0.5118
0.2756
0.0591
0.1181
0.0197
0.0197
–
–
E
12.900
13.100
0.5079
0.5157
E1
FD
FE
SD
SE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
30/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
PART NUMBERING
Table 19. Ordering Information Scheme
Example:
M28W640FST 70 ZA
6
T
Device Type
M28
Operating Voltage
W = V = 2.7V to 3.6V; V
= 1.65V to 3.6V
DDQ
DD
Device Function
320FS = 32 Mbit (2 Mb x16), Boot Block, Secure, 0.13µm
640FS = 64 Mbit (4 Mb x16), Boot Block, Secure, 0.13µm
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70ns
Package
ZA = TBGA64:10 x 13mm, 1mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel 24mm Packing
31/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 20. Daisy Chain Ordering Scheme
Example:
M28W640FS
-ZA
T
Device Type
M28W640FS
M28W320FS
Daisy Chain
-ZA = TBGA64: 10 x 13, 1mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = ECOPACK Package, Standard Packing
F = ECOPACK Package, Tape & Reel 24mm Packing
Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available
options (Speed, Package, etc.) or for further information on any aspect of this device, please contact
the ST Sales Office nearest to you.
32/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
APPENDIX A. BLOCK ADDRESS TABLES
Table 21. Top Boot Block Addresses,
M28W320FST
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F00000-F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
Size
(KWord)
#
Address Range
0
4
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
33/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 22. Bottom Boot Block Addresses,
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
M28W320FSB
Size
(KWord)
#
Address Range
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
8
7
6
4
5
4
4
4
3
4
2
4
1
4
0
4
34/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 23. Top Boot Block Addresses,
M28W640FST
Size
(KWord)
#
Address Range
Size
(KWord)
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
#
Address Range
0
4
3FF000-3FFFFF
3FE000-3FEFFF
3FD000-3FDFFF
3FC000-3FCFFF
3FB000-3FBFFF
3FA000-3FAFFF
3F9000-3F9FFF
3F8000-3F8FFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
35/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Size
(KWord)
Size
(KWord)
#
Address Range
#
Address Range
86
87
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
130
131
132
133
134
32
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
32
88
32
89
32
90
32
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
36/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 24. Bottom Boot Block Addresses,
M28W640FSB
Size
(KWord)
#
Address Range
Size
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
2A8000-2AFFFF
2A0000-2A7FFF
298000-29FFFF
290000-297FFF
288000-28FFFF
280000-287FFF
278000-27FFFF
270000-277FFF
268000-26FFFF
260000-267FFF
258000-25FFFF
250000-257FFF
248000-24FFFF
240000-247FFF
238000-23FFFF
230000-237FFF
228000-22FFFF
220000-227FFF
218000-21FFFF
210000-217FFF
208000-20FFFF
200000-207FFF
1F8000-1FFFFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
#
Address Range
(KWord)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
3F8000-3FFFFF
3F0000-3F7FFF
3E8000-3EFFFF
3E0000-3E7FFF
3D8000-3DFFFF
3D0000-3D7FFF
3C8000-3CFFFF
3C0000-3C7FFF
3B8000-3BFFFF
3B0000-3B7FFF
3A8000-3AFFFF
3A0000-3A7FFF
398000-39FFFF
390000-397FFF
388000-38FFFF
380000-387FFF
378000-37FFFF
370000-377FFF
368000-36FFFF
360000-367FFF
358000-35FFFF
350000-357FFF
348000-34FFFF
340000-347FFF
338000-33FFFF
330000-337FFF
328000-32FFFF
320000-327FFF
318000-31FFFF
310000-317FFF
308000-30FFFF
300000-307FFF
2F8000-2FFFFF
2F0000-2F7FFF
2E8000-2EFFFF
2E0000-2E7FFF
2D8000-2DFFFF
2D0000-2D7FFF
2C8000-2CFFFF
2C0000-2C7FFF
2B8000-2BFFFF
2B0000-2B7FFF
98
97
96
95
94
93
37/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Size
(KWord)
Size
(KWord)
#
Address Range
#
Address Range
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
007000-007FFF
006000-006FFF
005000-005FFF
4
3
2
1
0
4
4
4
4
4
004000-004FFF
003000-003FFF
002000-002FFF
001000-001FFF
000000-000FFF
8
7
6
4
5
4
38/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
structure is read from the memory. Tables 25, 26,
27, 28, 29 and 30 show the addresses used to re-
trieve the data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 30., Security Code Area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read
command to return to Read mode.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
Table 25. Query Structure Overview
Offset
00h
Sub-section Name
Description
Reserved for algorithm-specific information
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Reserved
10h
CFI Query Identification String
System Interface Information
Device Geometry Definition
1Bh
27h
Additional information specific to the Primary
Algorithm (optional)
P
A
Primary Algorithm-specific Extended Query table
Alternate Algorithm-specific Extended Query table
Additional information specific to the Alternate
Algorithm (optional)
Note: Query data are always presented on the lowest order data outputs.
Table 26. CFI Query Identification String
Offset
Data
Description
Value
00h
0020h
Manufacturer Code
Device Code
ST
8858h
8859h
880Ah
880Bh
Top
Bottom
01h
02h-0Fh
10h
reserved Reserved
0051h
"Q"
"R"
"Y"
11h
0052h
0059h
0003h
0000h
0035h
0000h
0000h
0000h
0000h
0000h
Query Unique ASCII String "QRY"
12h
13h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
Intel
compatible
14h
15h
Address for Primary Algorithm extended Query table (see Table 28.)
P = 35h
NA
16h
17h
Alternate Vendor Command Set and Control Interface ID Code second vendor -
specified algorithm supported (0000h means none exists)
18h
19h
Address for Alternate Algorithm extended Query table
(0000h means none exists)
NA
1Ah
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
39/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 27. CFI Query System Interface Information
Offset
Data
Description
Value
V
V
V
V
Logic Supply Minimum Program/Erase or Write voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
DD
1Bh
0027h
2.7V
Logic Supply Maximum Program/Erase or Write voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
DD
1Ch
1Dh
1Eh
0036h
00B4h
00C6h
3.6V
11.4V
12.6V
[Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
PP
[Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
PP
bit 3 to 0BCD value in 100 mV
n
1Fh
20h
21h
22h
23h
24h
25h
26h
0004h
0004h
000Ah
0000h
0005h
0005h
0003h
0000h
16µs
16µs
1s
Typical time-out per single word program = 2 µs
n
Typical time-out for Double/Quadruple Word Program = 2 µs
n
Typical time-out per individual block erase = 2 ms
n
NA
Typical time-out for full chip erase = 2 ms
n
512µs
512µs
8s
Maximum time-out for Word program = 2 times typical
n
Maximum time-out for Double/Quadruple Word Program = 2 times typical
n
Maximum time-out per individual block erase = 2 times typical
n
NA
Maximum time-out for chip erase = 2 times typical
40/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 28. Device Geometry Definition
Offset Word
Mode
Data
Description
Value
0016h
4 MByte
n
27h
Device Size = 2 in number of bytes
0017h
8 MByte
28h
29h
0001h
0000h
x16
Async.
Flash Device Interface Code description
2Ah
2Bh
0003h
0000h
n
8
2
Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.
2Ch
0002h
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.
2Dh
2Eh
003Eh
0000h
Region 1 Information
Number of identical-size erase block = 003Eh+1
63
64 KByte
8
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase block = 0007h+1
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
8 KByte
8
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
8 KByte
63
31h
32h
003Eh
0000h
Region 2 Information
Number of identical-size erase block = 003Eh=1
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
64 KByte
127
2Dh
2Eh
007Eh
0000h
Region 1 Information
Number of identical-size erase block = 007Eh+1
2Fh
30h
0000h
0001h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
64 KByte
8
31h
32h
0007h
0000h
Region 2 Information
Number of identical-size erase block = 0007h+1
33h
34h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
8 KByte
41/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Offset Word
Data
Description
Value
8
Mode
2Dh
2Eh
0007h
0000h
Region 1 Information
Number of identical-size erase block = 0007h+1
2Fh
30h
0020h
0000h
Region 1 Information
Block size in Region 1 = 0020h * 256 byte
8 KByte
127
31h
32h
007Eh
0000h
Region 2 Information
Number of identical-size erase block = 007Eh=1
33h
34h
0000h
0001h
Region 2 Information
Block size in Region 2 = 0100h * 256 byte
64 KByte
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 29. Primary Algorithm-Specific Extended Query Table
Offset
Data
Description
Value
(1)
P = 35h
(P+0)h = 35h
(P+1)h = 36h
(P+2)h = 37h
(P+3)h = 38h
(P+4)h = 39h
(P+5)h = 3Ah
(P+6)h = 3Bh
(P+7)h = 3Ch
(P+8)h = 3Dh
0050h
0052h
0049h
0031h
0030h
0066h
0000h
0000h
0000h
"P"
"R"
"I"
Primary Algorithm extended Query table unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
"1"
"0"
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
bit 0Chip Erase supported(1 = Yes, 0 = No)
bit 1Suspend Erase supported(1 = Yes, 0 = No)
bit 2Suspend Program supported(1 = Yes, 0 = No)
bit 3Legacy Lock/Unlock supported(1 = Yes, 0 = No)
bit 4Queued Erase supported(1 = Yes, 0 = No)
bit 5Instant individual block locking supported(1 = Yes, 0 = No)
bit 6Protection bits supported(1 = Yes, 0 = No)
bit 7Page mode read supported(1 = Yes, 0 = No)
bit 8Synchronous read supported(1 = Yes, 0 = No)
bit 31 to 9Reserved; undefined bits are ‘0’
No
Yes
Yes
No
No
Yes
Yes
No
No
(P+9)h = 3Eh
0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
bit 0Program supported after Erase Suspend (1 = Yes, 0 = No)
bit 7 to 1Reserved; undefined bits are ‘0’
Yes
(P+A)h = 3Fh
(P+B)h = 40h
0003h
0000h
Block Lock Status
Defines which bits in the Block Status Register section of the Query are
implemented.
Address (P+A)h contains less significant byte
bit 0Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)
bit 15 to 1Reserved for future use; undefined bits are ‘0’
Yes
Yes
(P+C)h = 41h
(P+D)h = 42h
(P+E)h = 43h
0030h
00C0h
0001h
V
Logic Supply Optimum Program/Erase voltage (highest performance)
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
3V
12V
01
DD
V
Supply Optimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
PP
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Offset
Data
Description
Value
(1)
P = 35h
(P+F)h = 44h
(P+10)h = 45h
(P+11)h = 46h
0080h
0000h
0003h
80h
00h
8
Protection Field 1: Protection Description
Bytes
This field describes user-available One Time Programmable (OTP) Protection
Register bytes. Some are pre-programmed with device unique serial
numbers. Others are user programmable. Bits 0–15 point to the Protection
Register Lock byte, the section’s first byte.
The following bytes are factory pre-programmed and user-programmable.
bit 0 to 7 Lock/bytes JEDEC-plane physical low address
8
Bytes
0003h
0004h
bit 8 to 15Lock/bytes JEDEC-plane physical high address
(P+12)
h = 47h
n
bit 16 to 23 "n" such that 2 = factory pre-programmed bytes
16
Bytes
n
bit 24 to 31 "n" such that 2 = user programmable bytes
(P+13)h = 48h
Reserved
Note: 1. See Table 26., offset 15 for P pointer definition.
Table 30. Security Code Area
Offset
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
Data
00XX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
Description
Protection Register Lock
64 bits: unique device number
128 bits: User Programmable OTP
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
APPENDIX C. FLOWCHARTS AND PSEUDO CODES
Figure 15. Program Flowchart and Pseudo Code
Start
program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0x40) ;
Write 40h or 10h
/*or writeToFlash (any_address, 0x10) ; */
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
} while (status_register.b7== 0) ;
YES
NO
NO
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
Program
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03538b
Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after
PP
a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 16. Double Word Program Flowchart and Pseudo Code
Start
Write 30h
double_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2)
{
writeToFlash (any_address, 0x30) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 1
& Data 1 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
/*Memory enters read status state after
the Program command*/
Write Address 2
& Data 2 (3)
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03539b
Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after
PP
a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 17. Quadruple Word Program Flowchart and Pseudo Code
Start
quadruple_word_program_command (addressToProgram1, dataToProgram1,
addressToProgram2, dataToProgram2,
addressToProgram3, dataToProgram3,
addressToProgram4, dataToProgram4)
{
Write 56h
Write Address 1
& Data 1 (3)
writeToFlash (any_address, 0x56) ;
writeToFlash (addressToProgram1, dataToProgram1) ;
/*see note (3) */
Write Address 2
& Data 2 (3)
writeToFlash (addressToProgram2, dataToProgram2) ;
/*see note (3) */
writeToFlash (addressToProgram3, dataToProgram3) ;
/*see note (3) */
Write Address 3
& Data 3 (3)
writeToFlash (addressToProgram4, dataToProgram4) ;
/*see note (3) */
Write Address 4
& Data 4 (3)
/*Memory enters read status state after
the Program command*/
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
Program
b4 = 0
YES
Error (1, 2)
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI06233
Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after
PP
a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase operations.
3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 18. Program Suspend & Resume Flowchart and Pseudo Code
Start
program_suspend_command ( ) {
writeToFlash (any_address, 0xB0) ;
Write B0h
Write 70h
writeToFlash (any_address, 0x70) ;
/* read status register to check if
program has already completed */
do {
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
Read Status
Register
NO
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
b2 = 1
YES
Program Complete
if (status_register.b2==0) /*program completed */
{ writeToFlash (any_address, 0xFF) ;
read_data ( ) ; /*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
}
Read data from
another address
else
{ writeToFlash (any_address, 0xFF) ;
read_data ( ); /*read data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume program*/
Write FFh
Read Data
Write D0h
}
}
Program Continues
AI03540b
48/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 19. Erase Flowchart and Pseudo Code
Start
erase_command ( blockToErase ) {
writeToFlash (any_address, 0x20) ;
Write 20h
writeToFlash (blockToErase, 0xD0) ;
/* only A12-A20 are significannt */
/* Memory enters read status state after
the Erase Command */
Write Block
Address & D0h
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
YES
NO
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
Error (1)
b3 = 0
YES
if ( (status_register.b4==1) && (status_register.b5==1) )
/* command sequence error */
Command
Sequence Error (1)
b4, b5 = 1
NO
error_handler ( ) ;
if ( (status_register.b5==1) )
/* erase error */
b5 = 0
YES
Erase Error (1)
error_handler ( ) ;
Erase to Protected
Block Error (1)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI03541b
Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code
Start
erase_suspend_command ( ) {
Write B0h
Write 70h
writeToFlash (any_address, 0xB0) ;
writeToFlash (any_address, 0x70) ;
/* read status register to check if
erase has already completed */
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
NO
} while (status_register.b7== 0) ;
b7 = 1
YES
if (status_register.b6==0) /*erase completed */
{ writeToFlash (any_address, 0xFF) ;
b6 = 1
YES
Erase Complete
read_data ( ) ;
/*read data from another block*/
/*The device returns to Read Array
(as if program/erase suspend was not issued).*/
Write FFh
Read data from
another block
or
Program/Protection Program
or
Block Protect/Unprotect/Lock
}
else
{ writeToFlash (any_address, 0xFF) ;
read_program_data ( );
Write D0h
Write FFh
Read Data
/*read or program data from another address*/
writeToFlash (any_address, 0xD0) ;
/*write 0xD0 to resume erase*/
}
}
Erase Continues
AI03542b
50/55
M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Figure 21. Protection Register Program Flowchart and Pseudo Code
Start
protection_register_program_command (addressToProgram, dataToProgram) {:
writeToFlash (any_address, 0xC0) ;
Write C0h
writeToFlash (addressToProgram, dataToProgram) ;
/*Memory enters read status state after
the Program Command*/
Write Address
& Data
do {
Read Status
Register
status_register=readFlash (any_address) ;
/* E or G must be toggled*/
NO
b7 = 1
YES
} while (status_register.b7== 0) ;
NO
V
Invalid
if (status_register.b3==1) /*VPP invalid error */
error_handler ( ) ;
PP
b3 = 0
YES
Error (1, 2)
NO
NO
Program
Error (1, 2)
if (status_register.b4==1) /*program error */
error_handler ( ) ;
b4 = 0
YES
Program to Protected
Block Error (1, 2)
if (status_register.b1==1) /*program to protect block error */
error_handler ( ) ;
b1 = 0
YES
End
}
AI04381
Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after
PP
a sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER
STATE
Table 31. Write State Machine Current/Next, sheet 1 of 2.
Command Input (and Next State)
Data
When
Read
Current
State
SR
bit 7
Read
Array
(FFh)
Program
Setup
(10/40h)
Erase
Setup
(20h)
Erase
Confirm
(D0h)
Prog/Ers
Suspend
(B0h)
Prog/Ers
Resume
(D0h)
Read
Status
(70h)
Clear
Status
(50h)
Read Array “1”
Array
Read Array Prog.Setup Ers. Setup
Read Array
Read Sts. Read Array
Read
“1”
Program
Setup
Erase
Setup
Read
Status
Read Array
Read Array
Read Array
Read Array
Read Array
Status
Status
Read
“1”
Electronic
Signature
Program
Setup
Erase
Setup
Read
Read Array
Read Array
Read Array
Status
Elect.Sg.
Read CFI
“1”
Program
Setup
Erase
Setup
Read
CFI
Read Array
Status
Query
Prot. Prog.
“1”
Status
Status
Protection Register Program
Protection Register Program continue
Setup
Prot. Prog.
“0”
(continue)
Prot. Prog.
“1”
Program
Setup
Erase
Setup
Read
Status
Status
Status
Read Array
Read Array
Program
Read Array
Status
(complete)
Prog. Setup “1”
Program
“0”
Prog. Sus
Read Sts
Program (continue)
Program (continue)
(continue)
Prog. Sus
“1”
Prog. Sus
Read Array
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
Status
Array
Status
(continue) Read Array (continue)
Program Prog. Sus Program
(continue) Read Array (continue)
Prog. Sus
“1”
Prog. Sus
Read Array
Program Suspend to
Read Array
Prog. Sus Prog. Sus
Read Sts Read Array
Read Array
Prog. Sus
Read
Elect.Sg.
Electronic Prog. Sus
Signature Read Array
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
“1”
(continue) Read Array (continue)
Prog. Sus
Read CFI
Prog. Sus
CFI
Program Suspend to
Read Array
Program
Prog. Sus
Program
Prog. Sus Prog. Sus
Read Sts Read Array
“1”
“1”
“1”
“1”
“0”
“1”
“1”
Read Array
(continue) Read Array (continue)
Program
(complete)
Program
Setup
Erase
Setup
Read
Status
Status
Status
Status
Status
Array
Read Array
Read Array
Read Array
Status
Erase
Setup
Erase
Erase
Erase
Erase Command Error
Erase Command Error
(continue) CmdError (continue)
Erase
Cmd.Error
Program
Setup
Erase
Setup
Read
Read Array
Read Array
Read Array
Status
Erase
(continue)
Erase Sus
Read Sts
Erase (continue)
Erase (continue)
Erase Sus
Read Sts
Erase Sus
Read Array
Program Erase Sus
Erase
Erase Sus
Erase
Erase
Erase Sus Erase Sus
Read Sts Read Array
Setup
Read Array (continue) Read Array (continue)
Erase Sus
Read Array
Erase Sus
Read Array
Program
Setup
Erase Sus
Erase
Erase Sus
Erase Sus Erase Sus
Read Sts Read Array
Read Array (continue) Read Array (continue)
Erase Sus
Read
Elect.Sg.
Electronic Erase Sus
Signature Read Array
Program
Setup
Erase Sus
Erase
Erase Sus
Erase
Erase Sus Erase Sus
Read Sts Read Array
“1”
Read Array (continue) Read Array (continue)
Erase Sus
Read CFI
Erase Sus
CFI
Program
Setup
Erase Sus
Erase
Erase Sus
Erase
Erase Sus Erase Sus
Read Sts Read Array
“1”
“1”
Read Array
Read Array (continue) Read Array (continue)
Erase
(complete)
Program
Setup
Erase
Read
Status
Read Array
Read Array
Setup
Read Array
Status
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Table 32. Write State Machine Current/Next, sheet 2 of 2.
Command Input (and Next State)
Current State
Read Elect.Sg.
(90h)
Read CFI Query
(98h)
Prot. Prog. Setup (C0h)
Read Array
Read Status
Read Elect.Sg.
Read Elect.Sg.
Read Elect.Sg.
Read Elect.Sg.
Read CFI Query
Read CFI Query
Prot. Prog. Setup
Prot. Prog. Setup
Prot. Prog. Setup
Prot. Prog. Setup
Read Elect.Sg.
Read CFI Query
Read CFI Query
Prot. Prog. Setup
Prot. Prog. (continue)
Prot. Prog. (complete)
Prog. Setup
Read CFI Query
Protection Register Program
Protection Register Program (continue)
Read CFI Query
Read Elect.Sg.
Prot. Prog. Setup
Program
Program (continue)
Program (continue)
Prog. Suspend
Read Status
Prog. Suspend Read Elect.Sg.
Prog. Suspend Read Elect.Sg.
Prog. Suspend Read Elect.Sg.
Prog. Suspend Read CFI Query Program Suspend Read Array
Prog. Suspend Read CFI Query Program Suspend Read Array
Prog. Suspend Read CFI Query Program Suspend Read Array
Prog. Suspend Read CFI Query Program Suspend Read Array
Prog. Suspend
Read Array
Prog. Suspend
Read Elect.Sg.
Prog. Suspend
Read CFI
Prog. Suspend Read Elect.Sg.
Read Elect.Sg.
Program (complete)
Erase Setup
Read CFIQuery
Erase Command Error
Read CFI Query
Prot. Prog. Setup
Prot. Prog. Setup
Erase Cmd.Error
Erase (continue)
Read Elect.Sg.
Erase (continue)
Erase Suspend
Read Ststus
Erase Suspend
Read CFI Query
Erase Suspend Read Elect.Sg.
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query
Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query
Erase Suspend Read Array
Erase Suspend Read Array
Erase Suspend Read Array
Prot. Prog. Setup
Erase Suspend Read Elect.Sg.
Erase Suspend Read CFI Query Erase Suspend Read Elect.Sg. Erase Suspend Read CFI Query
Erase (complete) Read Elect.Sg. Read CFI Query
Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
REVISION HISTORY
Table 33. Document Revision History
Date
Version
Revision Details
13-Jul-2004
0.1
First Issue.
DU (‘Do Not Use’) pins changed to NC (‘Not Connected’) in Figure 4., TBGA
Connections (Top view through package).
05-Nov-2004
0.2
Data at address 47h differentiated for M28W320FS and M28W640FS inTable
29., Primary Algorithm-Specific Extended Query Table.
20-Jan-2005
15-Mar-2005
01-Aug-2005
0.3
1.0
2.0
Datasheet status promoted to PRELIMINARY DATA.
Datasheet status promoted to FULL DATASHEET.
ECOPACK text updated.
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M28W320FST, M28W320FSB, M28W640FST, M28W640FSB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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