M29DW128G60ZA6 [STMICROELECTRONICS]
IC,EEPROM,NOR FLASH,8MX16,CMOS,BGA,64PIN,PLASTIC;
| 型号： | M29DW128G60ZA6 |
| 厂家： | 
ST |
| 描述： | IC,EEPROM,NOR FLASH,8MX16,CMOS,BGA,64PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总85页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29DW128G
128 Mbit (8 Mb x 16, multiple bank, page, dual boot)
3 V supply Flash memory
Features
■ Supply voltage
– V = 2.7 to 3.6 V for program, erase and
CC
read
– V
– V
= 1.65 to 3.6 V for I/O buffers
= 9 V for fast program (optional)
CCQ
PPH
■ Asynchronous random/page read
– Page width: 8 words
TSOP56 (NF)
14 x 20 mm
– Page access: 25 ns
– Random access: 60 or 70, 80 ns
BGA
■ Enhanced Buffered Program commands
– 256 words
■ Programming time
– 15 µs per word (typical)
– 32-word write buffer
TBGA64 (ZA)
10 x 13 mm
– Chip program time: 5 s with V
and 8 s
PPH
■ 100,000 program/erase cycles per block
without V
PPH
■ Low power consumption
■ Erase verify
– Standby and automatic standby
■ Memory blocks
■ Hardware block protection
– Quadruple bank memory array:
16 Mbit+48 Mbit+48 Mbit+16 Mbit
– V /WP pin for fast program and write
PP
protect of the four outermost parameter
blocks
– Parameter blocks (at top and bottom)
■ Dual operation
■ Security features
– while program or erase in one bank, read in
any of the other banks
– Volatile protection
– Non-volatile protection
– Password protection
– Additional block protection
■ Program/erase suspend and resume modes
– Read from any block during program
suspend
■ Extended memory block
– Read and program another block during
erase suspend
– Extra block (128-word factory locked and
128-word customer lockable) used as
security block or to store additional
information
■ Unlock Bypass/Block Erase/Chip Erase/Write
to Buffer/ Enhanced Buffered Program
commands
■ Electronic signature
– Faster production/batch programming
– Faster block and chip erase
– Manufacturer code: 0020h
– Device code: 227Eh+2220h+2202h
■ ECOPACK® packages available
■ Common Flash interface
– 64 bit security code
March 2008
Rev 1
1/85
www.st.com
1
Contents
M29DW128G
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VPP/write protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ready/busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
CC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CCQ input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
V
2.11 Vss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
3.5
3.6
Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4
Auto select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.0.1
4.0.2
4.0.3
Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Verify extended memory block protection indicator . . . . . . . . . . . . . . . . 18
Verify block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
6
Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1
Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Software protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1
Volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/85
M29DW128G
Contents
6.2
Non-volatile protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2.1
6.2.2
Non-volatile protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Non-volatile protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.3
Password protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1
Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
Write to Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Enhanced Buffered Program command . . . . . . . . . . . . . . . . . . . . . . . . . 31
Buffered Program Abort and Reset command . . . . . . . . . . . . . . . . . . . . 32
Write to Buffer Program Confirm command . . . . . . . . . . . . . . . . . . . . . . 33
Enhanced Buffered Program Confirm command . . . . . . . . . . . . . . . . . . 33
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Unlock Bypass Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . 34
Unlock Bypass Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.10 Unlock Bypass Write to Buffer Program command . . . . . . . . . . . . . . . . 34
7.2.11 Unlock Bypass Enhanced Buffered Program command . . . . . . . . . . . . 34
7.2.12 Unlock Bypass CFI command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.13 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3
Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Enter Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . 36
Exit Extended Memory Block command . . . . . . . . . . . . . . . . . . . . . . . . 37
Lock register command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Password protection mode command set . . . . . . . . . . . . . . . . . . . . . . . 37
Non-volatile protection mode command set . . . . . . . . . . . . . . . . . . . . . . 38
3/85
Contents
M29DW128G
7.3.6
7.3.7
7.3.8
NVPB lock bit command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Volatile protection mode command set . . . . . . . . . . . . . . . . . . . . . . . . . 40
Exit protection command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1
8.2
8.3
Lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
Volatile lock boot bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Password protection mode lock bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . 43
Non-volatile protection mode lock bit (DQ1) . . . . . . . . . . . . . . . . . . . . . 43
Extended block protection bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DQ15 to DQ5 and DQ3 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Data polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Erase timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Alternative toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Buffered program abort bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9
Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 51
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10
11
12
13
Appendix A Block addresses and read/modify protection groups . . . . . . . . . . 69
Appendix B Common Flash interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Appendix C Extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
C.1
C.2
Factory locked section of extended memory block . . . . . . . . . . . . . . . . . . 78
Customer lockable section of extended memory block . . . . . . . . . . . . . . . 79
Appendix D Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4/85
M29DW128G
Contents
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5/85
List of tables
M29DW128G
List of tables
Table 1.
Table 2.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3.
V
/WP functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PP
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Enhanced buffered program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Block protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 42
Lock register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Block protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Write AC characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Write AC characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Accelerated program and data polling/data toggle AC characteristics . . . . . . . . . . . . . . . . 65
TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data . . . . 66
TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data. . . . 67
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Extended memory block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
6/85
M29DW128G
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
NVPB program/erase algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Lock register program flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 10. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 12. Power-up waiting timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 13. Random read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 14. Page read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 15. Write enable controlled program waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 16. Chip enable controlled program waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 17. Reset AC waveforms (no program/erase ongoing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 18. Reset during program/erase operation AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 19. Accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 20. Data polling AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 21. TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . . . . . . 66
Figure 22. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline . . . . . . . . . . . 67
Figure 23. Write to buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 24. Enhanced buffered program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7/85
Description
M29DW128G
1
Description
The M29DW128G is a 128 Mbit (8 Mb x 16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to
3.6 V) supply. At power-up the memory defaults to its read mode.
The M29DW128G features an asymmetrical block architecture, with 8 parameter and 62
main blocks, divided into four banks, A, B, C and D, providing multiple bank operations.
While programming or erasing in one bank, read operations are possible in any other bank.
The bank architecture is summarized in Table 2. Four of the parameter blocks are at the top
of the memory address space, and four are at the bottom.
Program and erase commands are written to the command interface of the memory. An on-
chip program/erase controller simplifies the process of programming or erasing the memory
by taking care of all of the special operations that are required to update the memory
contents. The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The Chip Enable, Output Enable and Write Enable signals control the bus operations of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The device supports asynchronous random read and page read from all blocks of the
memory array. The device also features a write to buffer program capability that improves
the programming throughput by programming in one shot a buffer of 32 words. The
enhanced buffered program feature is also available to speed up the programming
throughput, allowing to program 256 words in one shot. The V /WP signal can be used to
PP
enable faster programming of the device.
The M29DW128G has one extra 256 words block (extended block, 128 words factory locked
and 128 words customer lockable) that can be accessed using a dedicated command. The
extended block can be protected and so is useful for storing security information. However
the protection is irreversible, once protected the protection cannot be undone.
Each block can be erased independently, so it is possible to preserve valid data while old
data is erased.
The device features different levels of hardware and software block protection to avoid
unwanted program or erase (modify):
■
■
Hardware protection
–
The V /WP provides a hardware protection of the four outermost parameter
PP
blocks (two at the top and two at the bottom of the address space)
Software protection
–
–
–
Volatile protection
Non-volatile protection
Password protection
■
Additional protection features are available upon customer request.
The memory is offered in TSOP56 (14 x 20 mm) and TBGA64 (10 x 13 mm, 1 mm pitch)
packages. The memory is delivered with all the bits erased (set to ‘1’).
8/85
M29DW128G
Description
Direction
Table 1.
Signal names
Signal name
Function
A0-A22
DQ0-DQ15
E
Address inputs
Inputs
I/O
Data inputs/outputs
Chip Enable
Input
G
Output Enable
Write Enable
Input
W
Input
RP
Input
Reset/Block Temporary Unprotect
Ready/Busy output
RB
Output
Supply
Supply
Supply/input
–
VCC
Supply voltage
VCCQ
VPP/WP
VSS
Input/output buffer supply voltage
VPP/Write Protect
Ground
NC
Not connected internally
–
Figure 1.
Logic diagram
V
V
/WP
PP
V
CC
CCQ
23
16
A0-A22
DQ0-DQ15
W
E
M29DW128G
G
RB
RP
V
SS
AI09208c
Table 2.
Bank
Bank architecture
Bank size
Parameter blocks
Block size
Main blocks
N. of blocks
N. of blocks
Block size
A
B
C
D
16 Mbit
48 Mbit
48 Mbit
16 Mbit
4
—
—
4
32 Kwords
—
7
24
24
7
128 Kwords
128 Kwords
128 Kwords
128 Kwords
—
32 Kwords
9/85
Description
M29DW128G
Figure 2.
TSOP connections
NC
A22
A15
A14
A13
A12
A11
A10
A9
1
56
NC
NC
A16
NC
V
SS
DQ15
DQ7
DQ14
DQ6
A8
DQ13
DQ5
A19
A20
W
DQ12
DQ4
14
15
43
42
V
RP
CC
M29DW128G
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
A21
V
/WP
RB
A18
A17
A7
PP
A6
A5
A4
V
A3
SS
E
A2
A0
A1
NC
NC
NC
28
29
V
CCQ
AI09209d
10/85
M29DW128G
Description
Figure 3.
TBGA connections (top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
NC
NC
A3
A4
A7
RB
W
A9
A8
A13
A12
NC
V
/WP
A17
RP
A21
A22
PP
NC
NC
NC
A2
A1
A0
E
A6
A5
A18
A20
DQ2
A10
A11
A14
A15
A16
NC
NC
V
A19
CCQ
V
DQ0
DQ8
DQ5
DQ12
DQ7
DQ14
SS
DQ10
NC
V
CCQ
NC
V
DQ15
G
DQ9
DQ1
DQ11
DQ3
DQ13
DQ6
NC
NC
CC
G
H
V
V
NC
DQ4
SS
SS
AI09210c
11/85
Description
Figure 4.
M29DW128G
Block addresses
Address lines A22-A0
000000h
400000h
41FFFFh
32 Kwords
128 Kwords
007FFFh
Total of 4
parameter
Total of 24
main blocks
Bank C
blocks
018000h
6E0000h
32 Kwords
128 Kwords
128 Kwords
01FFFFh
020000h
6FFFFFh
700000h
Bank A
128 Kwords
03FFFFh
71FFFFh
7C0000h
Total of 7
main blocks
Total of 7
main blocks
0E0000h
128 Kwords
128 Kwords
32 Kwords
0FFFFFh
100000h
7DFFFFh
7E0000h
Bank D
128 Kwords
11FFFFh
7E7FFFh
Total of 24
main blocks
Total of 4
parameter
blocks
Bank B
3E0000h
7F8000h
7FFFFFh
128 Kwords
32 Kwords
3FFFFFh
AI08967b
12/85
M29DW128G
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals
connected to this device.
2.1
2.2
Address inputs (A0-A22)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the program/erase controller.
Data inputs/outputs (DQ0-DQ15)
The data I/O outputs the data stored at the selected address during a bus read operation.
During bus write operations they represent the commands sent to the command interface of
the internal state machine. During bus write operations the command register does not use
DQ8-DQ15 bits that should be also ignored when reading the status register.
2.3
Chip Enable (E)
The Chip Enable pin, E, activates the memory, allowing bus read and bus write operations to
be performed. When chip enable is High, V , all other pins are ignored.
IH
2.4
2.5
Output Enable (G)
The Output Enable pin, G, controls the bus read operation of the memory.
Write Enable (W)
The Write Enable pin, W, controls the bus write operation of the memory’s command
interface.
2.6
VPP/write protect (VPP/WP)
The V /write protect pin provides two functions. The V
function allows the memory to
PPH
PP
use an external high voltage power supply to reduce the time required for program
operations. This is achieved by bypassing the unlock cycles.
The write protect function provides a hardware method of protecting the four outermost
blocks, that is the two 32-kword blocks at the top and the two 32-kword blocks at the bottom
of the address space (see Section 1: Description). When V /write protect is Low, V , the 4
PP
IL
outermost blocks are protected. Program and erase operations on this block are ignored
while V /write protect is Low.
PP
13/85
Signal descriptions
M29DW128G
When V /write protect is High, V , the memory reverts to the previous protection status of
PP
IH
the four outermost blocks. Program and erase operations can now modify the data in these
blocks unless the blocks are protected using block protection.
When V /write protect is raised to V
the memory automatically enters the unlock
PP
PPH
bypass mode (see Section 7.2.6).
When V /write protect is raised to V
, the execution time of the command is lower (see
PP
PPH
Table 12: Program, erase times and program, erase endurance cycles).
When V /write protect returns to V or V normal operation resumes. During unlock
PP
IH
IL
bypass program operations the memory draws I from the pin to supply the programming
PP
circuits. See the description of the Unlock Bypass command in the command interface
section. The transitions from V to V
and from V
to V must be slower than t
IH
PPH
PPH IH VHVPP
(see Figure 19: Accelerated program timing waveforms).
Never raise V /write protect to V from any mode except read mode, otherwise the
PP
PPH
memory may be left in an indeterminate state. A 0.1 µF capacitor should be connected
between the VPP/write protect pin and the V ground pin to decouple the current surges
SS
from the power supply. The PCB track widths must be sufficient to carry the currents
required during unlock bypass program (see I
, I
, I
, I
in Table 22: DC
PP1 PP2 PP3 PP4
characteristics).
The V /write protect pin may be left floating or unconnected because it features an internal
PP
pull-up.
Refer to Table 3 for a summary of V /WP functions.
PP
Table 3.
V
/WP functions
PP
VPP/WP
Function
Four outermost blocks(1) protected.
VIL
VIH
Four outermost blocks(1) unprotected unless a software protection is
activated (see Section 5: Hardware protection).
Unlock bypass mode. It supplies the current needed to speed up
programming.
VPPH
1. Two at the top and two at the bottom of the address space.
2.7
Reset (RP)
The reset pin can be used to apply a hardware reset to the memory.
A hardware reset is achieved by holding reset Low, V , for at least t
. After reset goes
IL
PLPX
High, V , the memory will be ready for bus read and bus write operations after t
or
PHEL
IH
t
, whichever occurs last. See Section 2.8: Ready/busy output (RB), Table 26: Reset AC
RHEL
characteristics, Figure 17 and Figure 18 for more details.
2.8
Ready/busy output (RB)
The ready/busy pin is an open-drain output that can be used to identify when the device is
performing a program or erase operation. During program or erase operations ready/busy is
Low, V (see Table 15: Status register bits). Ready/busy is high-impedance during read
OL
mode, auto select mode and erase suspend mode.
14/85
M29DW128G
Signal descriptions
After a hardware reset, bus read and bus write operations cannot begin until ready/busy
becomes high-impedance. See Table 26: Reset AC characteristics, Figure 17 and
Figure 18.
The use of an open-drain output allows the ready/busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.9
VCC supply voltage
V
provides the power supply for all operations (read, program and erase).
CC
The command interface is disabled when the V supply voltage is less than the lockout
CC
voltage, V
. This prevents bus write operations from accidentally damaging the data
LKO
during power-up, power-down and power surges. If the program/erase controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1 µF capacitor should be connected between the V supply voltage pin and the V
CC
SS
ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during program and erase operations (see
I
, I
, I
in Table 22: DC characteristics).
CC1 CC2 CC3
2.10
2.11
VCCQ input/output supply voltage
V
provides the power supply to the I/O pins and enables all outputs to be powered
CCQ
independently from V
.
CC
Vss ground
V
is the reference for all voltage measurements. The device features two V pins both of
SS
SS
which must be connected to the system ground.
15/85
Bus operations
M29DW128G
3
Bus operations
There are five standard bus operations that control the device. These are bus read (random
and page modes), bus write, output disable, standby and automatic standby.
Dual operations are possible in the M29DW128G, thanks to its multiple bank architecture.
While programming or erasing in one bank, read operations are possible in any of the other
banks. Write operations are only allowed in one bank at a time.
See Table 4: Bus operations for a summary. Typical glitches of less than 5 ns on chip
enable, write enable, and reset pins are ignored by the memory and do not affect bus
operations.
3.1
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. To speed up the read operation the memory array can be read in page mode
where data is internally read and stored in a page buffer. The page has a size of 8 words
and the specific word inside the page is addressed by the address inputs A0-A2.
A valid bus read operation involves setting the desired address on the address inputs,
applying a Low signal, V , to Chip Enable and Output Enable and keeping Write Enable
IL
High, V . The data inputs/outputs will output the value, see Figure 13: Random read AC
IH
waveforms, Figure 14: Page read AC waveforms, and Table 23: Read AC characteristics, for
details of when the output becomes valid.
3.2
Bus write
Bus write operations write to the command interface. A valid bus write operation begins by
setting the desired address on the address inputs. The address inputs are latched by the
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The data inputs/outputs are latched by the command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V ,
IH
during the whole bus write operation. See Figure 15: Write enable controlled program
waveforms and Table 24 and Table 25, Write AC characteristics, for details of the timing
requirements.
3.3
3.4
Output disable
The data inputs/outputs are in the high impedance state when output enable is High, V .
IH
Standby
Driving Chip Enable High, V , in read mode, causes the memory to enter standby mode
IH
and the data inputs/outputs pins are placed in the high-impedance state. To reduce the
supply current to the standby supply current, I
, Chip Enable should be held within
CC2
V
± 0.3 V. For the standby current level see Table 22: DC characteristics.
CC
16/85
M29DW128G
Bus operations
During program or erase operations the memory will continue to use the program/erase
supply current, I , for program or erase operations until the operation completes.
CC3
3.5
3.6
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when RP is at VIL. The power consumption is reduced to the
standby level, independently from the Chip Enable, Output Enable or Write Enable inputs.
Automatic standby
Automatic standby allows the memory to achieve low power consumption during read mode.
After a read operation, if CMOS levels (V ± 0.3 V) are used to drive the bus and the bus is
CC
inactive for t
+ 30 ns or more, the memory enters automatic standby where the internal
AVQV
supply current is reduced to the standby supply current, I
(see Table 22: DC
CC2
characteristics). The data inputs/outputs will still output data if a bus read operation is in
progress.
The power supplier of data bus, V
, can have a null consumption (depending on load
CCQ
circuits connected with data bus) when the memory enters automatic standby.
Table 4.
Bus operations
Address inputs
A22-A0
Data inputs/outputs
Operation(1)
E
G
W
RP
VPP/WP
DQ15-DQ0
Bus Read
Bus Write
VIL
VIL
VIH
X
VIL
VIH
X
VIH
VIL
X
VIH
VIH
VIH
VIH
VIL
X
X(2)
X
Cell address
Data output
Data input
Hi-Z
Command address
Standby
X
Address
X
Output Disable
Reset
VIH
X
VIH
X
X
Hi-Z
X
X
Hi-Z
1. X = VIL or VIH
.
2. To write the four outermost parameter blocks (first two and last two), VPP/WP must be equal to VIH
.
17/85
Auto select mode
M29DW128G
4
Auto select mode
The auto select mode allows the system or the programming equipment to read the
electronic signature, verify the protection status of the extended memory block, and
apply/remove block protection. For example, this mode can be used by a programming
equipment to automatically match a device and the application code to be programmed.
The auto select mode is entered by issuing the Auto Select command (see Section 7.1.2:
Auto Select command).
At power-up, the device is in read mode, and can then be put in auto select mode by issuing
the Auto Select command.
The device cannot enter auto select mode when a program or erase operation is ongoing
(RB Low). However, auto select mode can be entered if the erase operation has been
suspended by issuing an Erase Suspend command (see Section 7.1.6).
The auto select mode is exited by performing a reset. The device is returned to read mode,
except if the auto select mode was entered after an Erase Suspend or a Program Suspend
command. In this case, it returns to the erase or program suspend mode.
4.0.1
4.0.2
Read electronic signature
The memory has two codes, the manufacturer code and the device code used to identify the
memory. These codes can be accessed by performing read operations with control signals
and addresses set as shown in Table 6: Block protection and Table 5: Read electronic
signature.
Verify extended memory block protection indicator
The extended memory block is either factory locked or customer lockable.
The protection status of the extended memory block (factory locked or customer lockable)
can be accessed by reading the extended memory block protection indicator (see Table 6:
Block protection).
The protection status of the extended memory block is then output on bit DQ7 of the data
input/outputs (see Table 4: Bus operations).
4.0.3
Verify block protection status
The protection status of a block can be directly accessed by performing a read operation
with control signals and addresses set as shown in Table 6: Block protection.
If the block is protected, then 01h is output on data input/outputs DQ0-DQ7, otherwise 00h
is output.
18/85
M29DW128G
Auto select mode
Table 5.
Read electronic signature
Data
inputs/outputs
Address inputs
A5-
Read
E
G
W
cycle(1)
A22- A11-
A9 A8 A7-A6
A3 A2 A1
A0
DQ15-DQ0
0020h
A12
A10
A4
Manufacturer
code
X
VIL VIL VIL
VIL
Device code
(cycle 1)
VIL VIL VIL VIH
227Eh
VIL VIL VIH BKA
X
X
X
VIL
Device code
(cycle 2)
VIL VIH VIH VIH VIL
2220h
Device code
(cycle 3)
VIH VIH VIH VIH
2202h
1. X = VIL or VIH. BKA bank address.
Table 6.
Block protection
Address inputs
Data inputs/outputs
DQ15-DQ0
VPP
WP
/
Operation
E
G
W
RP
(1)
A22- A11-
A12 A10
A5- A3-
A4 A2
A9 A8 A7 A6
A1 A0
DQ15-DQ8=0
DQ7: 1=locked, 0=unlocked
DQ6: 1=locked, 0=unlocked
DQ5: 1=reserved,
Verify
extended
memory
block
indicator
bit
0=standard
BKA
VIH
DQ4, DQ3-Hardware write
protection: 00=WP protects 4
outermost blocks, 11=No WP
protection
VIL VIL VIH
X
X
X
VIL VIL VIL VIH
VIL
VIH VIH
DQ2-DQ0=0
Verify
0000h (unprotected)
0001h (protected)
block
protection
status
BAd
VIL
1. X = VIL or VIH. BAd any address in the block, BKA bank address.
19/85
Hardware protection
M29DW128G
5
Hardware protection
The M29DW128G features hardware protection/unprotection. Refer to Table 7: Hardware
protection for details on hardware block protection/unprotection using V /WP and RP pins.
PP
5.1
Write protect
The V /WP pin can be used to protect the four outermost parameter blocks (refer to
PP
Section 2: Signal descriptions for a detailed description of the signals). When V /WP is at
PP
V the four outermost parameter blocks are protected and remain protected regardless of
IL
the block protection status or the reset pin state.
Table 7.
Hardware protection
VPP/WP
Function
4 outermost parameter blocks (first two and last two) protected from
program/erase operations
VIL
VIH
4 outermost parameter blocks unprotected unless a software activated (see
Section 5: Hardware protection)
Unlock bypass mode. It supplies the current needed to speed up
programming
VPPH
6
Software protection
The M29DW128G has four different software protection modes:
■
■
■
Volatile protection
Non-volatile protection
Password protection
On first use all parts default to operate in non-volatile protection mode and the customer is
free to activate the non-volatile or the password protection mode.
The desired protection mode is activated by setting either the one-time programmable non-
volatile protection mode lock bit or the password protection mode lock bit of the lock register
(see Section 8.1: Lock register). Programming the non-volatile protection mode lock bit or
the password protection mode lock bit to ‘0’ will permanently activate the non-volatile or the
password protection mode, respectively. These three bits are one-time programmable and
non-volatile: once the protection mode has been programmed, it cannot be changed and the
device will permanently operate in the selected protection mode. It is recommended to
activate the desired software protection mode when first programming the device.
The non-volatile and password protection modes provide non-volatile protection. Volatilely
protected blocks and non-volatilely protected blocks can co-exist within the memory array.
However, the volatile protection only control the protection scheme for blocks that are not
protected using the non-volatile or password protection.
20/85
M29DW128G
Software protection
If the user attempts to program or erase a protected block, the device ignores the command
and returns to read mode.
The device is shipped with all blocks unprotected. The block protection status can be read
either by performing a read electronic signature (see Table 5: Read electronic signature) or
by issuing an Auto Select command (see Table 14: Block protection status).
For the four outermost blocks (that is the two blocks at the top and the two at the bottom of
the address space), an even higher level of block protection can be achieved by locking the
blocks using the non-volatile protection and then by holding the V /WP pin Low.
PP
6.1
Volatile protection mode
The volatile protection allows the software application to easily protect blocks against
inadvertent change. However, the protection can be easily disabled when changes are
needed. Volatile protection bits, VPBs, are volatile and unique for each block and can be
individually modified. VPBs only control the protection scheme for unprotected blocks that
have their non-volatile protection bits, NVPBs, cleared (erased to ‘1’) (see Section 6.2: Non-
volatile protection mode and Section 7.3.5: Non-volatile protection mode command set).
By issuing the VPB Program or VPB Clear commands, the VPBs are set (programmed to
‘0’) or cleared (erased to ‘1’), thus placing each block in the protected or unprotected state
respectively. The VPBs can be set (programmed to ‘0’) or cleared (erased to ‘1’) as often as
needed.
The default values of the volatile protections are set through the VLBB (volatile lock boot bit)
of the lock register (see Table 13: Lock register bits).
When the parts are first shipped, or after a power-up or hardware reset, the VPBs can be
set or cleared depending upon the ordering option chosen:
■
If the option to clear the VPBs after power-up is selected, then the blocks can be
programmed or erased depending on the NVPBs state (see Table 14: Block protection
status)
■
If the option to set the VPBs after power-up is selected, the blocks default to be
protected.
Refer to Section 7.3.7 for a description of the volatile protection mode command set.
6.2
Non-volatile protection mode
6.2.1
Non-volatile protection bits
A non-volatile protection bit (NVPB) is assigned to each block.
When a NVPB is set to ‘0’, the associated block is protected, preventing any program or
erase operations in this block.
The NVPB bits are set individually by issuing a NVPB Program command. They are non-
volatile and will remain set through a hardware reset or a power-down/power-up sequence.
The NVPBs cannot be cleared individually, they can only be cleared all at the same time by
issuing a Clear all Non-volatile Protection Bits command.
The NVPBs can be protected all at a time by setting a volatile bit, the NVPB lock bit (see
Section 6.2.2: Non-volatile protection bit lock bit).
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Software protection
M29DW128G
If one of the non-volatile protected blocks needs to be unprotected (corresponding NVPB
set to ‘1’), a few more steps are required:
1. First, the NVPB lock bit must be cleared by either putting the device through a power
cycle, or hardware reset
2. The NVPBs can then be changed to reflect the desired settings
3. The NVPB lock bit must be set once again to lock the NVPBs. The device operates
normally again.
Note:
1
2
To achieve the best protection, it is recommended to execute the NVPB Lock Bit Program
command early in the boot code and to protect the boot code by holding V /WP Low, V .
PP
IL
The NVPBs and VPBs have the same function when V /WP pin is High, V , as they do
PP
IH
when V /WP pin is at the voltage for program acceleration (V
).
PP
PPH
Refer to Table 14: Block protection status and Figure 5: Software protection scheme for
details on the block protection mechanism, and to Section 7.3.5 for a description of the non-
volatile protection mode command set.
6.2.2
Non-volatile protection bit lock bit
The non-volatile protection bit lock bit (NVPB lock bit) is a global volatile bit for all blocks.
When set (programmed to ‘0’), it prevents changing the state of the NVPBs. When cleared
(programmed to ‘1’), the NVPBs can be set and reset using the NVPB Program command
and Clear all NVPBs command, respectively.
There is only one NVPB lock bit per device.
Refer to Section 7.3.6 for a description of the NVPB lock bit command set.
Note:
1
2
No software command unlocks this bit unless the device is in password protection mode; it
can be cleared only by taking the device through a hardware reset or a power-up.
The NVPB lock bit must be set (programmed to ‘0’) only after all NVPBs are configured to
the desired settings.
6.3
Password protection mode
The password protection mode provides an even higher level of security than the non-
volatile protection mode by requiring a 64-bit password for unlocking the device NVPB lock
bit.
In addition to this password requirement, the NVPB lock bit is set ‘0’ after power-up and
reset to maintain the device in password protection mode. Successful execution of the
Password Unlock command by entering the correct password clears the NVPB lock bit,
allowing for block NVPBs to be modified.
If the password provided is not correct, the NVPL Lock bit remains locked and the state of
the NVPBs cannot be modified.
To place the device in password protection mode, the following steps are required:
1. Prior to entering the password protection mode, it is necessary to set a 64-bit password
and to verify it (see Password Program command and Password Read command).
Password verification is only allowed during the password programming operation
2. The password protection mode is then activated by programming the password
protection mode lock bit to ‘0’. This operation is not reversible and once the bit is
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M29DW128G
Software protection
programmed it cannot be erased, the device permanently remains in password
protection mode, and the 64-bit password can neither be retrieved nor reprogrammed.
Moreover, all commands to the address where the password is stored, are disabled.
Refer to Table 14: Block protection status and Figure 5: Software protection scheme for
details on the block protection scheme.
Refer to Section 7.3.4 for a description of the password protection mode command set.
Note:
There is no means to verify the password after it is set. If the password is lost after setting
the password mode lock bit, there is no way to clear the NVPB lock bit.
Figure 5.
Software protection scheme
(2)
VPB
(1)
NVPB
Parameter block or
main block
(3)
NVPB Lock bit
Volatile protection
Non-volatile protection
Non-volatile
protection mode
Password protection
mode
AI13676
1. NVPBs default to ‘1’ (block unprotected) after power-up and hardware reset. A block is protected or unprotected when its
NVPB is set to ‘0’ and ‘1’, respectively. NVPBs are programmed individually and cleared collectively.
2. VPB default status depends on ordering option. A block is protected or unprotected when its VPB is set to ‘0’ and ‘1’,
respectively. VPBs are programmed and cleared individually. For the volatile protection to be effective, the NVPB lock bit
must be set to ‘0’ (NVPB bits unlocked) and the block NVPB must be set to ‘1’ (block unprotected).
3. The NVPB Lock bit is volatile and default to ‘1’ (NVPB bits unlocked) after power-up and hardware reset. NVPB bits are
locked by setting the NVPB lock bit to ‘0’. Once programmed to ‘0’, the NVPB lock bit can be reset to ‘1’ only be taking the
device through a power-up or hardware reset.
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Command interface
M29DW128G
7
Command interface
All bus write operations to the memory are interpreted by the command interface.
Commands consist of one or more sequential bus write operations. Failure to observe a
valid sequence of bus write operations will result in the memory returning to read mode. The
long command sequences are imposed to maximize data security.
7.1
Standard commands
See Table 8: Standard commands for a summary of the standard commands.
7.1.1
Read/Reset command
The device is in read mode after reset or after power-up.
The Read/Reset command returns the memory to read mode. It also resets the errors in the
Status register. Either one or three bus write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between bus write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the timeout of a block erase operation, the memory will take up to 10 µs to
abort. During the abort period no valid data can be read from the memory.
The Read/Reset command will not abort an erase operation when issued while in erase
suspend.
7.1.2
Auto Select command
The Auto Select command puts the device in auto select mode (see Section 4: Auto select
mode). When in auto select mode, the system can read the manufacturer code, the device
code, the protection status of each block (block protection status) and the extended memory
block protection indicator.
Three consecutive bus write operations are required to issue the Auto Select command.
Once the Auto Select command is issued bus read operations to specific addresses output
the manufacturer code, the device code, the extended memory block protection indicator
and a block protection status (see Table 8: Standard commands in conjunction with Table 5:
Read electronic signature, and Table 6: Block protection). The memory remains in auto
select mode until a Read/Reset or CFI Query command is issued.
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M29DW128G
Command interface
7.1.3
Read CFI Query command
The memory contains an information area, named CFI data structure, which contains a
description of various electrical and timing parameters, density information and functions
supported by the memory. See Appendix B, Table 32, Table 33, Table 34, Table 35, Table 36
and Table 37 for details on the information contained in the common Flash interface (CFI)
memory area.
The Read CFI Query command is used to put the memory in read CFI query mode. Once in
read CFI query mode, bus read operations to the memory will output data from the common
Flash interface (CFI) memory area. One bus write cycle is required to issue the Read CFI
Query command. This command is valid only when the device is in the read array or auto
select mode.
The Read/Reset command must be issued to return the device to the previous mode (the
read array mode or auto select mode). A second Read/Reset command is required to put
the device in read array mode from auto select mode.
7.1.4
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six bus write operations are
required to issue the Chip Erase command and start the program/erase controller.
If some block are protected, then these are ignored and all the other blocks are erased. If all
of the blocks are protected the chip erase operation appears to start but will terminate within
about 100 µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 12. All bus read operations during the chip erase
operation will output the Status register on the data inputs/outputs. See Section 8.2: Status
register for more details.
After the chip erase operation has completed the memory will return to the read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status register. A Read/Reset command must be issued to reset the error condition and
return to read mode.
The Chip Erase command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
The chip erase operation is aborted by performing a reset or powering down the device. In
this case, data integrity cannot be ensured, and it is recommended to erase again the entire
chip.
7.1.5
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is
lost.
Six bus write operations are required to select the first block in the list. Each additional block
in the list can be selected by repeating the sixth bus write operation using the address of the
additional block. After the command sequence is written, a block erase timeout occurs.
During the timeout period, additional sector addresses and sector erase commands may be
written. Once the program/erase controller has started, it is not possible to select any more
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Command interface
M29DW128G
blocks. Each additional block must therefore be selected within the timeout period of the last
block. The timeout timer restarts when an additional block is selected. After the sixth bus
write operation, a bus read operation outputs the status register. See Figure 15: Write
enable controlled program waveforms for details on how to identify if the program/erase
controller has started the block erase operation.
After the block erase operation has completed, the memory returns to the read mode,
unless an error has occurred. When an error occurs, bus read operations will continue to
output the status register. A Read/Reset command must be issued to reset the error
condition and return to read mode.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the block erase operation appears to
start but will terminate within about 100 µs, leaving the data unchanged. No error condition
is given when protected blocks are ignored.
During the block erase operation the memory ignores all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the
timeout period. Typical block erase time and block erase timeout are given in Table 12.
The block erase operation is aborted by performing a reset or powering down the device. In
this case, data integrity cannot be ensured, and it is recommended to erase again the blocks
aborted.
7.1.6
Erase Suspend command
The Erase Suspend command can be used to temporarily suspend a block erase operation.
One bus write operation is required to issue the command together with the block address.
After the command sequence is written, a minimum block erase timeout occurs (see
Section 7.1.6: Erase Suspend command). During the timeout period, additional block
addresses and block erase commands can be written.
The program/erase controller suspends the erase operation within the erase suspend
latency time of the Erase Suspend command being issued. However, when the Erase
Suspend command is written during the block erase timeout, the device immediately
terminates the timeout period and suspends the erase operation.
Once the program/erase controller has stopped, the memory operates in read mode and the
erase is suspended.
During erase suspend it is possible to read and execute program or write to buffer program
operations in blocks that are not suspended; both read and program operations behave as
normal on these blocks. Reading from blocks that are suspended will output the Status
register. If any attempt is made to program in a protected block or in the suspended block
then the Program command is ignored and the data remains unchanged. In this case the
Status register is not read and no error condition is given.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an erase suspend. The Read/Reset command must be issued to return the device to
read array mode before the Resume command will be accepted.
During erase suspend a bus read operation to the extended memory block will output the
extended memory block data. Once in the extended block mode, the Exit Extended Block
command must be issued before the erase operation can be resumed.
The Erase Suspend command is ignored if written during chip erase operations.
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M29DW128G
Command interface
Refer to Table 12: Program, erase times and program, erase endurance cycles for the
values of block erase timeout and block erase suspend latency time.
If the erase suspend operation is aborted by performing a reset or powering down the
device, data integrity cannot be ensured, and it is recommended to erase again the blocks
suspended.
7.1.7
7.1.8
Erase Resume command
The Erase Resume command is used to restart the program/erase controller after an erase
suspend.
The device must be in read array mode before the Resume command will be accepted. An
erase can be suspended and resumed more than once.
Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the program suspend
latency time (see Table 12: Program, erase times and program, erase endurance cycles)
and updates the status register bits.
After the program operation has been suspended, the system can read array data from any
address. However, data read from program-suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in Erase
Suspend or Program Suspend. If a read is needed from the extended memory block area
(one-time program area), the user must use the proper command sequences to enter and
exit this region.
The system may also issue the Auto Select command sequence when the device is in the
program suspend mode. The system can read as many auto select codes as required.
When the device exits the auto select mode, the device reverts to the program suspend
mode, and is ready for another valid operation. See Auto Select command sequence for
more information.
If the program suspend operation is aborted by performing a reset or powering down the
device, data integrity cannot be ensured, and it is recommended to program again the words
or bytes aborted.
7.1.9
Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. Refer to Figure 15: Write enable controlled
program waveforms for details.
The system must issue a Program Resume command, to exit the program suspend mode
and to continue the programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
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Command interface
M29DW128G
7.1.10
Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four bus write operations, the final write operation latches
the address and data in the internal state machine and starts the program/erase controller.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 7.1.8: Program
Suspend command and Section 7.1.9: Program Resume command).
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status register is never read and no error condition is given.
After programming has started, bus read operations output the status register content. See
Figure 15: Write enable controlled program waveforms for more details. Typical program
times are given in Table 12: Program, erase times and program, erase endurance cycles.
After the program operation has completed the memory will return to the read mode, unless
an error has occurred. When an error occurs, bus read operations to the memory continue
to output the status register. A Read/Reset command must be issued to reset the error
condition and return to read mode.
One of the erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
The program operation is aborted by performing a reset or powering-down the device. In this
case data integrity cannot be ensured, and it is recommended to reprogram the word or byte
aborted.
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M29DW128G
Command interface
Table 8.
Standard commands
Bus operations(1)
3rd 4th
Add Data Add Data Add Data Add Data Add Data Add Data
Command
1st
2nd
5th
6th
1
3
X
F0
Read/Reset
Manufacturer code
555
AA 2AA 55
X
F0
90
A0
Device code
Extended memory
block protection
indicator
Auto
Select
(BKA)
555
(2)(3) (2)(3)
3
555
AA 2AA 55
Block protection
status
Program(4)
4
6
555
555
AA 2AA 55
AA 2AA 55
AA 2AA 55
B0
555
555
555
PA
PD
Chip Erase
80 555 AA 2AA 55 555 10
80 555 AA 2AA 55 BAd 30
Block Erase
6+ 555
Erase/Program Suspend
Erase/Program Resume
1
1
BKA
BKA
30
BKA
(555)
Read CFI Query
1
98
1. X don’t care, PA program address, PD program data, BAd any address in the block, BKA bank address. All values in the
table are in hexadecimal.
2. These cells represent read cycles. All the other cells are write cycles.
3. The auto select addresses and data are given in Table 5: Read electronic signature, and Table 6: Block protection, except
for A9 that is ‘don’t care’.
4. In unlock bypass, the first two unlock cycles are no more needed (see Table 9: Fast program commands).
29/85
Command interface
M29DW128G
7.2
Fast program commands
The M29DW128G offers a set of fast program commands to improve the programming
throughput:
■
■
■
Write to Buffer Program
Enhanced Buffered Program
Unlock Bypass.
See Table 9: Fast program commands for a summary of the fast program commands.
When V is applied to the V /write protect pin the memory automatically enters unlock
PPH
PP
bypass mode (see Section 7.2.6: Unlock Bypass command).
After programming has started, bus read operations in the memory output the Status
register content. Write to Buffer Program command can be suspended and then resumed by
issuing a Program Suspend command and a Program Resume command, respectively (see
Section 7.1.8: Program Suspend command and Section 7.1.9: Program Resume
command).
After the fast program operation has completed, the memory will return to the read mode,
unless an error has occurred. When an error occurs bus read operations to the memory will
continue to output the status register. A Read/Reset command must be issued to reset the
error condition and return to read mode. One of the erase commands must be used to set all
the bits in a block or in the whole memory from ’0’ to ’1’.
Typical program times are given in Table 12: Program, erase times and program, erase
endurance cycles.
7.2.1
Write to Buffer Program command
The Write to Buffer Program command makes use of the device’s 32-word write buffer to
speed up programming. 32 words can be loaded into the write buffer. Each write buffer has
the same A22-A5 addresses.The Write to Buffer Program command dramatically reduces
system programming time compared to the standard non-buffered Program command.
When issuing a Write to Buffer Program command, the V /WP pin can be either held High,
PP
V , or raised to V
.
IH
PPH
See Table 12 for details on typical write to buffer program times in both cases.
Five successive steps are required to issue the Write to Buffer Program command:
1. The Write to Buffer Program command starts with two unlock cycles
2. The third bus write cycle sets up the Write to Buffer Program command. The setup
code can be addressed to any location within the targeted block
3. The fourth bus write cycle sets up the number of words to be programmed. Value N is
written to the same block address, where N+1 is the number of words to be
programmed. N+1 must not exceed the size of the write buffer or the operation will
abort
4. The fifth cycle loads the first address and data to be programmed
5. Use N bus write cycles to load the address and data for each word into the write buffer.
Addresses must lie within the range from the start address+1 to the start address + N-
1. Optimum performance is obtained when the start address corresponds to a 32-word
boundary. If the start address is not aligned to a 32-word boundary, the total
programming time is doubled.
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M29DW128G
Command interface
All the addresses used in the write to buffer program operation must lie within the same
page.
To program the content of the write buffer, this command must be followed by a Write to
Buffer Program Confirm command.
If an address is written several times during a write to buffer program operation, the
address/data counter will be decremented at each data load operation and the data will be
programmed to the last word loaded into the buffer.
Invalid address combinations or failing to follow the correct sequence of bus write cycles will
abort the Write to Buffer Program.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during a write to buffer program operation.
It is possible to detect program operation fails when changing programmed data from ‘0’ to
‘1’, that is when reprogramming data in a portion of memory already programmed. The
resulting data will be the logical OR between the previous value and the current value.
See Appendix D, Figure 23: Write to buffer program flowchart and pseudocode, for a
suggested flowchart on using the Write to Buffer Program command.
7.2.2
Enhanced Buffered Program command
The Enhanced Buffered Program command makes use of the device’s 256-word write buffer
to speed up programming. 256 words can be loaded into the write buffer. Each write buffer
has the same A22-A8 addresses. The Enhanced Buffered Program command dramatically
reduces system programming time compared to both the standard non-buffered Program
command and the Write to Buffer command.
When issuing an Enhanced Buffered Program command, the V /WP pin can be either held
PP
High, V , or raised to V
.
IH
PPH
See Table 12: Program, erase times and program, erase endurance cycles for details on
typical enhanced buffered program times in both cases.
Three successive steps are required to issue the Enhanced Buffered Program command:
■
■
The Enhanced Buffered Program command starts with two unlock cycles
The third bus write cycle sets up the Enhanced Buffered Program command. The setup
code can be addressed to any location within the targeted block
■
The fourth bus write cycle loads the first address and data to be programmed. There a
total of 256 address and data loading cycles.
To program the content of the write buffer, the Enhanced Buffered Program command must
be followed by an Enhanced Buffered Program Confirm command. The command ends with
an internal enhanced buffered program confirm cycle.
Note that address/data cycles must be loaded in an increasing address order (from
ADD[7:0]=00000000 to ADD[7:0]=11111111) and completely (all 256 words). Invalid
address combinations or failing to follow the correct sequence of bus write cycles will abort
the enhanced buffered program.
The Status register bits DQ1, DQ5, DQ6, and DQ7 can be used to monitor the device status
during an enhanced buffered program operation.
An external supply (12 V) can be used to improve programming efficiency.
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M29DW128G
It is possible to detect program operation fails when changing programmed data from ‘0’ to
‘1’, that is when reprogramming data in a portion of memory already programmed. The
resulting data will be the logical OR between the previous and the current value.
See Appendix D and Figure 24: Enhanced buffered program flowchart and pseudocode, for
a suggested flowchart on using the Enhanced Buffered Program command.
7.2.3
Buffered Program Abort and Reset command
A Buffered Program Abort and Reset command must be issued to abort the write to buffer
program and enhanced buffered program operation and reset the device in read mode.
The write to buffer and enhanced buffered programming sequence can be aborted in the
following ways:
■
■
■
■
■
Load a value that is greater than the page buffer size during the number of locations to
program step in the Write to Buffer Program command
Write to an address in a block different than the one specified during the write-buffer-
load command
Write an address/data pair to a different write-buffer-page than the one selected by the
starting address during the write buffer data loading stage of the operation
Write data other than the Confirm command after the specified number of data load
cycles
Load address/data pairs in an incorrect sequence during the enhanced buffered
program.
The abort condition is indicated by DQ1 = 1, DQ7 = DQ7 (for the last address location
loaded), DQ6 = toggle, and DQ5 = 0 (all of which are Status register bits). A Buffered
Program Abort and Reset command sequence must be written to reset the device for the
next operation. Note that the full 3-cycle Buffered Program Abort and Reset command
sequence is required when using write to buffer and enhanced buffered programming
features in unlock bypass mode.
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M29DW128G
Command interface
7.2.4
7.2.5
7.2.6
Write to Buffer Program Confirm command
The Write to Buffer Program Confirm command is used to confirm a Write to Buffer Program
command and to program the N+1 words/bytes loaded in the write buffer by this command.
Enhanced Buffered Program Confirm command
The Enhanced Buffered Program Confirm command is used to confirm an Enhanced
Buffered Program command and to program the 256 words loaded in the buffer.
Unlock Bypass command
The Unlock Bypass command is used to place the device in unlock bypass mode. When the
device enters the unlock bypass mode, the two initial unlock cycles required in the standard
program command sequence are no more needed, and only two write cycles are required to
program data, instead of the normal four cycles (see Note 4 below Table 8: Standard
commands). This results in a faster total programming time.
Unlock Bypass command is consequently used in conjunction with the Unlock Bypass
Program command to program the memory faster than with the standard program
commands. When the cycle time to the device is long, considerable time saving can be
made by using these commands. Three bus write operations are required to issue the
Unlock Bypass command.
When in unlock bypass mode, only the following commands are valid:
■
■
■
■
■
■
■
The Unlock Bypass Program command can be issued to program addresses within the
memory
The Unlock Bypass Block Erase command can then be issued to erase one or more
memory blocks
The Unlock Bypass Chip Erase command can be issued to erase the whole memory
array
The Unlock Bypass Write to Buffer Program command can be issued to speed up
programming operation
The Unlock Bypass Enhanced Buffered Program command can be issued to speed up
programming operation
The Unlock Bypass CFI command can be issued to read the CFI when the memory is
in the unlock bypass mode
The Unlock Bypass Reset command can be issued to return the memory to read mode.
In unlock bypass mode the memory can be read as if in read mode.
7.2.7
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two bus write operations, the final write operation
latches the address and data and starts the program/erase controller.
The program operation using the Unlock Bypass Program command behaves identically to
the program operation using the Program command. The operation cannot be aborted, a
bus read operation to the memory outputs the Status register. See the Program command
for details on the behavior.
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Command interface
M29DW128G
7.2.8
Unlock Bypass Block Erase command
The Unlock Bypass Block Erase command can be used to erase one or more memory
blocks at a time. The command requires two bus write operations instead of six using the
standard Block Erase command. The final bus write operation latches the address of the
block and starts the program/erase controller.
To erase multiple block (after the first two bus write operations have selected the first block
in the list), each additional block in the list can be selected by repeating the second bus write
operation using the address of the additional block.
The Unlock Bypass Block Erase command behaves in the same way as the Block Erase
command: the operation cannot be aborted, and a bus read operation to the memory
outputs the Status register (see Section 7.1.5: Block Erase command for details).
7.2.9
Unlock Bypass Chip Erase command
The Unlock Bypass Chip Erase command can be used to erase all memory blocks at a time.
The command requires two bus write operations only instead of six using the standard Chip
Erase command. The final bus write operation starts the program/erase controller.
The Unlock Bypass Chip Erase command behaves in the same way as the Chip Erase
command: the operation cannot be aborted, and a bus read operation to the memory
outputs the Status register (see Section 7.1.4: Chip Erase command for details).
7.2.10
Unlock Bypass Write to Buffer Program command
The Unlock Bypass Write to Buffer command can be used to program the memory in fast
program mode. The command requires two bus write operations less than the standard
Write to Buffer Program command.
The Unlock Bypass Write to Buffer Program command behaves in the same way as the
Write to Buffer Program command: the operation cannot be aborted and a bus read
operation to the memory outputs the status register (see Section 7.2.1: Write to Buffer
Program command for details).
The Write to Buffer Program Confirm command is used to confirm an Unlock Bypass Write
to Buffer Program command and to program the N+1 words loaded in the write buffer by this
command.
7.2.11
Unlock Bypass Enhanced Buffered Program command
The Unlock Bypass Enhanced Buffered Program command can be used to program the
memory in fast program mode. The command requires two address/data loading cycles less
than the standard Enhanced Buffered Program command (see Table 10: Enhanced buffered
program commands).
The Unlock Bypass Enhanced Buffered Program command behaves identically to the
enhanced buffered program operation using the Enhanced Buffered Program command.
The operation cannot be aborted and a bus read operation to the memory outputs the
Status register (see Section 7.2.2: Enhanced Buffered Program command for details on the
behavior).
The Enhanced Buffered Program Confirm command is used to confirm an Unlock Bypass
Enhanced Buffered Program command and to program the 256 words loaded in the buffer.
34/85
M29DW128G
Command interface
7.2.12
7.2.13
Unlock Bypass CFI command
The Unlock Bypass CFI command allows to use any address in the bank to perform a CFI
query when the memory is in the unlock bypass mode.
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to read/reset mode from unlock
bypass mode. Two bus write operations are required to issue the Unlock Bypass Reset
command. Read/Reset command does not exit from unlock bypass mode.
Table 9.
Fast program commands
Bus write operations(1)
1st
2nd
3rd
4th
5th
6th
Command
Add Data Add Data Add Data Add Data Add Data Add Data
Write to Buffer
Program
WBL
N+5 555
BAd
AA 2AA
29
55
BAd
25
BAd N(2) PA(3)
PD
PD
(4)
Write to Buffer
Program Confirm
1
(5)
Buffered Program
Abort and Reset
3
3
2
555
555
X
AA 2AA
AA 2AA
55
55
555
555
F0
20
Unlock Bypass
Unlock Bypass
Program
A0
80
80
PA
BAd
X
PD
Unlock Bypass
Block Erase
2+
2
X
X
30
10
Unlock Bypass
Chip Erase
Unlock Bypass
Write to Buffer
Program
PA
WBL
N+3 BAd
25
BAd N(2)
PD
PD
(3)
(4)
Unlock Bypass
CFI
1
2
BKA
X
98
90
Unlock Bypass
Reset
X
00
1. X don’t care, PA program address, PD program data, BAd any address in the block, BKA bank address, WBL write buffer
location. All values in the table are in hexadecimal.
2. The maximum number of cycles in the command sequence is 36. N+1 is the number of words to be programmed during
the write to buffer program operation.
3. Each buffer has the same A22-A5 addresses. A0-A4 are used to select a word within the N+1 word page.
4. The 6th cycle has to be issued N time. WBL scans the word inside the page.
5. BAd must be identical to the address loaded during the write to buffer program 3rd and 4th cycles.
35/85
Command interface
M29DW128G
(1)(2)
Table 10. Enhanced buffered program commands
Bus write operations
... 257th
Command
1st
2nd
3rd
4th
258th
259th
260th
Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data
Enhanced
Buffered
Program
BAd
(00)
BAd
(FF)
259 555
AA
29
2AA
55
BAd
33
Data
...
...
Data
Enhanced
Buffered
Program
Confirm
BAd
1
(00)
Unlock
Bypass
Enhanced 257 BAd
Buffered
BAd
(00)
BAd
(FF)
33
Data
Data
Program
1. Only available from week 8 of 2008.
2. BAd any address in the block.
7.3
Protection commands
Blocks can be protected individually against accidental program, erase or read operations.
The device block protection scheme is shown in Figure 5: Software protection scheme. See
Table 11: Block protection commands for a summary of the block protection commands.
The memory block and extended memory block protection is configured through the Lock
register (see Section 8.1: Lock register).
7.3.1
Enter Extended Memory Block command
The M29DW128G has one extra 256-word block (extended memory block) that can only be
accessed using the Enter Extended Memory Block command.
The extended memory block is divided in two memory areas of 128 words each: the first one
is factory locked and the second one is customer lockable.
Three Bus Write cycles are required to issue the Extended Memory Block command. Once
the command has been issued the device enters the extended memory block mode where
all bus read or program operations are conducted on the extended memory block. Once the
device is in the extended block mode, the extended memory block is addressed by using the
addresses occupied by the boot blocks in the other operating modes (see Table 31: Block
addresses).
The device remains in extended memory block mode until the Exit Extended Memory Block
command is issued or power is removed from the device. After power-up or a hardware
reset, the device reverts to read mode where the commands issued to the boot block
address space will address the boot blocks.
The extended memory block cannot be erased, and can be treated as one-time
programmable (OTP) memory.
In extended block mode only array cell locations (bank A) with the same addresses as the
extended block are not accessible. In extended block mode dual operations are allowed and
36/85
M29DW128G
Command interface
the extended block physically belongs to bank A. In extended block mode, Erase, Chip
Erase, Erase Suspend and Erase Resume commands are not allowed.
To exit from the extended memory block mode the Exit Extended Memory Block command
must be issued.
The extended memory block can be protected by setting the extended memory block
protection bit to ‘1’ (see Section 8.1: Lock register); however once protected the protection
cannot be undone.
Note:
When the device is in the extended memory block mode, the V /WP pin cannot be used for
PP
fast programming and the unlock bypass mode is not available (see Section 2.6: VPP/write
protect (VPP/WP)).
7.3.2
Exit Extended Memory Block command
The Exit Extended Memory Block command is used to exit from the extended memory block
mode and return the device to read mode. Four bus write operations are required to issue
the command.
7.3.3
Lock register command set
The M29DW128G offers a set of commands to access the lock register and to configure
and verify its content. See the following sections in conjunction with Section 8.1: Lock
register and Table 11: Block protection commands.
Enter Lock Register Command Set command
Three bus write cycles are required to issue the Enter Lock Register Command set
command. Once the command has been issued, all bus read or program operations are
issued to the lock register.
Lock Register Program and Lock Register Read command
The Lock Register Program command allows to configure the lock register. The
programmed data can then be checked by issuing a Lock Register Read command.
An Exit Protection Command set command must then be issued to return the device to read
mode (see Section 7.3.8: Exit protection command set).
7.3.4
Password protection mode command set
Enter Password Protection Command Set command
Three bus write cycles are required to issue the Enter Password Protection Command Set
command. Once the command has been issued, the commands related to the password
protection mode can be issued to the device.
Password Program command
The Password Program command is used to program the 64-bit password used in the
password protection mode.
To program the 64-bit password, the complete command sequence must be entered four
times at four consecutive addresses selected by A1-A0.
The password can be checked by issuing a Password Read command.
37/85
Command interface
M29DW128G
Once password program operation has completed, an Exit Protection Command Set
command must be issued to return the device to read mode. The password protection mode
can then be selected.
By default, all password bits are set to ‘1’.
Password Read command
The Password Read command is used to verify the password used in password protection
mode.
To verify the 64-bit password, the complete command sequence must be entered four times
at four consecutive addresses selected by A1-A0.
If the password mode lock bit is programmed and the user attempts to read the password,
the device will output FFh onto the I/O data bus.
An Exit Protection Command Set command must be issued to return the device to read
mode.
Password Unlock command
The Password Unlock command is used to clear the NVPB lock bit allowing to modify the
NVPBs.
The Password Unlock command must be issued along with the correct password.
There must be a 1 µs delay between successive password unlock commands in order to
prevent hackers from cracking the password by trying all possible 64-bit combinations. If this
delay is not respected, the latest command will be ignored.
Approximately 1 µs is required for unlocking the device after the valid 64-bit password has
been provided.
7.3.5
Non-volatile protection mode command set
Enter Non-volatile Protection Command Set command
Three bus write cycles are required to issue the Enter Non-volatile Protection Command Set
command. Once the command has been issued, the commands related to the non-volatile
protection mode can be issued to the device.
Non-volatile Protection Bit Program command (NVPB Program)
A block can be protected from program or erase by issuing a Non-volatile Protection Bit
command along with the block address. This command sets the NVPB to ‘1’ for a given
block.
Read Non-volatile Protection Bit Status command (Read NVPB Status)
The status of a NVPB for a given block or group of blocks can be read by issuing a Read
Non-Volatile Modify Protection Bit command along with the block address.
Clear all Non-volatile Protection Bits command (Clear all NVPBs)
The NVPBs are erased simultaneously by issuing a Clear all Non-volatile Protection Bits
command. No specific block address is required. If the NVPB lock bit is set to ‘0’, the
command fails.
38/85
M29DW128G
Command interface
Figure 6.
NVPB program/erase algorithm
Enter NVPB
command set.
Program NVPB
Addr = BAd
Read Byte twice
Addr = BAd
NO
DQ6=
Toggle
YES
NO
DQ5=1
YES
Wait 500 µs
Read Byte twice
Addr = BAd
NO
Read Byte twice
Addr = BAd
DQ6=
Toggle
DQ0=
'1'(Erase)
'0'(Program)
NO
YES
Fail
Reset
Pass
Exit NVPB
command set
AI14242
39/85
Command interface
M29DW128G
7.3.6
NVPB lock bit command set
Enter NVPB Lock Bit Command Set command
Three bus write cycles are required to issue the Enter NVPB Lock Bit Command Set
command. Once the command has been issued, the commands allowing to set the NVPB
lock bit can be issued to the device.
NVPB Lock Bit Program command
This command is used to set the NVPB Lock bit to ‘0’ thus locking the NVPBs, and
preventing them from being modified.
Read NVPB Lock Bit Status command
This command is used to read the status of the NVPB lock bit.
7.3.7
Volatile protection mode command set
Enter Volatile Protection Command Set command
Three bus write cycles are required to issue the Enter Volatile Protection Command Set
command. Once the command has been issued, the commands related to the volatile
protection mode can be issued to the device.
Volatile Protection Bit Program command (VPB Program)
The VPB Program command individually sets a VPB to ‘0’ for a given block.
If the NVPB for the same block is set, the block is locked regardless of the value of the VPB
bit (see Table 14: Block protection status).
Read VPB Status command
The status of a VPB for a given block can be read by issuing a Read VPB Status command
along with the block address.
VPB Clear command
The VPB Clear command individually clears (sets to ‘1’) the VPB for a given block.
If the NVPB for the same block is set, the block is locked regardless of the value of the VPB
bit. (see Table 14: Block protection status).
7.3.8
Exit protection command set
The Exit Protection Command Set command is used to exit from the Lock register,
password protection, non-volatile protection, volatile protection, and NVPB lock bit
command set mode. It returns the device to read mode.
40/85
M29DW128G
Command interface
(1)(2)(3)
2nd
Table 11. Block protection commands
Bus operations
3rd 4th
Command
1st
5th
6th
7th
Ad
Data
Ad
Data
Ad
Data Ad Data Ad Data Ad Data Ad Data
Enter Lock Register
Command Set
3
555
AA
A0
2AA
00
55
555
40
(4)
(5)
Lock Register Program
Lock Register Read
2
1
X
X
DATA
(5)
DATA
Enter Password Protection
Command Set
3
555
AA
2AA
55
555
60
(4)
(6)(7)
Password Program
2
4
X
A0
PWAn PWDn
Password Read
00
PWD0
01
00
PWD1
03
02
00
PWD2 03 PWD3
(7)
Password Unlock
7
3
00
25
PWD0 01 PWD1 02 PWD2 03 PWD3 00
29
Enter Non-volatile Protection
(BKA)
555
555
AA
2AA
55
C0
(4)
Command Set
(BKA)
BAd
(8)
NVPB Program
2
2
1
X
X
A0
80
00
30
(9)
Clear all NVPBs
00
(BKA)
BAd
Read NVPB Status
RD(0)
Enter NVPB Lock Bit
Command Set
3
555
AA
2AA
X
55
00
555
50
NVPB Lock Bit Program
2
1
X
A0
Read NVPB Lock Bit Status
BKA
RD(0)
Enter Volatile Protection
Command Set
(BKA)
555
3
2
1
2
555
X
AA
A0
2AA
55
00
E0
(BKA)
BAd
VPB Program
Read VPB Status
VPB Clear
(BKA)
BAd
RD(0)
A0
(BKA)
BAd
X
01
55
(4)
3
2
1
555
X
AA
A0
2AA
PA
555
555
88
Enter Extended Block
(5)
Extended Block Program
Extended Block Read
DATA
(5)
Ad
DATA
Exit Extended Block
4
2
555
X
AA
90
2AA
X
55
00
90
X
00
(10)
Exit Protection Command Set
1.
PA program address, Ad address, BAd any address in the block, BKA bank address, RD read data, PWDn password word (n = 0 to 3), PWAn password address (n
= 0 to 3), X don’t care. All values in the table are in hexadecimal.
2.
3.
4.
Grey cells represent read cycles. The other cells are write cycles.
DQ15 to DQ8 are ‘don’t care’ during unlock and command cycles. A22 to A16 are ‘don’t care’ during unlock and command cycles unless an address is required.
An enter command sequence must be issued prior to any operation. It disables read and write operations from and to block 0. Read and write operations from any
other block are allowed.
5.
6.
7.
8.
9.
DATA = Lock register content.
Only one portion of password can be programmed or read by each Password Program command.
The password portion can be entered or read in any order as long as the entire 64-bit password is entered or read.
Protected and unprotected states correspond to 00 and 01, respectively.
The Clear all NVPBs command programs all NVPBs before erasure in order to prevent the over-erasure of previously cleared non-volatile modify protection bits.
10. If an Entry Command Set command is issued, an Exit Protection Command Set command must be issued to return the device to read mode.
41/85
Command interface
M29DW128G
Table 12. Program, erase times and program, erase endurance cycles
Parameter
Min
Typ(1)(2)
Max(2)
Unit
Chip Erase
40
1
400(3)
s
Block Erase (128 kwords)(4)
Erase Suspend latency time
Block Erase timeout
s
25
35
µs
µs
µs
50
Single Word Program
16
51
78
135
20
13
8
Word Program
VPP/WP = VPPH
VPP/WP = VIH
200(3)
Write to Buffer Program
(32 words at-a-time)
µs
Chip Program (word by word)
400(3)
200(3)
50(3)
40
s
Chip Program (Write to Buffer Program)(5)
s
(5)
Chip Program (Write to Buffer Program with VPP/WP = VPPH
Chip Program (Enhanced Buffered Program)(5)
)
s
s
(5)
Chip Program (Enhanced Buffered Program with VPP/WP = VPP
)
5
25
s
Program Suspend latency time
5
15
µs
Program/Erase cycles (per block)
Data retention
100,000
20
Cycles
Years
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,000 program/erase cycles.
4. Block Erase polling cycle time (seeFigure 20: Data polling AC waveforms).
5. Intrinsic program timing, that means without the time required to execute the bus cycles to load the program commands.
42/85
M29DW128G
Registers
8
Registers
The device feature two registers:
■
A lock register that allows to configure the memory blocks and extended memory block
protection (see Table 14: Block protection status)
■
A status register that provides information on the current or previous program or erase
operations.
8.1
Lock register
The lock register is a 16-bit one-time programmable register. The bits in the lock register are
summarized in Table 13: Lock register bits.
See Section 7.3.3: Lock register command set for a description of the commands allowing to
read and program the lock register.
8.1.1
8.1.2
Volatile lock boot bit (DQ4)
DQ4 sets the default values for volatile block protection: when programmed, the blocks are
protected at power-up.
Password protection mode lock bit (DQ2)
The password protection mode lock bit, DQ2, is one-time programmable. Programming
(setting to ‘0’) this bit permanently places the device in password protection mode.
Any attempt to program the password protection mode lock bit when the non-volatile
protection mode bit is programmed causes the operation to abort and the device to return to
read mode.
8.1.3
Non-volatile protection mode lock bit (DQ1)
The non-volatile protection mode lock bit, DQ1, is one-time programmable. Programming
(setting to ‘0’) this bit permanently places the device in non-volatile protection mode.
When shipped from the factory, all parts default to operate in non-volatile protection mode.
The memory blocks can be either unprotected (NVPBs set to ‘1’) or protected (NVPBs set to
‘0’), according to the ordering option that has been chosen.
Any attempt to program the non-volatile protection mode lock bit when the password
protection mode bit is programmed causes the operation to abort and the device to return to
read mode.
8.1.4
Extended block protection bit (DQ0)
If the device has not been shipped with the extended memory block factory locked, the block
can be protected by setting the extended memory block protection bit, DQ0, to ‘0’. However,
this bit is one-time programmable and once protected the extended memory block cannot be
unprotected.
43/85
Registers
M29DW128G
The extended memory block protection status can be read in auto select mode either by
applying V to A9 (see Table 6: Block protection) or by issuing an Auto Select command
ID
(see Table 8: Standard commands).
8.1.5
DQ15 to DQ5 and DQ3 reserved
They are ‘don’t care’.
(1)
Table 13. Lock register bits
DQ15-5
DQ4
DQ3
DQ2
DQ1
DQ0
Volatile lock
boot bit
Password protection
mode lock bit
Non-volatile protection
mode lock bit
Extended block
protection bit
Don’t care
Don’t care
1. DQ0, DQ1, DQ2 and DQ4 are set to ‘1’ when shipped from the factory.
Table 14. Block protection status
NVPB lock
bit(1)
Block
Block
Block protection
status
Block protection status
NVPB(2)
VPB(3)
0
0
0
1
1
1
0
1
1
0
1
1
x
1
0
x
0
1
01h
00h
00h
01h
01h
00h
Block protected (non-volatile protection through NVPB)
Block unprotected
Block protected (volatile protection through VPB)
Block protected (non-volatile protection through NVPB)
Block protected (volatile protection through VPB)
Block unprotected
1. If the NVPB lock bit is set to ‘0’, all NVPBs are locked. If the NVPB lock bit is set to ‘1’, all NVPBs are unlocked.
2. If the block NVPB is set to ‘0’, the block is protected, if set to ‘1’, it is unprotected.
3. If the block VPB is set to ‘0’, the block is protected, if set to ‘1’, it is unprotected.
44/85
M29DW128G
Registers
Figure 7.
Lock register program flowchart
START
Write Unlock cycles:
Add 555h, Data AAh
Add 2AAh, Data 55h
Unlock cycle 1
unlock cycle 2
Write
Enter Lock Register command set:
Add 555h, Data 40h
Program Lock Register Data:
Add Dont' care, Data A0h
(1)
Add Dont' care , Data PDh
Polling algorithm
YES
Done
NO
NO
DQ5 = 1
YES
PASS:
FAIL
Reset to return
the device to Read mode
Write Lock Register Exit command:
Add Dont' care, Data 90h
Device returned
to Read mode
Add Dont' care, Data 00h
ai13677
1. PD is the programmed data (see Table 13: Lock register bits).
2. The lock register can only be programmed once.
45/85
Registers
M29DW128G
8.2
Status register
The M29DW128G has one status register. The various bits convey information and errors
on the current and previous program/erase operation. Bus read operations from any
address within the memory, always read the Status register during program and erase
operations. It is also read during erase suspend when an address within a block being
erased is accessed.
The bits in the Status register are summarized in Table 15: Status register bits.
8.2.1
Data polling bit (DQ7)
The data polling bit can be used to identify whether the program/erase controller has
successfully completed its operation or if it has responded to an erase suspend. The data
polling bit is output on DQ7 when the status register is read.
During program operations the data polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the program operation the memory
returns to read mode and bus read operations, from the address just programmed, output
DQ7, not its complement.
During erase operations the data polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the erase operation the memory returns to read
mode.
In erase suspend mode the data polling bit will output a ’1’ during a bus read operation
within a block being erased. The data polling bit will change from ’0’ to ’1’ when the
program/erase controller has suspended the erase operation.
Figure 8: Data polling flowchart, gives an example of how to use the data polling bit. A valid
address is the address being programmed or an address within the block being erased.
8.2.2
Toggle bit (DQ6)
The toggle bit can be used to identify whether the program/erase controller has successfully
completed its operation or if it has responded to an erase suspend. The toggle bit is output
on DQ6 when the status register is read.
During a program/erase operation the toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive bus read operations at any address. After successful completion of the operation
the memory returns to read mode.
During erase suspend mode the toggle bit will output when addressing a cell within a block
being erased. The toggle bit will stop toggling when the program/erase controller has
suspended the erase operation.
Figure 9: Toggle flowchart, gives an example of how to use the data toggle bit.
8.2.3
Error bit (DQ5)
The error bit can be used to identify errors detected by the program/erase controller. The
error bit is set to ’1’ when a program, block erase or chip erase operation fails to write the
correct data to the memory. If the error bit is set a Read/Reset command must be issued
46/85
M29DW128G
Registers
before other commands are issued. The error bit is output on DQ5 when the status register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A bus read operation to that address will show the bit is still ‘0’. One
of the erase commands must be used to set all the bits in a block or in the whole memory
from ’0’ to ’1’.
8.2.4
8.2.5
Erase timer bit (DQ3)
The erase timer bit can be used to identify the start of program/erase controller operation
during a Block Erase command. Once the program/erase controller starts erasing the erase
timer bit is set to ’1’. Before the program/erase controller starts the erase timer bit is set to ’0’
and additional blocks to be erased may be written to the command interface. The erase
timer bit is output on DQ3 when the status register is read.
Alternative toggle bit (DQ2)
The alternative toggle bit can be used to monitor the program/erase controller during erase
operations. The alternative toggle bit is output on DQ2 when the status register is read.
During chip erase and block erase operations the toggle bit changes from ’0’ to ’1’ to ’0’,
etc., with successive bus read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to read mode.
During erase suspend the alternative toggle bit changes from ’0’ to ’1’ to ’0’, etc. with
successive bus read operations from addresses within the blocks being erased. Bus read
operations to addresses within blocks not being erased will output the memory array data as
if in read mode.
After an erase operation that causes the error bit to be set, the alternative toggle bit can be
used to identify which block or blocks have caused the error. The alternative toggle bit
changes from ’0’ to ’1’ to ’0’, etc. with successive bus read operations from addresses within
blocks that have not erased correctly. The alternative toggle bit does not change if the
addressed block has erased correctly.
8.3
Buffered program abort bit (DQ1)
The Buffered program abort bit, DQ1, is set to ‘1’ when a write to buffer program or
enhanced buffered program operation aborts. The Buffered Program Abort and Reset
command must be issued to return the device to read mode (see write to buffer program in
Section 7.1: Standard commands).
47/85
Registers
M29DW128G
(1)
Table 15. Status register bits
Operation
Address
DQ7
DQ6
DQ5 DQ3 DQ2 DQ1 RB
Program(2)
Program During Erase Suspend Bank address DQ7 Toggle
Bank address DQ7 Toggle
0
0
0
1
0
0
–
–
–
–
1
0
–
0
–
1
–
–
–
0
0
–
–
Buffered Program Abort(2)
Bank address DQ7 Toggle
Bank address DQ7 Toggle
0
Program Error
–
Hi-Z
0
Chip Erase
Any address
Erasing block
0
0
Toggle
Toggle
Toggle
Toggle
0
Block Erase before timeout
Block Erase
Non-erasing
block
No
toggle
0
0
0
Toggle
Toggle
Toggle
0
0
0
0
1
1
–
–
–
0
0
0
Erasing block
Toggle
Non-erasing
block
No
toggle
No
Toggle
Erasing block
1
0
–
Toggle
–
–
–
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Erase Suspend
Erase Error
Non-erasing
block
Data read as normal
Good block
address
No
toggle
0
0
Toggle
Toggle
1
1
1
1
Faulty block
address
Toggle
1. Unspecified data bits should be ignored.
2. DQ7 for write to buffer program and enhanced buffered program is related to the last address location
loaded.
48/85
M29DW128G
Registers
Figure 8.
Data polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5 = 1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI07760
49/85
Registers
M29DW128G
Figure 9.
Toggle flowchart
START
READ DQ6
ADDRESS = BKA
READ
DQ5 & DQ6
ADDRESS = BKA
DQ6
=
NO
TOGGLE
YES
NO
DQ5
= 1
YES
READ DQ6
TWICE
ADDRESS = BKA
DQ6
=
NO
TOGGLE
YES
FAIL
PASS
AI08929c
1. BKA=bank address being programmed or erased.
50/85
M29DW128G
Dual operations and multiple bank architecture
9
Dual operations and multiple bank architecture
The multiple bank architecture of the M29DW128G gives greater flexibility for software
developers to split the code and data spaces within the memory array. The dual operations
feature simplifies the software management of the device by allowing code to be executed
from one bank while another bank is being programmed or erased.
The dual operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency.
Only one bank at a time is allowed to be in program or erase mode. However, certain
commands can cross bank boundaries, which means that during an operation only the
banks that are not concerned with the cross bank operation are available for dual
operations. For example, if a Block Erase command is issued to erase blocks in both bank A
and bank B, then only banks C or D are available for read operations while the erase is
being executed.
If a read operation is required in a bank, which is programming or erasing, the program or
erase operation can be suspended.
Also if the suspended operation was erase then a program command can be issued to
another block, so the device can have one block in erase suspend mode, one programming
and other banks in read mode.
By using a combination of these features, read operations are possible at any moment.
Table 16 and Table 17 show the dual operations possible in other banks and in the same
bank. Note that only the commonly used commands are represented in these tables.
(1)
Table 16. Dual operations allowed in other banks
Commands allowed in another bank
Read
Status
Read
CFI
Query
Status of bank
Auto
Read/
Program/Erase Program/Erase
Program Erase
Reset Register
Suspend
Resume
Select
(2)
Idle
Yes
Yes
Yes
Yes(3)
No
Yes
No
No
Yes
No
No
Yes
–
Yes
–
Yes(3)
No
Yes(4)
No
Programming
Erasing
No
–
–
No
No
Program
suspended
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
No
-
-
Yes(5)
Yes(6)
Erase
suspended
Yes
1. If several banks are involved in a program or erase operation, then only the banks that are not concerned with the
operation are available for dual operations.
2. Read Status register is not a command. The status register can be read during a block program or erase operation.
3. Only after a program or erase operation in that bank.
4. Only after a Program or Erase Suspend command in that bank.
5. Only a program resume is allowed if the bank was previously in program suspend mode.
6. Only an erase resume is allowed if the bank was previously in erase suspend mode.
51/85
Dual operations and multiple bank architecture
Table 17. Dual operations allowed in same bank
M29DW128G
Commands allowed in another bank
Read
Status
Status of
bank
Program/
Erase
Suspend
Auto
Read/
Reset
Read CFI
Query
Program/Erase
Resume
Program
Erase
Register
Select
(1)
Idle
Yes
No
No
Yes
Yes
Yes
Yes
No
No
Yes
No
No
Yes
–
Yes
–
Yes(2)
Yes(4)
Yes(5)
Yes(3)
Programming
Erasing
–
–
–
No
Program
suspended
Yes
No
Yes
Yes
Yes
Yes
No
–
–
–
Yes
Yes
Erase
suspended
Yes(6)
Yes(7)
Yes(6)
No
1. Read status register is not a command. The status register can be read during a block program or erase operation.
2. Only after a program or erase operation in that bank.
3. Only after a Program or Erase Suspend command in that bank.
4. Only a program suspend.
5. Only an erase suspend.
6. Not allowed in the block or word that is being erased or programmed.
7. The status register can be read by addressing the block being erase suspended.
52/85
M29DW128G
Maximum ratings
10
Maximum ratings
Stressing the device above the rating listed in Table 18: Absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 18. Absolute maximum ratings
Symbol
Parameter
Temperature under bias
Min
Max
Unit
TBIAS
TSTG
VIO
−50
−65
125
150
°C
°C
V
Storage temperature
Input or output voltage(1)(2)
Supply voltage
−0.6
−0.6
−0.6
−0.6
−0.6
VCC + 0.6
4
VCC
VCCQ
VID
V
Input/output supply voltage
Identification voltage
Program voltage
4
V
10.5
10.5
V
(3)
VPPH
V
1. Minimum voltage may undershoot to −2 V during transition and for less than 20 ns during transitions.
2. Maximum voltage may overshoot to VCC + 2 V during transition and for less than 20 ns during transitions.
3. VPPH must not remain at 9 V for more than a total of 80 hrs.
53/85
DC and AC parameters
M29DW128G
11
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 19: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 19. Operating and AC measurement conditions
M29DW128G
Parameter
70 or 60 ns
80 ns
Unit
Min
Max
Min
Max
V
CC supply voltage
CCQ supply voltage (VCCQ ≤ VCC
2.7
2.7
3.6
3.6
85
2.7
3.6
3.6
85
V
V
V
)
1.65
− 40
Ambient operating temperature
Load capacitance (CL)
Input rise and fall times
Input pulse voltages
− 40
°C
pF
ns
V
30
30
10
10
0 to VCCQ
VCCQ/2
0 to VCCQ
VCCQ/2
Input and output timing ref. voltages
V
Figure 10. AC measurement load circuit
V
V
V
PP
CC
CCQ
25 kΩ
25 kΩ
DEVICE
UNDER
TEST
C
L
0.1 µF
0.1 µF
C
includes JIG capacitance
L
AI05558b
Figure 11. AC measurement I/O waveform
V
CCQ
V
/2
CCQ
0 V
AI05557b
54/85
M29DW128G
DC and AC parameters
Table 20. Power-up waiting timings
M29DW128G
Unit
Symbol
Alt.
Parameter
VCC(1) High to VCCQ(1) High
70 or 60 ns
80 ns
tVCHVCQH
Min
Min
Min
Min
Min
0
0
µs
µs
µs
µs
µs
(2)
tVCHRH
tVCS
tVIOS
tRH
VCC High to rising edge of RP
VCCQ High to rising edge of RP
RP High to Chip Enable Low
RP High to Write Enable Low
(2)
tVCQHRH
0
tRHEL
tRHWL
50
500
1. VCC and VCCQ ramps must be synchronized during power-up.
2. If RP is not stable for tVCHRH or tVCQHRH, the device does not permit any read and write operations and a hardware reset
is required.
Figure 12. Power-up waiting timings
t
VCHVCQH
V
CC
CCQ
V
t
RHEL
E
t
VCQHRH
RP
W
t
VCHRH
t
RHWL
AI14247
55/85
DC and AC parameters
M29DW128G
Unit
(1)
Table 21. Device capacitance
Symbol
Parameter
Input capacitance
Output capacitance
Test condition
Min
Max
CIN
VIN = 0 V
6
pF
pF
COUT
VOUT = 0 V
12
1. Sampled only, not 100% tested.
Table 22. DC characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
(1)
ILI
Input leakage current
Output leakage current
0 V ≤ VIN ≤ VCC
±1
±1
µA
µA
ILO
0 V ≤ VOUT ≤ VCC
E = VIL, G = VIH,
f = 6 MHz
Random read
10
15
mA
mA
µA
ICC1
Read current
E = VIL, G = VIH,
f = 10 MHz
Page read
E = VCCQ ± 0.2 V,
RP = VCCQ ± 0.2 V
ICC2
Supply current (standby)
100
VPP/WP =
VIL or VIH
20
20
5
mA
mA
µA
Program/Erase
controller active
(2)
ICC3
Supply current (program/erase)
V
PP/WP = VPPH
Read or
standby
IPP1
IPP2
IPP3
VPP/WP ≤ VCC
1
Program
current
Reset
RP = VSS ± 0.2 V
1
1
5
µA
Program
operation
ongoing
VPP/WP = 12 V ± 5%
10
mA
(Program)
V
PP/WP = VCC
1
3
1
5
10
5
µA
mA
µA
Erase
operation
ongoing
VPP/WP = 12 V ± 5%
Program
current (Erase)
IPP4
V
PP/WP = VCC
VIL
VIH
Input Low voltage
VCC ≥ 2.7 V
VCC ≥ 2.7 V
−0.5
0.3VCCQ
V
V
Input High voltage
0.7VCCQ
VCCQ+0.4
IOL = 100 µA, VCC = VCC(min)
VCCQ = VCCQ(min)
,
VOL
Output Low voltage
0.15VCCQ
V
I
OH = 100 µA, VCC = VCC(min)
,
VOH
VID
Output High voltage
Identification voltage
0.85VCCQ
8.5
V
V
V
VCCQ = VCCQ(min)
9.5
9.5
Voltage for VPP/WP program
acceleration
VPPH
8.5
Program/Erase lockout supply
voltage
(2)
VLKO
2.3
2.5
V
1. The maximum input leakage current is ±5 µA on the VPP/WP pin.
2. Sampled only, not 100% tested.
56/85
M29DW128G
DC and AC parameters
Figure 13. Random read AC waveforms
tAVAV
VALID
A0-A22
tAVQV
tAXQX
E
tELQV
tELQX
tEHQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ15
BYTE
VALID
tBHQV
tELBL/tELBH
tBLQZ
AI13698b
57/85
DC and AC parameters
M29DW128G
Figure 14. Page read AC waveforms
58/85
M29DW128G
DC and AC parameters
Table 23. Read AC characteristics
M29DW128G
Test
condition
80 ns
VCCQ=1.65 V to
VCC
Symbol Alt.
Parameter
Unit
60 ns
CCQ=VCC VCCQ=VCC
70 ns
V
Address Valid to Next
Address Valid
E = VIL
G = VIL
tAVAV
tAVQV
tRC
Min
60
60
25
0
70
70
25
0
80
80
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Output
Valid
E = VIL
G = VIL
tACC
Max
Max
Address Valid to Output
Valid (Page)
E = VIL
G = VIL
tAVQV1 tPAGE
Chip Enable Low to Output
Transition
(1)
tELQX
tLZ
tE
G = VIL Min
G = VIL Max
E = VIL Min
E = VIL Max
G = VIL Max
E = VIL Max
Chip Enable Low to Output
Valid
tELQV
60
0
70
0
80
0
Output Enable Low to
Output Transition
(1)
tGLQX
tOLZ
tOE
tHZ
tDF
Output Enable Low to
Output Valid
tGLQV
25
20
20
25
20
20
30
30
20
Chip Enable High to Output
Hi-Z
(1)
tEHQZ
Output Enable High to
Output Hi-Z
(1)
tGHQZ
tEHQX
tGHQX
tAXQX
Chip Enable, Output Enable
tOH or Address Transition to
Output Transition
Min
0
5
0
5
0
5
ns
ns
tELBL
tELFL Chip Enable to BYTE Low
Max
tELBH tELFH or High
tBLQZ tFLQZ BYTE Low to Output Hi-Z
tBHQV tFHQV BYTE High to Output Valid
1. Sampled only, not 100% tested.
Max
Max
25
30
25
30
25
30
ns
ns
59/85
DC and AC parameters
M29DW128G
Figure 15. Write enable controlled program waveforms
3rd cycle
4th cycle
Read cycle
Data polling
PA
tAVAV
tAVAV
A0-A22
555h
PA
tAVWL
tWLAX
tELQV
tELWL
tGHWL
tWHEH
E
tGLQV
G
tWLWH
tWHWL
W
tDVWH
tWHWH1
DQ7
tGHQZ
tAXQX
D
AOh
PD
tWHDX
D
OUT
DQ0-DQ15
OUT
AI13699b
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of status register data polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 8.2.1: Data polling bit (DQ7)).
4. SeeTable 24: Write AC characteristics, write enable controlled, Table 25: Write AC characteristics, chip enable controlled
and Table 23: Read AC characteristics for details on the timings.
60/85
M29DW128G
DC and AC parameters
Table 24. Write AC characteristics, write enable controlled
M29DW128G
Unit
Symbol
Alt
Parameter
60 ns
70 ns
80 ns
tAVAV
tELWL
tWLWH
tDVWH
tWHDX
tWHEH
tWHWL
tAVWL
tWLAX
tGHWL
tWHGL
tWC
tCS
tWP
tDS
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
60
0
70
0
80
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
35
45
0
35
45
0
35
45
0
tDH
tCH
tWPH
tAS
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Program/Erase Valid to RB Low
0
0
0
30
0
30
0
30
0
tAH
45
0
45
0
45
0
tOEH
tBUSY
tVCS
0
0
0
(1)
tWHRL
30
50
30
50
30
50
tVCHEL
VCC High to Chip Enable Low
1. Sampled only, not 100% tested.
61/85
DC and AC parameters
M29DW128G
Figure 16. Chip enable controlled program waveforms
3rd cycle
4th cycle
Data polling
PA
tAVAV
A0-A22
555h
PA
tAVEL
tELAX
tWLEL
tGHEL
tEHWH
W
G
tELEH
tEHEL1
E
tDVEH
tWHWH1
DQ7
D
AOh
PD
tEHDX
DQ0-DQ15
OUT
AI14100b
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of status register data polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 8.2.1: Data polling bit (DQ7)).
4. See Table 24: Write AC characteristics, write enable controlled, Table 25: Write AC characteristics, chip enable controlled
and Table 23: Read AC characteristics for details on the timings.
Table 25. Write AC characteristics, chip enable controlled
M29DW128G
Symbol
Alt.
Parameter
Unit
60 ns
70 ns
80 ns
tAVAV
tWLEL
tELEH
tDVEH
tEHDX
tEHWH
tEHEL
tAVEL
tELAX
tGHEL
tWC
tWS
tCP
tDS
tDH
tWH
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
60
0
70
0
80
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
45
0
35
45
0
35
45
0
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
0
0
0
tCPH Chip Enable High to Chip Enable Low
30
0
30
0
30
0
tAS
tAH
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
45
0
45
0
45
0
62/85
M29DW128G
DC and AC parameters
Figure 17. Reset AC waveforms (no program/erase ongoing)
RB
E, G
tPHEL,
tPHGL
RP
tPLPX
AI11300b
Figure 18. Reset during program/erase operation AC waveforms
tPLYH
RB
tRHEL, tRHGL
E, G
RP
tPLPX
AI11301b
Table 26. Reset AC characteristics
M29DW128G
Unit
Symbol
Alt.
Parameter
60 ns 70 ns 80 ns
(1)
tPLYH
tREADY RP Low to read mode, during program or erase
tRP RP pulse width
Max
Min
50
10
50
10
50
10
µs
µs
tPLPX
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
(1)
(1)
tPHEL, PHGL
t
tRH
Min
Min
50
50
50
ns
RP Low to standby mode, during read mode
tRPD
10
50
10
50
10
50
µs
µs
RP Low to standby mode, during program or erase Min
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
tRHEL, RHGL
t
tRB
Min
0
0
0
ns
1. Sampled only, not 100% tested.
63/85
DC and AC parameters
M29DW128G
Figure 19. Accelerated program timing waveforms
V
PPH
V
/WP
PP
V
or V
IH
IL
tVHVPP
tVHVPP
AI05563
Figure 20. Data polling AC waveforms
tEHQZ
tGHQZ
tWHEH
E
tELQV
tGLQV
G
tWHGL2
W
tWHWH1 or tWHWH2
Hi-Z
Hi-Z
DQ7=
DQ7 DATA
DQ7
Valid data
DQ6-DQ0=
Output flag
DQ6-DQ0=
Valid data
DQ6-DQ0
DATA
tWHRL
R/B
AI13336c
1. DQ7 returns valid data bit when the ongoing Program or Erase command is completed.
2. See Table 27: Accelerated program and data polling/data toggle AC characteristics and Table 23: Read AC characteristics
for details on the timings.
64/85
M29DW128G
DC and AC parameters
Table 27. Accelerated program and data polling/data toggle AC characteristics
M29DW128G
Symbol
Alt
Parameter
Unit
60 ns 70 ns 80 ns
tVHVPP
tAXGL
VPP/WP raising and falling time
Min
Min
250
10
250
10
250
10
ns
ns
Address setup time to Output Enable Low during
toggle bit polling
tASO
tAHT
tGHAX,
tEHAX
Address hold time from Output Enable during toggle
bit polling
Min
Min
Min
Max
10
10
20
30
10
10
20
30
10
10
20
30
ns
ns
ns
ns
tEHEL2
tEPH Chip Enable High during toggle bit polling
tOEH Output hold time during data and toggle bit polling
tBUSY Program/Erase Valid to RB Low
tWHGL2,
tGHGL2
tWHRL
65/85
Package mechanical
M29DW128G
12
Package mechanical
®
In order to meet environmental requirements, ST offers the M29DW128G in ECOPACK
packages. ECOPACK packages are lead-free. The category of second level Interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
Figure 21. TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package outline
1
56
e
B
D1
28
29
L1
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-K
1. Drawing is not to scale.
Table 28. TSOP56 – 56 lead plastic thin small outline, 14 x 20 mm, package
mechanical data
Millimeters
Min
Inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
B
1.20
0.15
1.05
0.27
0.21
0.10
14.10
20.20
18.50
–
0.047
0.006
0.041
0.011
0.008
0.004
0.555
0.795
0.728
–
0.10
1.00
0.22
0.05
0.95
0.17
0.10
0.004
0.039
0.009
0.002
0.037
0.007
0.004
C
CP
D1
E
14.00
20.00
18.40
0.50
0.60
3
13.90
19.80
18.30
–
0.551
0.787
0.724
0.020
0.024
3
0.547
0.780
0.720
–
E1
e
L
0.50
0
0.70
5
0.020
0
0.028
5
α
66/85
M29DW128G
Package mechanical
Figure 22. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline
D
D1
FD
FE
SD
SE
E
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
1. Drawing is not to scale.
Table 29. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.20
0.35
0.047
0.014
0.30
0.80
0.20
0.012
0.031
0.008
0.35
9.90
–
0.50
0.014
0.390
–
0.020
D
10.00
7.000
10.10
0.394
0.276
0.398
D1
ddd
e
–
–
0.10
0.004
1.00
13.00
7.00
1.50
3.00
0.50
0.50
–
–
0.039
0.512
0.276
0.059
0.118
0.020
0.020
–
–
E
12.90
13.10
0.508
0.516
E1
FD
FE
SD
SE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
67/85
Ordering information
M29DW128G
13
Ordering information
Table 30. Ordering information scheme
Example:
M29 D W 128G 60 NF 6 E
Device type
M29
Architecture
D = Dual operation
Operating voltage
W = VCC = 2.7 to 3.6 V
Device function
128G = 128 Mbit (x 16), page, dual boot
Speed
60= 60 ns (80 ns if VCCQ=1.65 V to VCC
)
70=70 ns (80 ns if VCCQ=1.65 V to VCC
)
Package
NF = TSOP56: 14 x 20 mm
ZA = TBGA64: 10 x 13 mm - 1 mm pitch
Temperature range
6 = -40 to 85 °C
Option
E = ECOPACK package, standard packing
F = ECOPACK package, tape & reel packing
Note:
This product is also available with the extended block factory locked.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
68/85
M29DW128G
Block addresses and read/modify protection groups
Appendix A Block addresses and read/modify protection
groups
Table 31. Block addresses
Block size
(Kwords)
16-bit address range
(in hexadecimal)
Bank
Block
Protection group
0
1
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
32
32
0000000–0007FFF
0008000–000FFFF
0010000–0017FFF
0018000–001FFFF
0020000–003FFFF
0040000–005FFFF
0060000–007FFFF
0080000–009FFFF
00A0000–00BFFFF
00C0000–00DFFFF
00E0000–00FFFFF
2
32
3
32
4
128
128
128
128
128
128
128
Bank A
5
6
7
8
9
10
69/85
Block addresses and read/modify protection groups
Table 31. Block addresses (continued)
M29DW128G
Block size
(Kwords)
16-bit address range
(in hexadecimal)
Bank
Block
Protection group
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0100000–011FFFF
0120000–013FFFF
0140000–015FFFF
0160000–017FFFF
0180000–019FFFF
01A0000–01BFFFF
01C0000–01DFFFF
01E0000–01FFFFF
0200000–021FFFF
0220000–023FFFF
0240000–025FFFF
0260000–027FFFF
0280000–029FFFF
02A0000–02BFFFF
02C0000–02DFFFF
02E0000–02FFFFF
0300000–031FFFF
0320000–033FFFF
0340000–035FFFF
0360000–037FFFF
0380000–039FFFF
03A0000–03BFFFF
03C0000–03DFFFF
03E0000–03FFFFF
Bank B
70/85
M29DW128G
Block addresses and read/modify protection groups
Table 31. Block addresses (continued)
Block size
(Kwords)
16-bit address range
(in hexadecimal)
Bank
Block
Protection group
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
0400000–041FFFF
0420000–043FFFF
0440000–045FFFF
0460000–047FFFF
0480000–049FFFF
04A0000–04BFFFF
04C0000–04DFFFF
04E0000–04FFFFF
0500000–051FFFF
0520000–053FFFF
0540000–055FFFF
0560000–057FFFF
0580000–059FFFF
05A0000–05BFFFF
05C0000–05DFFFF
05E0000–05FFFFF
0600000–061FFFF
0620000–063FFFF
0640000–065FFFF
0660000–067FFFF
0680000–069FFFF
06A0000–06BFFFF
06C0000–06DFFFF
06E0000–06FFFFF
Bank C
71/85
Block addresses and read/modify protection groups
Table 31. Block addresses (continued)
M29DW128G
Block size
(Kwords)
16-bit address range
(in hexadecimal)
Bank
Block
Protection group
59
60
61
62
63
64
65
66
67
68
69
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
128
128
128
128
128
128
128
32
0700000–071FFFF
0720000–073FFFF
0740000–075FFFF
0760000–077FFFF
0780000–079FFFF
07A0000–07BFFFF
07C0000–07DFFFF
07E0000–07E7FFF
07E8000–07EFFFF
07F0000–07F7FFF
07F8000–07FFFFF
Bank D
32
32
32
72/85
M29DW128G
Common Flash interface (CFI)
Appendix B Common Flash interface (CFI)
The common Flash interface is a JEDEC approved, standardized data structure that can be read from
the Flash memory device. It allows a system software to query the device to determine various electrical
and timing parameters, density information and functions supported by the memory. The system can
interface easily with the device, enabling the software to upgrade itself when necessary.
When the Read CFI Query command is issued, the memory enters read CFI query mode and read
operations output the CFI data. Table 32, Table 33, Table 34, Table 35, Table 36 and Table 37 show the
addresses (A0-A7) used to retrieve the data. The CFI data structure also contains a security area where
a 64-bit unique security number is written (see Table 37: Security code area). This area can be accessed
only in read mode by the final user. It is impossible to change the security number after it has been
written by ST.
(1)
Table 32. Query structure overview
Address
Sub-section name
Description
10h
1Bh
27h
CFI query identification string
System interface information
Device geometry definition
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Primary algorithm-specific extended query
table
Additional information specific to the primary
algorithm (optional)
40h
61h
Security code area
64 bit unique device number
1. Query data are always presented on the lowest order data outputs.
(1)
Table 33. CFI query identification string
Address
Data
Description
Value
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
0051h
‘Q’
‘R’
‘Y’
0052h Query unique ASCII string ‘QRY’
0059h
0002h
Primary algorithm command set and control interface ID code 16 bit ID
code defining a specific algorithm
Spansion
compatible
0000h
0040h
Address for primary algorithm extended query table (see Table 36)
P = 40h
NA
0000h
0000h
Alternate vendor command set and control interface ID code second
vendor - specified algorithm supported
0000h
0000h
Address for alternate algorithm extended query table
0000h
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
73/85
Common Flash interface (CFI)
M29DW128G
(1)
Table 34. CFI query system interface information
Address
Data
Description
Value
VCC logic supply minimum program/erase voltage
1Bh
0027h
bit 7 to 4 value in volts
2.7 V
bit 3 to 0 value in 100 mV
VCC logic supply maximum program/erase voltage
1Ch
1Dh
1Eh
0036h
0085h
0095h
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
3.6 V
8.5 V
9.5 V
VPPH [programming] supply minimum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
VPPH [programming] supply maximum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
1Fh
20h
0004h
0004h
1Fh 3Eh 0004h typical timeout for single byte/word program = 2n µs
16 µs
16 µs
20h 40h 0004h typical timeout for minimum size write buffer program
= 2n µs
21h
22h
23h
24h
25h
26h
000Ah
0010h
0004h
0002h
0004h
0004h
Typical timeout for individual block erase = 2n ms
Typical timeout for full Chip Erase = 2n ms
1 s
40 s
Maximum timeout for word program = 2n times typical
Maximum timeout for write buffer program = 2n times typical
Maximum timeout per individual block erase = 2n times typical
Maximum timeout for Chip Erase = 2n times typical
200 µs
200 µs
4.6 s
400 s
1. The values given in the above table are valid for both packages.
74/85
M29DW128G
Common Flash interface (CFI)
Table 35. Device geometry definition
Address
Data
Description
Value
27h
0018h Device size = 2n in number of bytes
16 Mbytes
28h
29h
0001h
Flash device interface code description
0000h
x 16 Async.
2Ah
2Bh
0006h
0000h
Maximum number of bytes in multiple-byte program or page= 2n
64
3
Number of erase block regions. It specifies the number of regions
containing contiguous erase blocks of the same size.
2Ch
0003h
0003h
0000h
2Dh
2Eh
2Fh
30h
Erase block region 1 information
2Dh-2Eh: number of erase blocks of identical size
2Fh-30h: block size (n*256 bytes)
4 blocks
64 Kbytes
0000h
0001h
31h
32h
33h
34h
003Dh
0000h
0000h
0004h
62 blocks
256 Kbytes
Erase block region 2 information
Erase block region 3 information
Erase block region 4 information
35h
36h
37h
38h
0003h
0000h
0000h
0001h
4 blocks
64 Kbytes
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
NA
75/85
Common Flash interface (CFI)
M29DW128G
Value
(1)
Table 36. Primary algorithm-specific extended query table
Address
Data
Description
40h
41h
42h
43h
44h
0050h
0052h
0049h
0031h
0033h
‘P’
‘R’
‘I’
Primary algorithm extended query table unique ASCII string ‘PRI’
Major version number, ASCII
Minor version number, ASCII
‘1’
‘3’
Address sensitive unlock (bits 1 to 0)
00 = required, 01= not required
Silicon revision number (bits 7 to 2)
Yes,
90 nm
45h
000Dh
Erase Suspend
00 = not supported, 01 = read only, 02 = read and write
46h
47h
48h
0002h
0001h
0000h
2
1
Block protection
00 = not supported, x = number of blocks per group
Temporary block unprotect
00 = not supported, 01 = supported
Not
supported
Block protect /unprotect
08 = M29DW128G
49h
4Ah
4Bh
4Ch
0008h
003Bh
0000h
0002h
8
Simultaneous operations: x= block number (excluding bank A)
Burst mode, 00 = not supported, 01 = supported
59
Not
supported
Page mode, 00 = not supported, 02 = 8-word page
Yes
VPPH [programming/erasing] supply minimum program/erase voltage
bit 7 to 4 value in volts
bit 3 to 0 value in 100 mV
4Dh
4Eh
0085h
0095h
8.5 V
VPPH [programming/erasing] supply maximum program/erase voltage
bit 7 to 4 value in volts
9.5 V
bit 3 to 0 value in 100 mV
4Fh
50h
51h
52h
57h
58h
59h
5Ah
5Bh
0001h
0001h
0001h
0008h
0004h
000Bh
0018h
0018h
000Bh
01 = dual boot
Dual boot
Program suspend, 00 = not supported, 01 = supported
Unlock bypass: 00 = not supported, 01 = supported
Extended memory block size (customer lockable), 2n bytes
Bank organization, 00 = data at 4Ah is 0, x= bank number
Bank A information, x = number of blocks in bank A
Bank B information, x = number of blocks in bank B
Bank C information, x = number of blocks in bank C
Bank D information, x = number of blocks in bank D
Supported
Supported
256
4
11
24
24
11
1. The values given in the above table are valid for both packages.
76/85
M29DW128G
Common Flash interface (CFI)
Table 37. Security code area
Address
Data
Description
Value
61h
62h
63h
64h
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
64 bit: unique device number
77/85
Extended memory block
M29DW128G
Appendix C Extended memory block
The M29DW128G has an extra block, the extended memory block, that can be accessed
using a dedicated command. This extended memory block is 256 words. It is used as a
security block (to provide a permanent security identification number) or to store additional
information.
The extended memory block is divided into two memory areas of 128 words each:
■
■
The first one is factory locked.
The second one is customer lockable. It is up to the customer to protect it from program
operations. Its status is indicated by bit DQ6 and DQ7. When DQ7 is set to ‘1’ and DQ6
to ‘0’, it indicates that this second memory area is customer lockable. When DQ7 and
DQ6 are both set to ‘1’, it indicates that the second part of the extended memory block
is customer locked and protected from program operations. Bit DQ7 being permanently
locked to either ‘1’ or ‘0’ is another security feature which ensures that a customer
lockable device cannot be used instead of a factory locked one.
Bits DQ6 and DQ7 are the most significant bits in the extended block protection indicator
and a specific procedure must be followed to read it. See Section 4.0.2: Verify extended
memory block protection indicator and Table 6: Block protection for details of how to read bit
DQ7.
The extended memory block can only be accessed when the device is in extended block
mode. For details of how the extended block mode is entered and exited, refer to the
Section 7.1.10: Program command and Section 7.3.2: Exit Extended Memory Block
command, and to Table 11: Block protection commands.
C.1
Factory locked section of extended memory block
The first section of the extended memory block is permanently protected from program
operations and cannot be unprotected. The random number, electronic serial number (ESN)
and security identification number (see Table 38: Extended memory block address and
data) are written in this section in the factory.
78/85
M29DW128G
Extended memory block
C.2
Customer lockable section of extended memory block
The device is delivered with the second section of the extended memory block ‘customer lockable’: bits
DQ7 and DQ6 are set to '1' and '0' respectively. It is up to the customer to program and protect this
section of the extended memory block but care must be taken because the protection is not reversible.
There are three ways of protecting this section:
■
■
■
Issue the Enter Extended Block command to place the device in extended block mode, then use the
in-system technique with RP either at V or at V .
IH
ID
Issue the Enter Extended Block command to place the device in extended block mode, then use the
programmer technique.
Issue a Set Extended Block Protection bit command to program the extended block protection bit to
‘1’ thus preventing the second section of the extended memory block from being programmed.
Bit DQ6 of the extended block protection indicator is automatically set to '1' to indicate that the second
section of the extended memory block is customer locked.
Once the extended memory block is programmed and protected, the Exit Extended Block command must
be issued to exit the extended block mode and return the device to read mode.
Table 38. Extended memory block address and data
Data
Device
Address(1)
Factory locked
Customer lockable
Random number, ESN(2)
,
000000h-00003Fh
000040h-00007Fh
Unavailable
security identification number
M29DW128G
Unavailable
Determined by customer
1. See Table 31: Block addresses.
2. ESN = electronic serial number.
79/85
Flowcharts
M29DW128G
Appendix D Flowcharts
Figure 23. Write to buffer program flowchart and pseudocode
Start
Write to Buffer
command,
block address
(1)
Write n
,
First three cycles of the
Write to Buffer and Program command
block address
Write Buffer Data,
start address
X=n
YES
YES
X = 0
NO
Write to a different
block address
Abort Write
to Buffer
NO
Write to Buffer and
Program Aborted
Write Next Data,
Program Address Pair
(3)
(2)
X = X-1
Write to Buffer Program
Confirm, block address
Read Status Register
(DQ1, DQ5, DQ7) at
last loaded address
YES
DQ7 = Data
NO
NO
NO
DQ1 = 1
YES
DQ5 = 1
YES
Check Status Register
(DQ5, DQ7) at
last loaded address
YES
DQ7 = Data
(4)
NO
(5)
END
FAIL OR ABORT
AI08968b
1. n+1 is the number of addresses to be programmed.
80/85
M29DW128G
Flowcharts
2. A write to buffer program abort and reset must be issued to return the device in read mode.
3. When the block address is specified, any address in the selected block address space is acceptable. However when
loading write buffer address with data, all addresses must fall within the selected write buffer page.
4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
5. If this flowchart location is reached because DQ5=’1’, then the Write to Buffer Program command failed. If this flowchart
location is reached because DQ1=’1’, then the Write to Buffer Program command aborted. In both cases, the appropriate
Reset command must be issued to return the device in read mode: a Reset command if the operation failed, a Write to
Buffer Program Abort and Reset command if the operation aborted.
6. See Table 8: Standard commands, for details on Write to Buffer Program command sequence.
81/85
Flowcharts
M29DW128G
Figure 24. Enhanced buffered program flowchart and pseudocode
Start
Enhanced Buffered
Program command,
First three cycles of the
Enhanced Buffered Program command
block address
Write Buffer Data,
start address (00),
X=255
YES
X = 0
NO
YES
Write to a different
block address
Abort Write
to Buffer
NO
Enhanced Buffered
Program Aborted(1)
Write Next Data,(2)
Program Address Pair
X = X-1
Enhanced Buffered
Program Confirm,
block address
Read Status Register
(DQ1, DQ5, DQ7) at
last loaded address
YES
DQ7 = Data
NO
NO
NO
DQ1 = 1
YES
DQ5 = 1
YES
Check Status Register
(DQ5, DQ7) at
last loaded address
YES
DQ7(=3)Data
NO
FAIL OR ABORT(4)
END
AI14243
1. A buffered program abort and reset must be issued to return the device in read mode.
2. When the block address is specified, all the addresses in the selected block address space must be issued starting from
(00). Furthermore, when loading write buffer address with data, data program addresses must be consecutive.
3. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
4. If this flowchart location is reached because DQ5=’1’, then the Enhanced Buffered Program command failed. If this
flowchart location is reached because DQ1=’1’, then the Enhanced Buffered Program command aborted. In both cases, the
appropriate reset command must be issued to return the device in read mode: a Reset command if the operation failed, a
82/85
M29DW128G
Flowcharts
Buffered Program Abort and Reset command if the operation aborted.
5. See Table 10: Enhanced buffered program commands, for details on Enhanced Buffered Program command sequence.
83/85
Revision history
M29DW128G
14
Revision history
Table 39. Document revision history
Date
Version
Revision details
03-Mar-2008
1
Initial release.
84/85
M29DW128G
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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
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