M29F002BT45K6T_技术文档

M29F002BT, M29F002BNT

M29F002BB, M29F002BNB

2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory

■ SINGLE 5V ± 10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 45 ns

■ PROGRAMMING TIME

– 8 µs by Byte typical

■ 7 MEMORY BLOCKS

PLCC32 (K)

TSOP32 (N)

8 x 20mm

– 1 Boot Block (Top or Bottom Location)

– 2 Parameter and 4 Main Blocks

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Polling and Toggle Bits

■ ERASE SUSPEND and RESUME MODES

32

– Read and Program another Block during

Erase Suspend

1

PDIP32 (P)

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ TEMPORARY BLOCK UNPROTECTION

Figure 1. Logic Diagram

MODE

■ LOW POWER CONSUMPTION

V

– Standby and Automatic Standby

CC

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

18

8

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

A0-A17

DQ0-DQ7

■ ELECTRONIC SIGNATURE

W

M29F002BT

– Manufacturer Code: 20h

M29F002BB

M29F002BNT

M29F002BNB

E

G

– Top Device Code M29F002BT: B0h

– Top Device Code M29F002BNT: B0h

– Bottom Device Code M29F002BB: 34h

– Bottom Device Code M29F002BNB: 34h

RP

V

SS

AI02957B

April 2002

1/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Figure 2. PLCC Connections

Figure 3. TSOP Connections

A11

A9

1

32

G

A10

E

A8

A13

A14

A17

W

DQ7

DQ6

DQ5

DQ4

DQ3

1 32

A7

A14

A13

A8

A6

A5

V

8

9

25

24

M29F002BT

M29F002BB

A4

A9

CC

M29F002BT

M29F002BB

M29F002BNB

V

SS

A3

A2

9

25 A11

G

RP

A16

DQ2

DQ1

DQ0

A0

A15

A12

A7

A1

A10

E

A0

DQ0

DQ7

17

A6

A1

A5

A2

A4

16

17

A3

AI02959B

AI02958

Figure 4. PDIP Connections

Table 1. Signal Names

A0-A17

Address Inputs

Data Inputs/Outputs

DQ0-DQ7

RP

A16

A15

A12

A7

1

2

3

4

5

6

7

8

9

32

31

V

CC

W

E

Chip Enable

G

W

Output Enable

30 A17

29 A14

28 A13

27 A8

Write Enable

M29F002BT, M29F002BB:

Reset/Block Temporary Unprotect

A6

M29F002BT

M29F002BB

M29F002BNT

A5

26 A9

RP

A4

25 A11

M29F002BNT, M29F002BNB:

Not Connected Internally

A3

24

23 A10

22

G

A2 10

A1 11

V

CC

Supply Voltage

Ground

E

A0 12

21 DQ7

20 DQ6

19 DQ5

18 DQ4

17 DQ3

V

SS

DQ0 13

DQ1 14

DQ2 15

V

16

SS

AI02960

2/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

Ambient Operating Temperature (Temperature Range Option 1)

Ambient Operating Temperature (Temperature Range Option 6)

Ambient Operating Temperature (Temperature Range Option 3)

Temperature Under Bias

0 to 70

T

–40 to 85

–40 to 125

–50 to 125

–65 to 150

°C

A

°C

T

°C

BIAS

T

Storage Temperature

°C

STG

(2)

Input or Output Voltage

–0.6 to 6

V

IO

V

Supply Voltage

–0.6 to 6

V

CC

V

Identification Voltage

–0.6 to 13.5

ID

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

SUMMARY DESCRIPTION

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

The blocks in the memory are asymmetrically ar-

ranged, see Tables 3A and 3B, Block Addresses.

The first or last 64 Kbytes have been divided into

four additional blocks. The 16 Kbyte Boot Block

can be used for small initialization code to start the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter storage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP32 (8 x 20mm),

PLCC32 and PDIP packages and it is supplied

with all the bits erased (set to ’1’).

The M29F002B is a 2 Mbit (256Kb x8) non-volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single 5V supply. On power-up the memory

defaults to its Read mode where it can be read in

the same way as a ROM or EPROM. The

M29F002B is fully backward compatible with the

M29F002.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

Table 3. Top Boot Block Addresses,

M29F002BT, M29F002BNT

Table 4. Bottom Boot Block Addresses,

M29F002BB

Size

(Kbytes)

Size

(Kbytes)

#

Address Range

#

Address Range

6

5

4

3

2

1

0

16

8

3C000h-3FFFFh

3A000h-3BFFFh

38000h-39FFFh

30000h-37FFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

6

5

4

3

2

1

0

64

32

8

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

08000h-0FFFFh

06000h-07FFFh

04000h-05FFFh

00000h-03FFFh

8

32

64

8

16

3/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

SIGNAL DESCRIPTIONS

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V , for at least

IL

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A17). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

t

. After Reset/Block Temporary Unprotect

PLPX

goes High, V , the memory will be ready for Bus

IH

Read and Bus Write operations after t

PHEL

or t

, whichever occurs last. See Table 15 and

PLYH

Figure 12, Reset/Temporary Unprotect AC Char-

acteristics for more details.

Holding RP at V will temporarily unprotect the

ID

protected blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V to V must be slower than

IH

ID

t

.

PHPHH

Reset/Block Temporary Unprotect can be left un-

connected. A weak internal pull-up resistor en-

sures that the memory always operates correctly.

V

Supply Voltage. The V

Supply Voltage

CC

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

High, V , all other pins are ignored.

IH

The Command Interface is disabled when the V

CC

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Supply Voltage is less than the Lockout Voltage,

. This prevents Bus Write operations from ac-

V

LKO

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP). The Re-

set/Block Temporary Unprotect pin can be used to

apply a Hardware Reset to the memory or to tem-

porarily unprotect all blocks that have been pro-

tected. On the M29F002BNT the pin is not

connected internally and this feature is not avail-

able.

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the V

Supply Voltage pin and the V Ground

CC

SS

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, I

.

CC4

V

Ground. The V Ground is the reference for

SS

all voltage measurements.

4/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

BUS OPERATIONS

When Chip Enable is at V the Supply Current is

IH

reduced to the TTL Standby Supply Current, I

.

CC2

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Table 5, Bus Operations, for a summary. Typically

glitches of less than 5ns on Chip Enable or Write

Enable are ignored by the memory and do not af-

fect bus operations.

To further reduce the Supply Current to the CMOS

Standby Supply Current, I , Chip Enable should

CC3

be held within V

± 0.2V. For Standby current

CC

levels see Table 11, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, I

til the operation completes.

Automatic Standby. If CMOS levels (V ± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

, for Program or Erase operations un-

CC4

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

CC

Inputs, applying a Low signal, V , to Chip Enable

IL

and Output Enable and keeping Write Enable

High, V . The Data Inputs/Outputs will output the

duced to the CMOS Standby Supply Current, I

The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

.

IH

CC3

value, see Figure 9, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Special Bus Operations

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require V to be applied to some pins.

ID

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Table 5, Bus Operations.

Block Protection and Blocks Unprotection. Each

block can be separately protected against acci-

dental Program or Erase. Protected blocks can be

unprotected to allow data to be changed.

able must remain High, V , during the whole Bus

IH

Write operation. See Figures 10 and 11, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. For further information refer to Application

Note AN1122, Applying Protection and Unprotec-

tion to M29 Series Flash.

High, V .

IH

Standby. When Chip Enable is High, V , the

IH

Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is re-

duced to the Standby level.

Table 5. Bus Operations

Data

Address Inputs

Operation

Bus Read

E

G

W

Inputs/Outputs

V

IL

V

IH

Cell Address

Data Output

Data Input

Hi-Z

IL

IH

V

Bus Write

Command Address

IL

Output Disable

Standby

X

IH

V

X

Hi-Z

IH

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

IL

ID

V

20h

IL

IH

Others V or V

IL

IH

B0h (M29F002BT)

B0h (M29F002BNT)

34h (M29F002BB)

A0 = V , A1 = V , A9 = V ,

IH

IL

ID

V

Read Device Code

Others V or V

IL

IH

Note: X = V or V

.

IH

IL

5/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

COMMAND INTERFACE

state machine and starts the Program/Erase Con-

troller.

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the memory will ig-

nore all commands. It is not possible to issue any

command to abort or pause the operation. Typical

program times are given in Table 7. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

The commands are summarized in Table 6, Com-

mands. Refer to Table 6 in conjunction with the

text descriptions below.

Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM. It also resets

the errors in the Status Register. Either one or

three Bus Write operations can be used to issue

the Read/Reset command.

If the Read/Reset command is issued during a

Block Erase operation or following a Programming

or Erase error then the memory will take upto 10µs

to abort. During the abort period no valid data can

be read from the memory. Issuing a Read/Reset

command during a Block Erase operation will

leave invalid data in the memory.

Auto Select Command. The Auto Select com-

mand is used to read the Manufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until another com-

mand is issued.

Unlock Bypass Command. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program command to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass command.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

with A0 = V and A1 = V . The other address bits

IL

may be set to either V or V . The Manufacturer

IL

IH

Code for STMicroelectronics is 20h.

The Device Code can be read using a Bus Read

Unlock Bypass Program Command. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write operations, the

final write operation latches the address and data

in the internal state machine and starts the Pro-

gram/Erase Controller.

operation with A0 = V and A1 = V . The other

IH

IL

address bits may be set to either V or V . The

IL

IH

Device Code for the M29F002BT is B0h, the

M29F002BNT is B0h and the M29F002BB is 34h.

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = V ,

IL

A1 = V , and A13-A17 specifying the address of

the block. The other address bits may be set to ei-

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be programmed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, which leaves the device in Unlock By-

pass Mode. See the Program command for details

on the behavior.

IH

ther V or V . If the addressed block is protected

IL

IH

then 01h is output on the Data Inputs/Outputs, oth-

erwise 00h is output.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

6/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 6. Commands

Command

Bus Write Operations

1st

2nd

3rd

4th

5th

6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1

3

4

3

X

F0

AA

Read/Reset

555

2AA

55

X

F0

90

A0

20

Auto Select

Program

555

PA

PD

Unlock Bypass

Program

2

X

A0

PA

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

555

2AA

555

80

555

AA

2AA

55

555

BA

10

30

Block Erase

6+ 555

Erase Suspend

Erase Resume

1

X

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.

Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write

Operations until the Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands

on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

Unlock Bypass Reset Command. The Unlock

Bypass Reset command can be used to return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100µs,

leaving the data unchanged. No error condition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

times are given in Table 7. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

7/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Write operation using the address of the

additional block. The Block Erase operation starts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer restarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for

details on how to identify if the Program/Erase

Controller has started the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Block Erase operation the memory will

ignore all commands except the Erase Suspend

and Read/Reset commands. Typical block erase

times are given in Table 7. All Bus Read opera-

tions during the Block Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend

Command may be used to temporarily suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

The Program/Erase Controller will suspend within

15µs of the Erase Suspend Command being is-

sued. Once the Program/Erase Controller has

stopped the memory will be set to Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is suspended immediately and will start im-

mediately when the Erase Resume Command is

issued. It will not be possible to select any further

blocks for erasure after the Erase Resume.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. Reading from blocks that

are being erased will output the Status Register. It

is also possible to enter the Auto Select mode: the

memory will behave as in the Auto Select mode on

all blocks until a Read/Reset command returns the

memory to Erase Suspend mode.

Erase Resume Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resumed more than once.

Table 7. Program, Erase Times and Program, Erase Endurance Cycles

(T = 0 to 70°C, –40 to 85°C or –40 to 125°C)

A

Typical after

(1)

Parameter

Min

Max

Unit

Typ

0.8

(1)

100k W/E Cycles

Chip Erase (All bits in the memory set to ‘0’)

Chip Erase

0.8

2.5

0.6

8

sec

2.5

0.6

8

10

4

Block Erase (64 Kbytes)

Program

sec

150

9

µs

Chip Program

2.3

sec

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. T = 25 °C, V = 5V.

A

CC

8/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

STATUS REGISTER

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is accessed.

The bits in the Status Register are summarized in

Table 8, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 6, Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’ and attempting to do so may

or may not set DQ5 at ’1’. In both cases, a succes-

sive Bus Read operation will show the bit is still ’0’.

One of the Erase commands must be used to set

all the bits in a block or in the whole memory from

’0’ to ’1’.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 5, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

Table 8. Status Register Bits

Operation

Program

Address

DQ7

DQ6

DQ5

DQ3

DQ2

Any Address

DQ7

Toggle

0

–

Program During Erase

Suspend

Any Address

DQ7

Toggle

0

–

Program Error

Chip Erase

Any Address

DQ7

Toggle

1

0

–

1

0

1

–

0

1

Toggle

Erasing Block

Toggle

Block Erase before timeout

Block Erase

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

No Toggle

Erase Suspend

Erase Error

Non-Erasing Block

Good Block Address

Faulty Block Address

Data read as normal

0

Toggle

1

No Toggle

Toggle

Note: Unspecified data bits should be ignored.

9/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Figure 5. Data Polling Flowchart

Figure 6. Data Toggle Flowchart

START

READ

DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

READ DQ6

DQ7

=

DATA

YES

DQ6

=

NO

TOGGLE

YES

NO

DQ5

= 1

NO

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

READ DQ6

TWICE

DQ7

=

YES

DQ6

=

DATA

NO

TOGGLE

NO

FAIL

YES

PASS

FAIL

PASS

AI03598

AI01370B

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional blocks to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Register is read.

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

within the blocks being erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

10/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 9. AC Measurement Conditions

Parameter

M29F002B

45 / 55

High Speed

30pF

70 / 90 / 120

Standard

100pF

AC Test Conditions

Load Capacitance (C )

L

Input Rise and Fall Times

≤ 10ns

Input Pulse Voltages

0 to 3V

1.5V

0.45 to 2.4V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 7. AC Testing Input Output Waveform

Figure 8. AC Testing Load Circuit

1.3V

High Speed

1N914

3V

1.5V

3.3kΩ

0V

DEVICE

UNDER

TEST

OUT

= 30pF or 100pF

Standard

C

2.4V

L

2.0V

0.8V

0.45V

AI01275B

C

includes JIG capacitance

AI03027

L

Table 10. Capacitance

(T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: Sampled only, not 100% tested.

11/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 11. DC Characteristics

(T = 0 to 70°C, –40 to 85°C or –40 to 125°C)

A

(3)

Symbol

Parameter

Test Condition

Min

Max

Unit

Typ

(1)

0V ≤ V ≤ V

Input Leakage Current

RP Leakage Current High

RP Leakage Current Low

Output Leakage Current

±1

µA

I

IN

CC

LI

I

RP = V

LR1

CC

SS

I

–0.2

–10

±1

LR2

I

0V ≤ V

≤ V

OUT CC

LO

E = V , G = V

,

IH

IL

I

Supply Current (Read)

5

15

1

mA

µA

CC1

f = 6MHz

I

E = V

Supply Current (Standby) TTL

Supply Current (Standby) CMOS

CC2

IH

E = V ±0.2V,

CC

I

30

100

CC3

RP = V ±0.2V

CC

Program/Erase

Controller active

(2)

Supply Current (Program/Erase)

20

mA

I

CC4

V

Input Low Voltage

–0.5

2

0.8

V

IL

V

IH

V

+0.5

CC

Input High Voltage

V

I

= 5.8mA

Output Low Voltage

Output High Voltage TTL

Output High Voltage CMOS

Identification Voltage

Identification Current

0.45

V

OL

I

= –12.5mA

= –100µA

2.4

V

OH

V

I

OH

I

V

–0.4

V

OH

CC

V

11.5

3.2

12.5

100

V

ID

A9 = V

µA

ID

Program/Erase Lockout Supply

Voltage

(2)

4.2

V

LKO

Note: 1. Excluding the RP input.

2. Sampled only, not 100% tested.

3. T = 25°C, V = 5V.

A

CC

12/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 12. Read AC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F002B

Symbol

Alt

Parameter

Test Condition

Unit

45

55

70 / 90 / 120

E = V ,

IL

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

45

55

70

ns

AVAV

RC

G = V

IL

E = V ,

IL

t

ACC

Max

45

55

AVQV

G = V

E = V

IL

Chip Enable Low to Output

Transition

(1)

t

Min

Max

Min

0

45

0

55

0

70

0

ns

t

LZ

ELQX

t

Chip Enable Low to Output Valid

ELQV

CE

Output Enable Low to Output

Transition

(1)

t

OLZ

GLQX

t

E = V

G = V

E = V

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Max

25

15

30

18

30

20

ns

GLQV

OE

IL

(1)

t

HZ

DF

IL

EHQZ

(1)

t

IL

GHQZ

t

Chip Enable, Output Enable or

Address Transition to Output

Transition

EHQX

t

Min

0

ns

GHQX

OH

t

AXQX

Note: 1. Sampled only, not 100% tested.

Figure 9. Read Mode AC Waveforms

tAVAV

VALID

A0-A17

tAVQV

tAXQX

tEHQX

E

tELQV

tELQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

VALID

DQ0-DQ7

AI02961

13/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 13. Write AC Characteristics, Write Enable Controlled

(T = 0 to 70°C, –40 to 85°C or –40 to 125°C)

A

M29F002B

Symbol

Alt

Parameter

Unit

45

0

55

0

70 / 90 / 120

t

WC

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

Min

70

0

ns

µs

AVAV

t

CS

ELWL

t

40

25

0

40

25

0

45

30

0

WLWH

WP

t

DVWH

DS

DH

CH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

WHDX

t

0

WHEH

t

WPH

20

0

20

0

20

0

WHWL

t

AS

AVWL

t

40

0

40

0

45

0

WLAX

AH

t

GHWL

t

OEH

0

WHGL

t

V

High to Chip Enable Low

CC

50

VCHEL

VCS

Figure 10. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A17

VALID

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

W

tGHWL

tWLWH

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7

V

CC

tVCHEL

AI02083

14/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 14. Write AC Characteristics, Chip Enable Controlled

(T = 0 to 70°C, –40 to 85°C or –40 to 125°C)

A

M29F002B

Symbol

Alt

Parameter

Unit

45

0

55

0

70 / 90 / 120

t

WC

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Min

70

0

ns

µs

AVAV

t

WS

WLEL

t

40

25

0

40

25

0

45

30

0

ELEH

CP

DS

t

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

Chip Enable High to Output Enable Low

EHDX

DH

t

WH

0

EHWH

t

20

0

20

0

20

0

EHEL

CPH

t

AS

AVEL

t

40

0

40

0

45

0

ELAX

AH

t

GHEL

t

0

EHGL

OEH

t

V

High to Write Enable Low

CC

50

VCHWL

VCS

Figure 11. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A17

VALID

tELAX

tAVEL

tEHWH

W

G

E

tWLEL

tEHGL

tGHEL

tELEH

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7

V

CC

tVCHWL

AI02084

15/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 15. Reset/Block Temporary Unprotect AC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)

M29F002B

Symbol

Alt

Parameter

Unit

45

55

70 / 90 / 120

(1)

t

PHWL

RP High to Write Enable Low, Chip Enable

Low, Output Enable Low

t

Min

50

ns

PHEL

RH

(1)

t

PHGL

t

RP Pulse Width

Min

Max

Min

500

10

500

10

500

10

ns

µs

ns

PLPX

(1)

RP

t

RP Low to Read Mode

t

READY

PLYH

(1)

t

RP Rise Time to V

500

t

VIDR

ID

PHPHH

Note: 1. Sampled only, not 100% tested.

Figure 12. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

tPLPX

RP

tPHPHH

tPLYH

AI02943

16/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 16. Ordering Information Scheme

Example:

M29F002BB

45

N

1

T

Device Type

M29

Operating Voltage

F = V = 5V ± 10%

CC

Device Function

002B = 2 Mbit (256Kb x8), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

NT = Top Boot, No Reset/Block Temporary Unprotect pin

NB = Bottom Boot, No Reset/Block Temporary Unprotect pin

Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

90 = 90 ns

120 = 120 ns

Package

K = PLCC32

N = TSOP32: 8 x 20 mm

P = PDIP32

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

3 = –40 to 125 °C

Option

T = Tape & Reel Packing

Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed

parts, otherwise devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

17/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Table 17. Revision History

Date

Rev.

Revision Details

July 1999

-01

First Issue

Chip Erase Max. specification added (Table 7)

Block Erase Max. specification added (Table 7)

Program Max. specification added (Table 7)

Chip Program Max. specification added (Table 7)

07-Oct-1999

-02

I

and I

Typ. specification added (Table 11)

CC1

CC3

Test Condition changed (Table 11)

New document template

Document type: from Preliminary Data to Data Sheet

Status Register bit DQ5 clarification

Data Polling Flowchart diagram change (Figure 5)

28-Jul-2000

22-Apr-2002

-03

-04

Data Toggle Flowchart diagram change (Figure 6)

M29F002BNB device added

PLCC32 package mechanical data modified

18/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline

D

A1

A2

D1

1

N

B1

e

E2

E3

E1 E

F

B

0.51 (.020)

1.14 (.045)

D3

A

R

CP

D2

PLCC-A

Note: Drawing is not to scale.

PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data

millimeters

Symbol

inches

Min

Typ

Min

3.18

1.53

0.38

0.33

0.66

Max

3.56

2.41

–

Typ

Max

0.140

0.095

–

A

A1

A2

B

0.125

0.060

0.015

0.013

0.026

0.53

0.81

0.10

12.57

11.51

5.66

–

0.021

0.032

0.004

0.495

0.453

0.223

–

B1

CP

D

12.32

11.35

4.78

–

0.485

0.447

0.188

–

D1

D2

D3

E

7.62

0.300

14.86

13.89

6.05

–

15.11

14.05

6.93

–

0.585

0.547

0.238

–

0.595

0.553

0.273

–

E1

E2

E3

e

10.16

1.27

0.400

0.050

–

F

0.00

32

0.13

0.000

32

0.005

N

R

0.89

–

0.035

–

19/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Note: Drawing is not to scale.

TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

8.10

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.3189

–

A

A1

A2

B

0.05

0.95

0.15

0.10

19.80

18.30

7.90

–

0.0020

0.0374

0.0059

0.0039

0.7795

0.7205

0.3110

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0276

5°

α

N

32

CP

0.10

0.0039

20/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline

A2

A

A1

e1

L

α

C

B1

B

eA

eB

D2

D

S

N

1

E1

E

PDIP

Note: 1. Drawing is not to scale.

PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data

mm

inches

Min.

–

Symb.

Typ.

Min.

–

Max.

5.08

–

Typ.

Max.

0.2000

–

A

A1

A2

B

0.38

3.56

0.38

–

0.0150

0.1402

0.0150

–

4.06

0.51

–

0.1598

0.0201

–

B1

C

1.52

0.0598

0.20

41.78

–

0.30

42.04

–

0.0079

1.6449

–

0.0118

1.6551

–

D

D2

E

38.10

15.24

1.5000

0.6000

–

E1

e1

eA

eB

L

13.59

–

13.84

–

0.5350

–

0.5449

–

2.54

0.1000

0.6000

15.24

–

15.24

3.18

1.78

0°

17.78

3.43

2.03

10°

0.6000

0.1252

0.0701

0°

0.7000

0.1350

0.0799

10°

S

α

N

32

21/22

M29F002BT, M29F002BB, M29F002BNT, M29F002BNB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong -

India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

www.st.com

22/22


型号：	M29F002BT45K6T
厂家：	ST
描述：	2 Mbit 256Kb x8, Boot Block Single Supply Flash Memory 2兆位256Kb的X8 ，引导块单电源闪存闪存存储内存集成电路
文件：	总22页 (文件大小：190K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M29F002BT45K6T [STMICROELECTRONICS]

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