M29F016D70N6 [STMICROELECTRONICS]
2MX8 FLASH 5V PROM, 70ns, PDSO40, 10 X 20 MM, PLASTIC, TSOP-40;
| 型号： | M29F016D70N6 |
| 厂家： | 
ST |
| 描述： | 2MX8 FLASH 5V PROM, 70ns, PDSO40, 10 X 20 MM, PLASTIC, TSOP-40 可编程只读存储器 光电二极管 内存集成电路 闪存 |
| 文件： | 总37页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M29F016D
16 Mbit (2Mb x8, Uniform Block)
5V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– V = 5V ±10% for PROGRAM, ERASE and
CC
READ OPERATIONS
■ ACCESS TIME: 55, 70, 90ns
■ PROGRAMMING TIME
– 10µs per Byte typical
■ 32 UNIFORM 64Kbyte MEMORY BLOCKS
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithms
■ ERASE SUSPEND and RESUME MODES
TSOP40 (N)
10 x 20mm
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ TEMPORARY BLOCK UNPROTECTION
MODE
SO44 (M)
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: ADh
July 2003
1/37
M29F016D
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
V
Supply Voltage (5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
SS
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/37
M29F016D
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 13
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 23
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 23
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline. . . . . . . . . . . . . . . . 24
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . . . . . . . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Block Addresses, M29F016D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3/37
M29F016D
Table 18. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 21. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 22. Programmer Technique Bus Operations, BYTE = V or V . . . . . . . . . . . . . . . . . . . . . 31
IH
IL
Figure 14. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36
4/37
M29F016D
SUMMARY DESCRIPTION
The M29F016D is a 16 Mbit (2Mb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single low voltage 5V supply. On power-up
the memory defaults to its Read mode where it can
be read in the same way as a ROM or EPROM.
the memory by taking care of all of the special op-
erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi-
fied. The command set required to control the
memory is consistent with JEDEC standards.
The memory is divided into 32 uniform blocks of
64Kbytes (see Figure 5, Block Addresses) that
can be erased independently so it is possible to
preserve valid data while old data is erased.
Blocks can be protected in groups of 4 to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com-
mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP40 (10 x 20mm) and
SO44 packages. Access times of 55, 70 and 90ns
are available. The memory is supplied with all the
bits erased (set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
Chip Enable
V
CC
E
G
Output Enable
21
8
W
RP
RB
Write Enable
A0-A20
DQ0-DQ7
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
W
E
M29F016D
V
CC
G
RB
V
SS
Ground
RP
NC
Not Connected Internally
V
SS
AI05269
5/37
M29F016D
Figure 3. TSOP Connections
Figure 4. SO Connections
NC
RP
A11
A10
A9
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
E
CC
2
A19
A18
A17
A16
A15
A14
A13
A12
E
1
40
A20
NC
3
A12
A13
A14
A15
A16
A17
A18
A19
NC
4
W
5
G
A8
6
RB
A7
7
DQ7
DQ6
DQ5
DQ4
A6
8
A5
9
A4
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
A3
V
10
11
31
30
V
V
V
CC
SS
SS
CC
NC
M29F016D
M29F016D
NC
A20
NC
RP
A11
A10
A9
A2
DQ3
DQ2
DQ1
DQ0
A0
A1
W
A0
G
DQ0
DQ1
DQ2
DQ3
RB
A8
DQ7
DQ6
DQ5
DQ4
A7
A6
A1
A5
A2
V
V
A4
20
21
A3
SS
SS
V
CC
AI05271
AI05280
6/37
M29F016D
Figure 5. Block Addresses
M29F016D
Block Addresses
1FFFFFh
64 KByte
64 KByte
64 KByte
1F0000h
1EFFFFh
1E0000h
1DFFFFh
1D0000h
1CFFFFh
Total of 32
64 KByte Blocks
02FFFFh
64 KByte
64 KByte
64 KByte
020000h
01FFFFh
010000h
00FFFFh
000000h
AI05270
Note: Also see Appendix A, Table 15 for a full listing of the Block Addresses.
7/37
M29F016D
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Erase operations on all blocks will be possible.
The transition from V to V must be slower than
IH
ID
t
.
PHPHH
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V . Ready/Busy is high-im-
OL
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 13 and Figure
13, Reset/Temporary Unprotect AC Characteris-
tics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, V , all other pins are ignored.
IH
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
V
Supply Voltage (5V). V
provides the
CC
CC
power supply for all operations (Read, Program
and Erase).
The Command Interface is disabled when the V
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
CC
Supply Voltage is less than the Lockout Voltage,
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
V
. This prevents Bus Write operations from ac-
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V , for at least
IL
A 0.1µF capacitor should be connected between
t
. After Reset/Block Temporary Unprotect
PLPX
the V
Supply Voltage pin and the V Ground
CC
SS
goes High, V , the memory will be ready for Bus
IH
pin to decouple the current surges from the power
supply, see Figure 10, AC Measurement Load Cir-
cuit. The PCB track widths must be sufficient to
carry the currents required during program and
Read and Bus Write operations after t
or
PHEL
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more
details.
erase operations, I
.
CC3
V
Ground. V is the reference for all voltage
SS
SS
Holding RP at V will temporarily unprotect the
protected Blocks in the memory. Program and
ID
measurements.
8/37
M29F016D
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Tables 2, Bus Operations, for a summary. Typical-
ly glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not af-
fect bus operations.
be held within V ± 0.2V. For the Standby current
level see Table 9, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
CC
Current, I
, for Program or Erase operations un-
CC3
til the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
CC
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
. The
CC2
Inputs, applying a Low signal, V , to Chip Enable
IL
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
and Output Enable and keeping Write Enable
High, V . The Data Inputs/Outputs will output the
IH
value, see Figure 10, Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
They require V to be applied to some pins.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2, Bus Operations.
able must remain High, V , during the whole Bus
Block Protection and Blocks Unprotection.
IH
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
Blocks can be protected in groups of 4 against ac-
cidental Program or Erase. See Appendix A, Table
15, Block Addresses, for details of which blocks
must be protected together as a group. Protected
blocks can be unprotected to allow data to be
changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on pro-
gramming equipment and the other for in-system
use. Block Protect and Chip Unprotect operations
are described in Appendix C.
High, V .
IH
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
Table 2. Bus Operations
Address Inputs
A0-A20
Data Inputs/Outputs
DQ7-DQ0
Operation
Bus Read
E
G
W
V
V
V
IH
Cell Address
Data Output
Data Input
Hi-Z
IL
IL
IL
IH
IH
V
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
X
IH
V
IH
X
X
X
Hi-Z
A0 = V , A1 = V , A9 = V , Others
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
V
20h
IL
IL
IL
IL
IH
IH
V
IL
or V
IH
A0 = V , A1 = V ,
IH
IL
V
Read Device Code
ADh
A9 = V , Others V or V
IH
ID
IL
Note: X = V or V
.
IH
IL
9/37
M29F016D
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Refer to Table 3, Commands, in conjunction with
the following text descriptions.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V and A1 = V . The other address bits
IL
IL
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in the memory array at a
time. The command requires two Bus Write oper-
ations, the final write operation latches the ad-
dress and data in the internal state machine and
starts the Program/Erase Controller.
may be set to either V or V . The Manufacturer
IL
IH
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V . The
IL
IH
Device Code for the M29F016D ADh.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V ,
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. A
protected block cannot be programmed; the oper-
ation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock By-
pass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
IL
A1 = V , and A12-A20 specifying the address of
IH
the block. The other address bits may be set to ei-
ther V or V . If the addressed block is protected
IL
IH
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
10/37
M29F016D
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 4. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
Bus Write operation. See the Status Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 4. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being is-
sued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
11/37
M29F016D
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
command is valid when the device is in the Read
Array mode, or when the device is in Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect-
ed mode.
See Appendix B, Tables 16, 17, 18, 19, 20 and 21
for details on the information contained in the
Common Flash Interface (CFI) memory area.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller after an Erase Suspend. The de-
vice must be in Read Array mode before the Re-
sume command will be accepted. An erase can be
suspended and resumed more than once.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
Block Protect and Chip Unprotect Com-
mands. Groups of blocks can be protected
against accidental Program or Erase. The Protec-
tion Groups are shown in Appendix A, Table 15.
The whole chip can be unprotected to allow the
data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix C.
Table 3. Commands
Bus Write Operations
Command
1st
2nd
3rd
4th
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
555
555
555
555
2AA
2AA
2AA
2AA
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
555
555
555
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
98
X
00
55
55
555
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Erase Suspend
Erase Resume
Read CFI Query
1
1
1
X
X
55
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
12/37
M29F016D
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
Typical after
(1)
Parameter
Min
Max
Unit
Typ
25
(1)
100k W/E Cycles
Chip Erase
25
120
6
s
Block Erase (64 Kbytes)
Program (Byte)
0.8
10
25
s
µs
200
120
Chip Program (Byte by Byte)
Program/Erase Cycles (per Block)
s
100,000
cycles
Note: 1. T = 25°C, V = 5V.
A
CC
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 5, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 6, Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A Valid Ad-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
ror is signalled and DQ6 toggles for approximately
1µs.
Figure 7, Data Toggle Flowchart, gives an exam-
ple of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
13/37
M29F016D
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Table 5. Status Register Bits
Operation
Program
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Toggle
Erasing Block
Toggle
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
No Toggle
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
0
0
Toggle
Toggle
1
1
1
No Toggle
Toggle
1
Note: Unspecified data bits should be ignored.
14/37
M29F016D
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
YES
FAIL
PASS
PASS
AI05278
AI05279
15/37
M29F016D
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
T
Temperature Under Bias
–50
125
°C
BIAS
T
–65
150
°C
STG
Storage Temperature
(1)
V
CC
+ 0.6
–0.6
–0.6
–0.6
V
V
V
V
Input or Output Voltage
Supply Voltage
IO
V
CC
6
V
Identification Voltage
13.5
ID
Note: 1. Minimum Voltage may undershoot to –2V or overshoot to V +2V during transition for a maximum of 20ns.
CC
16/37
M29F016D
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 7, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 7. Operating and AC Measurement Conditions
M29F016D
Parameter
55
70/ 90
Unit
Min
4.5
Max
5.5
85
Min
4.5
Max
5.5
85
V
Supply Voltage
V
°C
pF
ns
V
CC
Ambient Operating Temperature
– 40
– 40
Load Capacitance (C )
30
100
L
Input Rise and Fall Times
10
10
Input Pulse Voltages
0 to 3
1.5
0.45 to 2.4
0.8 and 2.0
Input and Output Timing Ref. Voltages
V
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
1.3V
High Speed (55ns)
3V
V
CC
1N914
1.5V
0V
3.3kΩ
DEVICE
UNDER
TEST
Standard (70, 90ns)
2.4V
OUT
C
L
2.0V
0.8V
0.1µF
0.45V
AI05276
C
includes JIG capacitance
AI05277
L
Table 8. Device Capacitance
Symbol
Parameter
Test Condition
Min
Max
6
Unit
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
pF
pF
IN
IN
C
OUT
V
OUT
12
Note: Sampled only, not 100% tested.
17/37
M29F016D
Table 9. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
±1
±1
20
2
Unit
µA
I
0V ≤ V ≤ V
Input Leakage Current
LI
IN
CC
I
0V ≤ V
≤ V
OUT CC
Output Leakage Current
Supply Current (Read)
Supply Current (Standby) TTL
µA
LO
I
E = V , G = V , f = 6MHz
IL IH
mA
mA
CC1
I
E = V
IH
CC2
E = V ± 0.2V,
CC
I
Supply Current (Standby) CMOS
Supply Current (Program/Erase)
150
µA
CC3
RP = V ±0.2V
CC
Program/Erase
Controller active
(1)
20
mA
I
CC4
V
Input Low Voltage
–0.5
2
0.8
V
V
IL
V
V
V
+ 0.5
CC
Input High Voltage
IH
I
= 5.8mA
= –2.5mA
= –100µA
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
Identification Voltage
Identification Current
0.45
V
OL
OL
I
I
2.4
V
OH
OH
V
OH
V
– 0.4
V
CC
V
11.5
12.5
100
V
ID
I
ID
A9 = V
µA
ID
Program/Erase Lockout Supply
Voltage
(1)
3.2
4.2
V
V
LKO
Note: 1. Sampled only, not 100% tested.
18/37
M29F016D
Figure 10. Read AC Waveforms
tAVAV
VALID
A0-A20
E
tAVQV
tAXQX
tEHQX
tELQV
tELQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ7
VALID
AI05272
Table 10. Read AC Characteristics
M29F016D
55 70/ 90
Symbol
Alt
Parameter
Test Condition
E = V ,
Unit
IL
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
55
55
70
70
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Max
AVQV
G = V
G = V
G = V
E = V
E = V
G = V
IL
IL
IL
IL
IL
IL
(1)
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Min
Max
Min
0
0
ns
ns
ns
ns
ns
ns
t
LZ
ELQX
t
t
55
0
70
0
ELQV
CE
(1)
t
t
OLZ
GLQX
t
t
OE
Max
Max
Max
30
18
18
30
20
20
GLQV
(1)
(1)
t
HZ
t
t
EHQZ
t
DF
E = V
IL
GHQZ
t
t
t
EHQX
Chip Enable, Output Enable or Address
Transition to Output Transition
t
Min
0
0
ns
GHQX
OH
AXQX
Note: 1. Sampled only, not 100% tested.
19/37
M29F016D
Figure 11. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
W
tGHWL
tWLWH
tWHWL
tDVWH
VALID
tWHDX
DQ0-DQ7
V
CC
tVCHEL
RB
tWHRL
AI05273
Table 11. Write AC Characteristics, Write Enable Controlled
M29F016D
Symbol
Alt
Parameter
Unit
55
55
0
70/ 90
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
t
CS
ELWL
t
t
45
45
0
45
45
0
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Program/Erase Valid to RB Low
WHDX
t
0
0
WHEH
t
t
WPH
20
0
20
0
WHWL
t
t
AS
AVWL
t
t
AH
45
0
45
0
WLAX
t
GHWL
t
t
OEH
0
0
WHGL
(1)
t
30
50
30
t
BUSY
WHRL
t
t
V
High to Chip Enable Low
CC
Min
50
µs
VCHEL
VCS
Note: 1. Sampled only, not 100% tested.
20/37
M29F016D
Figure 12. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20
VALID
tELAX
tAVEL
tEHWH
W
G
E
tWLEL
tEHGL
tGHEL
tELEH
tEHEL
tDVEH
VALID
tEHDX
DQ0-DQ7
V
CC
tVCHWL
RB
tEHRL
AI05274
Table 12. Write AC Characteristics, Chip Enable Controlled
M29F016D
Symbol
Alt
Parameter
Unit
55
55
0
70/ 90
t
t
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
WC
t
t
WLEL
WS
t
t
45
45
0
45
45
0
ELEH
CP
DS
DH
t
t
DVEH
t
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
Program/Erase Valid to RB Low
EHDX
t
t
WH
0
0
EHWH
t
t
20
0
20
0
EHEL
CPH
t
t
AS
AVEL
t
t
AH
45
0
45
0
ELAX
t
GHEL
t
t
0
0
EHGL
OEH
(1)
t
30
50
30
t
BUSY
EHRL
t
t
V
CC
High to Write Enable Low
Min
50
µs
VCHWL
VCS
Note: 1. Sampled only, not 100% tested.
21/37
M29F016D
Figure 13. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPHPHH
tPLPX
RP
tPLYH
AI02931B
Table 13. Reset/Block Temporary Unprotect AC Characteristics
M29F016D
Symbol
Alt
Parameter
Unit
55
70/ 90
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
t
Min
Min
50
50
0
ns
PHEL
RH
(1)
t
PHGL
(1)
(1)
(1)
t
t
RHWL
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
0
ns
t
RB
RHEL
RHGL
t
t
RP Pulse Width
Min
Max
Min
500
10
500
10
ns
µs
ns
PLPX
(1)
RP
t
RP Low to Read Mode
t
READY
PLYH
(1)
t
RP Rise Time to V
500
500
t
VIDR
ID
PHPHH
Note: 1. Sampled only, not 100% tested.
22/37
M29F016D
PACKAGE MECHANICAL
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
20.200
18.500
10.100
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
0.3976
–
A
A1
A2
B
0.050
0.950
0.170
0.100
19.800
18.300
9.900
–
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
0.3898
–
C
D
D1
E
e
0.500
0.0197
L
0.500
0°
0.700
5°
0.0197
0°
0.0276
5°
α
N
40
40
CP
0.100
0.0039
23/37
M29F016D
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
b
e
CP
D
N
E
EH
1
A1
α
L
SO-d
Note: Drawing is not to scale.
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
2.80
0.1102
0.10
2.20
0.35
0.10
0.0039
0.0866
0.0138
0.0039
2.30
0.40
0.15
2.40
0.50
0.20
0.08
13.50
28.40
–
0.0906
0.0157
0.0059
0.0945
0.0197
0.0079
0.0030
0.5315
1.1181
–
C
CP
E
13.30
28.20
1.27
13.20
28.00
–
0.5236
1.1102
0.0500
0.6299
0.0315
0.5197
1.1024
–
D
e
HE
L
16.00
0.80
15.75
16.25
0.6201
0.6398
N
44
44
α
8
8
24/37
M29F016D
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M29F016D
55
N
1
T
Device Type
M29
Operating Voltage
F = V = 5V ± 10%
CC
Device Function
016D = 16 Mbit (2Mb x8), Uniform Block
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Package
N = TSOP40: 10 x 20 mm
M = SO44
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
25/37
M29F016D
APPENDIX A. BLOCK ADDRESS TABLE
Table 15. Block Addresses, M29F016D
Size,
#
Address Range
Protection Group
KByte
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
1F0000h-1FFFFFh
1E0000h-1EFFFFh
1D0000h-1DFFFFh
1C0000h-1CFFFFh
1B0000h-1BFFFFh
1A0000h-1AFFFFh
190000h-19FFFFh
180000h-18FFFFh
170000h-17FFFFh
160000h-16FFFFh
150000h-15FFFFh
140000h-14FFFFh
130000h-13FFFFh
120000h-12FFFFh
110000h-11FFFFh
100000h-10FFFFh
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
26/37
M29F016D
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
is read from the memory. Tables 16, 17, 18, 19, 20
and 21 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 21, Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read
command to return to Read mode.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
Table 16. Query Structure Overview
Address
10h
Sub-section Name
CFI Query Identification String
System Interface Information
Device Geometry Definition
Description
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
1Bh
27h
Primary Algorithm-specific Extended Query
table
Additional information specific to the Primary
Algorithm (optional)
40h
61h
Security Code Area
64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 17. CFI Query Identification String
Address
10h
Data
51h
52h
59h
02h
00h
40h
00h
00h
00h
00h
00h
Description
Value
"Q"
11h
Query Unique ASCII String "QRY"
"R"
12h
"Y"
13h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code
defining a specific algorithm
AMD
Compatible
14h
15h
Address for Primary Algorithm extended Query table (see Table 19)
P = 40h
NA
16h
17h
Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported
18h
19h
Address for Alternate Algorithm extended Query table
NA
1Ah
27/37
M29F016D
Table 18. CFI Query System Interface Information
Address
Data
Description
Value
V
V
V
Logic Supply Minimum Program/Erase voltage
CC
1Bh
45h
4.5V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
Logic Supply Maximum Program/Erase voltage
CC
1Ch
55h
5.5V
bit 7 to 4
bit 3 to 0
BCD value in volts
BCD value in 100 mV
[Programming] Supply Minimum Program/Erase voltage
PP
1Dh
1Eh
00h
00h
NA
NA
00h not supported
V
[Programming] Supply Maximum Program/Erase voltage
PP
00h not supported
n
1Fh
20h
21h
22h
23h
24h
25h
26h
04h
00h
0Ah
00h
04h
00h
03h
00h
16µs
NA
Typical timeout per single byte program = 2 µs
n
Typical timeout for minimum size write buffer program = 2 µs
n
1s
Typical timeout per individual block erase = 2 ms
n
see note (1)
256µs
NA
Typical timeout for full chip erase = 2 ms
n
Maximum timeout for byte program = 2 times typical
n
Maximum timeout for write buffer program = 2 times typical
n
8s
Maximum timeout per individual block erase = 2 times typical
n
see note (1)
Maximum timeout for chip erase = 2 times typical
Note: 1. Not supported in the CFI
28/37
M29F016D
Table 19. Device Geometry Definition
Address
Data
Description
Value
n
27h
15h
2 MByte
Device Size = 2 in number of bytes
28h
29h
00h
00h
x8 only
Async.
Flash Device Interface Code description
2Ah
2Bh
00h
00h
n
NA
1
Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.
2Ch
01h
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.
2Dh
2Eh
1Fh
00h
Region 1 Information
Number of identical size erase block = 001Fh+1
32
2Fh
30h
00h
01h
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
64 Kbyte
29/37
M29F016D
Table 20. Primary Algorithm-Specific Extended Query Table
Address
40h
Data
50h
52h
49h
31h
30h
00h
Description
Value
"P"
"R"
"I"
41h
Primary Algorithm extended Query table unique ASCII string “PRI”
42h
43h
Major version number, ASCII
Minor version number, ASCII
"1"
44h
"0"
45h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Yes
Silicon Revision Number (bits 7 to 2)
46h
47h
48h
49h
02h
04h
01h
04h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
4
Block Protection
00 = not supported, x = number of blocks per group
Temporary Block Unprotect
00 = not supported, 01 = supported
yes
4
Block Protect /Unprotect
04 = M29W400B mode
4Ah
4Bh
4Ch
00h
00h
00h
Simultaneous Operations, 00 = not supported
No
No
No
Burst Mode, 00 = not supported, 01 = supported
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
Table 21. Security Code Area
Address
61h
Data
XX
XX
XX
XX
XX
XX
XX
XX
Description
62h
63h
64h
64 bit: unique device number
65h
66h
67h
68h
30/37
M29F016D
APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the memo-
ry. The blocks are protected in groups, refer to
Appendix A, Table 15 for details of the Protection
Groups. Once protected, Program and Erase op-
erations within the protected group fail to change
the data.
Programmer Technique Bus Operations, gives a
summary of each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
To protect the Extended Block issue the Enter Ex-
tended Block command and then use either the
Programmer or In-System technique. Once pro-
tected issue the Exit Extended Block command to
return to read mode. The Extended Block protec-
tion is irreversible, once protected the protection
cannot be undone.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the memory has been fitted to the sys-
tem.
To protect a group of blocks follow the flowchart in
Figure 16, In-System Block Protect Flowchart. To
unprotect the whole chip it is necessary to protect
all of the groups first, then all the groups can be
unprotected at the same time. To unprotect the
chip follow Figure 17, In-System Chip Unprotect
Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Programmer Technique
The Programmer technique uses high (V ) volt-
ID
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a group of blocks follow the flowchart in
Figure 14, Programmer Equipment Block Protect
Flowchart. To unprotect the whole chip it is neces-
sary to protect all of the groups first, then all
groups can be unprotected at the same time. To
unprotect the chip follow Figure 15, Programmer
Equipment Chip Unprotect Flowchart. Table 22,
Table 22. Programmer Technique Bus Operations, BYTE = V or V
IH
IL
Address Inputs
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
E
G
W
A0-A20
Block (Group)
A9 = V , A12-A20 Block Address
ID
V
V
V
V
Pulse
Pulse
X
X
IL
ID
ID
IL
IL
(1)
Others = X
Protect
A9 = V , A12 = V , A15 = V
ID
IH
IH
V
ID
V
Chip Unprotect
Others = X
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IL
ID
Block (Group)
Protection Verify
Pass = XX01h
Retry = XX00h
V
V
V
V
A12-A20 Block Address
Others = X
IL
IL
IL
IL
IH
IH
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IH
ID
Block (Group)
Unprotection Verify
Retry = XX01h
Pass = XX00h
V
V
A12-A20 Block Address
Others = X
Note: 1. Block Protection Groups are shown in Appendix A, Table 15.
31/37
M29F016D
Figure 14. Programmer Equipment Group Protect Flowchart
START
ADDRESS = GROUP ADDRESS
W = V
IH
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
E, G = V
,
IH
A0, A6 = V
A1 = V
,
IL
IH
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
Read DATA
DATA
=
01h
NO
YES
++n
= 25
NO
A9 = V
IH
E, G = V
IH
YES
PASS
A9 = V
E, G = V
IH
IH
AI05574
FAIL
Note: Block Protection Groups are shown in Appendix A, Table 15.
32/37
M29F016D
Figure 15. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL GROUPS
n = 0
CURRENT GROUP = 0
(1)
A6, A12, A15 = V
IH
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
ADDRESS = CURRENT GROUP ADDRESS
A0 = V , A1, A6 = V
IL
IH
E = V
IL
Wait 4µs
G = V
IL
INCREMENT
CURRENT GROUP
Wait 60ns
Read DATA
NO
YES
DATA
=
00h
LAST
GROUP
NO
NO
++n
= 1000
YES
YES
A9 = V
A9 = V
E, G = V
IH
IH
E, G = V
IH
IH
FAIL
PASS
AI05575
Note: Block Protection Groups are shown in Appendix A, Table 15.
33/37
M29F016D
Figure 16. In-System Equipment Group Protect Flowchart
START
n = 0
RP = V
ID
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
Wait 100µs
WRITE 40h
IL
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
DATA
NO
=
01h
YES
RP = V
++n
= 25
NO
IH
YES
RP = V
ISSUE READ/RESET
COMMAND
IH
PASS
ISSUE READ/RESET
COMMAND
FAIL
AI05576
Note: Block Protection Groups are shown in Appendix A, Table 15.
34/37
M29F016D
Figure 17. In-System Equipment Chip Unprotect Flowchart
START
PROTECT ALL GROUPS
n = 0
CURRENT GROUP = 0
RP = V
ID
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
IH
IH
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
Wait 10ms
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
Wait 4µs
INCREMENT
CURRENT GROUP
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
DATA
NO
YES
=
00h
++n
= 1000
NO
NO
LAST
GROUP
YES
RP = V
YES
RP = V
IH
IH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PASS
FAIL
AI05577
Note: Block Protection Groups are shown in Appendix A, Table 15.
35/37
M29F016D
REVISION HISTORY
Table 23. Document Revision History
Date
Version
Revision Details
22-Jun-2001
-01
First Issue
90ns Speed Class added, Block Protection Appendix added, SO44 drawing and package
mechanical data updated, CFI Table 22, address 2Fh data clarified, Read/Reset
operation during Erase Suspend clarified .
03-Dec-2001
05-Apr-2002
-02
-03
Description of Ready/Busy signal clarified (and Figure 13 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
Document promoted to full datasheet. No paragraphs, parameters or illustrations
changed. Revision numbering modified: a minor revision is indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot (revision
version 03 equals 3.0)
15-Jul-2003
3.1
36/37
M29F016D
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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