M29W008AT90N5TR_技术文档

M29W008AT

M29W008AB

8 Mbit (1Mb x8, Boot Block)

Low Voltage Single Supply Flash Memory

■ 2.7V to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ ACCESS TIME: 80ns

■ PROGRAMMING TIME: 10µs typical

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte

– Status Register bits and Ready/Busy Output

■ SECURITY PROTECTION MEMORY AREA

■ INSTRUCTIONS ADDRESS CODING: 3 digits

■ MEMORY BLOCKS

TSOP40 (N)

10 x 20mm

– Boot Block (Top or Bottom location)

– Parameter and Main blocks

■ BLOCK, MULTI-BLOCK and CHIP ERASE

■ MULTI BLOCK PROTECTION/TEMPORARY

UNPROTECTION MODES

Figure 1. Logic Diagram

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

V

■ LOW POWER CONSUMPTION

CC

– Stand-by and Automatic Stand-by

■ 100,000 PROGRAM/ERASE CYCLES per

20

8

BLOCK

A0-A19

DQ0-DQ7

RB

■ 20 YEARS DATA RETENTION

– Defectivity below 1ppm/year

W

E

M29W008AT

M29W008AB

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

G

– Top Device Code, M29W008AT: D2h

– Bottom Device Code, M29W008AB: DCh

RP

V

SS

AI02716

March 2000

1/30

M29W008AT, M29W008AB

Figure 2. TSOP Connections

Table 1. Signal Names

A0-A19

Address Inputs

A16

A15

A14

A13

A12

A11

A9

1

40

A17

DQ0-DQ7

Data Input/Outputs, Command Inputs

Chip Enable

V

SS

NC

E

A19

A10

DQ7

DQ6

DQ5

DQ4

G

Output Enable

W

RP

RB

Write Enable

A8

Reset/Block Temporary Unprotect

Ready/Busy Output

Supply Voltage

W

RP

NC

RB

A18

A7

10 M29W008AT 31

V

CC

M29W008AB

11

30

CC

V

CC

NC

DQ3

DQ2

DQ1

DQ0

G

V

SS

Ground

NC

Not Connected Internally

A6

A5

A4

Organisation

A3

V

E

SS

The M29W008A is organised as 1Mb x8. The

memory uses the address inputs A0-A19 and the

Data Input/Outputs DQ0-DQ7. Memory control is

provided by Chip Enable E, Output Enable G and

Write Enable W inputs.

A2

A1

20

21

A0

AI02717

A Reset/Block Temporary Unprotection RP tri-lev-

el input provides a hardware reset when pulled

Low, and when held High (at V ) temporarily un-

DESCRIPTION

ID

protects blocks previously protected allowing them

to be programed and erased. Erase and Program

operations are controlled by an internal Program/

Erase Controller (P/E.C.). Status Register data

output on DQ7 provides a Data Polling signal, and

DQ6 and DQ2 provide Toggle signals to indicate

the state of the P/E.C operations. A Ready/Busy

RB output indicates the completion of the internal

algorithms.

The M29W008A is a non-volatile memory that may

be erased electrically at the block or chip level and

programmed in-system on a Byte-by-Byte basis

using only a single 2.7V to 3.6V V

supply. For

CC

Program and Erase operations the necessary high

voltages are generated internally. The device can

also be programmed in standard programmers.

The array matrix organisation allows each block to

be erased and reprogrammed without affecting

other blocks. Blocks can be protected against pro-

graming and erase on programming equipment,

and temporarily unprotected to make changes in

the application. Each block can be programmed

and erased over 100,000 cycles.

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature or Block Protection

status, Programming, Block and Chip Erase,

Erase Suspend and Resume are written to the de-

vice in cycles of commands to a Command Inter-

face using standard microprocessor write timings.

The device is offered in TSOP40 (10 x 20mm)

package.

Memory Blocks

The devices feature asymmetrically blocked archi-

tecture providing system memory integration. Both

M29W008AT and M29W008AB devices have an

array of 19 blocks, one Boot Block of 16 Kbytes,

two Parameter Blocks of 8 Kbytes, one Main Block

of 32 Kbytes and fifteen Main Blocks of 64 Kbytes.

The M29W008AT has the Boot Block at the top of

the memory address space and the M29W008AB

locates the Boot Block starting at the bottom. The

memory maps are showed in Tables 3, 4. Each

block can be erased separately, any combination

of blocks can be specified for multi-block erase or

the entire chip may be erased. The Erase opera-

tions are managed automatically by the P/E.C.

2/30

M29W008AT, M29W008AB

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

(3)

T

–40 to 85

–50 to 125

–65 to 150

–0.6 to 5

A

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

T

BIAS

T

STG

(2)

Input or Output Voltage

Supply Voltage

V

IO

V

–0.6 to 5

V

CC

(A9, E, G, RP)

(2)

A9, E, G, RP Voltage

–0.6 to 13.5

V

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

3. Depends on range.

The block erase operation can be suspended in

order to read from or program to any block not be-

ing erased, and then resumed.

Block protection provides additional data security.

Each block can be separately protected or unpro-

tected against Program or Erase on programming

equipment. All previously protected blocks can be

temporarily unprotected in the application.

Instructions

Seven instructions are defined to perform Read

Array, Auto Select (to read the Electronic Signa-

ture or Block Protection Status), Program, Block

Erase, Chip Erase, Erase Suspend and Erase Re-

sume. The internal P/E.C. automatically handles

all timing and verification of the Program and

Erase operations. The Status Register Data Poll-

ing, Toggle, Error bits and the RB output may be

read at any time, during programming or erase, to

monitor the progress of the operation.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

Command Interface which is common to all in-

structions (see Table 9). The third cycle inputs the

instruction set-up command. Subsequent cycles

output the addressed data, Electronic Signature or

Block Protection Status for Read operations. In or-

der to give additional data protection, the instruc-

tions for Program and Block or Chip Erase require

further command inputs. For a Program instruc-

tion, the fourth command cycle inputs the address

and data to be programmed. For an Erase instruc-

tion (Block or Chip), the fourth and fifth cycles in-

put a further Coded sequence before the Erase

confirm command on the sixth cycle. Erasure of a

memory block may be suspended, in order to read

data from another block or to program data in an-

other block, and then resumed.

Bus Operations

The following operations can be performed using

the appropriate bus cycles: Read (Array, Electron-

ic Signature, Block Protection Status), Write com-

mand, Output Disable, Stand-by, Reset, Block

Protection, Unprotection, Protection Verify, Unpro-

tection Verify and Block Temporary Unprotection.

See Tables 5 and 6.

Command Interface

Instructions, made up of commands written in cy-

cles, can be given to the Program/Erase Controller

through a Command Interface (C.I.). For added

data protection, program or erase execution starts

after 4 or 6 cycles. The first, second, fourth and

fifth cycles are used to input Coded cycles to the

C.I. This Coded sequence is the same for all Pro-

gram/Erase Controller instructions. The ’Com-

mand’ itself and its confirmation, when applicable,

are given on the third, fourth or sixth cycles. Any

incorrect command or any improper command se-

quence will reset the device to Read Array mode.

When power is first applied or if V falls below V

CC

L-

, the command interface is reset to Read Array.

KO

3/30

M29W008AT, M29W008AB

Table 3. Top Boot Block Addresses,

M29W008AT

Table 4. Bottom Boot Block Addresses,

M29W008AB

Size

#

Address Range

#

Address Range

(Kbytes)

16

8

(Kbytes)

64

32

8

18

17

16

15

14

13

12

11

10

9

FC000h-FFFFFh

FA000h-FBFFFh

F8000h-F9FFFh

F0000h-F7FFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

18

17

16

15

14

13

12

11

10

9

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

08000h-0FFFFh

06000h-07FFFh

04000h-05FFFh

00000h-03FFFh

8

32

64

8

7

6

5

4

3

2

1

8

0

16

4/30

M29W008AT, M29W008AB

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A19). The address inputs

for the memory array are latched during a write op-

eration on the falling edge of Chip Enable E or

Ready/Busy Output (RB). Ready/Busy is an

open-drain output and gives the internal state of

the P/E.C. of the device. When RB is Low, the de-

vice is Busy with a Program or Erase operation

and it will not accept any additional program or

erase instructions except the Erase Suspend in-

struction.

When RB is High, the device is ready for any

Read, Program or Erase operation. The RB will

also be High when the memory is put in Erase

Suspend or Stand-by modes.

Write Enable W. When A9 is raised to V , either a

ID

Read Electronic Signature Manufacturer or Device

Code, Block Protection Status or a Write Block

Protection or Block Unprotection is enabled de-

pending on the combination of levels on A0, A1

A6, A12 and A15.

Reset/Block Temporary Unprotect Input (RP).

Data Input/Outputs (DQ0-DQ7). The input is

data to be programmed in the memory array or a

command to be written to the C.I. Both are latched

on the rising edge of Chip Enable E or Write En-

able W. The output is data from the Memory Array,

the Electronic Signature Manufacturer or Device

codes, the Block Protection Status or the Status

register Data Polling bit DQ7, the Toggle Bits DQ6

and DQ2, the Error bit DQ5 or the Erase Timer bit

DQ3. Outputs are valid when Chip Enable E and

Output Enable G are active. The output is high im-

pedance when the chip is deselected or the out-

puts are disabled and when RP is at a Low level.

The RP Input provides hardware reset and pro-

tected block(s) temporary unprotection functions.

Reset of the memory is achieved by pulling RP to

V

for at least t

. When the reset pulse is giv-

IL

PLPX

en, if the memory is in Read or Stand-by modes, it

will be available for new operations in t

the rising edge of RP.

after

PHEL

If the memory is in Erase, Erase Suspend or Pro-

gram modes the reset will take t during which

PLYH

the RB signal will be held at V . The end of the

IL

memory reset will be indicated by the rising edge

of RB. A hardware reset during an Erase or Pro-

gram operation will corrupt the data being pro-

grammed or the sector(s) being erased. See

Tables 15, 16 and Figure 8.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. E High deselects the

memory and reduces the power consumption to

the stand-by level. E can also be used to control

writing to the command register and to the memo-

ry array, while W remains at a low level. The Chip

Temporary block unprotection is made by holding

RP at V . In this condition previously protected

ID

blocks can be programmed or erased. The transi-

tion of RP from V to V must slower than t

IH

ID

PH-

Enable must be forced to V during the Block Un-

ID

. (See Tables 17, 18 and Figure 8). When RP

PHH

protection operation.

is returned from V to V all blocks temporarily

ID

IH

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

eration. When G is High the outputs are High im-

unprotected will be again protected.

V

Supply Voltage. The power supply for all

CC

operations (Read, Program and Erase).

pedance. G must be forced to V level during

ID

V

Ground. V is the reference for all voltage

SS

Block Protection and Unprotection operations.

measurements.

Write Enable (W). This input controls writing to

the Command Register and Address and Data

latches.

5/30

M29W008AT, M29W008AB

DEVICE OPERATIONS

See Tables 5, 6 and 7.

Block Protection. Each block can be separately

protected against Program or Erase on program-

ming equipment. Block protection provides addi-

tional data security, as it disables all program or

erase operations. This mode is activated when

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register or the Block Protection

Status. Both Chip Enable E and Output Enable G

must be low in order to read the output of the mem-

ory. A new read operation is initiated either on the

falling edge of Chip, Enable E, or on any address

both A9 and G are raised to V and an address in

ID

the block is applied on A13-A19. Block protection

is initiated on the edge of W falling to V . Then af-

IL

ter a delay of 100µs, the edge of W rising to V

IH

ends the protection operations. Block protection

verify is achieved by bringing G, E, A0 and A6 to

transition with E at V .

IL

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch input

data to be programmed. A write operation is initi-

ated when Chip Enable E is Low and Write Enable

W is Low with Output Enable G High. Addresses

are latched on the falling edge of W or E whichever

occurs last. Commands and Input Data are

latched on the rising edge of W or E whichever oc-

curs first.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is High with

Write Enable W High.

Stand-by. The memory is in stand-by when Chip

Enable E is High and the P/E.C. is idle. The power

consumption is reduced to the stand-by level and

the outputs are high impedance, independent of

the Output Enable G or Write Enable W inputs.

V

and A1 to V , while W is at V and A9 at V .

IH IH ID

IL

Under these conditions, reading the data output

will yield 01h if the block defined by the inputs on

A13-A19 is protected. Any attempt to program or

erase a protected block will be ignored by the de-

vice.

Block Temporary Unprotection. Any previously

protected block can be temporarily unprotected in

order to change stored data. The temporary un-

protection mode is activated by bringing RP to V .

ID

During the temporary unprotection mode the pre-

viously protected blocks are unprotected. A block

can be selected and data can be modified by exe-

cuting the Erase or Program instruction with the

RP signal held at V . When RP is returned to V ,

all the previously protected blocks are again pro-

tected.

ID

IH

Block Unprotection. All protected blocks can be

unprotected on programming equipment to allow

updating of bit contents. All blocks must first be

protected before the unprotection operation. Block

unprotection is activated when A9, G and E are at

Automatic Stand-by. After 150ns of bus inactivi-

ty (no address transition, E = V ) and when CMOS

IL

levels are driving the addresses, the chip automat-

ically enters a pseudo-stand-by mode where con-

sumption is reduced to the CMOS stand-by value,

V

and A12, A15 at V . Unprotection is initiated

while outputs still drive the bus (if G = V ).

ID

IH

IL

by the edge of W falling to V . After a delay of

IL

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory. The manufacturer’s code for STMicro-

electronics is 20h, the device code is D2h for the

M29W008AT (Top Boot) and DCh for the

M29W008AB (Bottom Boot). These codes allow

programming equipment or applications to auto-

matically match their interface to the characteris-

tics of the M29W008A. The Electronic Signature is

output by a Read operation when the voltage ap-

10ms, the unprotection operation will end. Unpro-

tection verify is achieved by bringing G and E to

V

while A0 is at V , A6 and A1 are at V and A9

IL

IL IH

remains at V . In these conditions, reading the

ID

output data will yield 00h if the block defined by the

inputs A13-A19 has been successfully unprotect-

ed. Each block must be separately verified by giv-

ing its address in order to ensure that it has been

unprotected.

plied to A9 is at V and address inputs A1 is Low.

ID

The manufacturer code is output when the Ad-

dress input A0 is Low and the device code when

this input is High. Other Address inputs are ig-

nored. The Electronic Signature can also be read,

without raising A9 to V , by giving the memory the

ID

Instruction AS.

6/30

M29W008AT, M29W008AB

(1)

Table 5. User Bus Operations

Operation

Read Byte

Write Byte

Output Disable

Stand-by

E

G

W

RP

A0

X

A1

X

A6

X

A9

X

A12

X

A15

X

DQ0-DQ7

Data Output

Data Input

Hi-Z

V

IH

V

IL

IH

V

IL

IH

V

IH

V

X

Hi-Z

IH

V

Reset

X

Hi-Z

IL

Block

V

Pulse

V

X

IL

ID

IL

IH

ID

(2,4)

Protection

Blocks

V

ID

Pulse

V

IH

V

IH

ID

IL

IH

ID

(4)

Unprotection

Block

Protection

Protect

V

A12

X

A15

X

IL

IH

IL

IH

IL

ID

(2,4)

(3)

Verify

Status

Block

Protect

Unprotection

V

IH

V

IH

V

IL

IH

IL

IH

ID

(2,4)

(3)

Verify

Status

Block

Temporary

Unprotection

V

X

ID

Note: 1. X = V or V

.

IH

IL

2. Block Address must be given an A13-A19 bits.

3. See Table 7.

4. Operation performed on programming equipment.

Table 6. Read Electronic Signature (following AS instruction or with A9 = V )

ID

Other

Addresses

Code

Device

E

G

W

A0

A1

DQ0-DQ7

V

IL

V

IL

V

IH

V

IL

V

IL

Manufact. Code

Don’t Care

20h

Table 7. Read Block Protection with AS Instruction

Other

Addresses

Code

E

G

W

A0

A1

A13-A19

DQ0-DQ7

V

Protected Block

Block Address

Don’t Care

01h

00h

IL

IH

IL

IH

V

IL

V

IL

V

IH

Unprotected Block

7/30

M29W008AT, M29W008AB

INSTRUCTIONS AND COMMANDS

'1' at the start of the Erase Suspend. In order to

monitor DQ7 in the Erase Suspend mode an ad-

dress within a block being erased must be provid-

ed. For a Read Operation in Erase Suspend

mode, DQ7 will output '1' if the read is attempted

on a block being erased and the data value on oth-

er blocks. During Program operation in Erase Sus-

pend Mode, DQ7 will have the same behavior as

in the normal program execution outside of the

suspend mode.

Toggle Bit (DQ6). When Programming or Eras-

ing operations are in progress, successive at-

tempts to read DQ6 will output complementary

data. DQ6 will toggle following toggling of either G,

or E when G is low. The operation is completed

when two successive reads yield the same output

data. The next read will output the bit last pro-

grammed or a '1' after erasing. The toggle bit DQ6

is valid only during P/E.C. operations, that is after

the fourth W pulse for programming or after the

sixth W pulse for Erase. If the blocks selected for

erasure are protected, DQ6 will toggle for about

100µs and then return back to Read. DQ6 will be

set to '1' if a Read operation is attempted on an

Erase Suspend block. When erase is suspended

DQ6 will toggle during programming operations in

a block different to the block in Erase Suspend. Ei-

ther E or G toggling will cause DQ6 to toggle. See

Figure 11 for Toggle Bit flowchart and Figure 12

for Toggle Bit waveforms.

The Command Interface latches commands writ-

ten to the memory. Instructions are made up from

one or more commands to perform Read Memory

Array, Read Electronic Signature, Read Block Pro-

tection, Program, Block Erase, Chip Erase, Erase

Suspend and Erase Resume. Commands are

made of address and data sequences. The in-

structions require from 1 to 6 cycles, the first or first

three of which are always write operations used to

initiate the instruction. They are followed by either

further write cycles to confirm the first command or

execute the command immediately. Command se-

quencing must be followed exactly. Any invalid

combination of commands will reset the device to

Read Array. The increased number of cycles has

been chosen to assure maximum data security. In-

structions are initialised by two initial Coded cycles

which unlock the Command Interface. In addition,

for Erase, instruction confirmation is again preced-

ed by the two Coded cycles.

Status Register Bits

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mand execution will automatically output these

five Status Register bits. The P/E.C. automatically

sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other

bits (DQ0, DQ1 and DQ4) are reserved for future

use and should be masked. See Tables 10 and 11.

Table 8. Commands

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputs a ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programming or

after the sixth W pulse for erase. It must be per-

formed at the address being programmed or at an

address within the block being erased. If all the

blocks selected for erasure are protected, DQ7 will

be set to '0' for about 100µs, and then return to the

previous addressed memory data value. See Fig-

ure 10 for the Data Polling flowchart and Figure 9

for the Data Polling waveforms. DQ7 will also flag

the Erase Suspend mode by switching from '0' to

Hex Code

00h

Command

Invalid/Reserved

10h

Chip Erase Confirm

Reserved

20h

30h

Block Erase Resume/Confirm

Set-up Erase

80h

Read Electronic Signature/

Block Protection Status

90h

A0h

B0h

F0h

Program

Erase Suspend

Read Array/Reset

8/30

M29W008AT, M29W008AB

(1)

Table 9. Instructions

Mne.

Instr.

Cyc.

1st Cyc.

X

2nd Cyc.

3rd Cyc.

4th Cyc.

5th Cyc.

6th Cyc.

7th Cyc.

(3,7)

Addr.

Data

1+

3+

Read Memory Array until a new write cycle is initiated.

F0h

Read/Reset

Memory Array

(2,4)

RD

555h

AAh

555h

AAh

2AAh

55h

555h

F0h

Addr.

Data

Read Memory Array until a new write cycle is

initiated.

Read Electronic Signature or Block Protection

Status until a new write cycle is initiated. See Note 5

and 6.

2AAh

55h

555h

90h

Addr.

Data

(4)

Auto Select

Program

AS

Program

Address

(3,7)

555h

AAh

2AAh

55h

555h

A0h

Addr.

Data

Read Data Polling or Toggle Bit until

Program completes.

PG

4

Program

Data

Additional

Block

Address

(3,7)

6

555h

2AAh

555h

2AAh

Addr.

Data

(8)

Block

BE

CE

Block Erase

AAh

555h

AAh

X

55h

2AAh

55h

80h

555h

80h

AAh

555h

AAh

55h

2AAh

55h

30h

555h

10h

30h

Addr.

Data

Chip Erase

Note 9

(3,7)

Addr.

Data

Read until Toggle stops, then read all the data needed from any Block(s) not

being erased then Resume Erase.

(10)

Erase Suspend

Erase Resume

1

ES

B0h

X

Addr.

Data

Read Data Polling or Toggle Bits until Erase completes or Erase is suspended

another time.

ER

30h

Note: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of t is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new

PLYH

operation (see Tables 15, 16 and Figure 9).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-

mand cycles.

5. Signature Address bits A0, A1, at V will output Manufacturer code (20h). Address bits A0 at V and A1, at V will output Device

IL

IH

IL

code.

6. Block Protection Address: A0, at V , A1 at V and A13-A19 within the Block will output the Block Protection status.

IL

IH

7. For Coded cycles address inputs A15-A19 are don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout statuscan be

verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit

until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

9/30

M29W008AT, M29W008AB

Table 10. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase block

in Erase Suspend

’1’

’0’

Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits DQ5 for program or Erase

Success.

Erase On-going

Data

Polling

7

Program Complete or data of

non erase block during Erase

Suspend

DQ

Program On-going

’-1-0-1-0-1-0-1-’ Erase or Program On-going

Successive reads output complementary

data on DQ6 while Programming or Erase

operations are on-going. DQ6 remains at

constant level when P/E.C. operations are

completed or Erase Suspend is

DQ

Program Complete

6

Toggle Bit

Erase Complete or Erase

’-1-1-1-1-1-1-1-’ Suspend on currently

addressed block

acknowledged.

’1’

’0’

Program or Erase Error

This bit is set to ‘1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started. Only

possible command entry is Erase Suspend

(ES).

’1’

’0’

Erase Timeout Period Expired

Erase Timeout Period On-going

Erase

Time Bit

3

An additional block to be erased in parallel

can be entered to the P/E.C.

Chip Erase, Erase or Erase

Suspend on the currently

addressed block.

’-1-0-1-0-1-0-1-’

Erase Error due to the currently

addressed block

(when DQ5 = ‘1’).

Indicates the erase status and allows to

identify the erased block.

2

1

Toggle Bit

Program on-going, Erase on-

going on another block or

Erase Complete

1

Erase Suspend read on non

Erase Suspend block

DQ

Reserved

0

Note:

Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

10/30

M29W008AT, M29W008AB

Table 11. Polling and Toggle Bits

confirmation command. The Coded cycles consist

of writing the data AAh at address 555h during the

first cycle. During the second cycle the Coded cy-

cles consist of writing the data 55h at address

2AAh. A0 to A11 are valid, other address lines are

’don’t care’. The Coded cycles happen on first and

second cycles of the command write or on the

fourth and fifth cycles.

Mode

DQ7

0

DQ6

DQ2

Program

Erase

Toggle

1

Toggle Note 1

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

Instructions

See Table 9.

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

N/A

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

command F0h. It can be optionally preceded by

the two Coded cycles. Subsequent read opera-

tions will read the memory array addressed and

output the data read. A wait state of 10µs is nec-

essary after Read/Reset prior to any valid read if

the memory was in an Erase mode when the RD

instruction is given. The Read/Reset command is

not accepted during Erase and Erase Suspend.

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command 90h to address 555h for

command set-up. A subsequent read will output

the manufacturer code and the device code or the

block protection status depending on the levels of

A0 and A1. The manufacturer code, 20h, is output

when the addresses lines A0 and A1 are Low, the

device code, EAh for Top Boot, EBh for Bottom

Boot is output when A0 is High with A1 Low.

The AS instruction also allows access to the block

protection status. After giving the AS instruction,

A0 and A6 are set to V with A1 at V , while A13-

A19 define the address of the block to be verified.

A read in these conditions will output a 01h if the

block is protected and a 00h if the block is not pro-

tected.

Program (PG) Instruction. This instruction uses

four write cycles. The Program command A0h is

written to address 555h on the third cycle after two

Coded cycles. A fourth write operation latches the

Address on the falling edge of W or E and the Data

to be written on the rising edge and starts the P/

E.C. Read operations output the Status Register

bits after the programming has started. Memory

programming is made only by writing '0' in place of

'1'. Status bits DQ6 and DQ7 determine if pro-

gramming is on-going and DQ5 allows verification

of any possible error. Programming at an address

not in blocks being erased is also possible during

erase suspend. In this case, DQ2 will toggle at the

address being programmed.

Erase Suspend Program

Toggle

Note: 1. Toggle if the address is within a block being erased.

’1’ if the address is within a block not being erased.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

during the Erase operations. It can also be used to

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to '1' during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to '1' dur-

ing program operation and when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to '1', DQ2 will toggle if the faulty block

is addressed.

Error Bit (DQ5). This bit is set to '1' by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

the memory block. In case of an error in block

erase or program, the block in which the error oc-

curred or to which the programmed data belongs,

must be discarded. The DQ5 failure condition will

also appear if a user tries to program a '1' to a lo-

cation that is previously programmed to '0'. Other

Blocks may still be used. The error bit resets after

a Read/Reset (RD) instruction. In case of success

of Program or Erase, the error bit will be set to '0'.

IL

IH

Erase Timer Bit (DQ3). This bit is set to '0' by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 50µs to 90µs, DQ3 returns

to '1'.

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. They are followed by an input command or a

11/30

M29W008AT, M29W008AB

Table 12. AC Measurement Conditions

Figure 4. AC Testing Load Circuit

Input Rise and Fall Times

≤10ns

0.8V

Input Pulse Voltages

0 to 3V

1.5V

Input and Output Timing Ref. Voltages

1N914

Figure 3. AC Testing Input Output Waveform

3.3kΩ

DEVICE

UNDER

TEST

OUT

= 30pF or 100pF

3V

C

L

1.5V

0V

AI01417

C

includes JIG capacitance

L

AI01968

(1)

Table 13. Capacitance

Symbol

(T = 25 °C, f = 1 MHz)

A

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: Sampled only, not 100% tested.

Table 14. DC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C; V = 2.7V to 3.6V)

A

CC

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Supply Current (Stand-by)

Test Condition

Min

Max

±1

Unit

Typ.

I

0V ≤ V ≤ V

µA

LI

IN

CC

I

LO

0V ≤ V

≤ V

OUT CC

±1

I

E = V , G = V , f = 6MHz

IL IH

3

10

mA

µA

CC1

I

E = V , G = V , f = 6MHz

IL IL

4.5

30

100

CC2

I

E = V ±0.2V

CC3

CC

Supply Current

(Program or Erase)

Byte program, Block or

Chip Erase in progress

(1)

20

mA

I

CC4

V

Input Low Voltage

–0.5

0.8

V

IL

V

0.7 V

V

+ 0.3

Input High Voltage

IH

CC

I

OL

= 1.8mA

Output Low Voltage

0.45

V

OL

V

I

= –100µA

V

–0.4V

CC

Output High Voltage CMOS

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

V

OH

V

11.5

12.5

100

V

ID

I

A9 = V

30

µA

ID

Supply Voltage (Erase and

Program lock-out)

(1)

2.0

2.3

V

LKO

Note: 1. Sampled only, not 100% tested.

12/30

M29W008AT, M29W008AB

Table 15. Read AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

80

90

Test

Condition

Symbol

Alt

Parameter

Unit

V

CC

= 3.0V to 3.6V

CL = 30pF

V

CC

= 3.0V to 3.6V

CL = 30pF

Min

80

Max

Min

90

Max

E = V

G = V

Address Valid to Next Address

Valid

IL,

t

ns

AVAV

RC

IL

E = V

G = V

IL,

t

ACC

Address Valid to Output Valid

80

90

ns

AVQV

IL

E = V

Address Transition to Output

Transition

IL,

t

0

AXQX

OH

G = V

IL

Chip Enable High to Output

Transition

t

G = V

ns

EHQX

OH

(1)

t

G = V

Chip Enable High to Output Hi-Z

Chip Enable Low to Output Valid

30

80

30

90

ns

t

HZ

IL

EHQZ

(2)

(1)

t

CE

ELQV

ELQX

Chip Enable Low to Output

Transition

t

G = V

E = V

0

ns

t

LZ

IL

Output Enable High to Output

Transition

t

GHQX

OH

(1)

t

E = V

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

30

35

30

35

ns

t

DF

IL

GHQZ

(2)

(1)

t

OE

GLQV

Output Enable Low to Output

Transition

t

E = V

0

ns

µs

ns

t

OLZ

IL

GLQX

t

RH

RP High to Chip Enable Low

RP Low to Read Mode

RP Pulse Width

50

PHEL

t

RRB

(1,3)

10

t

PLYH

t

READY

t

500

PLPX

RP

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

13/30

M29W008AT, M29W008AB

Table 16. Read AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

100

120

Test

Condition

Symbol

Alt

Parameter

Unit

V

CC

= 2.7V to 3.6V

CL = 30pF

V

CC

= 2.7V to 3.6V

CL = 30pF

Min

100

Max

Min

120

Max

E = V

G = V

Address Valid to Next Address

Valid

IL,

t

ns

AVAV

RC

IL

E = V

G = V

IL,

t

ACC

Address Valid to Output Valid

100

120

ns

AVQV

IL

E = V

Address Transition to Output

Transition

IL,

t

0

AXQX

OH

G = V

IL

Chip Enable High to Output

Transition

t

G = V

ns

EHQX

OH

IL

(1)

t

G = V

Chip Enable High to Output Hi-Z

Chip Enable Low to Output Valid

30

ns

t

HZ

IL

EHQZ

(2)

(1)

t

100

120

t

CE

IL

ELQV

Chip Enable Low to Output

Transition

t

G = V

E = V

0

ns

t

LZ

IL

ELQX

Output Enable High to Output

Transition

t

GHQX

(1)

OH

IL

t

E = V

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

30

40

30

50

ns

t

DF

IL

GHQZ

(2)

(1)

t

OE

IL

GLQV

Output Enable Low to Output

Transition

t

E = V

0

ns

µs

ns

OLZ

IL

GLQX

t

RH

RP High to Chip Enable Low

RP Low to Read Mode

RP Pulse Width

50

PHEL

t

RRB

(1,3)

10

t

PLYH

t

READY

t

500

PLPX

RP

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

14/30

M29W008AT, M29W008AB

Figure 5. Read Mode AC Waveforms

15/30

M29W008AT, M29W008AB

Table 17. Write AC Characteristics, W Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

80

90

Symbol

Alt

Parameter

Unit

V

CC

= 3.0V to 3.6V

CL = 30pF

V

CC

= 3.0V to 3.6V

CL = 30pF

Min

80

Max

Min

90

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Write Enable Low

Input Valid to Write Enable High

ns

AVAV

t

0

35

0

AVWL

AS

DS

CS

t

45

0

DVWH

t

Chip Enable Low to Write Enable Low

Output Enable High to Write Enable Low

ELWL

t

0

GHWL

(1, 2)

t

RP Rise Time to V

500

4

t

VIDR

ID

PHPHH

(1)

t

RP High to Write Enable Low

4

µs

t

RSP

PHWL

t

RP Pulse Width

500

50

0

500

50

0

ns

µs

ns

PLPX

RP

t

V

CC

High to Chip Enable Low

VCHEL

VCS

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

Program Erase Valid to RB Delay

WHDX

WHEH

DH

CH

t

0

t

OEH

0

WHGL

(1)

t

90

t

BUSY

WHRL

t

WPH

Write Enable High to Write Enable Low

Write Enable Low to Address Transition

Write Enable Low to Write Enable High

30

45

35

30

45

35

WHWL

t

AH

WLAX

t

WLWH

WP

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to address 5555h

on third cycle after the two Coded cycles. The

Block Erase Confirm command 30h is similarly

written on the sixth cycle after another two Coded

cycles. During the input of the second command

an address within the block to be erased is given

and latched into the memory. Additional block

Erase Confirm commands and block addresses

can be written subsequently to erase other blocks

in parallel, without further Coded cycles. The

erase will start after the erase timeout period (see

Erase Timer Bit DQ3 description). Thus, additional

Erase Confirm commands for other blocks must

be given within this delay. The input of a new

Erase Confirm command will restart the timeout

period. The status of the internal timer can be

monitored through the level of DQ3, if DQ3 is ’0’

the Block Erase Command has been given and

the timeout is running, if DQ3 is ’1’, the timeout has

expired and the P/E.C. is erasing the Block(s). If

the second command given is not an erase con-

firm or if the Coded cycles are wrong, the instruc-

tion aborts, and the device is reset to Read Array.

It is not necessary to program the block with 00h

as the P/E.C. will do this automatically before to

erasing to FFh. Read operations after the sixth ris-

ing edge of W or E output the status register status

bits.

16/30

M29W008AT, M29W008AB

Table 18. Write AC Characteristics, W Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

100

120

Symbol

Alt

Parameter

Unit

V

CC

= 2.7V to 3.6V

CL = 30pF

V

CC

= 2.7V to 3.6V

CL = 30pF

Min

100

Max

Min

120

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Write Enable Low

Input Valid to Write Enable High

ns

AVAV

t

0

45

0

AVWL

AS

DS

CS

t

50

0

DVWH

t

Chip Enable Low to Write Enable Low

Output Enable High to Write Enable Low

ELWL

t

0

GHWL

(1, 2)

t

RP Rise Time to V

500

4

t

VIDR

ID

PHPHH

(1)

t

RP High to Write Enable Low

4

µs

t

RSP

PHWL

t

RP Pulse Width

500

50

0

500

50

0

ns

µs

ns

PLPX

RP

t

V

CC

High to Chip Enable Low

VCHEL

VCS

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

Program Erase Valid to RB Delay

WHDX

WHEH

DH

CH

t

0

t

OEH

0

WHGL

(1)

t

90

t

BUSY

WHRL

t

WPH

Write Enable High to Write Enable Low

Write Enable Low to Address Transition

Write Enable Low to Write Enable High

30

45

35

30

50

WHWL

t

AH

WLAX

t

WLWH

WP

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

During the execution of the erase by the P/E.C.,

the memory accepts only the Erase Suspend ES

and Read/Reset RD instructions. Data Polling bit

DQ7 returns ’0’ while the erasure is in progress

and ’1’ when it has completed. The Toggle bit DQ2

and DQ6 toggle during the erase operation. They

stop when erase is completed. After completion

the Status Register bit DQ5 returns ’1’ if there has

been an erase failure. In such a situation, the Tog-

gle bit DQ2 can be used to determine which block

is not correctly erased. In the case of erase failure,

a Read/Reset RD instruction is necessary in order

to reset the P/E.C.

ter the two Coded cycles. The Chip Erase Confirm

command 10h is similarly written on the sixth cycle

after another two Coded cycles. If the second

command given is not an erase confirm or if the

Coded cycles are wrong, the instruction aborts

and the device is reset to Read Array. It is not nec-

essary to program the array with 00h first as the P/

E.C. will automatically do this before erasing it to

FFh. Read operations after the sixth rising edge of

W or E output the Status Register bits. During the

execution of the erase by the P/E.C., Data Polling

bit DQ7 returns ’0’, then ’1’ on completion. The

Toggle bits DQ2 and DQ6 toggle during erase op-

eration and stop when erase is completed. After

completion the Status Register bit DQ5 returns ’1’

if there has been an Erase Failure.

Chip Erase (CE) Instruction. This

instruction

uses six write cycles. The Erase Set-up command

80h is written to address 555h on the third cycle af-

17/30

M29W008AT, M29W008AB

Figure 6. Write AC Waveforms, W Controlled

tAVAV

VALID

A0-A19

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7

V

CC

tVCHEL

RB

tWHRL

AI02192

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

Erase Suspend (ES) Instruction. The

Block

suspended, a Read from blocks being erased will

output DQ2 toggling and DQ6 at '1'. A Read from

a block not being erased returns valid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions. A Program operation can be initiated during

erase suspend in one of the blocks not being

erased. It will result in both DQ2 and DQ6 toggling

when the data is being programmed. A Read/Re-

set command will definitively abort erasure and re-

sult in invalid data in the blocks being erased.

Erase Resume (ER) Instruction. If an Erase

Suspend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

Erase operation may be suspended by this in-

struction which consists of writing the command

B0h without any specific address. No Coded cy-

cles are required. It permits reading of data from

another block and programming in another block

while an erase operation is in progress. Erase sus-

pend is accepted only during the Block Erase in-

struction execution. Writing this command during

Erase timeout will, in addition to suspending the

erase, terminate the timeout. The Toggle bit DQ6

stops toggling when the P/E.C. is suspended. The

Toggle bits will stop toggling between 0.1µs and

15µs after the Erase Suspend (ES) command has

been written. The device will then automatically be

set to Read Memory Array mode. When erase is

18/30

M29W008AT, M29W008AB

Table 19. Write AC Characteristics, E Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

80

90

Symbol

Alt

Parameter

Unit

V

CC

= 3.0V to 3.6V

CL = 30pF

V

CC

= 3.0V to 3.6V

CL = 30pF

Min

80

Max

Min

90

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Chip Enable Low

Input Valid to Chip Enable High

ns

AVAV

t

0

35

0

AVEL

AS

DS

t

45

0

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

EHDX

DH

t

30

0

30

0

EHEL

CPH

t

EHGL

OEH

(1)

t

Program Erase Valid to RB Delay

90

ns

t

BUSY

EHRL

t

Chip Enable High to Write Enable High

Chip Enable Low to Address Transition

Chip Enable Low to Chip Enable High

Output Enable High Chip Enable Low

0

45

35

0

45

35

0

EHWH

WH

t

AH

ELAX

t

ELEH

CP

t

GHEL

(1, 2)

t

RP Rise TIme to V

500

t

VIDR

ID

PHPHH

(1)

t

RP High to Write Enable Low

4

500

50

0

4

500

50

0

µs

ns

µs

ns

t

RSP

PHWL

t

RP Pulse Width

PLPX

RP

t

V

CC

High to Write Enable Low

VCHWL

VCS

t

WS

Write Enable Low to Chip Enable Low

WLEL

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

POWER SUPPLY

Power Up

The memory Command Interface is reset on pow-

er up to Read Array. The device does not accept

commands on the first rising edge of W, if both W

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

have the V rail decoupled with a 0.1µF capacitor

CC

close to the V

widths should be sufficient to carry the V

gram and erase currents required.

and V

pins. The PCB trace

CC

SS

pro-

CC

and E are at V with G at V during power-up.

IL

IH

Any write cycle initiation is blocked when V

is

CC

below V

.

LKO

19/30

M29W008AT, M29W008AB

Table 20. Write AC Characteristics, E Controlled

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

100

120

Symbol

Alt

Parameter

Unit

V

CC

= 2.7V to 3.6V

CL = 30pF

V

CC

= 2.7V to 3.6V

CL = 30pF

Min

100

Max

Min

120

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Chip Enable Low

Input Valid to Chip Enable High

ns

AVAV

t

0

45

0

AVEL

AS

DS

t

50

0

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

EHDX

DH

t

30

0

20

0

EHEL

CPH

t

EHGL

OEH

(1)

t

Program Erase Valid to RB Delay

90

ns

t

BUSY

EHRL

t

Chip Enable High to Write Enable High

Chip Enable Low to Address Transition

Chip Enable Low to Chip Enable High

Output Enable High Chip Enable Low

0

45

35

0

50

0

EHWH

WH

t

AH

ELAX

t

ELEH

CP

t

GHEL

(1, 2)

t

RP Rise TIme to V

500

t

VIDR

ID

PHPHH

(1)

t

RP High to Write Enable Low

4

500

50

0

4

500

50

0

µs

ns

µs

ns

t

RSP

PHWL

t

RP Pulse Width

PLPX

RP

t

V

CC

High to Write Enable Low

VCHWL

VCS

t

WS

Write Enable Low to Chip Enable Low

WLEL

Note: 1. Sampled only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

20/30

M29W008AT, M29W008AB

Figure 7. Write AC Waveforms, E Controlled

tAVAV

VALID

A0-A19

tELAX

tAVEL

tEHWH

tEHGL

W

tWLEL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7

V

CC

tVCHWL

RB

tEHRL

AI02193

Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

Figure 8. Read and Write AC Characteristics, RP Related

E

tPHEL

W

tPHWL

RB

tPLPX

RP

tPHPHH

tPLYH

AI02091

21/30

M29W008AT, M29W008AB

(1)

CC

Table 21. Data Polling and Toggle Bit AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

80

90

Symbol

Parameter

Unit

V

= 3.0V to 3.6V

CL = 30pF

V

= 3.0V to 3.6V

CL = 30pF

CC

Min

10

Max

Min

10

Max

Chip Enable High to DQ7 Valid

(Program, E Controlled)

2400

µs

t

EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

60

1.0

60

sec

Chip Enable High to Output Valid (Program)

Chip Enable High to Output Valid (Chip Erase)

Q7 Valid to Output Valid (Data Polling)

10

2400

60

10

2400

60

µs

sec

ns

t

EHQV

1.0

t

35

Q7VQV

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

2400

60

10

2400

60

ms

t

WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

1.0

sec

Write Enable High to Output Valid (Program)

Write Enable High to Output Valid (Chip Erase)

10

2400

60

10

2400

60

µs

t

WHQV

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

(1)

Table 22. Data Polling and Toggle Bit AC Characteristics

(T = 0 to 70°C, –20 to 85°C or –40 to 85°C)

A

M29W008AT / M29W008AB

100 120

Symbol

Parameter

Unit

V

= 2.7V to 3.6V

CL = 30pF

V

= 2.7V to 3.6V

CL = 30pF

CC

Min

10

Max

Min

10

Max

Chip Enable High to DQ7 Valid

(Program, E Controlled)

2400

µs

t

EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

60

1.0

60

sec

Chip Enable High to Output Valid (Program)

Chip Enable High to Output Valid (Chip Erase)

Q7 Valid to Output Valid (Data Polling)

10

2400

60

10

2400

60

µs

sec

ns

t

EHQV

1.0

t

40

50

Q7VQV

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

2400

60

10

2400

60

ms

t

WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

1.0

sec

Write Enable High to Output Valid (Program)

Write Enable High to Output Valid (Chip Erase)

10

2400

60

10

2400

60

µs

t

WHQV

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

22/30

M29W008AT, M29W008AB

Figure 9. Data Polling DQ7 AC Waveforms

23/30

M29W008AT, M29W008AB

Figure 10. Data Polling Flowchart

Figure 11. Data Toggle Flowchart

START

READ

DQ2, DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

NO

DQ2, DQ6

=

DQ7

=

DATA

YES

TOGGLE

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ7

READ DQ2, DQ6

DQ7

=

DATA

YES

NO

DQ2, DQ6

=

TOGGLE

NO

YES

FAIL

PASS

FAIL

PASS

AI01369

AI01873

Table 23. Program, Erase Times and Program, Erase Endurance Cycles

(T = 0 to 70°C; V = 2.7V to 3.6V)

A

CC

M29W008AT / M29W008AB

Parameter

Unit

Typical after

Typ

Min

Max

100k W/E Cycles

Chip Erase (Preprogrammed, V = 2.7V)

10

15

1.5

5

10

15

sec

CC

Chip Erase (V = 2.7V)

CC

Main Block Erase (V = 2.7V)

15

CC

(1)

5

Chip Program (Byte)

Byte Program

10

µs

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Excluded the time required to execute bus cycles sequence for program operation.

24/30

M29W008AT, M29W008AB

Figure 12. Data Toggle DQ6, DQ2 AC Waveforms

25/30

M29W008AT, M29W008AB

SECURITY PROTECTION MEMORY AREA

Read Security Data (RDS) Instruction. This RDS

uses a single write cycle instruction: the command

B8h is written to the address AAh. This sets the

memory to the Read Security mode. Any succes-

sive read attempt will output the addressed Secu-

rity byte until a new write cycle is initiated.

The M29W008A features a security protection

memory area. It consists of a memory block of 256

bytes which is programmed in the ST factory to

store a unique code that uniquely identifies the

part.

This memory block can be read by using the Read

Security Data instruction (RDS) as shown in Table

24.

Table 24. Security Block Instruction

Unlock Cycle

1st Cyc.

AAh

Mne.

Instr.

Cyc.

2nd Cyc.

(1)

(2)

Read

Security

Data

Addr.

Data

RDS

1

Read OTP Data until a new write cycle is initiated.

B8h

Note: 1. Address bits A10-A19 are don’t care for coded address inputs.

2. Data bits DQ8-DQ15 are don’t care for coded address inputs.

Figure 13. Security Block Address Table

TOP BOOT BLOCK

BOTTOM BOOT BLOCK

000FFh

0E0FFh

Security

Memory Block

00000h

0E000h

AI02740

26/30

M29W008AT, M29W008AB

Table 25. Ordering Information Scheme

Example:

M29W008AT

80

N

1

T

Device Type

M29

Operating Voltage

W = 2.7 to 3.6V

Device Function

008A = 8 Mbit (1Mb x8), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

80 = 80 ns

90 = 90 ns

100 = 100 ns

120 = 120 ns

Package

N = TSOP40: 10 x 20 mm

Temperature Range

1 = 0 to 70 °C

5 = –20 to 85°C

6 = –40 to 85 °C

Option

T = Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

27/30

M29W008AT, M29W008AB

Table 26. Revision History

Date

Description

November 1998 First issue

New document template

Document type: from Preliminary Data to Data Sheet

02/09/00

03/06/00

Program Erase Times change (Table 23)

28/30

M29W008AT, M29W008AB

Table 27. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

mm

inches

Symbol

Typ

Min

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

10.10

–

Typ

Min

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.7953

0.7283

0.3976

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

9.90

–

0.0020

0.0374

0.0067

0.0039

0.7795

0.7205

0.3898

–

C

D

D1

E

e

0.50

0.0197

L

0.50

0°

0.70

5°

0.0197

0°

0.0276

5°

α

N

40

CP

0.10

0.0039

Figure 14. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Drawing is not to scale.

A1

α

L

29/30

M29W008AT, M29W008AB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

30/30


型号：	M29W008AT90N5TR
厂家：	ST
描述：	1MX8 FLASH 2.7V PROM, 90ns, PDSO40, 10 X 20 MM, PLASTIC, TSOP-40 闪存存储内存集成电路光电二极管
文件：	总30页 (文件大小：219K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M29W008AT90N5TR [STMICROELECTRONICS]

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