M29W320DT90N1 [STMICROELECTRONICS]
32 Mbit 4Mb x8 or 2Mb x16, Boot Block 3V Supply Flash Memory; 32兆位4Mb的X8或X16的2Mb ,引导块3V电源快闪记忆体型号: | M29W320DT90N1 |
厂家: | ST |
描述: | 32 Mbit 4Mb x8 or 2Mb x16, Boot Block 3V Supply Flash Memory |
文件: | 总46页 (文件大小:853K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M29W320DT
M29W320DB
32 Mbit (4Mb x8 or 2Mb x16, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– V = 2.7V to 3.6V for Program, Erase and
CC
Read
– V =12V for Fast Program (optional)
PP
■ ACCESS TIME: 70, 90ns
■ PROGRAMMING TIME
– 10µs per Byte/Word typical
TSOP48 (N)
12 x 20mm
■ 67 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 64 Main Blocks
■ PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithms
■ ERASE SUSPEND and RESUME MODES
FBGA
TFBGA63 (ZA)
TFBGA48 (ZE)
– Read and Program another Block during
Erase Suspend
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ V /WP PIN for FAST PROGRAM and WRITE
PP
PROTECT
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29W320DT: 22CAh
– Bottom Device Code M29W320DB: 22CBh
August 2005
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M29W320DT, M29W320DB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. TFBGA63 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V Write Protect (V WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PP/ PP/
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
V
Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
SS
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Bus Operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IL
Table 2. Bus Operations, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IH
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29W320DT, M29W320DB
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Commands, 16-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IH
Table 4. Commands, 8-bit mode, BYTE = V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IL
Table 5. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10.Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Bottom View Package Outline . . 28
Table 15. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 28
Figure 19.TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline. . . . . . . . . . . 29
Table 16. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . . 29
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M29W320DT, M29W320DB
Figure 20.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 30
Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Top Boot Block Addresses, M29W320DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Bottom Boot Block Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 22. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 26. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 27. Programmer Technique Bus Operations, BYTE = V or V
IH
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 23.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 24.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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M29W320DT, M29W320DB
SUMMARY DESCRIPTION
The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode where it can be read in the same way
as a ROM or EPROM.
Figure 2. Logic Diagram
V
V
/WP
CC PP
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
21
15
A0-A20
DQ0-DQ14
DQ15A–1
W
E
M29W320DT
M29W320DB
G
RB
RP
BYTE
The blocks in the memory are asymmetrically ar-
ranged, see Figure 6. and Figure 7., Table 19. and
Table 20.The first or last 64 Kbytes have been di-
vided into four additional blocks. The 16 Kbyte
Boot Block can be used for small initialization code
to start the microprocessor, the two 8 Kbyte Pa-
rameter Blocks can be used for parameter storage
and the remaining 32 Kbyte is a small Main Block
where the application may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
V
SS
AI90189B
Table 1. Signal Names
A0-A20
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
Address Inputs
Data Inputs/Outputs
Data Inputs/Outputs
The memory is offered in TSOP48 (12 x 20mm)
TFBGA63 (7x11mm, 0.8mm pitch) and TFBGA48
(6x8mm, 0.8mm pitch) packages. The memory is
supplied with all the bits erased (set to 1).
Data Input/Output or Address Input
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
Ready/Busy Output
RB
BYTE
Byte/Word Organization Select
Supply Voltage
V
CC
V
/Write Protect
V
V
/WP
PP
PP
Ground
SS
NC
Not Connected Internally
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M29W320DT, M29W320DB
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
1
48
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ14
DQ6
A8
DQ13
DQ5
A19
A20
W
DQ12
DQ4
RP
NC
/WP
RB
A18
A17
A7
12
13
37
36
V
M29W320DT
M29W320DB
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
PP
A6
A5
A4
A3
V
E
SS
A2
A1
24
25
A0
AI90190
6/46
M29W320DT, M29W320DB
Figure 4. TFBGA63 Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
A13
RB
W
A3
A4
A7
A17
A6
A9
A8
C
D
V
/
WP
RP
NC
A12
A14
PP
E
F
A2
A1
A0
E
A18
A10
A5
A20
A19
A11
A15
DQ2
DQ5
G
H
J
DQ0
DQ8
DQ9
DQ1
DQ7
DQ14
DQ13
DQ6
A16
BYTE
DQ10
DQ11
DQ3
DQ12
DQ15
A–1
G
V
CC
K
L
V
DQ4
V
SS
SS
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
M
AI05525B
Note: 1. Balls are shorted together via the substrate but not connected to the die.
7/46
M29W320DT, M29W320DB
Figure 5. TFBGA48 Connections (Top view through package)
1
2
3
4
5
6
RB
W
A
B
A3
A4
A7
A17
A6
A9
A8
A13
A12
V
/
WP
RP
NC
PP
A2
A1
A0
E
A18
A10
A14
C
D
A5
A20
A19
A11
A15
DQ2
DQ5
DQ0
DQ8
DQ9
DQ1
DQ7
DQ14
DQ13
DQ6
A16
E
F
BYTE
DQ10
DQ11
DQ3
DQ12
DQ15
A–1
G
V
G
H
CC
V
DQ4
V
SS
SS
AI08084
8/46
M29W320DT, M29W320DB
Figure 6. Block Addresses (x8)
M29W320DT
Top Boot Block Addresses (x8)
M29W320DB
Bottom Boot Block Addresses (x8)
3FFFFFh
16 KByte
3FC000h
3FBFFFh
3FFFFFh
64 KByte
64 KByte
3F0000h
3EFFFFh
8 KByte
3FA000h
3F9FFFh
3E0000h
Total of 63
64 KByte Blocks
8 KByte
3F8000h
3F7FFFh
32 KByte
3F0000h
3EFFFFh
01FFFFh
64 KByte
64 KByte
32 KByte
8 KByte
8 KByte
16 KByte
3E0000h
010000h
00FFFFh
008000h
007FFFh
Total of 63
64 KByte Blocks
006000h
005FFFh
01FFFFh
64 KByte
010000h
00FFFFh
004000h
003FFFh
64 KByte
000000h
000000h
AI90192
Note: Also see APPENDIX A., Table 19. and Table 20. for a full listing of the Block Addresses.
9/46
M29W320DT, M29W320DB
Figure 7. Block Addresses (x16)
M29W320DT
M29W320DB
Top Boot Block Addresses (x16)
Bottom Boot Block Addresses (x16)
1FFFFFh
8 KWord
1FE000h
1FDFFFh
1FFFFFh
32 KWord
32 KWord
1F8000h
1F7FFFh
4 KWord
1FD000h
1FCFFFh
1F0000h
Total of 63
32 KWord Blocks
4 KWord
1FC000h
1FBFFFh
16 KWord
1F8000h
1F7FFFh
00FFFFh
32 KWord
32 KWord
16 KWord
4 KWord
4 KWord
8 KWord
1F0000h
008000h
007FFFh
004000h
003FFFh
Total of 63
32 KWord Blocks
003000h
002FFFh
00FFFFh
32 KWord
008000h
007FFFh
002000h
001FFFh
32 KWord
000000h
000000h
AI90193
Note: Also see Appendix APPENDIX A., Table 19. and Table 20. for a full listing of the Block Addresses.
10/46
M29W320DT, M29W320DB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
When V /Write Protect is High, V , the memory
PP IH
reverts to the previous protection status of the 16
Kbyte boot block. Program and Erase operations
can now modify the data in the 16 Kbyte Boot
Block unless the block is protected using Block
Protection.
When V /Write Protect is raised to V the mem-
PP
PP
ory automatically enters the Unlock Bypass mode.
When V /Write Protect returns to V or V nor-
PP
IH
IL
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the internal state ma-
chine.
mal operation resumes. During Unlock Bypass
Program operations the memory draws I from
PP
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
than t
to V
VHVPP
and from V
, see Figure 17..
to V must be slower
IH
PP
PP IH
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
Never raise V /Write Protect to V
from any
PP
PP
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
A 0.1µF capacitor should be connected between
V . When BYTE is Low, V , these pins are not
IH
IL
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
the V /Write Protect pin and the V Ground pin
PP
SS
to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Unlock Bypass
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, V , this pin behaves as a
IH
Program, I
.
PP
Data Input/Output pin (as DQ8-DQ14). When
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
BYTE is Low, V , this pin behaves as an address
IL
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address In-
puts to include this pin when BYTE is Low except
when stated explicitly otherwise.
Note that if V /WP is at V , then the 16 KByte
PP
IL
outermost boot block will remain protect even if RP
is at V .
ID
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V , for at least
IL
t
. After Reset/Block Temporary Unprotect
PLPX
High, V , all other pins are ignored.
goes High, V , the memory will be ready for Bus
IH
IH
Read and Bus Write operations after t
or
PHEL
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
t
, whichever occurs last. See the Ready/Busy
RHEL
Output section, Table 14. and Figure 16., Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V will temporarily unprotect the
ID
V
Write Protect (V /WP). The
V
PP
/Write
PP/
PP
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
Protect pin provides two functions. The V func-
PP
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Unlock Bypass Program operations. The
Write Protect function provides a hardware meth-
od of protecting the 16 Kbyte Boot Block. The
The transition from V to V must be slower than
IH
ID
t
.
PHPHH
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
V
/Write Protect pin must not be left floating or
PP
unconnected.
Ready/Busy is Low, V . Ready/Busy is high-im-
OL
When V /Write Protect is Low, V , the memory
PP
IL
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
protects the 16 Kbyte Boot Block; Program and
Erase operations in this block are ignored while
V
/Write Protect is Low.
PP
11/46
M29W320DT, M29W320DB
Note that if V /WP is at V , then the 16 KByte
outermost boot block will remain protect even if RP
V
Supply Voltage (2.7V to 3.6V). V
CC
pro-
PP
IL
CC
vides the power supply for all operations (Read,
Program and Erase).
is at V .
ID
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 14. and Figure
Figure 16., Reset/Temporary Unprotect AC Char-
acteristics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
. This prevents Bus Write operations from ac-
V
LKO
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V
Supply Voltage pin and the V Ground
CC
SS
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, I
.
CC3
Low, V , the memory is in x8 mode, when it is
IL
High, V , the memory is in x16 mode.
V
Ground. V is the reference for all voltage
SS SS
IH
measurements.
12/46
M29W320DT, M29W320DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby. See
Figure 8. and Table 2., Bus Operations, for a sum-
mary. Typically glitches of less than 5ns on Chip
Enable or Write Enable are ignored by the memory
and do not affect bus operations.
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, I
, Chip Enable should
CC2
be held within V ± 0.2V. For the Standby current
CC
level see Table 10., DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Current, I
til the operation completes.
Automatic Standby. If CMOS levels (V ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
, for Program or Erase operations un-
CC3
CC
Inputs, applying a Low signal, V , to Chip Enable
IL
and Output Enable and keeping Write Enable
High, V . The Data Inputs/Outputs will output the
IH
. The
CC2
value, see Figure 13., Read Mode AC Waveforms,
and Table 11., Read AC Characteristics, for de-
tails of when the output becomes valid.
Special Bus Operations
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En-
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They require V to be applied to some pins.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Figure 8. and Table 2., Bus Operations.
able must remain High, V , during the whole Bus
IH
Write operation. See Figure 14. and Figure 15.,
Write AC Waveforms, and Table 12. and Table
13., Write AC Characteristics, for details of the tim-
ing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
Block Protect and Chip Unprotect. Each
block
can be separately protected against accidental
Program or Erase. The whole chip can be unpro-
tected to allow the data inside the blocks to be
changed.
High, V .
IH
Block Protect and Chip Unprotect operations are
described in APPENDIX C..
Standby. When Chip Enable is High, V , the
memory enters Standby mode and the Data In-
IH
Figure 8. Bus Operations, BYTE = V
IL
Data Inputs/Outputs
Address Inputs
DQ15A–1, A0-A20
Operation
Bus Read
E
G
W
DQ14-DQ8
Hi-Z
DQ7-DQ0
Data Output
Data Input
Hi-Z
V
IL
V
V
IH
Cell Address
IL
IH
IH
V
IL
V
V
V
V
Bus Write
Command Address
Hi-Z
IL
Output Disable
Standby
X
X
Hi-Z
IH
V
X
X
X
Hi-Z
Hi-Z
IH
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
Hi-Z
Hi-Z
20h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V ,
CAh (M29W320DT)
CBh (M29W320DB)
IH
IL
V
V
Read Device Code
A9 = V , Others V or V
IH
ID
IL
Note: X = V or V
.
IH
IL
13/46
M29W320DT, M29W320DB
Table 2. Bus Operations, BYTE = V
IH
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
Bus Read
E
G
W
V
IL
V
V
IH
Cell Address
Data Output
Data Input
Hi-Z
IL
IH
IH
V
IL
V
V
V
V
Bus Write
Command Address
IL
Output Disable
Standby
X
X
IH
V
IH
X
X
X
Hi-Z
A0 = V , A1 = V , A9 = V ,
Read Manufacturer
Code
IL
IL
ID
V
V
V
V
0020h
IL
IL
IL
IL
IH
IH
Others V or V
IL
IH
A0 = V , A1 = V , A9 = V ,
22CAh (M29W320DT)
22CBh (M29W320DB)
IH
IL
ID
V
V
Read Device Code
Others V or V
IL
IH
Note: X = V or V
IL
.
IH
14/46
M29W320DT, M29W320DB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. The long command sequences
are imposed to maximize data security.
command is valid when the device is in the Read
Array mode, or when the device is in Autoselected
mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The address used for the commands changes de-
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 3., or Table 4., depend-
ing on the configuration that is being used, for a
summary of the commands.
Read/Reset Command. The Read/Reset com-
mand returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless other-
wise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select com-
mand is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect-
ed mode.
See APPENDIX B., Table 21., Table 22., Table
23., Table 24., Table 25. and Table 26. for details
on the information contained in the Common Flash
Interface (CFI) memory area.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command re-
quires four Bus Write operations, the final write op-
eration latches the address and data in the internal
state machine and starts the Program/Erase Con-
troller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 5.. Bus Read op-
erations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memo-
ry. When the cycle time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these com-
mands. Three Bus Write operations are required
to issue the Unlock Bypass command.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V and A1 = V . The other address bits
IL
IL
may be set to either V or V . The Manufacturer
IL
IH
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = V and A1 = V . The other
IH
IL
address bits may be set to either V or V . The
IL
IH
Device Code for the M29W320DT is 22CAh and
for the M29W320DB is 22CBh.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V ,
IL
A1 = V , and A12-A20 specifying the address of
IH
the block. The other address bits may be set to ei-
ther V or V . If the addressed block is protected
IL
IH
then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
15/46
M29W320DT, M29W320DB
Once the Unlock Bypass command has been is-
sued the memory will only accept the Unlock By-
pass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Register on the Data Inputs/Outputs. See the sec-
tion on the Status Register for more details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read Mode.
The memory offers accelerated program opera-
tions through the V /Write Protect pin. When the
PP
system asserts V on the V /Write Protect pin,
PP
PP
the memory automatically enters the Unlock By-
pass mode. The system may then write the two-
cycle Unlock Bypass program command se-
quence. The memory uses the higher voltage on
The Chip Erase Command sets all of the bits in un-
protected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase com-
mand can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register sec-
tion for details on how to identify if the Program/
Erase Controller has started the Block Erase oper-
ation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error condition is given when protect-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 5.. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command must be issued to re-
set the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
the V /Write Protect pin, to accelerate the Unlock
PP
Bypass Program operation.
Never raise V /Write Protect to V
from any
PP
PP
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
Unlock Bypass Program Command. The Un-
lock Bypass Program command can be used to
program one address in the memory array at a
time. The command requires two Bus Write oper-
ations, the final write operation latches the ad-
dress and data in the internal state machine and
starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pro-
gram operation using the Program command. The
operation cannot be aborted, the Status Register
is read and protected blocks cannot be pro-
grammed. Errors must be reset using the Read/
Reset command, which leaves the device in Un-
lock Bypass Mode. See the Program command for
details on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase com-
mand can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap-
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 5.. All Bus Read operations during
the Chip Erase operation will output the Status
16/46
M29W320DT, M29W320DB
The Program/Erase Controller will suspend within
the Erase Suspend Latency Time (refer to Table 5.
for value) of the Erase Suspend Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start im-
mediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller after an Erase Suspend. The de-
vice must be in Read Array mode before the Re-
sume command will be accepted. An erase can be
suspended and resumed more than once.
Block Protect and Chip Unprotect Commands.
Each block can be separately protected against
accidental Program or Erase. The whole chip can
be unprotected to allow the data inside the blocks
to be changed.
Block Protect and Chip Unprotect operations are
described in APPENDIX C..
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read-
17/46
M29W320DT, M29W320DB
Table 3. Commands, 16-bit mode, BYTE = V
IH
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
555
555
555
555
2AA
2AA
2AA
2AA
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
555
555
555
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
X
00
55
55
555
2AA
2AA
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
BA
10
30
Block Erase
6+ 555
Erase Suspend
Erase Resume
Read CFI Query
1
1
1
X
X
55
98
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V
.
IH
IL
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Read/Reset command is
ignored during algorithm execution.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-
mands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-
gram/Erase Controller completes and the memory returns to Read Mode.
CFI Query. Command is valid when device is ready to read array data or when device is in autoselected mode.
18/46
M29W320DT, M29W320DB
Table 4. Commands, 8-bit mode, BYTE = V
IL
Bus Write Operations
3rd 4th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Command
1st
2nd
5th
6th
1
3
3
4
3
X
F0
AA
AA
AA
AA
Read/Reset
AAA
AAA
AAA
AAA
555
555
555
555
55
55
55
55
X
F0
90
A0
20
Auto Select
Program
AAA
AAA
AAA
PA
PD
Unlock Bypass
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
Chip Erase
2
6
X
90
AA
AA
B0
30
X
00
55
55
AAA
555
555
AAA
AAA
80
80
AAA
AAA
AA
AA
555
555
55
55
AAA
BA
10
30
Block Erase
6+ AAA
Erase Suspend
Erase Resume
Read CFI Query
1
1
1
X
X
AA
98
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V
.
IH
IL
Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued. Read/Reset command is
ignored during algorithm execution.
Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/
Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional
Bus Write Operations until Timeout Bit is set.
Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-
mands on non-erasing blocks as normal.
Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-
gram/Erase Controller completes and the memory returns to Read Mode.
CFI Query. Command is valid when device is ready to read array data or when device is in autoselected mode.
19/46
M29W320DT, M29W320DB
Table 5. Program, Erase Times and Program, Erase Endurance Cycles
(1, 2)
(2)
Parameter
Min
Unit
s
Typ
40
Max
(3)
Chip Erase
200
(4)
Block Erase (64 KBytes)
0.8
15
10
8
s
6
(4)
Erase Suspend Latency Time
Program (Byte or Word)
µs
µs
µs
s
25
(3)
(3)
(3)
(3)
200
150
200
100
Accelerated Program (Byte or Word)
Chip Program (Byte by Byte)
40
20
Chip Program (Word by Word)
Program/Erase Cycles (per Block)
Data Retention
s
100,000
20
cycles
years
Note: 1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.
CC
4. Maximum value measured at worst case conditions for both temperature and V
.
CC
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus-
pend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 6., Status Register Bits.
Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the operation the memo-
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any at-
tempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
ror is signalled and DQ6 toggles for approximately
1µs.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure Figure 9., Data Polling Flowchart, gives an
example of how to use the Data Polling Bit. A Valid
Figure Figure 10., Data Toggle Flowchart, gives
an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
20/46
M29W320DT, M29W320DB
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
Table 6. Status Register Bits
Operation
Program
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Chip Erase
Any Address
Any Address
DQ7
Toggle
Toggle
1
0
0
0
0
0
0
–
1
0
0
1
1
–
–
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Toggle
Erasing Block
Toggle
Toggle
Block Erase before
timeout
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
Toggle
Block Erase
Erase Suspend
Erase Error
Non-Erasing Block
Erasing Block
Toggle
No Toggle
Toggle
No Toggle
Non-Erasing Block
Good Block Address
Faulty Block Address
Data read as normal
0
0
Toggle
Toggle
1
1
1
No Toggle
Toggle
1
Note: Unspecified data bits should be ignored.
21/46
M29W320DT, M29W320DB
Figure 9. Data Polling Flowchart
Figure 10. Data Toggle Flowchart
START
START
READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
YES
DQ6
NO
=
NO
TOGGLE
YES
NO
DQ5
= 1
NO
DQ5
YES
= 1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
NO
NO
FAIL
TOGGLE
YES
FAIL
PASS
PASS
AI90194
AI01370C
22/46
M29W320DT, M29W320DB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
Symbol
Parameter
Min
–50
Max
125
150
Unit
°C
°C
V
T
Temperature Under Bias
Storage Temperature
BIAS
T
–65
STG
(1,2)
V
IO
V
+0.6
–0.6
–0.6
–0.6
–0.6
CC
Input or Output Voltage
Supply Voltage
V
4
V
CC
V
ID
Identification Voltage
Program Voltage
13.5
13.5
V
V
PP
V
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.
CC
23/46
M29W320DT, M29W320DB
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 8., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 8. Operating and AC Measurement Conditions
M29W320D
Parameter
70
90
Unit
Min
3.0
Max
3.6
85
Min
2.7
Max
3.6
85
V
Supply Voltage
V
°C
pF
ns
V
CC
Ambient Operating Temperature
–40
–40
Load Capacitance (C )
30
30
L
Input Rise and Fall Times
10
10
0 to V
0 to V
Input Pulse Voltages
CC
CC
V
CC
/2
V
/2
CC
Input and Output Timing Ref. Voltages
V
Figure 11. AC Measurement I/O Waveform
Figure 12. AC Measurement Load Circuit
V
V
V
CC
PP
CC
V
CC
V
/2
CC
25kΩ
25kΩ
0V
DEVICE
UNDER
TEST
AI90196
C
L
0.1µF
0.1µF
C
includes JIG capacitance
L
AI90197
Table 9. Device Capacitance
Symbol
Parameter
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
Input Capacitance
Output Capacitance
6
pF
pF
IN
IN
C
V
OUT
12
OUT
Note: Sampled only, not 100% tested.
24/46
M29W320DT, M29W320DB
Table 10. DC Characteristics
Symbol
Parameter
Test Condition
Min
Typ.
Max
±1
Unit
µA
I
LI
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
±1
µA
E = V , G = V ,
IL
IH
I
Supply Current (Read)
5
10
100
20
mA
µA
mA
mA
CC1
f = 6MHz
E = V ±0.2V,
CC
I
Supply Current (Standby)
35
CC2
RP = V ±0.2V
CC
V
V
/WP =
or V
IH
PP
Program/
Erase
IL
Supply Current (Program/
Erase)
(1)
I
CC3
Controller
active
V
/WP =
PP
20
V
PP
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
IH
0.7V
V
+0.3
CC
CC
Voltage for V /WP
PP
Program Acceleration
V
V
V
= 3.0V ±10%
11.5
12.5
V
PP
PP
CC
CC
Current for V /WP
PP
I
= 3.0V ±10%
= 1.8mA
10
mA
Program Acceleration
Output Low Voltage
Output High Voltage
Identification Voltage
Identification Current
V
V
I
I
0.45
V
V
OL
OL
V
–0.4
= –100µA
OH
CC
OH
V
11.5
1.8
12.5
100
V
ID
ID
I
A9 = V
ID
µA
Program/Erase Lockout
Supply Voltage
V
LKO
2.3
V
Note: 1. Sampled only, not 100% tested.
25/46
M29W320DT, M29W320DB
Figure 13. Read Mode AC Waveforms
tAVAV
VALID
A0-A20/
A–1
tAVQV
tAXQX
tEHQX
E
tELQV
tELQX
tEHQZ
G
tGLQX
tGLQV
tGHQX
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI90198
Table 11. Read AC Characteristics
M29W320D
Symbol
Alt
Parameter
Test Condition
Unit
70
90
E = V ,
IL
t
t
Address Valid to Next Address Valid
Address Valid to Output Valid
Min
70
70
90
90
ns
ns
AVAV
RC
G = V
IL
E = V ,
IL
t
t
ACC
Max
AVQV
G = V
G = V
G = V
IL
IL
IL
(1)
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Min
0
0
ns
ns
t
t
LZ
ELQX
t
t
Max
70
90
ELQV
CE
Output Enable Low to Output
Transition
(1)
t
E = V
Min
0
0
ns
OLZ
IL
GLQX
t
t
E = V
G = V
E = V
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Max
Max
Max
30
25
25
35
30
30
ns
ns
ns
GLQV
OE
IL
(1)
(1)
t
t
t
HZ
IL
EHQZ
t
DF
IL
GHQZ
t
t
t
EHQX
Chip Enable, Output Enable or
Address Transition to Output Transition
t
Min
0
5
0
5
ns
ns
GHQX
OH
AXQX
t
t
t
ELFL
ELBL
Chip Enable to BYTE Low or High
Max
t
ELBH
ELFH
t
t
BYTE Low to Output Hi-Z
BYTE High to Output Valid
Max
Max
25
30
30
40
ns
ns
BLQZ
FLQZ
t
t
FHQV
BHQV
Note: 1. Sampled only, not 100% tested.
26/46
M29W320DT, M29W320DB
Figure 14. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A20/
VALID
A–1
tWLAX
tAVWL
tWHEH
tWHGL
E
tELWL
G
tGHWL
tWLWH
W
tWHWL
tWHDX
tDVWH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHEL
RB
tWHRL
AI90199
Table 12. Write AC Characteristics, Write Enable Controlled
M29W320D
Unit
Symbol
Alt
Parameter
70
70
0
90
90
0
t
t
WC
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AVAV
t
t
CS
ELWL
t
t
45
45
0
50
50
0
WLWH
WP
t
t
DVWH
DS
DH
CH
t
t
t
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Program/Erase Valid to RB Low
WHDX
t
0
0
WHEH
t
t
WPH
30
0
30
0
WHWL
t
t
AS
AVWL
t
t
45
0
50
0
WLAX
AH
t
GHWL
t
t
OEH
0
0
WHGL
(1)
t
30
50
35
50
t
BUSY
WHRL
t
t
V
CC
High to Chip Enable Low
VCHEL
VCS
Note: 1. Sampled only, not 100% tested.
27/46
M29W320DT, M29W320DB
Figure 15. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A20/
VALID
A–1
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tEHDX
tDVEH
VALID
DQ0-DQ7/
DQ8-DQ15
V
CC
tVCHWL
RB
tEHRL
AI90200
Table 13. Write AC Characteristics, Chip Enable Controlled
M29W320D
Symbol
Alt
Parameter
Unit
70
70
0
90
t
t
WC
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
AVAV
t
t
WS
WLEL
t
t
45
45
0
50
50
0
ELEH
CP
DS
t
t
t
DVEH
t
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low
Chip Enable High to Output Enable Low
Program/Erase Valid to RB Low
EHDX
DH
t
t
WH
0
0
EHWH
t
t
30
0
30
0
EHEL
CPH
t
t
AS
AVEL
t
t
45
0
50
0
ELAX
AH
t
GHEL
t
t
0
0
EHGL
OEH
(1)
t
30
50
35
50
t
BUSY
EHRL
t
t
V
CC
High to Write Enable Low
VCHWL
VCS
Note: 1. Sampled only, not 100% tested.
28/46
M29W320DT, M29W320DB
Figure 16. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Table 14. Reset/Block Temporary Unprotect AC Characteristics
M29W320D
Symbol
Alt
Parameter
Unit
70
90
(1)
t
PHWL
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
t
Min
Min
50
50
0
ns
PHEL
RH
(1)
t
PHGL
(1)
(1)
(1)
t
t
RHWL
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
t
0
ns
t
RB
RHEL
RHGL
t
t
RP Pulse Width
Min
Max
Min
Min
500
10
500
10
ns
µs
ns
ns
PLPX
RP
(1)
t
RP Low to Read Mode
t
READY
PLYH
(1)
(1)
t
RP Rise Time to V
500
250
500
250
t
VIDR
ID
PHPHH
V
PP
Rise and Fall Time
t
VHVPP
Note: 1. Sampled only, not 100% tested.
Figure 17. Accelerated Program Timing Waveforms
V
PP
V
/WP
PP
V
or V
IH
IL
tVHVPP
tVHVPP
AI90202
29/46
M29W320DT, M29W320DB
PACKAGE MECHANICAL
Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Bottom View Package Outline
1
48
e
D1
B
L1
24
25
A2
A
E1
E
A1
α
L
DIE
C
CP
TSOP-G
Note: Drawing not to scale.
Table 15. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
0.080
12.100
20.200
18.500
–
Typ
Max
A
A1
A2
B
0.0472
0.0059
0.0413
0.0106
0.0083
0.0031
0.4764
0.7953
0.7283
–
0.100
1.000
0.220
0.050
0.950
0.170
0.100
0.0039
0.0394
0.0087
0.0020
0.0374
0.0067
0.0039
C
CP
D1
E
12.000
20.000
18.400
0.500
0.600
0.800
3
11.900
19.800
18.300
–
0.4724
0.7874
0.7244
0.0197
0.0236
0.0315
3
0.4685
0.7795
0.7205
–
E1
e
L
0.500
0.700
0.0197
0.0276
L1
α
0
5
0
5
30/46
M29W320DT, M29W320DB
Figure 19. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Outline
D
D1
SD
FD
e
ddd
SE
E
E1
BALL "A1"
FE
e
b
A
A2
A1
BGA-Z33
Note: Drawing is not to scale.
Table 16. TFBGA63 7x11mm - 6x8 active ball array, 0.8mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.250
0.0098
0.900
0.0354
0.350
0.450
0.0138
0.0177
D
7.000
5.600
–
6.900
7.100
0.2756
0.2205
–
0.2717
0.2795
D1
ddd
E
–
–
–
–
–
0.100
–
0.0039
11.000
8.800
0.800
0.700
1.100
0.400
0.400
10.900
11.100
0.4331
0.3465
0.0315
0.0276
0.0433
0.0157
0.0157
0.4291
0.4370
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
31/46
M29W320DT, M29W320DB
Figure 20. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z32
Note: Drawing not to scale.
Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.260
0.0102
0.900
0.0354
0.350
5.900
–
0.450
0.0138
0.2323
–
0.0177
D
6.000
4.000
6.100
0.2362
0.1575
0.2402
D1
ddd
E
–
–
0.100
0.0039
8.000
5.600
0.800
1.000
1.200
0.400
0.400
7.900
8.100
0.3150
0.2205
0.0315
0.0394
0.0472
0.0157
0.0157
0.3110
0.3189
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
32/46
M29W320DT, M29W320DB
PART NUMBERING
Table 18. Ordering Information Scheme
Example:
M29W320DB
90 N
1
T
Device Type
M29
Operating Voltage
W = V = 2.7 to 3.6V
CC
Device Function
320D = 32 Mbit (x8/x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
ZA = TFBGA63: 7x11mm, 0.80 mm pitch
ZE = TFBGA48: 6 x 8mm, 0.8mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
33/46
M29W320DT, M29W320DB
APPENDIX A. BLOCK ADDRESS TABLE
Table 19. Top Boot Block Addresses,
M29W320DT
34 64/32 220000h-22FFFFh 110000h-117FFFh
33 64/32 210000h-21FFFFh 108000h-10FFFFh
32 64/32 200000h-20FFFFh 100000h-107FFFh
31 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh
30 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh
29 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh
28 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh
27 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh
26 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh
25 64/32 190000h-19FFFFh 0C8000h-0CFFFFh
24 64/32 180000h-18FFFFh 0C0000h-0C7FFFh
23 64/32 170000h-17FFFFh 0B8000h-0BFFFFh
22 64/32 160000h-16FFFFh 0B0000h-0B7FFFh
21 64/32 150000h-15FFFFh 0A8000h-0AFFFFh
20 64/32 140000h-14FFFFh 0A0000h-0A7FFFh
19 64/32 130000h-13FFFFh 098000h-09FFFFh
18 64/32 120000h-12FFFFh 090000h-097FFFh
17 64/32 110000h-11FFFFh 088000h-08FFFFh
16 64/32 100000h-10FFFFh 080000h-087FFFh
15 64/32 0F0000h-0FFFFFh 078000h-07FFFFh
14 64/32 0E0000h-0EFFFFh 070000h-077FFFh
13 64/32 0D0000h-0DFFFFh 068000h-06FFFFh
12 64/32 0C0000h-0CFFFFh 060000h-067FFFh
11 64/32 0B0000h-0BFFFFh 058000h-05FFFFh
10 64/32 0A0000h-0AFFFFh 050000h-057FFFh
Size
(KByte/
KWord)
Address Range
(x8)
Address Range
(x16)
#
66
65
64
16/8 3FC000h-3FFFFFh 1FE000h-1FFFFFh
8/4
8/4
3FA000h-3FBFFFh 1FD000h-1FDFFFh
3F8000h-3F9FFFh 1FC000h-1FCFFFh
63 32/16 3F0000h-3F7FFFh 1F8000h-1FBFFFh
62 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh
61 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh
60 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh
59 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh
58 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh
57 64/32 390000h-39FFFFh 1C8000h-1CFFFFh
56 64/32 380000h-18FFFFh 1C0000h-1C7FFFh
55 64/32 370000h-37FFFFh 1B8000h-1BFFFFh
54 64/32 360000h-36FFFFh 1B0000h-1B7FFFh
53 64/32 350000h-35FFFFh 1A8000h-1AFFFFh
52 64/32 340000h-34FFFFh 1A0000h-1A7FFFh
51 64/32 330000h-33FFFFh 198000h-19FFFFh
50 64/32 320000h-32FFFFh 190000h-197FFFh
49 64/32 310000h-31FFFFh 188000h-18FFFFh
48 64/32 300000h-30FFFFh 180000h-187FFFh
47 64/32 2F0000h-2FFFFFh 178000h-17FFFFh
46 64/32 2E0000h-2EFFFFh 170000h-177FFFh
45 64/32 2D0000h-2DFFFFh 168000h-16FFFFh
44 64/32 2C0000h-2CFFFFh 160000h-167FFFh
43 64/32 2B0000h-2BFFFFh 158000h-15FFFFh
42 64/32 2A0000h-2AFFFFh 150000h-157FFFh
41 64/32 290000h-29FFFFh 148000h-14FFFFh
40 64/32 280000h-28FFFFh 140000h-147FFFh
39 64/32 270000h-27FFFFh 138000h-13FFFFh
38 64/32 260000h-26FFFFh 130000h-137FFFh
37 64/32 250000h-25FFFFh 128000h-12FFFFh
36 64/32 240000h-24FFFFh 120000h-127FFFh
35 64/32 230000h-23FFFFh 118000h-11FFFFh
9
8
7
6
5
4
3
2
1
0
64/32 090000h-09FFFFh 048000h-04FFFFh
64/32 080000h-08FFFFh 040000h-047FFFh
64/32 070000h-07FFFFh 038000h-03FFFFh
64/32 060000h-06FFFFh 030000h-037FFFh
64/32 050000h-05FFFFh 028000h-02FFFFh
64/32 040000h-04FFFFh 020000h-027FFFh
64/32 030000h-03FFFFh 018000h-01FFFFh
64/32 020000h-02FFFFh 010000h-017FFFh
64/32 010000h-01FFFFh 008000h-00FFFFh
64/32 000000h-00FFFFh 000000h-007FFFh
34/46
M29W320DT, M29W320DB
Table 20. Bottom Boot Block Addresses,
M29W320DB
34 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh
33 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh
32 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh
31 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh
30 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh
29 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh
28 64/32 190000h-19FFFFh 0C8000h-0CFFFFh
27 64/32 180000h-18FFFFh 0C0000h-0C7FFFh
26 64/32 170000h-17FFFFh 0B8000h-0BFFFFh
25 64/32 160000h-16FFFFh 0B0000h-0B7FFFh
24 64/32 150000h-15FFFFh 0A8000h-0AFFFFh
23 64/32 140000h-14FFFFh 0A0000h-0A7FFFh
22 64/32 130000h-13FFFFh 098000h-09FFFFh
21 64/32 120000h-12FFFFh 090000h-097FFFh
20 64/32 110000h-11FFFFh 088000h-08FFFFh
19 64/32 100000h-10FFFFh 080000h-087FFFh
18 64/32 0F0000h-0FFFFFh 078000h-07FFFFh
17 64/32 0E0000h-0EFFFFh 070000h-077FFFh
16 64/32 0D0000h-0DFFFFh 068000h-06FFFFh
15 64/32 0C0000h-0CFFFFh 060000h-067FFFh
14 64/32 0B0000h-0BFFFFh 058000h-05FFFFh
13 64/32 0A0000h-0AFFFFh 050000h-057FFFh
12 64/32 090000h-09FFFFh 048000h-04FFFFh
11 64/32 080000h-08FFFFh 040000h-047FFFh
10 64/32 070000h-07FFFFh 038000h-03FFFFh
Size
(KByte/
KWord)
Address Range
(x8)
Address Range
(x16)
#
66 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh
65 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh
64 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh
63 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh
62 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh
61 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh
60 64/32 390000h-39FFFFh 1C8000h-1CFFFFh
59 64/32 380000h-18FFFFh 1C0000h-1C7FFFh
58 64/32 370000h-37FFFFh 1B8000h-1BFFFFh
57 64/32 360000h-36FFFFh 1B0000h-1B7FFFh
56 64/32 350000h-35FFFFh 1A8000h-1AFFFFh
55 64/32 340000h-34FFFFh 1A0000h-1A7FFFh
54 64/32 330000h-33FFFFh 198000h-19FFFFh
53 64/32 320000h-32FFFFh 190000h-197FFFh
52 64/32 310000h-31FFFFh 188000h-18FFFFh
51 64/32 300000h-30FFFFh 180000h-187FFFh
50 64/32 2F0000h-2FFFFFh 178000h-17FFFFh
49 64/32 2E0000h-2EFFFFh 170000h-177FFFh
48 64/32 2D0000h-2DFFFFh 168000h-16FFFFh
47 64/32 2C0000h-2CFFFFh 160000h-167FFFh
46 64/32 2B0000h-2BFFFFh 158000h-15FFFFh
45 64/32 2A0000h-2AFFFFh 150000h-157FFFh
44 64/32 290000h-29FFFFh 148000h-14FFFFh
43 64/32 280000h-28FFFFh 140000h-147FFFh
42 64/32 270000h-27FFFFh 138000h-13FFFFh
41 64/32 260000h-26FFFFh 130000h-137FFFh
40 64/32 250000h-25FFFFh 128000h-12FFFFh
39 64/32 240000h-24FFFFh 120000h-127FFFh
38 64/32 230000h-23FFFFh 118000h-11FFFFh
37 64/32 220000h-22FFFFh 110000h-117FFFh
36 64/32 210000h-21FFFFh 108000h-10FFFFh
35 64/32 200000h-20FFFFh 100000h-107FFFh
9
8
7
6
5
4
3
2
1
0
64/32 060000h-06FFFFh 030000h-037FFFh
64/32 050000h-05FFFFh 028000h-02FFFFh
64/32 040000h-04FFFFh 020000h-027FFFh
64/32 030000h-03FFFFh 018000h-01FFFFh
64/32 020000h-02FFFFh 010000h-017FFFh
64/32 010000h-01FFFFh 008000h-00FFFFh
32/16 008000h-00FFFFh 004000h-007FFFh
8/4
8/4
006000h-007FFFh 003000h-003FFFh
004000h-005FFFh 002000h-002FFFh
000000h-003FFFh 000000h-001FFFh
16/8
35/46
M29W320DT, M29W320DB
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
is read from the memory. Table 21., Table 22., Ta-
ble 23., Table 24., Table 25. and Table 26. show
the addresses used to retrieve the data.
The CFI data structure also contains a security
area where a 64 bit unique security number is writ-
ten (see Table 26., Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num-
ber after it has been written by ST. Issue a Read
command to return to Read mode.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
Table 21. Query Structure Overview
Address
Sub-section Name
Description
x16
10h
1Bh
27h
x8
20h
36h
4Eh
CFI Query Identification String
System Interface Information
Device Geometry Definition
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
40h
80h
61h
C2h
Security Code Area
64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 22. CFI Query Identification String
Address
Data
Description
Value
x16
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
x8
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
“Q”
"R"
"Y"
Query Unique ASCII String "QRY"
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
AMD
Compatible
Address for Primary Algorithm extended Query table (see Table 24.)
P = 40h
NA
Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported
Address for Alternate Algorithm extended Query table
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
36/46
M29W320DT, M29W320DB
Table 23. CFI Query System Interface Information
Address
Data
Description
Value
x16
x8
V
V
V
V
Logic Supply Minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
CC
1Bh
36h
0027h
0036h
00B5h
00C5h
2.7V
3.6V
Logic Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
CC
1Ch
1Dh
1Eh
38h
3Ah
3Ch
[Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
PP
11.5V
12.5V
[Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
PP
bit 3 to 0BCD value in 100 mV
n
1Fh
20h
21h
22h
23h
24h
25h
26h
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
16µs
NA
Typical timeout per single byte/word program = 2 µs
n
Typical timeout for minimum size write buffer program = 2 µs
n
1s
Typical timeout per individual block erase = 2 ms
n
NA
Typical timeout for full chip erase = 2 ms
n
512µs
NA
Maximum timeout for byte/word program = 2 times typical
n
Maximum timeout for write buffer program = 2 times typical
n
16s
NA
Maximum timeout per individual block erase = 2 times typical
n
Maximum timeout for chip erase = 2 times typical
Table 24. Device Geometry Definition
Address
Data
Description
Value
x16
x8
n
27h
4Eh
0016h
4 MByte
Device Size = 2 in number of bytes
28h
29h
50h
52h
0002h
0000h
x8, x16
Async.
Flash Device Interface Code description
2Ah
2Bh
54h
56h
0000h
0000h
n
NA
4
Maximum number of bytes in multi-byte program or page = 2
Number of Erase Block Regions within the device.
2Ch
58h
0004h
It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size.
2Dh
2Eh
5Ah
5Ch
0000h
0000h
Region 1 Information
Number of identical size erase block = 0000h+1
1
2Fh
30h
5Eh
60h
0040h
0000h
Region 1 Information
Block size in Region 1 = 0040h * 256 byte
16 Kbyte
2
31h
32h
62h
64h
0001h
0000h
Region 2 Information
Number of identical size erase block = 0001h+1
33h
34h
66h
68h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
8 Kbyte
37/46
M29W320DT, M29W320DB
Address
Data
Description
Value
x16
x8
35h
36h
6Ah
6Ch
0000h
0000h
Region 3 Information
Number of identical size erase block = 0000h+1
1
37h
38h
6Eh
70h
0080h
0000h
Region 3 Information
Block size in Region 3 = 0080h * 256 byte
32 Kbyte
63
39h
3Ah
72h
74h
003Eh
0000h
Region 4 Information
Number of identical-size erase block = 003Eh+1
3Bh
3Ch
76h
78h
0000h
0001h
Region 4 Information
Block size in Region 4 = 0100h * 256 byte
64 Kbyte
Table 25. Primary Algorithm-Specific Extended Query Table
Address
Data
Description
Value
x16
40h
41h
42h
43h
44h
45h
x8
80h
82h
84h
86h
88h
8Ah
0050h
0052h
0049h
0031h
0030h
0000h
"P"
"R"
"I"
Primary Algorithm extended Query table unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
"1"
"0"
Yes
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
46h
47h
48h
49h
8Ch
8Eh
90h
92h
0002h
0001h
0001h
0004h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
1
Block Protection
00 = not supported, x = number of blocks in per group
Temporary Block Unprotect
00 = not supported, 01 = supported
Yes
4
Block Protect /Unprotect
04 = M29W400B
4Ah
4Bh
4Ch
4Dh
94h
96h
98h
9Ah
0000h
0000h
0000h
00B5h
Simultaneous Operations, 00 = not supported
No
No
Burst Mode, 00 = not supported, 01 = supported
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
No
V
Supply Minimum Program/Erase voltage
11.5V
PP
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
4Eh
4Fh
9Ch
9Eh
00C5h
000xh
V
Supply Minimum Program/Erase voltage
12.5V
–
PP
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
Top/Bottom Boot Block Flag
02h = Bottom Boot device, 03h = Top Boot device
38/46
M29W320DT, M29W320DB
Table 26. Security Code Area
Address
Data
Description
x16
61h
62h
63h
64h
x8
C3h, C2h
C5h, C4h
C7h, C6h
C9h, C8h
XXXX
XXXX
XXXX
XXXX
64 bit: unique device number
39/46
M29W320DT, M29W320DB
APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example, the tech-
niques for AMD parts will not work on STMicro-
electronics parts. Care should be taken when
changing drivers for one part to work on another.
Programmer Technique Bus Operations, gives a
summary of each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the micro-
processor bus, therefore this technique is suitable
for use after the Flash has been fitted to the sys-
tem.
To protect a block follow the flowchart in Figure
Figure 23., In-System Block Protect Flowchart. To
unprotect the whole chip it is necessary to protect
all of the blocks first, then all the blocks can be un-
protected at the same time. To unprotect the chip
follow Figure Figure 24., In-System Chip Unpro-
tect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Programmer Technique
The Programmer technique uses high (V ) volt-
ID
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure
Figure 21., Programmer Equipment Block Protect
Flowchart. To unprotect the whole chip it is neces-
sary to protect all of the blocks first, then all blocks
can be unprotected at the same time. To unprotect
the chip follow Figure Figure 22., Programmer
Equipment Chip Unprotect Flowchart. Table 27.,
Table 27. Programmer Technique Bus Operations, BYTE = V or V
IH
IL
Address Inputs
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Operation
Block Protect
E
G
W
A0-A20
A9 = V , A12-A20 Block Address
ID
V
IL
V
ID
V
V
Pulse
Pulse
X
X
IL
Others = X
A9 = V , A12 = V , A15 = V
ID
IH
IH
V
ID
V
ID
Chip Unprotect
IL
Others = X
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IL
ID
Block Protection
Verify
Pass = XX01h
Retry = XX00h
V
V
V
V
A12-A20 Block Address
Others = X
IL
IL
IL
IL
IH
A0 = V , A1 = V , A6 = V , A9 = V ,
IL
IH
IH
ID
Block Unprotection
Verify
Retry = XX01h
Pass = XX00h
V
V
IH
A12-A20 Block Address
Others = X
40/46
M29W320DT, M29W320DB
Figure 21. Programmer Equipment Block Protect Flowchart
START
ADDRESS = BLOCK ADDRESS
W = V
IH
n = 0
G, A9 = V
E = V
,
ID
IL
Wait 4µs
W = V
IL
Wait 100µs
W = V
IH
E, G = V
,
IH
A0, A6 = V
A1 = V
,
IL
IH
E = V
IL
Wait 4µs
G = V
IL
Wait 60ns
Read DATA
DATA
=
01h
NO
YES
++n
= 25
NO
A9 = V
E, G = V
IH
IH
YES
PASS
A9 = V
IH
E, G = V
IH
AI03469
FAIL
41/46
M29W320DT, M29W320DB
Figure 22. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
(1)
A6, A12, A15 = V
IH
E, G, A9 = V
ID
Wait 4µs
W = V
IL
Wait 10ms
W = V
IH
E, G = V
IH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1, A6 = V
IL
IH
E = V
IL
Wait 4µs
G = V
IL
INCREMENT
CURRENT BLOCK
Wait 60ns
Read DATA
NO
YES
DATA
=
00h
LAST
BLOCK
NO
NO
++n
= 1000
YES
YES
A9 = V
IH
A9 = V
IH
E, G = V
E, G = V
IH
IH
FAIL
PASS
AI03470
42/46
M29W320DT, M29W320DB
Figure 23. In-System Equipment Block Protect Flowchart
START
n = 0
RP = V
ID
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
Wait 100µs
WRITE 40h
IL
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
Wait 4µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IL
DATA
NO
=
01h
YES
++n
= 25
NO
RP = V
IH
YES
ISSUE READ/RESET
COMMAND
RP = V
IH
PASS
ISSUE READ/RESET
COMMAND
FAIL
AI03471
43/46
M29W320DT, M29W320DB
Figure 24. In-System Equipment Chip Unprotect Flowchart
START
PROTECT ALL BLOCKS
n = 0
CURRENT BLOCK = 0
RP = V
ID
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
IH
IH
WRITE 60h
ANY ADDRESS WITH
A0 = V , A1 = V , A6 = V
IL
IH
Wait 10ms
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
Wait 4µs
INCREMENT
CURRENT BLOCK
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = V , A1 = V , A6 = V
IL
IH
IH
DATA
NO
YES
=
00h
++n
= 1000
NO
NO
LAST
BLOCK
YES
RP = V
YES
RP = V
IH
IH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PASS
FAIL
AI03472
44/46
M29W320DT, M29W320DB
REVISION HISTORY
Table 28. Document Revision History
Date
Version
-01
Revision Details
March-2001
08-Jun-2001
First Issue (Brief Data)
Document expanded to full Product Preview
-02
Minor text corrections to Read/Reset and Read CFI commands and Status Register Error
and Toggle Bits.
22-Jun-2001
-03
Document type: from Product Preview to Preliminary Data
TFBGA connections and Block Addresses (x16) diagrams clarification
Write Protect and Block Unprotect clarification
27-Jul-2001
-04
CFI Primary Algorithm table, Block Protection change
Added Block Protection Appendix
“Write Protect/V ” pin renamed to “V /Write Protect” to be consistent with abbreviation.
PP
PP
Changes to the V /WP pin description, Figure Figure 17. and Table 14.. I added to
PP
PP
05-Oct-2001
-05
Table 10. and I
clarified. Modified description of V /WP operation in Unlock Bypass
PP
CC3
Command section. Added V /WP decoupling capacitor to Figure Figure 12..
PP
Clarified Read/Reset operation during Erase Suspend.
07-Feb-2002
05-Apr-2002
-06
-07
TFBGA package changed from 48 ball to 63 ball
Description of Ready/Busy signal clarified (and Figure 16 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
Erase Suspend Latency Time (typical and maximum) added to Program, Erase Times
and Program, Erase Endurance Cycles table.
Typical values added for Icc1 and Icc2 in DC characteristics table.
Logic Diagram and Data Toggle Flowchart corrected.
19-Nov-2002
7.1
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 07 equals 7.0). Document promoted to full datasheet.
Data Retention added to Table 5., Program, Erase Times and Program, Erase Endurance
Cycles, and Typical after 100k W/E Cycles column removed. TSOP48 package
mechanical updated. Lead-free package options E and F added to Table 18., Ordering
Information Scheme.
26-May-2003
16-Aug-2005
7.2
8.0
TFBGA48 package added throughout document.
45/46
M29W320DT, M29W320DB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such
information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support
devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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46/46
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