M29W800B120M6TR_技术文档

M29W800T

M29W800B

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

Low Voltage Single Supply Flash Memory

NOT FOR NEW DESIGN

M29W800T and M29W800B are replaced

respectively by the M29W800AT and

M29W800AB

2.7V to 3.6V SUPPLY VOLTAGEfor

PROGRAM, ERASE and READ OPERATIONS

FASTACCESS TIME: 90ns

44

FAST PROGRAMMING TIME

– 10µs by Byte / 20µs by Word typical

PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte or Word-by-Word

– Status Register bits and Ready/Busy Output

MEMORY BLOCKS

1

TSOP48 (N)

12 x 20 mm

SO44 (M)

– Boot Block (Top or Bottom location)

– Parameterand Main blocks

BLOCK, MULTI-BLOCK and CHIP ERASE

MULTI BLOCK PROTECTION/TEMPORARY

UNPROTECTION MODES

Figure 1. Logic Diagram

ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

LOW POWER CONSUMPTION

– Stand-byand AutomaticStand-by

100,000 PROGRAM/ERASE CYCLES per

BLOCK

V

CC

20 YEARSDATARETENTION

– Defectivity below 1ppm/year

ELECTRONIC SIGNATURE

19

15

A0-A18

DQ0-DQ14

– ManufacturerCode: 0020h

– Device Code, M29W800T: 00D7h

– Device Code, M29W800B: 005Bh

W

E

DQ15A–1

BYTE

RB

M29W800T

M29W800B

G

DESCRIPTION

RP

The M29W800 is a non-volatile memory that may

be erased electrically at the block or chiplevel and

programmedin-systemona Byte-by-Byteor Word-

by-Wordbasisusing onlya single2.7V to3.6V V_CC

supply. For Program and Erase operations the

necessary high voltages are generated internally.

The device can also be programmed in standard

programmers.

V

SS

AI02178

The array matrix organisationallows each block to

be erased and reprogrammed without affecting

other blocks. Blocks can be protectedagainst pro-

graming and erase on programming equipment,

June 1999

1/33

This is informationon a product still in productionbut not recommended for new designs.

M29W800T, M29W800B

Figure 2A. TSOP Pin Connections

Figure 2B. TSOP Reverse Pin Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

1

48

A15

A14

A13

A12

A11

A10

A9

BYTE

V

SS

DQ15A–1

SS

DQ15A–1

DQ7

DQ14

DQ6

DQ14

DQ6

A8

DQ13

DQ5

DQ13

DQ5

A8

NC

W

NC

W

DQ12

DQ4

DQ12

DQ4

M29W800T

M29W800B

(Normal)

M29W800T

M29W800B

(Reverse)

RP

NC

RB

A18

A17

A7

12

13

37

36

V

12

13

37

36

RP

NC

RB

A18

A17

A7

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

A6

A5

A4

A3

V

E

V

A3

SS

E

A2

A1

24

25

A0

24

25

A1

AI02179

AI02180

Warning: NC = Not Connected.

Figure 2C. SO Pin Connections

Table 1. Signal Names

A0-A18

DQ0-DQ7

DQ8-DQ14

DQ15A–1

E

Address Inputs

RB

A18

A17

A7

A6

A5

A4

A3

A2

A1

A0

E

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

RP

Data Input/Outputs, Command Inputs

Data Input/Outputs

2

W

3

A8

4

A9

5

A10

A11

A12

A13

A14

A15

A16

BYTE

Data Input/Output or Address Input

Chip Enable

6

7

8

9

G

Output Enable

10

11

12

13

14

15

16

17

18

19

20

21

22

M29W800T

M29W800B

W

Write Enable

V

RP

Reset / Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organisation

Supply Voltage

SS

G

SS

DQ15A–1

DQ0

DQ8

DQ7

RB

DQ14

DQ6

BYTE

V_CC

DQ1

DQ9

DQ13

DQ5

DQ2

DQ10

DQ3

DQ12

DQ4

V_SS

Ground

DQ11

V

CC

AI02181

2/33

M29W800T, M29W800B

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

Unit

Ambient Operating Temperature ⁽³⁾

Temperature Under Bias

Storage Temperature

–40 to 85

–50 to 125

–65 to 150

–0.6 to 5

C

°

T_BIAS

T_STG

C

°

C

°

(2)

V_IO

Input or Output Voltages

Supply Voltage

V

V_CC

–0.6 to 5

V

(2)

V_{(A9, E, G, RP)}

A9, E, G, RP Voltage

–0.6 to 13.5

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”AbsoluteMaximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltagemay undershoot to –2V during transitionand for less than 20ns.

3. Depends on range.

the P/E.C operations. A Ready/Busy RB output

indicates the completionof the internal algorithms.

DESCRIPTION (Cont’d)

and temporarily unprotected to make changes in

the application. Each block can be programmed

and erased over 100,000 cycles.

Memory Blocks

The devices feature asymmetrically blockedarchi-

tectureprovidingsystem memory integration.Both

M29W800Tand M29W800Bdeviceshavean array

of 19 blocks, one Boot Block of 16 KBytes or 8

KWords, two Parameter Blocks of 8 KBytes or 4

KWords, one Main Block of 32 KBytes or 16

KWordsand fifteenMain Blocksof 64 KBytesor 32

KWords.TheM29W800Thas theBoot Blockatthe

top of the memory address space and the

M29W800B locates the Boot Block starting at the

bottom. The memory maps are showed in Figure

3.

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature or Block Protection

status,Programming, Blockand ChipErase, Erase

Suspend and Resume are written to the device in

cyclesof commandstoa CommandInterfaceusing

standardmicroprocessor write timings.

The device is offeredin TSOP48(12 x 20mm) and

SO44 packages.Both normal and reversepinouts

are available for the TSOP48package.

Organisation

TheM29W800 is organisedas 1 Mx8 or 512Kx16

bits selectable by the BYTEsignal. When BYTEis

Low the Byte-wide x8 organisationis selectedand

the address lines are DQ15A–1 and A0-A18. The

Data Input/Output signal DQ15A–1 acts as ad-

dress line A–1 which selects the lower or upper

Byte of the memory word for output on DQ0-DQ7,

DQ8-DQ14 remain at High impedance. When

BYTEis Highthe memoryuses the addressinputs

A0-A18 and the Data Input/Outputs DQ0-DQ15.

Memory control is provided by Chip Enable E,

Output Enable G and Write Enable W inputs.

Each block can be erased separately, any combi-

nation of blocks can be specified for multi-block

erase or the entire chip may be erased. The Erase

operations are managed automatically by the

P/E.C. The block erase operation can be sus-

pended in order to read from or program to any

block not being ersased, and then resumed.

Block protection provides additional data security.

Each block can be separately protected or unpro-

tected against Program or Erase on programming

equipment. All previously protected blocks can be

temporarily unprotectedin the application.

AReset/BlockTemporaryUnprotection RPtri-level

input provides a hardware reset when pulled Low,

andwhen heldHigh(atV_ID)temporarily unprotects

blocks previously protected allowing them to be

programedand erased.Erase andProgramopera-

tions are controlled by an internal Program/Erase

Controller(P/E.C.). StatusRegisterdata output on

DQ7 provides a Data Polling signal, and DQ6 and

DQ2 provide Toggle signals to indicatethe state of

Bus Operations

The following operations can be performed using

theappropriatebus cycles:Read(Array, Electronic

Signature, Block Protection Status), Write com-

mand, Output Disable, Standby,Reset, Block Pro-

tection, Unprotection, Protection Verify,

Unprotection Verify and Block Temporary Unpro-

tection. See Tables4 and 5.

3/33

M29W800T, M29W800B

Figure 3A. Top Boot Block Memory Map and Block Address Table

TOP BOOT BLOCK

Word-Wide

7FFFFh

Byte-Wide

FFFFFh

Byte-Wide Word-Wide

FFFFFh

7FFFFh

16K BOOT BLOCK

8K PARAMETER BLOCK

32K MAIN BLOCK

78000h

77FFFh

F0000h

EFFFFh

FC000h

FBFFFh

7E000h

7DFFFh

64K MAIN BLOCK

70000h

6FFFFh

E0000h

DFFFFh

FA000h

F9FFFh

7D000h

7CFFFh

68000h

67FFFh

D0000h

CFFFFh

F8000h

F7FFFh

7C000h

7BFFFh

60000h

5FFFFh

C0000h

BFFFFh

F0000h

78000h

58000h

57FFFh

B0000h

AFFFFh

50000h

4FFFFh

A0000h

9FFFFh

48000h

47FFFh

90000h

8FFFFh

40000h

3FFFFh

80000h

7FFFFh

38000h

37FFFh

70000h

6FFFFh

30000h

2FFFFh

60000h

5FFFFh

28000h

27FFFh

50000h

4FFFFh

20000h

1FFFFh

40000h

3FFFFh

18000h

17FFFh

30000h

2FFFFh

10000h

0FFFFh

20000h

1FFFFh

08000h

07FFFh

10000h

0FFFFh

00000h

AI01725B

4/33

M29W800T, M29W800B

Figure 3B. Bottom Boot Block Memory Map and Block Address Table

BOTTOM BOOT BLOCK

Word-Wide

7FFFFh

Byte-Wide

FFFFFh

64K MAIN BLOCK

78000h

77FFFh

F0000h

EFFFFh

70000h

6FFFFh

E0000h

DFFFFh

68000h

67FFFh

D0000h

CFFFFh

60000h

5FFFFh

C0000h

BFFFFh

58000h

57FFFh

B0000h

AFFFFh

50000h

4FFFFh

A0000h

9FFFFh

48000h

47FFFh

90000h

8FFFFh

40000h

3FFFFh

80000h

7FFFFh

38000h

37FFFh

70000h

6FFFFh

30000h

2FFFFh

60000h

5FFFFh

28000h

27FFFh

50000h

4FFFFh

Byte-Wide Word-Wide

20000h

1FFFFh

40000h

3FFFFh

0FFFFh

07FFFh

32K MAIN BLOCK

8K PARAMETER BLOCK

16K BOOT BLOCK

18000h

17FFFh

30000h

2FFFFh

08000h

07FFFh

04000h

03FFFh

10000h

0FFFFh

20000h

1FFFFh

06000h

05FFFh

03000h

02FFFh

08000h

07FFFh

10000h

0FFFFh

04000h

03FFFh

02000h

01FFFh

00000h

AI01731B

5/33

M29W800T, M29W800B

Table 3A. M29W800TBlock Address Table

Address Range (x8)

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-7FFFFh

80000h-8FFFFh

90000h-9FFFFh

A0000h-AFFFFh

B0000h-BFFFFh

C0000h-CFFFFh

D0000h-DFFFFh

E0000h-EFFFFh

F0000h-F7FFFh

F8000h-F9FFFh

FA000h-FBFFFh

FC000h-FFFFFh

Address Range (x16)

00000h-07FFFh

08000h-0FFFFh

10000h-17FFFh

18000h-1FFFFh

20000h-27FFFh

28000h-2FFFFh

30000h-37FFFh

38000h-3FFFFh

40000h-47FFFh

48000h-4FFFFh

50000h-57FFFh

58000h-5FFFFh

60000h-67FFFh

68000h-6FFFFh

70000h-77FFFh

78000h-7BFFFh

7C000h-7CFFFh

7D000h-7DFFFh

7E000h-7FFFFh

A18

0

A17

0

A16

0

A15

0

A14

X

0

A13

X

0

A12

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Command Interface

This Coded sequence is the same for all Pro-

gram/Erase Controller instructions. The ’Com-

mand’ itself and its confirmation, when applicable,

are given on the third, fourth or sixth cycles. Any

incorrect command or any improper command se-

quence will reset the device to Read Array mode.

Instructions, made up of commands written in cy-

cles, can be givento theProgram/EraseController

through a Command Interface (C.I.). For added

data protection, program or erase executionstarts

after4 or 6 cycles. Thefirst, second,fourthand fifth

cycles are used to input Coded cycles to the C.I.

6/33

M29W800T, M29W800B

Table 3B. M29W800B Block Address Table

Address Range (x8)

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-7FFFFh

80000h-8FFFFh

90000h-9FFFFh

A0000h-AFFFFh

B0000h-BFFFFh

C0000h-CFFFFh

D0000h-DFFFFh

E0000h-EFFFFh

F0000h-FfFFFh

Address Range (x16)

00000h-01FFFh

02000h-02FFFh

03000h-03FFFh

04000h-07FFFh

08000h-0FFFFh

10000h-17FFFh

18000h-1FFFFh

20000h-27FFFh

28000h-2FFFFh

30000h-37FFFh

38000h-3FFFFh

40000h-47FFFh

48000h-4FFFFh

50000h-57FFFh

58000h-5FFFFh

60000h-67FFFh

68000h-6FFFFh

70000h-77FFFh

78000h-7FFFFh

A18

0

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

0

1

0

1

0

1

X

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Instructions

data, Electronic Signature or Block Protection

Status for Read operations. In order to give addi-

tional data protection, the instructions for Program

and Block or Chip Erase require further command

inputs. For a Program instruction, the fourth com-

mand cycle inputs the address and data to be

programmed. For an Erase instruction (Block or

Chip), the fourth and fifth cycles input a further

Coded sequence before the Erase confirm com-

mandonthe sixthcycle. Erasureof amemoryblock

may be suspended, in order to read data from

anotherblock or to programdata in another block,

and then resumed.

Seven instructions are defined to perform Read

Array,AutoSelect(toread the ElectronicSignature

or Block ProtectionStatus), Program, BlockErase,

Chip Erase, Erase Suspend and Erase Resume.

The internal P/E.C. automatically handles all tim-

ing and verification of the Program and Erase

operations.TheStatus RegisterData Polling,Tog-

gle, Error bits and the RB output may be read at

any time, during programmingor erase, to monitor

the progress of the operation.

Instructions are composed of up to six cycles. The

first two cycles input a Coded sequence to the

CommandInterfacewhich iscommontoall instruc-

tions (see Table 8).

When power is first applied or if V_CCfalls below

V_LKO, the command interface is reset to Read

Array.

The third cycle inputs the instruction set-up com-

mand. Subsequent cycles output the addressed

7/33

M29W800T, M29W800B

SIGNAL DESCRIPTIONS

impedance. G must be forced to V_IDlevel during

Block Protection and Unprotection operations.

See Figure 1 and Table1.

WriteEnable (W). This inputcontrols writing to the

CommandRegisterand Addressand Datalatches.

Address Inputs (A0-A18). The address inputs for

the memory array are latchedduring a write opera-

tion on the falling edge at Chip Enable E or Write

Enable W. In Word-wide organisation the address

lines are A0-A18, in Byte-wide organisation

DQ15A–1 acts as an additional LSB address line.

When A9 is raised to V_ID, either a Read Electronic

Signature Manufacturer or Device Code, Block

Protection Status or a Write Block Protection or

Block Unprotection is enabled depending on the

combinationof levelson A0, A1, A12 and A15.

Byte/Word Organization Select (BYTE). The

BYTE input selects the outputconfigurationfor the

device: Byte-wide (x8) mode or Word-wide (x16)

mode. When BYTEis Low, the Byte-wide mode is

selectedand the data is read and programmed on

DQ0-DQ7. In this mode, DQ8-DQ14 are at high

impedance and DQ15A–1 is the LSB address.

When BYTE is High, the Word-wide mode is se-

lected and the data is read and programmed on

DQ0-DQ15.

Data Input/Outputs (DQ0-DQ7). These In-

puts/Outputsare used in the Byte-wideand Word-

wide organisations. The input is data to be

programmed in the memory array or a command

to be written to the C.I. Both are latched on the

rising edge of Chip Enable E or Write Enable W.

The output is data from the Memory Array, the

Electronic Signature Manufacturer or Device

codes, the Block Protection Status or the Status

register Data Polling bit DQ7, the ToggleBits DQ6

and DQ2, the Error bit DQ5 or the Erase Timer bit

DQ3. Outputs are valid when Chip Enable E and

Output Enable G are active. The output is high

impedance when the chip is deselected or the

outputsaredisabledand whenRPis ata Lowlevel.

Ready/Busy Output (RB). Ready/Busy is an

open-drainoutputandgivestheinternalstateof the

P/E.C. of the device. When RB is Low, the device

is Busy with a Program or Erase operation and it

will not accept any additional program or erase

instructions except the Erase Suspend instruction.

When RB is High, thedeviceis readyforany Read,

Program or Erase operation. The RB will also be

High when the memory is put in Erase Suspend or

Standby modes.

Reset/Block Temporary Unprotect Input (RP).

The RP Input provides hardware reset and pro-

tected block(s) temporary unprotection functions.

Reset of the memory is acheived by pulling RP to

V_ILforatleast t_PLPX. When the resetpulse is given,

if the memory is in Read or Standby modes, it will

be available for new operations in t_PHELafter the

rising edgeof RP. If the memoryis in Erase, Erase

Suspend or Program modes the reset will take

t_PLYHduring which the RB signal will be held at V_IL.

The end of the memory reset will be indicated by

the rising edge of RB. A hardware reset during an

Erase or Program operation will corrupt the data

being programmed or the sector(s) being erased.

See Table 14 and Figure 9.

Data Input/Outputs (DQ8-DQ14 and DQ15A–1).

These Inputs/Outputs are additionally used in the

Word-wideorganisation.WhenBYTEis HighDQ8-

DQ14 and DQ15A–1 act as the MSB of the Data

Input or Output, functioning as described for DQ0-

DQ7 above, and DQ8 - DQ15 are ’don’t care’ for

command inputs or status outputs. When BYTEis

Low,DQ0-DQ14 are high impedance,DQ15A–1is

the Address A–1 input.

Chip Enable (E). The Chip Enable input activates

the memory control logic, input buffers, decoders

andsenseamplifiers.E Highdeselectsthememory

andreducesthe powerconsumptiontothestandby

level. E can also be used to control writing to the

command register and to the memory array, while

W remains ata low level. TheChip Enablemust be

forced to V_IDduringthe Block Unprotectionopera-

tion.

Temporary block unprotection is made by holding

RP at V_ID. In this condition previously protected

blocks can be programmed or erased. The transi-

tion of RP from V_IHto V_IDmustslower thant_PHPHH

.

See Table 15 and Figure 9. When RP is returned

from V_IDto V_IHall blocks temporarily unprotected

will be again protected.

V_CCSupply Voltage. The power supply for all

operations (Read, Program and Erase).

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. When G is High the outputs are High

V_SSGround. V_SSis the reference for all voltage

measurements.

8/33

M29W800T, M29W800B

DEVICE OPERATIONS

thecodesareoutput on DQ0-DQ7with DQ8-DQ14

at High impedance;if the Word-wide configuration

is selectedthe codes are output on DQ0-DQ7with

DQ8-DQ15 at 00h.

See Tables 4, 5 and 6.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register or the BlockProtection

Status. Both Chip Enable E and Output Enable G

must be low in order to read the output of the

memory.

Block Protection. Each block can be separately

protected against Program or Erase on program-

ming equipment. Block protection provides addi-

tional data security, as it disables all program or

eraseoperations.Thismode isactivatedwhenboth

A9 and G are raised to V_IDand an address in the

block is applied on A12-A18. Block protection is

initiated on the edge of W falling to V_IL. Then after

a delay of 100µs, the edge of W rising to V_IHends

the protectionoperations. Block protectionverifyis

achievedby bringingG, E, A0and A6 toV_ILandA1

to V_IH, while W is atV_IHand A9at V_ID. Underthese

conditions,reading the data output will yield 01h if

the block defined by the inputs on A12-A18 is

protected.Any attempt to programor erase a pro-

tected block will be ignored by the device.

Write. Writeoperationsare usedto giveInstruction

Commands to the memory or to latch input data to

be programmed.Awrite operationis initiatedwhen

Chip Enable E is Low and Write Enable W is Low

withOutput Enable G High. Addressesare latched

on the fallingedge of W or E whicheveroccurs last.

CommandsandInputDataarelatchedontherising

edge of W or E whichever occurs first.

Output Disable. The data outputsare high imped-

ance when the Output Enable G is High with Write

Enable W High.

Standby. The memory is in standby when Chip

Enable E is High and the P/E.C. is idle. The power

consumption is reduced to the standby level and

the outputs are high impedance, independent of

the Output Enable G or WriteEnable W inputs.

Block Temporary Unprotection. Any previously

protected block can be temporarily unprotectedin

ordertochangestored data. Thetemporaryunpro-

tection mode is activated by bringing RP to V_ID.

During the temporary unprotection mode the pre-

viously protected blocks are unprotected. A block

can be selected and data can be modified by

executingtheEraseor Programinstructionwiththe

Automatic Standby. After 150ns of bus inactivity

and when CMOS levels are driving the addresses,

the chip automatically enters a pseudo-standby

mode whereconsumptionis reducedto the CMOS

standbyvalue, while outputs still drive the bus.

RP signal held at V . When RP is returnedto V_IH,

ID

all the previously protected blocks are again pro-

tected.

Electronic Signature. Two codes identifying the

manufacturer and thedevice canbe read fromthe

memory. The manufacturer’s code for STMi-

croelectronicsis20h, the devicecodeis D7hfor the

M29W800T(TopBoot)and 5BhfortheM29W800B

(Bottom Boot). These codes allow programming

equipment or applications to automatically match

their interface to the characteristics of the

M29W800. The Electronic Signatureis outputby a

Read operation when the voltage applied to A9 is

at V_IDand addressinputsA1 is Low.The manufac-

turer code is output when the Address input A0 is

Low and the device code when this input is High.

Other Address inputs are ignored. The codes are

output on DQ0-DQ7.

Block Unprotection. All protected blocks can be

unprotected on programming equipment to allow

updating of bit contents. All blocks must first be

protectedbefore the unprotectionoperation.Block

unprotectionis activated when A9, G and E are at

V_IDand A12, A15 at V_IH. Unprotection is initiated

bytheedgeof WfallingtoV_IL. Afteradelayof10ms,

the unprotection operation will end. Unprotection

verify is achieved by bringing G and E to V_ILwhile

A0 is at V_IL, A6 and A1 are at V_IHand A9 remains

at V_ID. Inthese conditions,reading the output data

will yield 00h if the block defined by the inputs

A12-A18 has been succesfully unprotected. Each

block must be separately verified by giving its ad-

dress in order to ensure that it has been unpro-

tected.

TheElectronic Signaturecan alsobe read, without

raisingA9 toV_ID, bygiving the memory the Instruc-

tion AS. If the Byte-wide configuration is selected

9/33

M29W800T, M29W800B

Table 4. User Bus Operations ⁽¹⁾

DQ15

A–1

DQ8-

DQ14

Operation

Read Word

Read Byte

Write Word

Write Byte

E

G

W

RP

V_IH

BYTE

V_IH

A0

A1

A6

A9

A12 A15

DQ0-DQ7

Data

Output

Data

Output

Data

Output

V_IL

V_IH

V_IL

Address

Input

Data

Output

V_IL

Hi-Z

Data

Input

V_IH

A12 A15 Data Input Data Input

Address

Data

Input

V_IL

A12 A15

Hi-Z

Input

Hi-Z

Output Disable

Standby

V_IL

V_IH

X

V_IH

X

V_IH

X

V_IH

V_IL

X

Hi-Z

Reset

X

Block

V_IL

V_ID

V_IDV_ILPulse V_IH

X

V_ID

X

Protection^(2,4)

Blocks

V_IH

Unprotection⁽⁴⁾

Block

Protect

Status ⁽³⁾

Protection

V_IL

X

V_IL

X

V_IH

X

V_IH

V_ID

X

V_IL

X

V_IH

X

V_IL

V_IH

X

V_ID

X

A12 A15

X

Verify^(2,4)

Block

Protect

Status ⁽³⁾

Unprotection

Verify^(2,4)

Block

Temporary

X

Unprotection

Notes: 1. X = V_ILor V_IH

2. Block Address must be given on A12-A18 bits.

3. See Table 6.

4. Operation performed on programming equipment.

Table 5. Read Electronic Signature (following AS instruction or with A9 = V_ID)

Other

Addresses A–1

DQ15

DQ8-

DQ14

DQ0-

DQ7

Org.

Code

Device

E

G

W

BYTE

A0

A1

Manufact.

Code

V_IL

V_IH

V_IL

Don’t Care

0

00h

20h

Word-

wide

M29W800T V_IL

M29W800B V_IL

V_IL

V_IH

V_IL

Don’t Care

0

00h

D7h

5Bh

Device

Code

Manufact.

Code

Don’t

Care

V_IL

M29W800T V_IL

M29W800B V_IL

V_IL

V_IH

V_IL

V_IH

V_IL

Don’t Care

Hi-Z

20h

D7h

5Bh

Byte-

wide

Don’t

Care

Device

Code

Don’t

Care

Table 6. Read Block Protection with AS Instruction

Other

Code

E

G

W

A0

A1

A12-A18

DQ0-DQ7

Addresses

Don’t Care

Protected Block

V_IL

V_IH

V_IL

V_IH

Block Address

01h

00h

Unprotected Block

10/33

M29W800T, M29W800B

INSTRUCTIONS AND COMMANDS

monitor DQ7 in the Erase Suspend mode an ad-

dress within a block being erased must be pro-

vided. For a Read Operation in Erase Suspend

mode, DQ7 will output ’1’ if the read is attempted

ona blockbeingerasedand thedatavalueon other

blocks. During Program operation in Erase Sus-

pend Mode, DQ7 will have the same behaviour as

in the normal program execution outside of the

suspend mode.

Toggle Bit (DQ6). When Programming or Erasing

operationsare in progress,successiveattempts to

readDQ6will outputcomplementarydata.DQ6 will

toggle following toggling of either G, or E when G

is low. The operationis completed when two suc-

cessivereads yieldthe same outputdata. Thenext

readwilloutputthe bitlastprogrammedor a’1’after

erasing. The toggle bit DQ6 is valid only during

P/E.C. operations, that is after the fourth W pulse

for programming or after the sixth W pulse for

Erase. If the blocks selected for erasure are pro-

The Command Interface latches commands writ-

ten to the memory. Instructions are made up from

one or more commands to perform Read Memory

Array, Read ElectronicSignature,Read BlockPro-

tection, Program, Block Erase, Chip Erase, Erase

Suspend and Erase Resume. Commands are

made of address and data sequences. The in-

structionsrequire from1 to6 cycles,the firstor first

three of which are always write operationsused to

initiate the instruction. They are followed by either

furtherwrite cycles to confirmthe first command or

executethe commandimmediately.Command se-

quencing must be followed exactly. Any invalid

combination of commands will reset the device to

Read Array. The increased number of cycles has

been chosen to assure maximum data security.

Instructions are initialised by two initial Coded cy-

cleswhich unlock the CommandInterface.In addi-

tion, for Erase, instruction confirmation is again

preceded by the two Coded cycles.

tected, DQ6 will toggle for about 100 s and then

µ

returnback to Read.DQ6 willbe setto ’1’if a Read

operationis attemptedon anEraseSuspendblock.

When erase is suspended DQ6 will toggle during

programming operations in a block different to the

block in Erase Suspend. Either E or G toggling will

cause DQ6 to toggle. See Figure 12 for ToggleBit

flowchart and Figure 13 for Toggle Bit waveforms.

Status Register Bits

P/E.C.statusis indicatedduring executionby Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mandexecutionwill automaticallyoutput thesefive

StatusRegister bits. TheP/E.C. automaticallysets

bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits

(DQ0, DQ1 and DQ4) are reserved for future use

and should be masked. See Tables 9 and 10.

Table 7. Commands

Hex Code

00h

Command

Invalid/Reserved

Data Polling Bit (DQ7). When Programming op-

erations are in progress, this bit outputs the com-

plement of the bit being programmed on DQ7.

During Erase operation, it outputsa ’0’. After com-

pletion of the operation, DQ7 will output the bit last

programmed or a ’1’ after erasing. Data Polling is

valid and only effective during P/E.C. operation,

that is after the fourth W pulse for programmingor

after the sixth W pulse for erase. It must be per-

formed at the address being programmed or at an

address within the block being erased. If all the

blocksselectedfor erasureare protected,DQ7 will

be set to ’0’ for about 100µs, and then return to the

previous addressed memory data value. See Fig-

ure 11 for the Data Polling flowchart and Figure 10

for the Data Polling waveforms. DQ7 will also flag

the Erase Suspend mode by switching from ’0’ to

’1’ at the start of the Erase Suspend. In order to

10h

Chip Erase Confirm

Reserved

20h

30h

Block Erase Resume/Confirm

Set-up Erase

80h

Read Electronic Signature/

Block Protection Status

90h

A0h

B0h

F0h

Program

Erase Suspend

Read Array/Reset

11/33

M29W800T, M29W800B

Table 8. Instructions ⁽¹⁾

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

Addr. ^(3,7)

Data

X

1+

Read Memory Array until a new writecycle is initiated.

F0h

Read/Reset

MemoryArray

RD ^(2,4)

Byte

AAAAh

5555h

AAh

5555h

2AAAh

55h

AAAAh

5555h

F0h

Addr. ^(3,7)

Read Memory Array untila new write cycle

is initiated.

3+

Word

Data

Byte

AAAAh

5555h

AAh

5555h

2AAAh

55h

AAAAh

5555h

90h

Addr. ^(3,7)

Read Electronic Signature or Block

Protection Status until a new write cycle is

initiated. See Note 5 and 6.

AS ⁽⁴⁾

Auto Select

Program

Word

Data

Byte

AAAAh

5555h

2AAAh

AAAAh

5555h

Program

Address

Addr. ^(3,7)

Read Data Polling or Toggle Bit

until Program completes.

PG

4

Word

Program

Data

AAh

55h

A0h

Byte

AAAAh

5555h

AAh

AAAAh

5555h

AAh

X

5555h

2AAAh

55h

AAAAh

5555h

80h

AAAAh

5555h

AAh

5555h

2AAAh

55h

Block

Additional

Addr. ^(3,7)

Address Block ⁽⁸⁾

BE

CE

Block Erase

Chip Erase

6

Word

Data

30h

AAAAh

5555h

10h

30h

Byte

5555h

2AAAh

55h

AAAAh

5555h

80h

AAAAh

5555h

AAh

5555h

2AAAh

55h

Addr. ^(3,7)

Note 9

Word

Data

Addr. ^(3,7)

Data

Erase

Suspend

Read until Toggle stops, then read all the data needed from any

Block(s) not being erased then Resume Erase.

ES ⁽¹⁰⁾

1

B0h

Addr. ^(3,7)

Data

X

Erase

Resume

Read Data Polling or ToggleBits until Erase completes or Erase is

suspended another time

ER

30h

Notes: 1. Commands not interpreted in this table will default to read array mode.

2. Await of t_PLYHis necessary after a Read/Reset command if the memory was in an Erase or Program mode

before starting any new operation (see Table 14 and Figure 9).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after

the command cycles.

5. Signature Address bits A0,A1, at V_ILwill output Manufacturer code (20h). Address bits A0 at V_IHand A1, at V_ILwill output

Device code.

6. Block Protection Address: A0, at V_IL, A1 at V_IHand A15-A18 within the Block will output the Block Protection status.

7. For Coded cycles address inputs A15-A18are don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status

can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling

or Toggle bit until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

12/33

M29W800T, M29W800B

Table 9. Status Register Bits

DQ

Name

Logic Level

Definition

Note

Erase Complete or erase

block in Erase Suspend

’1’

’0’

Indicates the P/E.C. status, check during

Program or Erase, and on completion

before checking bits DQ5 for Program or

Erase Success.

Erase On-going

Data

Polling

7

Program Complete or data

of non erase block during

Erase Suspend

DQ

Program On-going

’-1-0-1-0-1-0-1-’ Erase or Program On-going

Successive reads output complementary

data on DQ6 while Programming or Erase

operations are on-going. DQ6 remains at

constant level when P/E.C. operations are

completed or Erase Suspend is

DQ

Program Complete

6

Toggle Bit

Erase Complete or Erase

’-1-1-1-1-1-1-1-’ Suspend on currently

addressed block

acknowledged.

’1’

’0’

Program or Erase Error

This bit is set to ’1’ in the case of

Programming or Erase failure.

5

4

Error Bit

Program or Erase On-going

Reserved

P/E.C. Erase operation has started. Only

possible command entry is Erase Suspend

(ES).

’1’

’0’

Erase Timeout Period Expired

Erase

Time Bit

3

Erase Timeout Period

On-going

An additional block to be erased in parallel

can be entered to the P/E.C.

Chip Erase, Erase or Erase

Suspend on the currently

addressed block.

Erase Error due to the

currently addressed block

(when DQ5 = ’1’).

’-1-0-1-0-1-0-1-’

Indicates the erase status and allows to

identify the erased block

2

Toggle Bit

Program on-going, Erase

on-going on another block or

Erase Complete

1

Erase Suspend read on

non Erase Suspend block

DQ

1

0

Reserved

Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.

13/33

M29W800T, M29W800B

Table 10. Polling and Toggle Bits

During the second cycle the Coded cycles consist

of writing the data 55h at address 5555h in the

Byte-wide configuration and at address 2AAAh in

the Word-wideconfiguration.Inthe Byte-widecon-

figurationthe addresslines A–1 to A14 are valid, in

Word-wideA0 to A15are valid, otheraddresslines

are ’don’t care’. The Coded cycles happen on first

and second cycles of the command write or on the

fourth and fifth cycles.

Mode

DQ7

0

DQ6

DQ2

Program

Erase

Toggle

1

Toggle Note 1

Erase Suspend Read

(in Erase Suspend

block)

1

Toggle

Instructions

See Table 8.

Erase Suspend Read

(outside Erase Suspend

block)

DQ7

DQ6

DQ2

N/A

Read/Reset (RD) Instruction. The Read/Reset

instruction consists of one write cycle giving the

commandF0h. It canbe optionallyprecededby the

twoCodedcycles.Subsequentread operationswill

read the memory array addressed and output the

data read. A wait state of 10µs is necessaryafter

Read/Reset prior to any valid read if the memory

was in an Erase mode when the RD instruction is

given.

Auto Select (AS) Instruction. This instruction

uses the two Coded cycles followed by one write

cycle giving the command 90h to address AAAAh

in the Byte-wideconfiguration or address 5555h in

the Word-wide configuration for command set-up.

A subsequent read will output the manufacturer

code and the device code or the block protection

status dependingon the levels of A0 and A1. The

manufacturer code, 20h, is output when the ad-

dresseslines A0 and A1 areLow, the device code,

EEh for Top Boot, EFh for Bottom Boot is output

when A0 is Highwith A1 Low.

Erase Suspend Program

Toggle

Note: 1. Toggle if the address is within a block being erased.

’1’ if the address is within a block not being erased.

Toggle Bit (DQ2). This toggle bit, together with

DQ6, can be used to determine the device status

duringthe Erase operations.It can also be usedto

identify the block being erased. During Erase or

Erase Suspend a read from a block being erased

will cause DQ2 to toggle. A read from a block not

being erased will set DQ2 to ’1’ during erase and

to DQ2 during Erase Suspend. During Chip Erase

a read operation will cause DQ2 to toggle as all

blocks are being erased. DQ2 will be set to ’1’

during program operationand when erase is com-

plete. After erase completion and if the error bit

DQ5 is set to ’1’, DQ2 will toggle if the faulty block

is addressed.

Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.

when there is a failure of programming, block

erase, or chip erase that results in invalid data in

thememoryblock.In caseof anerrorin blockerase

or program,the block in whichthe error occured or

to which the programmed data belongs, must be

discarded. The DQ5 failure condition will also ap-

pear if a usertries to programa ’1’ toa locationthat

is previously programmedto ’0’. OtherBlocksmay

stillbe used.Theerrorbit resetsaftera Read/Reset

(RD) instruction. In case of success of Program or

Erase, the error bit will be set to ’0’ .

The AS instruction also allows access to the block

protectionstatus.After givingtheASinstruction,A0

is set to V_ILwith A1 at V_IH, while A12-A18 define

the address of the block to be verified. A read in

these conditions will output a 01h if the block is

protected and a 00h if the block is not protected.

Program (PG) Instruction. This instruction uses

four write cycles. Both for Byte-wide configuration

and for Word-wide configuration. The Program

command A0h is written to address AAAAh in the

Byte-wideconfigurationor to address5555h in the

Word-wideconfigurationon thethirdcycleaftertwo

Coded cycles. Afourth write operation latches the

Addresson the falling edgeof W or E andthe Data

to be written on the rising edge and starts the

P/E.C. Read operationsoutputthe StatusRegister

bits after the programming has started. Memory

programmingis made onlyby writing ’0’ in placeof

’1’.StatusbitsDQ6and DQ7determineif program-

mingison-goingand DQ5allows verificationof any

possible error. Programming at an address not in

blocks being erased is also possible during erase

suspend. In this case, DQ2 will toggle at the ad-

dress being programmed.

Erase Timer Bit (DQ3). This bit is set to ’0’ by the

P/E.C. when the last block Erase command has

been entered to the Command Interface and it is

awaiting the Erase start. When the erase timeout

period is finished, after 50 s to 90 s, DQ3 returns

to ’1’.

µ

Coded Cycles

The two Coded cycles unlock the Command Inter-

face. They are followed by an input command or a

confirmation command. The Coded cycles consist

of writing the data AAh at address AAAAh in the

Byte-wide configuration and at address 5555h in

the Word-wide configuration during the first cycle.

14/33

M29W800T, M29W800B

Table 11. AC MeasurementConditions

Figure 5. AC Testing Load Circuit

Input Rise and Fall Times

10ns

≤

0.8V

Input Pulse Voltages

0 to 3V

1.5V

1N914

Input and Output Timing Ref. Voltages

Figure 4. AC Testing Input Output Waveform

3.3kΩ

DEVICE

UNDER

TEST

OUT

= 30pF or 100pF

3V

C

L

1.5V

0V

AI01417

C

includes JIG capacitance

L

AI01968

Table 12. Capacitance⁽¹⁾(T_A= 25 °C, f = 1 MHz )

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Test Condition

V_IN= 0V

Min

Max

6

Unit

pF

C_OUT

V_OUT= 0V

12

pF

Note: 1. Sampled only, not 100% tested.

Table 13. DC Characteristics

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C; V_CC= 2.7V to 3.6V)

°

A

Symbol

I_LI

Parameter

Test Condition

0V ≤ V_IN≤ V_CC

Min

Max

±1

Unit

Input Leakage Current

µA

I_LO

Output Leakage Current

Supply Current (Read) Byte

Supply Current (Read) Word

Supply Current (Standby)

0V ≤ V_OUT≤ V_CC

±1

I_CC1

I_CC3

E = V_IL, G = V_IH, f = 6MHz

10

mA

10

E = V_CC0.2V

100

A

µ

±

Byte program, Block or

Chip Erase in progress

(1)

I_CC4

Supply Current (Program or Erase)

20

mA

V_IL

V_IH

V_OL

V_OH

V_ID

I_ID

Input Low Voltage

–0.5

0.8

V

Input High Voltage

0.7 V_CC

V_CC+ 0.3

0.45

Output Low Voltage

I_OL= 1.8mA

Output High Voltage CMOS

A9 Voltage (Electronic Signature)

A9 Current (Electronic Signature)

I_OH= –100 A

V_CC–0.4V

11.5

µ

12.5

100

A9 = V_ID

A

µ

Supply Voltage(Erase and

Program lock-out)

V_LKO

2.0

2.3

V

Note: 1. Sampled only, not 100% tested.

15/33

M29W800T, M29W800B

Table 14A. Read AC Characteristics

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C)

°

A

M29W800T / M29W800B

-90

-100

Test

Condition

Symbol

Alt

Parameter

Unit

V_CC= 3.0V to 3.6V

C_L= 30pF

V_CC= 2.7V to 3.6V

C_L= 30pF

Min

Max

Min

Max

Address Validto Next

Address Valid

E = V_IL,

G = V_IL

t_AVAV

t_RC

t_ACC

t_LZ

90

100

ns

µs

Address Validto Output

Valid

E = V_IL,

G = V_IL

t_AVQV

90

100

Chip Enable Low to

Output Transition

(1)

t_ELQX

G = V_IL

E = V_IL

G = V_IL

E = V_IL

0

Chip Enable Low to

Output Valid

(2)

t_ELQV

t_CE

90

35

30

10

100

40

30

10

Output Enable Low to

Output Transition

(1)

t_GLQX

t_OLZ

t_OE

t_OH

t_HZ

Output Enable Low to

Output Valid

(2)

t_GLQV

Chip Enable High to

Output Transition

t_EHQX

Chip Enable High to

Output Hi-Z

(1)

t_EHQZ

Output Enable High to

Output Transition

t_GHQX

t_OH

t_DF

Output Enable High to

Output Hi-Z

(1)

t_GHQZ

Address Transition to

Output Transition

E = V_IL,

G = V_IL

t_AXQX

t_OH

t_RRB

t_READY

(1,3)

t_PLYH

RP Low to Read Mode

RP High to Chip Enable

Low

t_PHEL

t_RH

50

ns

t_PLPX

t_ELBL

t_ELBH

t_BLQZ

t_BHQV

t_RPRP Pulse Width

500

t_ELFLChip Enable to BYTE

t_ELFHSwitching Low or High

5

BYTE Switching Low to

t_FLQZ

50

ns

Output High Z

BYTE Switching High to

Output Valid

t_FHQV

Notes: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t_ELQV- t_GLQVafterthe falling edge of E without increasing t_ELQV

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

.

16/33

M29W800T, M29W800B

Table 14B. Read AC Characteristics

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C)

°

A

M29W800T / M29W800B

-120

-150

Test

Condition

Symbol

Alt

Parameter

Unit

V_CC= 2.7V to 3.6V

C_L= 100pF

V

_CC= 2.7V to 3.6V

C_L= 100pF

Min

Max

Min

Max

Address Valid to Next

Address Valid

E = V_IL,

G = V_IL

t_AVAV

t_RC

t_ACC

t_LZ

120

150

0

ns

Address Valid to Output

Valid

E = V_IL,

G = V_IL

t_AVQV

120

150

Chip Enable Low to

Output Transition

(1)

t_ELQX

G = V_IL

E = V_IL

G = V_IL

E = V_IL

0

Chip Enable Low to

Output Valid

(2)

t_ELQV

t_CE

t_OLZ

t_OE

t_OH

t_HZ

120

50

30

10

150

55

40

10

Output Enable Low to

Output Transition

(1)

t_GLQX

0

Output Enable Low to

Output Valid

(2)

t_GLQV

Chip Enable High to

Output Transition

t_EHQX

0

Chip Enable High to

Output Hi-Z

(1)

t_EHQZ

Output Enable High to

Output Transition

t_GHQX

t_OH

t_DF

0

Output Enable High to

Output Hi-Z

(1)

t_GHQZ

Address Transition to

Output Transition

E = V_IL,

G = V_IL

t_AXQX

t_OH

0

t_RRB

t_READY

(1,3)

t_PLYH

RP Low to Read Mode

s

µ

RP High to Chip Enable

Low

t_PHEL

t_RH

50

ns

t_PLPX

t_ELBL

t_ELBH

t_BLQZ

t_BHQV

t_RPRP Pulse Width

500

t_ELFLChip Enable to BYTE

t_ELFHSwitching Low or High

5

BYTE Switching Low to

t_FLQZ

60

ns

Output High Z

BYTE Switching High to

Output Valid

t_FHQV

Notes: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t_ELQV- t_GLQVafterthe falling edge of E without increasing t_ELQV

3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode.

.

17/33

M29W800T, M29W800B

Figure 6. Read Mode AC Waveforms

18/33

M29W800T, M29W800B

Table 15A. Write AC Characteristics, Write Enable Controlled

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C)

°

A

M29W800T / M29W800B

-90

-100

Symbol

Alt

Parameter

Unit

V_CC= 3.0V to 3.6V

C_L= 30pF

V_CC= 2.7V to 3.6V

C_L= 30pF

Min

90

0

Max

Min

100

0

Max

t_AVAV

t_ELWL

t_WCAddress Validto Next Address Valid

t_CSChip Enable Low to Write Enable Low

t_WPWrite Enable Low to Write Enable High

t_DSInput Valid to Write Enable High

t_DHWrite Enable High to Input Transition

t_CHWrite Enable High to Chip Enable High

t_WPHWrite Enable High to Write Enable Low

t_ASAddress Valid to Write Enable Low

t_AHWrite Enable Low to Address Transition

Output Enable High to Write Enable Low

t_VCSV_CCHigh to Chip Enable Low

ns

µs

ns

t_WLWH

t_DVWH

t_WHDX

t_WHEH

t_WHWL

t_AVWL

t_WLAX

t_GHWL

t_VCHEL

t_WHGL

45

0

50

0

30

0

30

0

45

0

50

0

50

0

50

0

t_OEHWrite Enable High to Output Enable Low

t_VIDRRP Rise Timeto V_ID

(1,2)

t_PHPHH

500

t_PLPX

t_RPRP Pulse Width

(1)

t_WHRL

t_PHWL

t_BUSYProgram Erase Valid to RB Delay

t_RSPRP High to Write Enable Low

90

4

s

µ

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotectionoperation.

19/33

M29W800T, M29W800B

Table 15B. Write AC Characteristics, Write Enable Controlled

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C)

°

A

M29W800T / M29W800B

-120

-150

Symbol

Alt

Parameter

Unit

V_CC= 2.7V to 3.6V

C_L= 100pF

V_CC= 2.7V to 3.6V

C_L= 100pF

Min

120

0

Max

Min

150

0

Max

t_AVAV

t_ELWL

t_WCAddress Validto Next Address Valid

t_CSChip Enable Low to Write Enable Low

t_WPWrite Enable Low to Write Enable High

t_DSInput Valid to Write Enable High

t_DHWrite Enable High to Input Transition

t_CHWrite Enable High to Chip Enable High

t_WPHWrite Enable High to Write Enable Low

t_ASAddress Valid to Write Enable Low

t_AHWrite Enable Low to Address Transition

Output Enable High to Write Enable Low

t_VCSV_CCHigh to Chip Enable Low

ns

µs

ns

t_WLWH

t_DVWH

t_WHDX

t_WHEH

t_WHWL

t_AVWL

t_WLAX

t_GHWL

t_VCHEL

t_WHGL

50

0

65

0

30

0

35

0

50

0

65

0

50

0

50

0

t_OEHWrite Enable High to Output Enable Low

t_VIDRRP Rise Timeto V_ID

(1,2)

t_PHPHH

500

t_PLPX

t_RPRP Pulse Width

(1)

t_WHRL

t_PHWL

t_BUSYProgram Erase Valid to RB Delay

t_RSPRP High to Write Enable Low

90

4

s

µ

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotectionoperation.

Block Erase (BE) Instruction. This instruction

uses a minimum of six write cycles. The Erase

Set-up command 80h is written to addressAAAAh

in the Byte-wideconfiguration or address5555h in

theWord-wideconfigurationon thirdcycleafter the

two Coded cycles. The Block Erase Confirm com-

mand30h is similarlywritten onthe sixthcycleafter

another two Coded cycles. During the input of the

secondcommandan addresswithinthe blockto be

erasedis given and latchedinto the memory.Addi-

tional block Erase Confirm commands and block

addresses can be written subsequently to erase

other blocks in parallel, without further Coded cy-

cles. The erase will start after the erase timeout

period (see Erase Timer Bit DQ3 description).

Thus, additional Erase Confirm commands for

other blocks must be given within this delay. The

input of a new Erase Confirm commandwill restart

the timeout period. The status of the internal timer

can be monitoredthrough the level of DQ3,if DQ3

is ’0’ the Block Erase Command has been given

andthe timeoutis running,if DQ3is ’1’, the timeout

has expired and the P/E.C. is erasingthe Block(s).

If the second command given is not an erase

confirm or if the Coded cycles are wrong, the

instruction aborts, and the device is reset to Read

Array. It is not necessary toprogram the block with

00h as the P/E.C. will do this automaticallybefore

to erasing to FFh. Read operations after the sixth

rising edge of W or E output the status register

status bits.

20/33

M29W800T, M29W800B

Figure 7. Write AC Waveforms, W Controlled

tAVAV

VALID

A0-A18/

A–1

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI02183

Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

Duringthe executionof theeraseby theP/E.C.,the

memory accepts onlythe Erase Suspend ES and

Read/Reset RD instructions. Data Polling bit DQ7

returns ’0’ while the erasure is in progress and ’1’

when it has completed. The Toggle bit DQ2 and

DQ6 toggle during the erase operation. They stop

when erase is completed. After completion the

StatusRegisterbit DQ5returns’1’ iftherehas been

an erase failure. In such a situation, the Toggle bit

DQ2 can be used to determine which block is not

correctly erased. In the case of erase failure, a

Read/ResetRDinstruction is necessaryin orderto

reset the P/E.C.

configurationon the thirdcycleafter the two Coded

cycles. The Chip Erase Confirm command 10h is

similarly writtenon thesixth cycleafter anothertwo

Coded cycles. If the secondcommand given is not

an erase confirm or if the Codedcyclesare wrong,

the instruction aborts and the device is reset to

ReadArray.It is notnecessaryto programthearray

with00h firstas theP/E.C.will automaticallydo this

before erasing it to FFh. Read operationsafter the

sixth rising edge of W or E output the Status

Registerbits. Duringthe executionof the erase by

theP/E.C.,Data Polling bitDQ7 returns’0’, then’1’

on completion. The Toggle bits DQ2 and DQ6

toggleduring eraseoperationand stopwhen erase

is completed. After completion the StatusRegister

bit DQ5 returns ’1’ if there has been an Erase

Failure.

ChipErase(CE)Instruction.Thisinstructionuses

six write cycles. The Erase Set-up command 80h

is written to address AAAAh in the Byte-wide con-

figuration or the address 5555h in the Word-wide

21/33

M29W800T, M29W800B

Table 16A. Write AC Characteristics,Chip Enable Controlled

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C)

°

A

M29W800T / M29W800B

-90 -100

_CC= 3.0V to 3.6V V_CC= 2.7V to 3.6V

Unit

Symbol

Alt

Parameter

V

C_L= 30pF C_L= 30pF

Min

Max

Min

Max

t_AVAV

t_WLEL

t_ELEH

t_DVEH

t_EHDX

t_EHWH

t_EHEL

t_AVEL

t_WC

t_WS

t_CP

t_DS

t_DH

t_WH

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

V_CCHigh to Write Enable Low

90

0

100

0

ns

45

0

50

0

t_CPH

t_AS

30

0

30

0

t_ELAX

t_GHEL

t_VCHWL

t_EHGL

t_AH

45

0

50

0

t_VCS

t_OEH

t_VIDR

t_RP

50

0

50

0

s

µ

Chip Enable High to Output Enable Low

RP Rise TIme to V_ID

ns

(1,2)

t_PHPHH

500

t_PLPX

RP Pulse Width

(1)

t_EHRL

t_BUSY

t_RSP

Program Erase Valid to RB Delay

RP High to Write Enable Low

90

(1)

t_PHWL

4

s

µ

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotectionoperation.

Erase Suspend (ES) Instruction. The Block

Eraseoperationmay be suspendedbythis instruc-

tion which consists of writing the command B0h

without any specific address.No Codedcycles are

required. It permits reading of data from another

block and programming in another block while an

erase operation is in progress. Erase suspend is

accepted only during the Block Erase instruction

execution. Writing this command during Erase

timeout will, in addition to suspending the erase,

terminate the timeout. The Toggle bit DQ6 stops

togglingwhentheP/E.C.is suspended.The Toggle

bitswill stoptogglingbetween0.1µs and15µs after

the Erase Suspend (ES) command has been writ-

ten. The device will then automatically be set to

Read Memory Array mode. When erase is sus-

pended, a Read from blocks being erased will

output DQ2 toggling and DQ6 at ’1’. A Read from

a blocknot being erased returns valid data. During

suspension the memory will respond only to the

Erase Resume ER and the Program PG instruc-

tions. A Program operation can be initiated during

erase suspend in one of the blocks not being

erased. Itwill resultin both DQ2 andDQ6 toggling

whenthe datais beingprogrammed.ARead/Reset

command will definitively abort erasure and result

in invalid data in the blocks being erased.

22/33

M29W800T, M29W800B

Table 16B. Write AC Characteristics,Chip Enable Controlled

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C)

°

A

M29W800T / M29W800B

-120

-150

Unit

Symbol

Alt

Parameter

V_CC= 2.7V to 3.6V

C_L= 100pF

V_CC= 2.7V to 3.6V

C_L= 100pF

Min

120

0

Max

Min

150

0

Max

t_AVAV

t_WLEL

t_ELEH

t_DVEH

t_EHDX

t_EHWH

t_EHEL

t_AVEL

t_WC

t_WS

t_CP

t_DS

t_DH

t_WH

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

V_CCHigh to Write Enable Low

ns

50

0

65

0

t_CPH

t_AS

30

0

35

0

t_ELAX

t_GHEL

t_VCHWL

t_EHGL

t_AH

50

0

65

0

t_VCS

t_OEH

t_VIDR

t_RP

50

0

50

0

s

µ

Chip Enable High to Output Enable Low

RP Rise TIme to V_ID

ns

(1,2)

t_PHPHH

500

t_PLPX

RP Pulse Width

(1)

t_EHRL

t_BUSY

t_RSP

Program Erase Valid to RB Delay

RP High to Write Enable Low

90

(1)

t_PHWL

4

s

µ

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotectionoperation.

EraseResume(ER)Instruction. Ifan Erase Sus-

pend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

during Power Up to allow maximum security and

thepossibility to writea commandon thefirst rising

edge of E and W. Any write cycle initiation is

blocked when Vcc is below V_LKO

.

Supply Rails

Normal precautionsmust be taken for supply volt-

age decoupling; each device in a system should

have the V_CCrail decoupledwith a 0.1µF capacitor

close to the V_CCand V_SSpins. The PCB trace

widths should be sufficient to carry the V_CCpro-

gram and erase currents required.

POWER SUPPLY

Power Up

ThememoryCommandInterfaceis reseton power

up to Read Array. Either E or W mustbe tied to V_IH

23/33

M29W800T, M29W800B

Figure 8. Write AC Waveforms, E Controlled

tAVAV

VALID

A0-A18/

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tDVEH

VALID

tEHDX

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI02184

Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

Figure 9. Read and Write AC Characteristics, RP Related

E

tPHEL

W

tPHWL

RB

tPLPX

RP

tPHPHH

tPLYH

AI02091

24/33

M29W800T, M29W800B

Table 17A. Data Polling and Toggle Bit AC Characteristics⁽¹⁾

(T = 0 to 70 C, –20 to 85 C or –40 to 85 C)

°

A

M29W800T / M29W800B

-90

-100

Sym-

bol

Parameter

Unit

V

_CC= 3.0V to 3.6V

C_L= 30pF

V_CC= 2.7V to 3.6V

C_L= 30pF

Min

Max

Min

Max

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

2400

10

2400

ms

t_WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

1.0

10

60

2400

60

1.0

10

60

2400

60

sec

Chip Enable High to DQ7 Valid

(Program, E Controlled)

s

µ

t_EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

sec

ns

t_Q7VQVQ7 Valid to Output Valid(Data Polling)

35

2400

60

40

2400

60

Write Enable High to Output Valid (Program)

t_WHQV

10

1.0

10

1.0

10

s

µ

Write Enable High to Output Valid (Chip Erase)

sec

Chip Enable High to Output Valid(Program)

t_EHQV

2400

60

2400

60

s

µ

Chip Enable High to Output Valid(Chip Erase)

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

Table 17B. Data Polling and Toggle Bit AC Characteristics⁽¹⁾

(T_A= 0 to 70°C, –20 to 85°C or –40 to 85°C)

M29W800T / M29W800B

-120 -150

Sym-

Parameter

bol

Unit

V_CC= 2.7V to 3.6V

C_L= 100pF

V_CC= 2.7V to 3.6V

C_L= 100pF

Min

Max

Min

Max

Write Enable High to DQ7 Valid

(Program, W Controlled)

10

2400

10

2400

ms

sec

µs

t_WHQ7V

Write Enable High to DQ7 Valid

(Chip Erase, W Controlled)

1.0

10

60

2400

60

1.0

10

60

2400

60

Chip Enable High to DQ7 Valid

(Program, E Controlled)

t_EHQ7V

Chip Enable High to DQ7 Valid

(Chip Erase, E Controlled)

1.0

sec

t_Q7VQVQ7 Valid to Output Valid(Data Polling)

50

2400

60

55

2400

60

ns

µs

Write Enable High to Output Valid (Program)

t_WHQV

10

1.0

10

1.0

10

Write Enable High to Output Valid (Chip Erase)

sec

µs

Chip Enable High to Output Valid(Program)

t_EHQV

2400

60

2400

60

Chip Enable High to Output Valid(Chip Erase)

1.0

sec

Note: 1. All other timings are defined in Read AC Characteristics table.

25/33

M29W800T, M29W800B

Figure 10. DataPolling DQ7 AC Waveforms

26/33

M29W800T, M29W800B

Figure 11. DataPolling Flowchart

Figure 12. Data Toggle Flowchart

START

READ

DQ2, DQ5 & DQ6

READ DQ5 & DQ7

at VALID ADDRESS

NO

DQ2, DQ6

=

DQ7

=

DATA

YES

TOGGLE

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ2, DQ6

READ DQ7

DQ7

=

DATA

YES

NO

DQ2, DQ6

=

TOGGLE

NO

YES

FAIL

PASS

AI01369

AI01873

Table 18. Program, Erase Times and Program, Erase Endurance Cycles

(T = 0 to 70 C; V_CC= 2.7Vto 3.6V)

°

A

M29W800T / M29W800B

Parameter

Unit

Typical after

Typ

Min

Max

100k W/E Cycles

Chip Erase (Preprogrammed)

Chip Erase

5

sec

12

2.4

2.3

2.7

3.3

8

12

Boot Block Erase

Parameter Block Erase

Main Block (32Kb) Erase

Main Block (64Kb) Erase

Chip Program (Byte)

Byte Program

15

8

10

20

10

20

s

µ

Word Program

Program/Erase Cycles (per Block)

100,000

cycles

27/33

M29W800T, M29W800B

Figure 13. DataToggle DQ6, DQ2 AC Waveforms

28/33

M29W800T, M29W800B

ORDERING INFORMATION SCHEME

Example:

M29W800T

-90

N

1

TR

Operating Voltage

Option

W

2.7V to 3.6V

R

Reverse

Pinout

TR Tape & Reel

Packing

Array Matrix

Top Boot

Speed

-90 90ns

Package

Temp. Range

T

B

N

TSOP48

12 x 20mm

1

5

6

0 to 70 C

°

Bottom Boot

-100 100ns

-120 120ns

-150 150ns

–20 to 85 C

°

M

SO44

–40 to 85 C

°

M29W800T and M29W800B are replaced respectively by the new version M29W800AT and

M29W800AB

Devices are shipped from the factory with the memory content erased (to FFh).

Fora list ofavailableoptions(Speed, Package,etc...)or for furtherinformationon anyaspect of thisdevice,

please contact the STMicroelectronics Sales Office nearest to you.

29/33

M29W800T, M29W800B

TSOP48 Normal Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

-

Typ

Max

0.047

0.006

0.041

0.011

0.008

0.795

0.728

0.476

-

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

-

0.002

0.037

0.007

0.004

0.780

0.720

0.469

-

C

D

D1

E

e

0.50

0.020

L

0.50

0.70

0.020

0.028

0

°

5

°

0

°

5

°

α

N

48

CP

0.10

0.004

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Drawing is not to scale.

30/33

M29W800T, M29W800B

TSOP48 Reverse Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

12.10

–

Typ

Max

0.047

0.006

0.041

0.011

0.008

0.795

0.728

0.476

–

A

A1

A2

B

0.05

0.95

0.17

0.10

19.80

18.30

11.90

–

0.002

0.037

0.007

0.004

0.780

0.720

0.469

–

C

D

D1

E

e

0.50

0.020

L

0.50

0.70

0.020

0.028

0

°

5

°

0

°

5

°

α

N

48

CP

0.10

0.004

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-b

A1

α

L

Drawing is not to scale.

31/33

M29W800T, M29W800B

SO44 - 44 lead Plastic Small Outline, 525 mils body width

mm

Min

2.42

0.22

2.25

inches

Min

Symb

Typ

Max

2.62

0.23

2.35

0.50

0.25

28.30

13.40

Typ

Max

0.103

0.010

0.093

0.020

0.010

1.114

0.528

A

A1

A2

B

0.095

0.009

0.089

C

0.10

28.10

13.20

0.004

1.106

0.520

D

E

e

H

1.27

0.80

0.050

0.031

15.90

44

16.10

0.626

44

0.634

L

3

°

3

α

°

N

CP

0.10

0.004

A2

A

C

B

CP

e

D

N

1

E

H

A1

α

L

SO-b

Drawing is not to scale.

32/33

M29W800T, M29W800B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implicationor otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http://www.st.com

33/33


型号：	M29W800B120M6TR
厂家：	ST
描述：	8 Mbit 1Mb x8 or 512Kb x16, Boot Block Low Voltage Single Supply Flash Memory 8兆位1Mb的X8或X16 512KB ，引导块低电压单电源闪存闪存
文件：	总33页 (文件大小：233K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M29W800B120M6TR [STMICROELECTRONICS]

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