M29W800DT90ZA1F_技术文档

M29W800DT

M29W800DB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■

SUPPLY VOLTAGE

V_CC= 2.7V to 3.6V for Program, Erase

and Read

Figure 1. Packages

–

■

ACCESS TIME: 70, 90ns

PROGRAMMING TIME

–

10µs per Byte/Word typical

■

19 MEMORY BLOCKS

–

1 Boot Block (Top or Bottom Location)

2 Parameter and 16 Main Blocks

SO44 (M)

■

PROGRAM/ERASE CONTROLLER

–

Embedded Byte/Word Program

algorithms

ERASE SUSPEND and RESUME MODES

–

Read and Program another Block during

Erase Suspend

TSOP48 (N)

12 x 20mm

UNLOCK BYPASS PROGRAM COMMAND

Faster Production/Batch Programming

–

■

TEMPORARY BLOCK UNPROTECTION

MODE

COMMON FLASH INTERFACE

FBGA

–

64 bit Security Code

LOW POWER CONSUMPTION

Standby and Automatic Standby

■

TFBGA48 (ZA)

6 x 9 mm

–

■

100,000 PROGRAM/ERASE CYCLES per

BLOCK

ELECTRONIC SIGNATURE

FBGA

–

Manufacturer Code: 0020h

Top Device Code M29W800DT: 22D7h

Bottom Device Code M29W800DB:

225Bh

TFBGA48 (ZE)

6 x 8mm

April 2004

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M29W800DT, M29W800DB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 5. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V_CCSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Bus Operations, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Bus Operations, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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M29W800DT, M29W800DB

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protect and Chip Unprotect Commands.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Commands, 16-bit mode, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. Commands, 8-bit mode, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 14.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 15.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 16.SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . 24

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data 24

Figure 17.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline. . . . . . . . . 25

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25

Figure 18.TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline. . . . 26

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M29W800DT, M29W800DB

Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 26

Figure 19.TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline. . . . 27

Table 19. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data. . 27

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 21. Top Boot Block Addresses, M29W800DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 22. Bottom Boot Block Addresses, M29W800DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 24. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 27. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 28. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 29. Programmer Technique Bus Operations, BYTE = V_IHor V_{IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 33}

Figure 20.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 22.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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M29W800DT, M29W800DB

SUMMARY DESCRIPTION

The M29W800D is a 8 Mbit (1Mb x8 or 512Kb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode where it can be read in the same way

as a ROM or EPROM.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents.

command set required to control the memory is

consistent with JEDEC standards.

The blocks in the memory are asymmetrically ar-

ranged, see Figures 6 and 7, Block Addresses.

The first or last 64 Kbytes have been divided into

four additional blocks. The 16 Kbyte Boot Block

can be used for small initialization code to start the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter storage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in SO44, TSOP48 (12 x

20mm), TFBGA48 6 x 9mm (0.8mm pitch) and

TFBGA48 6 x 8mm (0.8mm pitch) packages. The

memory is supplied with all the bits erased (set to

’1’).

The end of a program or erase operation can be

detected and any error conditions identified. The

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A18

Address Inputs

DQ0-DQ7

Data Inputs/Outputs

Data Input/Output or Address Input

Chip Enable

V

CC

DQ8-DQ14

19

15

DQ15A–1

A0-A18

DQ0-DQ14

DQ15A–1

E

W

E

G

Output Enable

M29W800DT

M29W800DB

W

RP

Write Enable

G

RB

Reset/Block Temporary Unprotect

RP

Ready/Busy Output

(not available on SO44 package)

RB

BYTE

Byte/Word Organization Select

Supply Voltage

V

CC

V

SS

AI05470B

V

Ground

SS

NC

Not Connected Internally

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M29W800DT, M29W800DB

Figure 3. SO Connections

Figure 4. TSOP Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

BYTE

RP

A18

A17

A7

A6

A5

A4

A3

A2

A1

A0

E

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

W

V

SS

2

NC

DQ15A–1

3

A8

DQ7

4

A9

DQ14

DQ6

5

A10

A11

A12

A13

A14

A15

A16

BYTE

6

A8

DQ13

DQ5

7

NC

W

8

DQ12

DQ4

9

10

11

12

13

14

15

16

17

18

19

20

21

22

RP

NC

RB

A18

A17

A7

12

13

37

36

V

M29W800DT

M29W800DB

CC

M29W800DT

M29W800DB

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

V

SS

DQ15A–1

SS

G

DQ0

DQ8

DQ7

DQ14

DQ6

DQ1

A6

DQ9

DQ13

DQ5

A5

DQ2

A4

DQ10

DQ3

DQ12

DQ4

A3

V

E

SS

A2

DQ11

V

CC

A1

24

25

A0

AI05462b

AI05461

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M29W800DT, M29W800DB

Figure 5. TFBGA Connections (Top view through package)

1

2

3

4

5

6

A9

A8

A

B

C

D

E

F

A3

A4

A7

RB

NC

W

A13

A12

RP

A17

A2

A1

A6

A5

A18

NC

A10

A11

A14

A15

A0

DQ0

DQ2

DQ5

DQ7

A16

DQ12

DQ14

DQ13

DQ6

E

DQ8

DQ9

DQ1

DQ10

DQ11

DQ3

BYTE

DQ15

A–1

G

H

G

V

CC

V

DQ4

V

SS

AI00656

7/41

M29W800DT, M29W800DB

Figure 6. Block Addresses (x8)

M29W800DT

M29W800DB

Top Boot Block Addresses (x8)

Bottom Boot Block Addresses (x8)

FFFFFh

16 KByte

64 KByte

FC000h

FBFFFh

F0000h

EFFFFh

8 KByte

FA000h

F9FFFh

E0000h

Total of 15

64 KByte Blocks

8 KByte

F8000h

F7FFFh

32 KByte

F0000h

EFFFFh

1FFFFh

64 KByte

32 KByte

8 KByte

16 KByte

E0000h

10000h

0FFFFh

08000h

07FFFh

Total of 15

64 KByte Blocks

06000h

05FFFh

1FFFFh

64 KByte

10000h

0FFFFh

04000h

03FFFh

64 KByte

00000h

AI05463

Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.

8/41

M29W800DT, M29W800DB

Figure 7. Block Addresses (x16)

M29W800DT

Top Boot Block Addresses (x16)

M29W800DB

Bottom Boot Block Addresses (x16)

7FFFFh

8 KWord

7E000h

7DFFFh

7FFFFh

32 KWord

78000h

77FFFh

4 KWord

7D000h

7CFFFh

70000h

Total of 15

32 KWord Blocks

4 KWord

7C000h

7BFFFh

16 KWord

78000h

77FFFh

0FFFFh

32 KWord

16 KWord

4 KWord

8 KWord

70000h

08000h

07FFFh

04000h

03FFFh

Total of 15

32 KWord Blocks

03000h

02FFFh

0FFFFh

32 KWord

08000h

07FFFh

02000h

01FFFh

32 KWord

00000h

AI05464

Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.

9/41

M29W800DT, M29W800DB

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A18). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Data Inputs/Outputs (DQ8-DQ14). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation when BYTE

is High, V_IH. When BYTE is Low, V_IL, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits. When reading the Status Register

these bits should be ignored.

Read and Bus Write operations after t_PHELor

_RHEL, whichever occurs last. See the Ready/Busy

Output section, Table 15 and Figure 15, Reset/

Temporary Unprotect AC Characteristics for more

details.

t

Holding RP at V_IDwill temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V_IHto V_IDmust be slower than

t_PHPHH

.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

Ready/Busy is Low, V_OL. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 15 and Figure

15, Reset/Temporary Unprotect AC Characteris-

tics.

Data Input/Output or Address Input (DQ15A-

1). When BYTE is High, V_IH, this pin behaves as

a Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, V_IL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to include this pin when BYTE is Low except

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, V_IH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to temporarily unprotect all Blocks that have been

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V_IL, for at least

t_PLPX. After Reset/Block Temporary Unprotect

goes High, V_IH, the memory will be ready for Bus

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the 8-bit and 16-bit Bus modes of

the memory. When Byte/Word Organization Se-

lect is Low, V_IL, the memory is in 8-bit mode, when

it is High, V_IH, the memory is in 16-bit mode.

V_CCSupply Voltage. The V_CCSupply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the V_CC

Supply Voltage is less than the Lockout Voltage,

V_LKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the V_CCSupply Voltage pin and the V_SSGround

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, I_CC3

.

Vss Ground. The V_SSGround is the reference

for all voltage measurements.

10/41

M29W800DT, M29W800DB

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Tables 2 and 3, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V_IL, to Chip Enable

and Output Enable and keeping Write Enable

High, V_IH. The Data Inputs/Outputs will output the

value, see Figure 12, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, V_IH, during the whole Bus

Write operation. See Figures 13 and 14, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

ance state. To reduce the Supply Current to the

Standby Supply Current, I_CC2, Chip Enable should

be held within V_CC± 0.2V. For the Standby current

level see Table 11, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, I_CC3, for Program or Erase operations un-

til the operation completes.

Automatic Standby. If CMOS levels (V_CC± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, I_CC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Special Bus Operations. Additional bus opera-

tions can be performed to read the Electronic Sig-

nature and also to apply and remove Block

Protection. These bus operations are intended for

use by programming equipment and are not usu-

ally used in applications. They require V_IDto be

applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Tables 2 and 3, Bus Operations.

Block Protection and Blocks Unprotection.

Each block can be separately protected against

accidental Program or Erase. Protected blocks

can be unprotected to allow data to be changed.

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. Block Protect and Chip Unprotect operations

are described in Appendix C.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, V_IH.

Standby. When Chip Enable is High, V_IH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

Table 2. Bus Operations, BYTE = V_IL

Data Inputs/Outputs

Address Inputs

Operation

E

G

W

DQ15A–1, A0-A18

DQ14-DQ8

Hi-Z

DQ7-DQ0

Data Output

Data Input

Hi-Z

V

IL

V

IH

Bus Read

Cell Address

IL

IH

V

IL

V

Bus Write

Command Address

Hi-Z

IL

Output Disable

Standby

X

Hi-Z

IH

V

X

Hi-Z

IH

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

IL

ID

V

Hi-Z

20h

IL

IH

Others V or V

IL

IH

A0 = V , A1 = V , A9 = V ,

D7h (M29W800DT)

5Bh (M29W800DB)

IH

IL

ID

V

Read Device Code

Others V or V

IL

IH

Note: X = V or V

.

IH

IL

11/41

M29W800DT, M29W800DB

Table 3. Bus Operations, BYTE = V_IH

Address Inputs

A0-A18

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

Bus Read

E

G

W

V

IL

V

IH

Cell Address

Data Output

Data Input

Hi-Z

IL

IH

V

IL

V

Bus Write

Command Address

IL

Output Disable

Standby

X

IH

V

X

Hi-Z

IH

A0 = V , A1 = V , A9 = V ,

Read Manufacturer

Code

IL

ID

V

0020h

IL

IH

Others V or V

IL

IH

A0 = V , A1 = V , A9 = V ,

22D7h (M29W800DT)

225Bh (M29W800DB)

IH

IL

ID

V

Read Device Code

Others V or V

IL

IH

Note: X = V or V

.

IH

IL

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. See either Table 4, or 5, depending on

the configuration that is being used, for a summary

of the commands.

Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM, unless other-

wise stated. It also resets the errors in the Status

Register. Either one or three Bus Write operations

can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. Once the program or erase operation

has started the Read/Reset command is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A0 = V_ILand A1 = V_IL. The other address bits

may be set to either V_ILor V_IH. The Manufacturer

Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read

operation with A0 = V_IHand A1 = V_IL. The other

address bits may be set to either V_ILor V_IH. The

Device Code for the M29W800DT is 22D7h and

for the M29W800DB is 225Bh.

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = V_IL,

A1 = V_IH, and A12-A18 specifying the address of

the block. The other address bits may be set to ei-

ther V_ILor V_IH. If the addressed block is protect-

ed then 01h is output on Data Inputs/Outputs

DQ0-DQ7, otherwise 00h is output.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data in the internal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the memory will ig-

nore all commands. It is not possible to issue any

command to abort or pause the operation. Typical

program times are given in Table 6. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

Auto Select Command. The Auto Select com-

mand is used to read the Manufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until a Read/Reset

command is issued. Read CFI Query and Read/

Reset commands are accepted in Auto Select

mode, all other commands are ignored.

12/41

M29W800DT, M29W800DB

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

Unlock Bypass Command. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program command to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass command.

During the erase operation the memory will ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

times are given in Table 6. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Write operation using the address of the

additional block. The Block Erase operation starts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50µs of the last block. The 50µs

timer restarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for

details on how to identify if the Program/Erase

Controller has started the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Block Erase operation the memory will

ignore all commands except the Erase Suspend

command. Typical block erase times are given in

Table 6. All Bus Read operations during the Block

Erase operation will output the Status Register on

the Data Inputs/Outputs. See the section on the

Status Register for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Program Command. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write operations, the

final write operation latches the address and data

in the internal state machine and starts the Pro-

gram/Erase Controller.

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be programmed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, which leaves the device in Unlock By-

pass Mode. See the Program command for details

on the behavior.

Unlock Bypass Reset Command. The Unlock

Bypass Reset command can be used to return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command. Read/Reset

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100µs,

leaving the data unchanged. No error condition is

given when protected blocks are ignored.

The Block Erase Command sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

13/41

M29W800DT, M29W800DB

Erase Suspend Command. The Erase Suspend

Command may be used to temporarily suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

mode before the Resume command will be ac-

cepted.

Erase Resume Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resumed more than once.

Read CFI Query Command. The Read CFI

Query Command is used to read data from the

Common Flash Interface (CFI) Memory Area. This

command is valid when the device is in the Read

Array mode, or when the device is in Autoselected

mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subsequent Bus Read operations read from

the Common Flash Interface Memory Area.

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Autoselected mode). A second Read/

Reset command would be needed if the device is

to be put in the Read Array mode from Autoselect-

ed mode.

See Appendix B, Tables 23, 24, 25, 26, 27 and for

details on the information contained in the Com-

mon Flash Interface (CFI) memory area.

Block Protect and Chip Unprotect Commands.

Each block can be separately protected against

accidental Program or Erase. The whole chip can

be unprotected to allow the data inside the blocks

to be changed.

Block Protect and Chip Unprotect operations are

described in Appendix C.

The Program/Erase Controller will suspend within

the Erase Suspend Latency Time (refer to Table 6

for value) of the Erase Suspend Command being

issued. Once the Program/Erase Controller has

stopped the memory will be set to Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is suspended immediately and will start im-

mediately when the Erase Resume Command is

issued. It is not possible to select any further

blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protected block or in the suspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not read and no error condition is given. Read-

ing from blocks that are being erased will output

the Status Register.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass commands during

an Erase Suspend. The Read/Reset command

must be issued to return the device to Read Array

14/41

M29W800DT, M29W800DB

Table 4. Commands, 16-bit mode, BYTE = V_IH

Bus Write Operations

3rd 4th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command

1st

2nd

5th

6th

1

3

4

3

X

F0

AA

Read/Reset

555

2AA

55

X

F0

90

A0

20

Auto Select

Program

555

PA

PD

Unlock Bypass

Program

2

X

A0

PA

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

555

2AA

555

80

555

AA

2AA

55

555

BA

10

30

Block Erase

6+ 555

Erase Suspend

Erase Resume

Read CFI Query

1

X

55

98

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IH

IL

15/41

M29W800DT, M29W800DB

Table 5. Commands, 8-bit mode, BYTE = V_IL

Bus Write Operations

3rd 4th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command

1st

2nd

5th

6th

1

3

4

3

X

F0

AA

Read/Reset

AAA

555

55

X

F0

90

A0

20

Auto Select

Program

AAA

PA

PD

Unlock Bypass

Program

2

X

A0

PA

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

AAA

555

AAA

80

AAA

AA

555

55

AAA

BA

10

30

Block Erase

6+ AAA

Erase Suspend

Erase Resume

Read CFI Query

1

X

AA

98

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IH

IL

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

(1, 2)

(2)

Parameter

Min

Unit

s

Typ

12

Max

(3)

Chip Erase

60

(4)

Block Erase (64 Kbytes)

0.8

15

10

12

6

s

6

(3)

Erase Suspend Latency Time

Program (Byte or Word)

µs

s

25

(3)

200

(3)

Chip Program (Byte by Byte)

60

30

(4)

Chip Program (Word by Word)

Program/Erase Cycles (per Block)

Data Retention

s

100,000

20

cycles

years

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V after 100,00 program/erase cycles.

CC

4. Maximum value measured at worst case conditions for both temperature and V

.

CC

16/41

M29W800DT, M29W800DB

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is accessed.

The bits in the Status Register are summarized in

Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 8, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

ror is signalled and DQ6 toggles for approximately

1µs.

Figure 9, Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress will show the bit is still ‘0’. One of the Erase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional blocks to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Register is read.

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

If any attempt is made to erase a protected block,

the operation is aborted, no error is signalled and

DQ6 toggles for approximately 100µs. If any at-

tempt is made to program a protected block or a

suspended block, the operation is aborted, no er-

17/41

M29W800DT, M29W800DB

Table 7. Status Register Bits

Operation

Program

Address

DQ7

DQ6

DQ5

DQ3

DQ2

RB

Any Address

DQ7

Toggle

0

–

0

Program During Erase

Suspend

DQ7

Toggle

0

–

0

Program Error

Chip Erase

Any Address

DQ7

Toggle

1

0

–

1

0

1

–

0

1

0

1

Toggle

Erasing Block

Toggle

Block Erase before

timeout

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

Block Erase

Erase Suspend

Erase Error

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

No Toggle

Non-Erasing Block

Good Block Address

Faulty Block Address

Data read as normal

0

Toggle

1

No Toggle

Toggle

1

Note: Unspecified data bits should be ignored.

Figure 8. Data Polling Flowchart

Figure 9. Data Toggle Flowchart

START

READ DQ6

READ DQ5 & DQ7

at VALID ADDRESS

READ

DQ5 & DQ6

DQ7

=

DATA

YES

DQ6

NO

=

TOGGLE

NO

YES

NO

DQ5

= 1

NO

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

READ DQ6

TWICE

DQ7

=

DATA

YES

DQ6

=

NO

FAIL

TOGGLE

PASS

YES

FAIL

PASS

AI03598

AI01370C

18/41

M29W800DT, M29W800DB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 8. Absolute Maximum Ratings

Symbol

Parameter

Min

–50

–65

–0.6

Max

125

150

Unit

°C

V

T

Temperature Under Bias

Storage Temperature

BIAS

T

STG

(1,2)

V

IO

V

+0.6

CC

Input or Output Voltage

Supply Voltage

V

CC

4

V

ID

Identification Voltage

13.5

V

Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.

CC

19/41

M29W800DT, M29W800DB

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 9, Operating and

AC Measurement Conditions. Designers should

check that the operating conditions in their circuit

match the operating conditions when relying on

the quoted parameters.

Table 9. Operating and AC Measurement Conditions

M29W800D

Parameter

70

90

Unit

Min

2.7

–40

0

Max

3.6

85

Min

2.7

–40

0

Max

3.6

85

V

Supply Voltage

V

CC

Ambient Operating Temperature (range 6)

Ambient Operating Temperature (range 1)

°C

70

Load Capacitance (C )

30

100

pF

ns

V

L

Input Rise and Fall Times

10

0 to V

Input Pulse Voltages

CC

V

/2

V

CC

/2

Input and Output Timing Ref. Voltages

V

CC

Figure 10. AC Measurement I/O Waveform

Figure 11. AC Measurement Load Circuit

V

CC

V

CC

V

/2

CC

25kΩ

0V

DEVICE

UNDER

TEST

AI04498

25kΩ

0.1µF

C

L

AI04499

C

includes JIG capacitance

L

Table 10. Device Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

IN

= 0V

IN

C

V

OUT

12

pF

OUT

Note: Sampled only, not 100% tested.

20/41

M29W800DT, M29W800DB

Table 11. DC Characteristics

Symbol

Parameter

Test Condition

Min

Max

±1

Unit

µA

I

LI

0V ≤ V ≤ V

Input Leakage Current

Output Leakage Current

IN

CC

I

LO

0V ≤ V

≤ V

OUT CC

±1

µA

E = V , G = V ,

IL

IH

I

Supply Current (Read)

10

mA

µA

mA

CC1

f = 6MHz

E = V ±0.2V,

CC

I

Supply Current (Standby)

Supply Current (Program/Erase)

100

CC2

RP = V ±0.2V

CC

Program/Erase

Controller active

(1)

20

I

CC3

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Identification Voltage

Identification Current

–0.5

0.8

V

IL

V

0.7V

V

+0.3

IH

CC

I

= 1.8mA

OL

0.45

V

OL

V

–0.4

I

= –100µA

V

OH

CC

OH

V

ID

11.5

12.5

100

V

I

ID

A9 = V

µA

ID

Program/Erase Lockout Supply

Voltage

V

LKO

1.8

2.3

V

Note: 1. Sampled only, not 100% tested.

Figure 12. Read Mode AC Waveforms

tAVAV

VALID

A0-A18/

A–1

tAVQV

tAXQX

tEHQX

E

tELQV

tELQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

DQ0-DQ7/

DQ8-DQ15

VALID

tBHQV

BYTE

tELBL/tELBH

tBLQZ

AI05448

21/41

M29W800DT, M29W800DB

Table 12. Read AC Characteristics

M29W800D

Symbol

Alt

Parameter

Test Condition

Unit

70

90

E = V ,

IL

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

70

90

ns

AVAV

RC

G = V

IL

E = V ,

IL

t

ACC

Max

90

AVQV

G = V

IL

(1)

t

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

Min

0

ns

t

LZ

ELQX

t

Max

70

90

ELQV

CE

Output Enable Low to Output

Transition

(1)

t

E = V

Min

0

ns

t

OLZ

IL

GLQX

t

E = V

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Max

30

25

35

30

ns

GLQV

OE

(1)

t

G = V

HZ

DF

IL

EHQZ

GHQZ

t

E = V

t

EHQX

Chip Enable, Output Enable or

Address Transition to Output Transition

t

Min

0

5

0

5

ns

GHQX

OH

AXQX

t

ELBL

ELFL

Chip Enable to BYTE Low or High

Max

ELBH

ELFH

t

BYTE Low to Output Hi-Z

BYTE High to Output Valid

Max

25

30

40

ns

BLQZ

FLQZ

t

FHQV

BHQV

Note: 1. Sampled only, not 100% tested.

22/41

M29W800DT, M29W800DB

Figure 13. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A18/

VALID

A–1

tWLAX

tAVWL

tWHEH

tWHGL

E

tELWL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI05449

Table 13. Write AC Characteristics, Write Enable Controlled

M29W800D

Unit

Symbol

Alt

Parameter

70

0

90

0

t

WC

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

Min

Max

ns

AVAV

t

CS

ELWL

t

45

0

50

0

WLWH

WP

t

DVWH

DS

DH

CH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

Program/Erase Valid to RB Low

WHDX

t

0

WHEH

t

WPH

30

0

30

0

WHWL

t

AS

AVWL

t

45

0

50

0

WLAX

AH

t

GHWL

t

OEH

0

WHGL

(1)

t

30

50

35

50

t

BUSY

WHRL

t

V

High to Chip Enable Low

CC

Min

µs

VCHEL

VCS

Note: 1. Sampled only, not 100% tested.

23/41

M29W800DT, M29W800DB

Figure 14. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A18/

VALID

A–1

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI05450

Table 14. Write AC Characteristics, Chip Enable Controlled

M29W800D

Symbol

Alt

Parameter

Unit

70

0

90

t

WC

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Min

Max

90

0

ns

AVAV

t

WS

WLEL

t

45

0

50

0

ELEH

CP

DS

DH

t

DVEH

t

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

Chip Enable High to Output Enable Low

Program/Erase Valid to RB Low

EHDX

t

WH

0

EHWH

t

30

0

30

0

EHEL

CPH

t

AS

AVEL

t

45

0

50

0

ELAX

AH

t

GHEL

t

0

EHGL

OEH

(1)

t

30

50

35

t

BUSY

EHRL

t

V

High to Write Enable Low

CC

Min

50

µs

VCHWL

VCS

Note: 1. Sampled only, not 100% tested.

24/41

M29W800DT, M29W800DB

Figure 15. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPLPX

RP

tPHPHH

tPLYH

AI06870

Table 15. Reset/Block Temporary Unprotect AC Characteristics

M29W800D

Symbol

Alt

Parameter

Unit

70

90

(1)

t

PHWL

RP High to Write Enable Low, Chip Enable Low,

Output Enable Low

t

Min

50

ns

PHEL

RH

(1)

t

PHGL

(1)

t

RHWL

RB High to Write Enable Low, Chip Enable Low,

Output Enable Low

t

0

ns

t

RB

RHEL

RHGL

t

RP Pulse Width

Min

Max

Min

500

10

500

10

ns

µs

ns

PLPX

RP

(1)

t

RP Low to Read Mode

t

READY

PLYH

(1)

t

RP Rise Time to V

500

t

VIDR

ID

PHPHH

Note: 1. Sampled only, not 100% tested.

25/41

M29W800DT, M29W800DB

PACKAGE MECHANICAL

Figure 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline

A2

A

C

b

e

CP

D

N

E

EH

1

A1

α

L

SO-d

Note: Drawing is not to scale.

Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

2.80

0.1102

0.10

2.20

0.35

0.10

0.0039

0.0866

0.0138

0.0039

2.30

0.40

0.15

2.40

0.50

0.20

0.08

28.40

13.50

16.25

–

0.0906

0.0157

0.0059

0.0945

0.0197

0.0079

0.0030

1.1181

0.5315

0.6398

–

C

CP

D

28.20

13.30

16.00

1.27

28.00

13.20

15.75

–

1.1102

0.5236

0.6299

0.0500

0.0315

1.1024

0.5197

0.6201

–

E

EH

e

L

0.80

a

8

N

44

26/41

M29W800DT, M29W800DB

Figure 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

1

48

e

D1

B

L1

24

25

A2

A

E1

E

A1

α

L

DIE

C

CP

TSOP-G

Note: Drawing is not to scale.

Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.080

12.100

20.200

18.500

–

Typ

Max

A

A1

A2

B

0.0472

0.0059

0.0413

0.0106

0.0083

0.0031

0.4764

0.7953

0.7283

–

0.100

1.000

0.220

0.050

0.950

0.170

0.100

0.0039

0.0394

0.0087

0.0020

0.0374

0.0067

0.0039

C

CP

D1

E

12.000

20.000

18.400

0.500

0.600

0.800

3

11.900

19.800

18.300

–

0.4724

0.7874

0.7244

0.0197

0.0236

0.0315

3

0.4685

0.7795

0.7205

–

E1

e

L

0.500

0.700

0.0197

0.0276

L1

a

0

5

0

5

27/41

M29W800DT, M29W800DB

Figure 18. TFBGA48 6x9mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

SE

BALL "A1"

E

E1

ddd

e

b

A

A2

A1

BGA-Z00

Note: Drawing is not to scale.

Table 18. TFBGA48 6x9mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.200

0.0079

1.000

0.0394

0.400

6.000

4.000

0.350

5.900

–

0.450

0.0157

0.2362

0.1575

0.0138

0.2323

–

0.0177

D

6.100

0.2402

D1

ddd

E

–

0.100

0.0039

9.000

0.800

5.600

1.000

1.700

0.400

8.900

9.100

0.3543

0.0315

0.2205

0.0394

0.0669

0.0157

0.3504

0.3583

e

–

E1

FD

FE

SD

SE

28/41

M29W800DT, M29W800DB

Figure 19. TFBGA48 6x8mm – 6x8 ball array – 0.80mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

SE

BALL "A1"

E

E1

ddd

e

b

A

A2

A1

BGA-Z32

Note: Drawing is not to scale.

Table 19. TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

0.900

0.0354

0.350

5.900

–

0.450

0.0138

0.2323

–

0.0177

D

6.000

4.000

6.100

0.2362

0.1575

0.2402

D1

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.000

1.200

0.400

7.900

8.100

0.3150

0.2205

0.0315

0.0394

0.0472

0.0157

0.3110

0.3189

E1

e

–

FD

FE

SD

SE

29/41

M29W800DT, M29W800DB

PART NUMBERING

Table 20. Ordering Information Scheme

Example:

M29W800DB

90

N

6

T

Device Type

M29

Operating Voltage

W = V = 2.7 to 3.6V

CC

Device Function

800D = 8 Mbit (x8/x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

M = SO44

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6x9mm, 0.80mm pitch

ZE = TFBGA48: 6x8mm, 0.80mm pitch

Temperature Range

6 = –40 to 85 °C

1 = 0 to 70 °C

Option

T = Tape & Reel Packing

E = Lead-free Package, Standard Packing

F = Lead-free Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact your nearest ST Sales Office.

30/41

M29W800DT, M29W800DB

APPENDIX A. BLOCK ADDRESS TABLE

Table 21. Top Boot Block Addresses,

M29W800DT

Table 22. Bottom Boot Block Addresses,

M29W800DB

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

Size

(Kbytes)

Address Range

(x8)

Address Range

(x16)

#

18

17

16

15

14

13

12

11

10

9

16

8

FC000h-FFFFFh

FA000h-FBFFFh

F8000h-F9FFFh

F0000h-F7FFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

7E000h-7FFFFh

7D000h-7DFFFh

7C000h-7CFFFh

78000h-7BFFFh

70000h-77FFFh

68000h-6FFFFh

60000h-67FFFh

58000h-5FFFFh

50000h-57FFFh

48000h-4FFFFh

40000h-47FFFh

38000h-3FFFFh

30000h-37FFFh

28000h-2FFFFh

20000h-27FFFh

18000h-1FFFFh

10000h-17FFFh

08000h-0FFFFh

00000h-07FFFh

18

17

16

15

14

13

12

11

10

9

64

32

8

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

08000h-0FFFFh

06000h-07FFFh

04000h-05FFFh

00000h-03FFFh

78000h-7FFFFh

70000h-77FFFh

68000h-6FFFFh

60000h-67FFFh

58000h-5FFFFh

50000h-57FFFh

48000h-4FFFFh

40000h-47FFFh

38000h-3FFFFh

30000h-37FFFh

28000h-2FFFFh

20000h-27FFFh

18000h-1FFFFh

10000h-17FFFh

08000h-0FFFFh

04000h-07FFFh

03000h-03FFFh

02000h-02FFFh

00000h-01FFFh

8

32

64

8

7

6

5

4

3

2

1

8

0

16

31/41

M29W800DT, M29W800DB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

is read from the memory. Tables 23, 24, 25, 26, 27

and 27 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table , Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the CFI Query Command is issued the de-

vice enters CFI Query mode and the data structure

Table 23. Query Structure Overview

Address

Sub-section Name

Description

x16

10h

1Bh

27h

x8

20h

36h

4Eh

CFI Query Identification String

System Interface Information

Device Geometry Definition

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Primary Algorithm-specific Extended

Query table

Additional information specific to the Primary

Algorithm (optional)

40h

61h

80h

C2h

Security Code Area

64 bit unique device number

Note: Query data are always presented on the lowest order data outputs.

Table 24. CFI Query Identification String

Address

Data

Description

Value

x16

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

x8

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h

0059h

0002h

0000h

0040h

0000h

"Q"

"R"

"Y"

Query Unique ASCII String "QRY"

Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm

AMD

Compatible

Address for Primary Algorithm extended Query table (see Table 26)

P = 40h

NA

Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

NA

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

32/41

M29W800DT, M29W800DB

Table 25. CFI Query System Interface Information

Address

Data

Description

Value

x16

x8

V

Logic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

CC

1Bh

36h

0027h

0036h

2.7V

3.6V

Logic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

CC

1Ch

38h

bit 3 to 0BCD value in 100 mV

V

[Programming] Supply Minimum Program/Erase voltage

1Dh

1Eh

1Fh

3Ah

3Ch

3Eh

0000h

0004h

NA

PP

[Programming] Supply Maximum Program/Erase voltage

PP

n

16µs

Typical timeout per single byte/word program = 2 µs

n

20h

21h

22h

23h

24h

25h

26h

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

000Ah

0000h

0004h

0000h

0003h

0000h

NA

1s

Typical timeout for minimum size write buffer program = 2 µs

n

Typical timeout per individual block erase = 2 ms

n

see note (1)

256µs

NA

Typical timeout for full chip erase = 2 ms

n

Maximum timeout for byte/word program = 2 times typical

n

Maximum timeout for write buffer program = 2 times typical

n

8s

Maximum timeout per individual block erase = 2 times typical

n

see note (1)

Maximum timeout for chip erase = 2 times typical

Note: 1. Not supported in the CFI

Table 26. Device Geometry Definition

Address

Data

Description

Value

x16

x8

n

27h

4Eh

0014h

1 MByte

Device Size = 2 in number of bytes

28h

29h

50h

52h

0002h

0000h

x8, x16

Async.

Flash Device Interface Code description

2Ah

2Bh

54h

56h

0000h

n

NA

4

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

2Ch

58h

0004h

It specifies the number of regions within the device containing

contiguous Erase Blocks of the same size.

2Dh

2Eh

5Ah

5Ch

0000h

Region 1 Information

Number of identical size erase block = 0000h+1

1

2Fh

30h

5Eh

60h

0040h

0000h

Region 1 Information

Block size in Region 1 = 0040h * 256 byte

16 Kbyte

31h

32h

62h

64h

0001h

0000h

Region 2 Information

Number of identical size erase block = 0001h+1

2

8 Kbyte

1

33h

34h

66h

68h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

35h

36h

6Ah

6Ch

0000h

Region 3 Information

Number of identical size erase block = 0000h+1

33/41

M29W800DT, M29W800DB

Address

Data

Description

Value

x16

x8

37h

38h

6Eh

70h

0080h

0000h

Region 3 Information

Block size in Region 3 = 0080h * 256 byte

32 Kbyte

15

39h

3Ah

72h

74h

000Eh

0000h

Region 4 Information

Number of identical-size erase block = 000Eh+1

3Bh

3Ch

76h

78h

0000h

0001h

Region 4 Information

Block size in Region 4 = 0100h * 256 byte

64 Kbyte

Table 27. Primary Algorithm-Specific Extended Query Table

Address

Data

Description

Value

x16

40h

41h

42h

43h

44h

45h

x8

80h

82h

84h

86h

88h

8Ah

0050h

0052h

0049h

0031h

0030h

0000h

"P"

"R"

"I"

Primary Algorithm extended Query table unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Yes

Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

46h

47h

48h

49h

8Ch

8Eh

90h

92h

0002h

0001h

0004h

Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write

2

1

Block Protection

00 = not supported, x = number of sectors in per group

Temporary Block Unprotect

00 = not supported, 01 = supported

Yes

4

Block Protect /Unprotect

04 = M29W400B

4Ah

4Bh

4Ch

94h

96h

98h

0000h

Simultaneous Operations, 00 = not supported

No

Burst Mode, 00 = not supported, 01 = supported

Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word

Table 28. Security Code Area

Address

Data

Description

x16

61h

62h

63h

64h

x8

C3h, C2h

C5h, C4h

C7h, C6h

C9h, C8h

XXXX

64 bit: unique device number

34/41

M29W800DT, M29W800DB

APPENDIX C. BLOCK PROTECTION

Block protection can be used to prevent any oper-

ation from modifying the data stored in the Flash.

Each Block can be protected individually. Once

protected, Program and Erase operations on the

block fail to change the data.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In-System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pin, RP; this is described in the Signal De-

scriptions section.

Unlike the Command Interface of the Program/

Erase Controller, the techniques for protecting and

unprotecting blocks change between different

Flash memory suppliers. For example, the tech-

niques for AMD parts will not work on STMicro-

electronics parts. Care should be taken when

changing drivers for one part to work on another.

Technique Bus Operations, gives a summary of

each operation.

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do

not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP. This can be achieved without violating the

maximum ratings of the components on the micro-

processor bus, therefore this technique is suitable

for use after the Flash has been fitted to the sys-

tem.

To protect a block follow the flowchart in Figure 22,

In-System Block Protect Flowchart. To unprotect

the whole chip it is necessary to protect all of the

blocks first, then all the blocks can be unprotected

at the same time. To unprotect the chip follow Fig-

ure 23, In-System Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do

not allow the microprocessor to service interrupts

that will upset the timing and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

Programmer Technique

The Programmer technique uses high (V_ID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard microprocessor bus,

therefore the technique is recommended only for

use in Programming Equipment.

To protect a block follow the flowchart in Figure 20,

Programmer Equipment Block Protect Flowchart.

To unprotect the whole chip it is necessary to pro-

tect all of the blocks first, then all blocks can be un-

protected at the same time. To unprotect the chip

follow Figure 21, Programmer Equipment Chip

Unprotect Flowchart. Table 29, Programmer

Table 29. Programmer Technique Bus Operations, BYTE = V_IHor V_IL

Address Inputs

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

A0-A18

A9 = V , A12-A18 Block Address

ID

V

Pulse

Block Protect

X

IL

ID

IL

Others = X

A9 = V , A12 = V , A15 = V

ID

IH

V

ID

Chip Unprotect

ID

IL

Others = X

A0 = V , A1 = V , A6 = V , A9 = V ,

IL

IH

IL

ID

Block Protection

Verify

Pass = XX01h

Retry = XX00h

V

A12-A18 Block Address

Others = X

IL

IH

A0 = V , A1 = V , A6 = V , A9 = V ,

IL

IH

ID

Block Unprotection

Verify

Retry = XX01h

Pass = XX00h

V

A12-A18 Block Address

Others = X

35/41

M29W800DT, M29W800DB

Figure 20. Programmer Equipment Block Protect Flowchart

START

ADDRESS = BLOCK ADDRESS

W = V

IH

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

E, G = V

,

IH

A0, A6 = V

A1 = V

,

IL

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

NO

YES

++n

= 25

NO

A9 = V

E, G = V

IH

YES

PASS

A9 = V

IH

E, G = V

IH

AI03469

FAIL

36/41

M29W800DT, M29W800DB

Figure 21. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

(1)

A6, A12, A15 = V

IH

E, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = V , A1, A6 = V

IL

IH

E = V

IL

Wait 4µs

G = V

IL

INCREMENT

CURRENT BLOCK

Wait 60ns

Read DATA

NO

YES

DATA

=

00h

LAST

BLOCK

NO

++n

= 1000

YES

A9 = V

IH

A9 = V

IH

E, G = V

IH

FAIL

PASS

AI03470

37/41

M29W800DT, M29W800DB

Figure 22. In-System Equipment Block Protect Flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 100µs

WRITE 40h

IL

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

Wait 4µs

READ DATA

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

DATA

NO

=

01h

YES

++n

= 25

NO

RP = V

IH

YES

ISSUE READ/RESET

COMMAND

RP = V

IH

PASS

ISSUE READ/RESET

COMMAND

FAIL

AI03471

38/41

M29W800DT, M29W800DB

Figure 23. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

Wait 10ms

WRITE 40h

ADDRESS = CURRENT BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 4µs

INCREMENT

CURRENT BLOCK

READ DATA

ADDRESS = CURRENT BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

DATA

NO

YES

=

00h

++n

= 1000

NO

LAST

BLOCK

YES

RP = V

IH

RP = V

IH

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PASS

FAIL

AI03472

39/41

M29W800DT, M29W800DB

REVISION HISTORY

Table 30. Document Revision History

Version

Revision Details

August 2001

1.0

First Issue

Block Protection Appendix added, SO44 drawing and package mechanical data updated,

CFI Table 26, address 39h/72h data clarified, Read/Reset operation during Erase

Suspend clarified

03-Dec-2001

2.0

Description of Ready/Busy signal clarified (and Figure 15 modified)

Clarified allowable commands during block erase

Clarified the mode the device returns to in the CFI Read Query command section

01-Mar-2002

11-Apr-2002

3.0

4.0

Temperature range 1 added

Document promoted from Preliminary Data to full Data Sheet

Erase Suspend Latency Time (typical and maximum) and Data Retention parameters

added to Table 6, Program, Erase Times and Program, Erase Endurance Cycles, and

Typical after 100k W/E Cycles column removed. Minimum voltage corrected for 70ns

Speed Class in Table 9, Operating and AC Measurement Conditions.

31-Mar-2003

4.1

Logic Diagram and Data Toggle Flowchart corrected.

Lead-free package options E and F added to Table 20, Ordering Information Scheme.

TSOP48 package Outline and Mechanical Data updated.

13-Feb-2004

23-Apr-2004

5.0

6.0

TFBGA48 6x8mm – 6x8 active ball array – 0.80mm pitch added.

Table 9.Operating and AC Measurement Conditions updated for 70ns speed option.

Figure 3., SO Connections updated.

40/41

M29W800DT, M29W800DB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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41/41


型号：	M29W800DT90ZA1F
厂家：	ST
描述：	8 Mbit (1Mb x8 or 512Kb x16, Boot Block) 3V Supply Flash Memory
文件：	总41页 (文件大小：651K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M29W800DT90ZA1F [STMICROELECTRONICS]

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