M36W0R6040T0ZAQF [STMICROELECTRONICS]
SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88;
| 型号： | M36W0R6040T0ZAQF |
| 厂家： | 
ST |
| 描述： | SPECIALTY MEMORY CIRCUIT, PBGA88, 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88 闪存 静态存储器 |
| 文件： | 总18页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M36W0R6040T0
M36W0R6040B0
64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory
and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
FEATURES SUMMARY
■
MULTI-CHIP PACKAGE
Figure 1. Package
–
–
1 die of 64 Mbit (4Mb x 16) Flash Memory
1 die of 16 Mbit (1Mb x 16) Pseudo SRAM
■
SUPPLY VOLTAGE
VDDF = VDDP = VDDQ = 1.7V to 1.95V
–
FBGA
■
■
LOW POWER CONSUMPTION
ELECTRONIC SIGNATURE
–
–
Manufacturer Code: 20h
Device Code (Top Flash Configuration),
M36W0R6040T0: 8810h
–
Device Code (Bottom Flash
Configuration), M36W0R6040B0: 8811h
Stacked TFBGA88 (ZA)
8 x 10mm
■
PACKAGES
–
Compliant with Lead-Free Soldering
Processes
–
Lead-Free Versions
FLASH MEMORY
■
■
BLOCK LOCKING
■
PROGRAMMING TIME
–
–
–
All blocks locked at Power-up
Any combination of blocks can be locked
WPF for Block Lock-Down
–
8µs by Word typical for Fast Factory
Program
–
–
Double/Quadruple Word Program option
Enhanced Factory Program options
SECURITY
–
–
128-bit user programmable OTP cells
64-bit unique device number
■
■
MEMORY BLOCKS
–
Multiple Bank Memory Array: 4 Mbit
Banks
■
■
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
–
Parameter Blocks (Top location)
SYNCHRONOUS / ASYNCHRONOUS READ
PSRAM
–
–
Synchronous Burst Read mode: 66MHz
Asynchronous/ Synchronous Page Read
mode
■
■
■
ACCESS TIME: 70ns
LOW STANDBY CURRENT: 110µA
DEEP POWER DOWN CURRENT: 10µA
–
Random Access: 70ns
■
DUAL OPERATIONS
–
Program Erase in one Bank while Read in
others
–
No delay between Read and Write
operations
December 2004
1/18
M36W0R6040T0, M36W0R6040B0
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A20-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Output Enable (GF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Latch Enable (LF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Clock (KF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Wait (WAITF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSRAM Chip Enable (E1P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSRAM Chip Enable (E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSRAM Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Write Enable (WP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
DDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
V
V
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
FLASH MEMORY DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PSRAM DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/18
M36W0R6040T0, M36W0R6040B0
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. PSRAM DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline . . 15
Table 9. Stacked TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/18
M36W0R6040T0, M36W0R6040B0
SUMMARY DESCRIPTION
The M36W0R6040T0 and M36W0R6040B0 are
Multiple Memory Products which combine two
memory devices; a 64-Mbit, Multiple Bank Flash
memories, the M58WR064FT/B, and a 16-Mbit
Pseudo SRAM, the M69AR024B. Recommended
operating conditions do not allow more than one
memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8x10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
Table 1. Signal Names
A0-A19
Common Address Inputs
DQ0-DQ15
Common Data Input/Output
Flash Memory Power Supply
V
DDF
Common Flash and PSRAM Power
Supply for I/O Buffers
V
V
DDQ
Common Flash Optional Supply
Voltage for Fast Program & Erase
PPF
V
V
Ground
SS
PSRAM Power Supply
Not Connected Internally
Do Not Use as Internally Connected
DDP
NC
DU
All packages are compliant with Lead-free solder-
ing processes.
The memory is supplied with all the bits erased
(set to ‘1’).
Flash Memory Control Functions
Address Inputs for the Flash memory
only
A21-A20
Figure 2. Logic Diagram
L
Latch Enable input
Chip Enable input
Output Enable input
Write Enable input
Reset input
F
V
V
PPF
DDQ
E
F
V
V
DDF
DDP
G
F
22
16
DQ0-DQ15
W
F
A0-A21
RP
F
WP
Write Protect input
Burst Clock
F
E
G
F
F
F
K
F
WAIT
F
WAIT
Wait Data in Burst Mode
F
W
PSRAM control functions
RP
F
E1
G
Chip Enable input
P
WP
F
Output Enable input
Write Enable input
P
L
F
M36W0R6040T
M36W0R6040B
W
P
K
F
E2
Power-down input
P
E1
P
UB
LB
Upper Byte Enable input
Lower Byte Enable input
P
G
P
P
W
P
E2
P
UB
P
P
LB
V
SS
AI08448
4/18
M36W0R6040T0, M36W0R6040B0
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
DU
A4
A5
A3
A2
A1
A0
DU
A21
NC
DU
DU
A11
A12
A13
A15
A16
NC
A18
A19
NC
NC
NC
V
V
NC
V
SS
SS
DDF
LB
P
NC
K
F
A17
A7
V
W
P
E
P
A9
PPF
WP
L
F
A20
A8
A10
A14
WAIT
F
A6
UB
P
RP
W
F
F
G
H
J
DQ8
DQ0
DQ2
DQ1
DQ9
NC
DQ10
DQ3
DQ11
NC
DQ5
DQ12
DQ4
DQ13
DQ14
DQ6
NC
F
G
P
DQ7
NC
NC
G
F
DQ15
V
DDQ
E
F
K
L
NC
V
V
E2
P
DDP
DDQ
V
V
V
V
V
V
V
V
SS
SS
DDQ
DDF
SS
SS
SS
SS
DU
DU
M
DU
DU
AI08525
5/18
M36W0R6040T0, M36W0R6040B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A19). Addresses A0-A19
are common inputs for the Flash Memory and
PSRAM components. The Address Inputs select
the cells in the memory array to access during Bus
Read operations. During Bus Write operations
they control the commands sent to the Command
Interface of the Flash memory Program/Erase
Controller, and they select the cells to access in
the PSRAM.
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064F(T/B) datasheet).
Flash Reset (RPF). The Reset input provides a
hardware reset of the memory. When Reset is at
VIL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to
Table 6., Flash Memory DC Characteristics - Cur-
rents, for the value of IDD2. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at VIH, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Flash memory is accessed through the Chip
Enable signal (E ) and through the Write Enable
F
(WF) signal, while the PSRAM is accessed through
two Chip Enable signals (E1P and E2P) and the
Write Enable signal (WP).
Address Inputs (A20-A21). Addresses A20-A21
are inputs for the Flash memory component only.
The Flash memory is accessed through the Chip
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
(refer to Table 7., Flash Memory DC Characteris-
tics - Voltages).
Enable signals (E ) and through the Write Enable
F
(WF) signal.
Flash Latch Enable (LF). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, VIL,
and it is inhibited when Latch Enable is High, VIH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (KF). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at VIL. Clock is don't care during
Asynchronous Read and in write operations.
Data Input/Output (DQ0-DQ15). For the Flash
memory, the Data I/O outputs the data stored at
the selected address during a Bus Read operation
or inputs a command or the data to be pro-
grammed during a Write Bus operation.
For the PSRAM, the Upper Byte Data Inputs/Out-
puts carry the data to or from the upper part of the
selected address during a Write or Read opera-
tion, when Upper Byte Enable (UBP) is driven Low.
Likewise, the Lower Byte Data Inputs/Outputs car-
ry the data to or from the lower part of the selected
address during a Write or Read operation, when
Lower Byte Enable (LBP) is driven Low.
Flash Chip Enable (EF). The Chip Enable in-
puts activate the memory control logics, input buff-
ers, decoders and sense amplifiers. When Chip
Enable is Low, VIL, and Reset is High, VIH, the de-
vice is in active mode. When Chip Enable is at VIH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is re-
duced to the standby level.
Flash Wait (WAITF). WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at VIH or Flash Reset is at VIL. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAITF signal is not gated
by Output Enable.
Flash Output Enable (GF). The Output Enable
pins control data outputs during Flash memory
Bus Read operations.
PSRAM Chip Enable (E1P). When
asserted
(Low), the Chip Enable, E1P, activates the memo-
ry state machine, address buffers and decoders,
allowing Read and Write operations to be per-
formed. When de-asserted (High), all other pins
are ignored, and the device is put, automatically, in
low-power Standby mode.
PSRAM Chip Enable (E2P). The Chip Enable,
E2P, puts the device in Deep Power-down mode
when it is driven Low. This is the lowest power
mode.
Flash Write Enable (W ). The Write Enable
F
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
6/18
M36W0R6040T0, M36W0R6040B0
PSRAM Output Enable (GP). The Output En-
able, GP, provides a high speed tri-state control,
allowing fast read/write cycles to be achieved with
the common I/O data bus.
VPPF Program Supply Voltage. VPPF is both a
Flash Memory control input and a Flash Memory
power supply pin. The two functions are selected
by the voltage range applied to the pin.
PSRAM Write Enable (WP). The Write Enable,
WP, controls the Bus Write operation of the mem-
ory.
PSRAM Upper Byte Enable (UBP). The Upper
Byte Enable, UBP, gates the data on the Upper
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LBP). The Lower
Byte Enable, LBP, gates the data on the Lower
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
If VPPF is kept in a low voltage range (0V to VDDQ
)
V
PPF is seen as a control input. In this case a volt-
age lower than VPPLKF gives an absolute protec-
tion against Program or Erase, while VPPF > VPP1F
enables these functions (see Tables 6 and 7, DC
Characteristics for the relevant values). VPPF is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If VPPF is in the range of VPPHF it acts as a power
supply pin. In this condition VPPF must be stable
until the Program/Erase algorithm is completed.
VSS Ground. VSS is the common ground refer-
ence for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips.
V
DDF Supply Voltage. VDDF provides the power
supply to the internal core of the Flash memory
component. It is the main power supplies for all
Flash memory operations (Read, Program and
Erase).
Note: Each Flash memory device in a system
should have its supply voltage (VDDF) and the
program supply voltage VPPF decoupled with a
0.1µF ceramic capacitor close to the pin (high
frequency, inherently low inductance capaci-
tors should be as close as possible to the
package). See Figure 6., AC Measurement
Load Circuit. The PCB track widths should be
sufficient to carry the required VPPF program
and erase currents.
VDDP Supply Voltage. The VDDP Supply Volt-
age supplies the power for all operations (Read or
Write) and for driving the refresh logic, even when
the device is not being accessed.
V
DDQ Supply Voltage. VDDQ provides the power
supply for the Flash Memory and PSRAM I/O pins.
This allows all Outputs to be powered indepen-
dently of the Flash Memory and PSRAM core pow-
er supplies: VDDF and VDDP, respectively.
7/18
M36W0R6040T0, M36W0R6040B0
FUNCTIONAL DESCRIPTION
The Flash Memory and PSRAM components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En-
able inputs: EF for the Flash memory and E1P and
E2P for the PSRAM.
most common example is simultaneous read oper-
ations on the Flash memory and the PSRAM
which would result in a data bus contention.
Therefore it is recommended to put the other de-
vices in the high impedance state when reading
the selected device.
Recommended operating conditions do not allow
more than one device to be active at a time. The
Figure 4. Functional Block Diagram
V
V
V
DDQ
DDF
PPF
A20-A21
E
F
64 Mbit
Flash
G
F
Memory
W
WAIT
F
F
L
F
K
F
RP
F
WP
F
A0-A19
DQ0-DQ15
V
DDP
E1
P
16 Mbit
PSRAM
G
P
W
P
E2
P
UB
P
LB
P
V
SS
AI08449
8/18
M36W0R6040T0, M36W0R6040B0
Table 2. Main Operating Modes
(4)
E
F
G
W
L
RP
E1
E2
G
W
UB
LB
P
Operation
DQ15-DQ0
P
P
F
F
WAIT
P
P
P
P
P
F
V
V
V
V
V
Flash Read
Flash Write
Flash Data Out
Flash Data In
Flash Data Out
IL
IL
IL
IH
IL(2)
IL(2)
IH
V
V
V
IH
V
V
V
V
IL
IH
PSRAM must be disabled
Flash Address
Latch
V
V
V
IL
X
IL
IL
IH
IH
(3)
or Hi-Z
Flash Output
Disable
V
V
V
IH
V
V
X
Flash Hi-Z
IH
IH
IH
Any PSRAM mode is allowed
Flash Standby
Flash Reset
X
X
X
X
Hi-Z
Hi-Z
Flash Hi-Z
Flash Hi-Z
IH
V
X
X
X
IL
PSRAM data
out
V
V
V
V
V
V
V
V
V
PSRAM Read
IL
IH
IL
IH
IL
IL
Flash Memory must be disabled
Any Flash mode is allowed.
V
V
V
V
V
V
PSRAM Write
Output Disable
PSRAM data in
PSRAM Hi-Z
IL
IH
IH
IH
IL
IL
IL
V
X
X
IL
IH
IH
PSRAM
Standby
V
V
IH
X
X
X
X
X
X
PSRAM Hi-Z
PSRAM Hi-Z
IH
PSRAM Deep
Power-Down
V
X
X
X
IL
Note: 1. X = Don't care.
2. L can be tied to V if the valid address has been previously latched.
F
IH
3. Depends on G .
F
4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064F(T/B) datasheet for details.
9/18
M36W0R6040T0, M36W0R6040B0
FLASH MEMORY DEVICE
The M36W0R6040T0 and M36W0R6040B0 con-
tain a 64Mbit Flash memory. For detailed informa-
tion on how to use it, see the M58WR064F(T/B)
datasheet which is available from your local STMi-
croelectronics distributor.
PSRAM DEVICE
The M36W0R6040T0 and M36W0R6040B0 con-
tain a 16Mbit PSRAM. For detailed information on
how to use it, see the M69AR024B datasheet
which is available from your local STMicroelec-
tronics distributor.
10/18
M36W0R6040T0, M36W0R6040B0
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
–30
–40
–65
Max
85
T
Ambient Operating Temperature
Temperature Under Bias
°C
°C
°C
°C
V
A
T
125
155
(1)
BIAS
T
Storage Temperature
STG
T
Lead Temperature during Soldering
Input or Output Voltage
LEAD
V
V
+0.6
–0.5
–0.2
–0.2
–0.2
–0.2
IO
DDQ
V
Flash Memory Core Supply Voltage
Input/Output Supply Voltage
PSRAM Supply Voltage
2.45
2.45
3.3
V
DDF
V
V
DDQ
V
V
DDP
V
Flash Memory Program Voltage
Output Short Circuit Current
14
V
PPF
I
100
mA
hours
O
t
Time for V
at V
PPF PPFH
100
VPPFH
®
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
11/18
M36W0R6040T0, M36W0R6040B0
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Flash Memory
PSRAM
Parameter
Unit
Min
1.7
–
Max
1.95
–
Min
–
Max
–
V
V
V
Supply Voltage
V
V
V
V
DDF
DDP
DDQ
Supply Voltage
Supply Voltage
1.7
–
1.95
–
1.7
11.4
1.95
12.6
VPPF Supply Voltage (Factory environment)
VPPF Supply Voltage (Application environment)
Ambient Operating Temperature
–
–
V
+0.4
–0.4
–40
–
–
V
°C
pF
ns
V
DDQ
85
–30
85
Load Capacitance (C )
30
50
L
Input Rise and Fall Times
5
0 to V
0 to V
Input Pulse Voltages
DDQ
DDP
V
/2
DDQ
V
/2
DDP
Input and Output Timing Ref. Voltages
V
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VDDQ
V
DDQ
VDDF
VDDQ
V
/2
DDQ
16.7kΩ
0V
DEVICE
UNDER
TEST
AI06161
CL
0.1µF
16.7kΩ
0.1µF
CL includes JIG capacitance
AI08364
Table 5. Device Capacitance
Symbol
Parameter
Test Condition
Min
Max
12
Unit
C
V
IN
= 0V
= 0V
Input Capacitance
Output Capacitance
pF
pF
IN
C
V
OUT
15
OUT
Note: Sampled only, not 100% tested.
12/18
M36W0R6040T0, M36W0R6040B0
Table 6. Flash Memory DC Characteristics - Currents
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Typ
Max
±1
Unit
µA
I
LI
0V ≤ V ≤ V
IN
DDQ
I
LO
0V ≤ V
≤ V
OUT DDQ
±1
µA
Supply Current
Asynchronous Read (f=6MHz)
E = V , G = V
IH
3
6
mA
F
IL
F
4 Word
8 Word
7
16
18
22
25
17
20
25
30
50
50
50
15
20
15
20
mA
mA
mA
mA
mA
mA
mA
mA
µA
10
12
13
8
Supply Current
Synchronous Read (f=54MHz)
16 Word
Continuous
4 Word
I
DD1
8 Word
11
14
16
10
10
10
8
Supply Current
Synchronous Read (f=66MHz)
16 Word
Continuous
I
I
I
RP = V ± 0.2V
Supply Current (Reset)
DD2
DD3
DD4
F
SS
E = V
± 0.2V
Supply Current (Standby)
µA
F
DDF
E = V , G = V
IH
Supply Current (Automatic Standby)
µA
F
IL
F
V
V
V
V
= V
mA
mA
mA
mA
PPF
PPH
DDF
PPH
DDF
Supply Current (Program)
Supply Current (Erase)
= V
= V
= V
10
8
PPF
PPF
PPF
(1)
I
DD5
10
Program/Erase in one
Bank, Asynchronous
Read in another Bank
13
26
mA
Supply Current
(Dual Operations)
(1,2)
(1)
I
DD6
Program/Erase in one
Bank, Synchronous
Read in another Bank
23
10
45
50
mA
µA
Supply Current Program/ Erase
Suspended (Standby)
E = V
± 0.2V
I
I
F
DDF
DD7
V
= V
2
5
5
5
5
5
5
mA
µA
mA
µA
µA
µA
PPF
PPF
PPF
PPF
PPF
PPH
DDF
PPH
DDF
DDF
V
Supply Current (Program)
Supply Current (Erase)
PPF
PPF
V
V
V
V
V
= V
= V
= V
≤ V
≤ V
0.2
2
(1)
PP1
V
0.2
0.2
0.2
I
V
V
Supply Current (Read)
PP2
PPF
(1)
Supply Current (Standby)
I
PPF
PPF
DDF
PP3
Note: 1. Sampled only, not 100% tested.
2. V Dual Operation current is the sum of read and program or erase currents.
DDF
13/18
M36W0R6040T0, M36W0R6040B0
Table 7. Flash Memory DC Characteristics - Voltages
Symbol
Parameter
Input Low Voltage
Test Condition
Min
Typ
Max
Unit
V
V
IL
–0.5
0.4
V
V
V
–0.4
V
+ 0.4
DDQ
Input High Voltage
Output Low Voltage
Output High Voltage
V
IH
DDQ
V
I
= 100µA
OL
0.1
V
OL
V
I
= –100µA
OH
–0.1
V
OH
DDQ
V
V
Program Voltage-Logic
Program, Erase
Program, Erase
1.1
1.8
12
3.3
12.6
0.4
V
PP1
PPF
PPF
V
V
Program Voltage Factory
11.4
V
PPH
V
Program or Erase Lockout
V Lock Voltage
DDF
V
PPLK
V
LKO
1
V
RP pin Extended High
Voltage
F
V
3.3
V
RPH
Table 8. PSRAM DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
t
Read /
Write =
AVAV
I
t
20
mA
CC1
AVAV
V
= 1.95V,
= V or V ,
IH IL
DDP
minimum
V
IN
V
Active Current
DDP
E1 = V and E2 = V ,
P
IL
P
IH
t
t
Read /
Write =
AVAV
I
= 0mA
OUT
I
3
mA
CC2
AVAV
maximum
I
0V ≤ V ≤ V
IN DDP
Input Leakage Current
Output Leakage Current
–1
–1
1
1
µA
µA
LI
I
LO
0V ≤ V
≤ V
OUT DDP
V
= 1.95V,
DDP
I
E1 ≥ V
–0.2V or E1 ≤ V ,
P IL
–0.2V or V ≤ 0.2V
IN
Deep Power Down Current
10
µA
µA
PD
P
DDP
DDP
V
≥ V
IN
V
= 1.95V,
DDP
Standby Supply Current
CMOS
I
E1 = E2 ≥ V
–0.3V,
110
SB
P
P
DDP
I
= 0mA
OUT
(1)
0.8V
V
DDP
+ 0.2
Input High Voltage
Input Low Voltage
V
V
V
DDP
IH
(2)
–0.3
0.4
0.2
V
IL
V
–
DDP
V
I
= –0.5mA
= 0.1mA
Output High Voltage
Output Low Voltage
V
OH
OH
0.2
V
I
OL
V
OL
Note: 1. The maximum DC voltage on input and I/O pins is V
periods of up to 5ns.
+0.2V. During voltage transitions, inputs may overshoot V
by 1.0V for
DDP
DDP
2. The minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, inputs may undershoot V by 1.0V for periods
SS
of up to 5ns.
14/18
M36W0R6040T0, M36W0R6040B0
PACKAGE MECHANICAL
Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Outline
D
D1
e
SE
E
E2 E1
b
BALL "A1"
ddd
FE FE1
FD
SD
A
A2
A1
BGA-Z42
Note: Drawing is not to scale.
Table 9. Stacked TFBGA88 8x10mm - 8x10 ball array, 0.8mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.200
0.0079
0.850
0.350
8.000
5.600
0.0335
0.0138
0.3150
0.2205
0.300
7.900
0.400
8.100
0.0118
0.3110
0.0157
0.3189
D
D1
ddd
E
0.100
0.0039
0.3976
10.000
7.200
8.800
0.800
1.200
1.400
0.600
0.400
0.400
9.900
10.100
0.3937
0.2835
0.3465
0.0315
0.0472
0.0551
0.0236
0.0157
0.0157
0.3898
E1
E2
e
–
–
–
–
FD
FE
FE1
SD
SE
15/18
M36W0R6040T0, M36W0R6040B0
PART NUMBERING
Table 10. Ordering Information Scheme
Example:
M36 W0 R 6 0 4 0 T 0 ZAQ T
Device Type
M36 = Multiple Memory Product (Multiple Flash + RAM)
Flash 1 Architecture
W = Multiple Bank, Burst mode
Flash 2 Architecture
0 = none present
Operating Voltage
R = V
= V
=V
= 1.7V to 1.95V
DDF
DDQ
DDP
Flash 1 Density
6 = 64 Mbit
Flash 2 Density
0 = none present
RAM 1 Density
4 = 16 Mbit
RAM 0 Density
0 = none present
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
Product Version
0 = 0.13µm Flash technology, 70ns;
0.18µm RAM, 70ns speed
Package
ZAQ = Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-Free and RoHS Package, Standard Packing
F = Lead-Free and RoHS Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-
tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST-
Microelectronics Sales Office nearest to you.
16/18
M36W0R6040T0, M36W0R6040B0
REVISION HISTORY
Table 11. Document Revision History
Date
Version
Revision Details
07-Nov-2003
1.0
First Issue
Document status promoted from Target Specification to full Datasheet.
Package specification updated. The TFBGA88 package is fully compliant with the ST
ECOPACK specification.
Flash memory and PSRAM data updated to the M58WR064FT/B datasheet version
5.0 of 08-Oct-2004 and to the M69AR024B datasheet version 6.0 of 29-Sep-2004,
respectively.
02-Dec-2004
2.0
17/18
M36W0R6040T0, M36W0R6040B0
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
18/18
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