M40Z111MH6E [STMICROELECTRONICS]
5V or 3V NVRAM supervisor for up to two LPSRAMs; 5V或3V NVRAM主管长达两个LPSRAMs
| 型号： | M40Z111MH6E |
| 厂家： | 
ST |
| 描述： | 5V or 3V NVRAM supervisor for up to two LPSRAMs |
| 文件： | 总21页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M40Z111
M40Z111W
5V or 3V NVRAM supervisor for up to two LPSRAMs
Features
■ Convert low power SRAMs into NVRAMs
■ Precision power monitoring and power
switching circuitry
SNAPHAT (SH)
battery
■ Automatic write-protection when V is out-of-
CC
tolerance
■ Choice of supply voltages and
power-fail deselect voltages:
– M40Z111: V = 4.5 to 5.5V
CC
THS = V ; 4.5 ≤ V
≤ 4.75V
SS
PFD
THS = V
; 4.2 ≤ V
≤ 4.5V
PFD
OUT
– M40Z111W: V = 3.0 to 3.6V
CC
THS = V ; 2.8 ≤ V
CC
≤ 3.0V
SS
PFD
V
= 2.7 to 3.3V
THS = V
; 2.5 ≤ V
≤ 2.7V
28
OUT
PFD
1
■ Less than 15ns chip enable access
propagation delay (for 5.0v device)
■ Packaging includes a 28-lead SOIC and
®
SOH28 (MH)
SNAPHAT top (to be ordered separately)
■ SOIC package provides direct connection for a
SNAPHAT top which contains the battery
■ RoHS compliant
– Lead-free second level interconnect
November 2007
Rev 4
1/21
www.st.com
1
Contents
M40Z111, M40Z111W
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
Data retention lifetime calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 10
V
3
4
5
6
7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
M40Z111, M40Z111W
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 16
4-pin SNAPHAT housing for 48mAh battery, package mechanical data . . . . . . . . . . . . . . 17
4-pin SNAPHAT housing for 120mAh battery, package mechanical data . . . . . . . . . . . . . 18
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
List of figures
M40Z111, M40Z111W
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SOIC28 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 15
4-pin SNAPHAT housing for 48mAh battery, package outline . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. 4-pin SNAPHAT housing for 120mAh battery, package outline . . . . . . . . . . . . . . . . . . . . . 18
4/21
M40Z111, M40Z111W
Description
1
Description
The M40Z111/W NVRAM supervisor is a self-contained device which converts a standard
low-power SRAM into a non-volatile memory.
A precision voltage reference and comparator monitors the V input for an out-of-tolerance
CC
condition.
When an invalid V condition occurs, the conditioned chip enable (E
) output is forced
CC
CON
inactive to write-protect the stored data in the SRAM.
During a power failure, the SRAM is switched from the V pin to the lithium cell within the
CC
®
SNAPHAT to provide the energy required for data retention. On a subsequent power-up,
the SRAM remains write protected until a valid power condition returns.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
connection to a separate SNAPHAT housing containing the battery. The unique design
allows the SNAPHAT battery package to be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the
high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape
& Reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is
“M4Z28-BR00SH1” or “M4Z32-BR00SH1” (See Table 11 on page 19).
Figure 1.
Logic diagram
V
CC
THS
V
E
OUT
M40Z111
M40Z111W
E
CON
V
SS
AI02238B
5/21
Description
M40Z111, M40Z111W
Table 1.
Signal names
THS
Threshold select input
Chip enable input
E
ECON
VOUT
VCC
VSS
NC
Conditioned chip enable output
Supply voltage output
Supply voltage
Ground
Not connected internally
Figure 2.
SOIC28 connections
V
1
28
V
E
OUT
NC
CC
2
27
NC
NC
NC
3
26
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E
4
25
5
24
23
V
V
6
CC
NC
7
M40Z111 22
M40Z111W
8
21
20
19
18
17
16
15
CC
NC
9
NC
NC
NC
10
11
12
13
14
THS
CON
V
NC
SS
AI02239B
6/21
M40Z111, M40Z111W
Figure 3. Hardware hookup
Description
3.0, 3.3, or 5V
V
V
V
CC
CC
OUT
E2
CMOS
SRAM
1N5817 or
MBR5120T3
0.1μF
0.1μF
M40Z111/W
E
E
CON
E
x8 or x16
Thereshold
THS
V
SS
AI02394
7/21
Operation
M40Z111, M40Z111W
2
Operation
The M40Z111/W, as shown in Figure 3 on page 7, can control up to two standard low-power
SRAMs. These SRAMs must be configured to have the chip enable input disable all other
input signals. Most slow, low-power SRAMs are configured like this, however many fast
SRAMs are not. During normal operating conditions, the conditioned chip enable (E
)
CON
output pin follows the chip enable (E) input pin with timing shown in Table 2 on page 10. An
internal switch connects V to V . This switch has a voltage drop of less than 0.3V
CC
OUT
(I
).
OUT1
When V degrades during a power failure, E
is forced inactive independent of E. In this
CC
CON
situation, the SRAM is unconditionally write protected as V falls below an out-of-tolerance
CC
threshold (V
). The power fail detection value associated with V
is selected by the
PFD
PFD
THS pin and is shown in Table 6 on page 14.
Note:
Note: The THS pin must be connected to either V or V
.
OUT
SS
If chip enable access is in progress during a power fail detection, that memory cycle
continues to completion before the memory is write protected. If the memory cycle is not
terminated within time t , E
is unconditionally driven high, write protecting the SRAM.
WP CON
A power failure during a write cycle may corrupt data at the currently addressed location, but
does not jeopardize the rest of the SRAM's contents. At voltages below V (min), the user
PFD
can be assured the memory will be write protected provided the V fall time exceeds t .
CC
F
As V continues to degrade, the internal switch disconnects V and connects the internal
CC
CC
battery to V
. This occurs at the switchover voltage (V ). Below the V , the battery
OUT
SO SO
provides a voltage V
to the SRAM and can supply current I
(see Table 6 on
OHB
OUT2
page 14). When V rises above V , V
is switched back to the supply voltage. Output
CC
SO OUT
E
is held inactive for t (200ms maximum) after the power supply has reached V
,
CON
ER
PFD
independent of the E input, to allow for processor stabilization (see Figure 5 on page 9).
2.1
Data retention lifetime calculation
Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of which SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and
SRAMs to be “Don't Care” once V falls below V
(min). The SRAM should also
CC
PFD
guarantee data retention down to V = 2.0V. The chip enable access time must be
CC
sufficient to meet the system needs with the chip enable propagation delays included. If the
SRAM includes a second chip enable pin (E2), this pin should be tied to V
. If data
OUT
retention lifetime is a critical parameter for the system, it is important to review the data
retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0V.
Manufacturers generally specify a typical condition for room temperature along with a worst
case condition (generally at elevated temperatures). The system level requirements will
determine the choice of which value to use. The data retention current value of the SRAMs
can then be added to the I
value of the M40Z111/W to determine the total current
CCDR
requirements for data retention.
8/21
M40Z111, M40Z111W
Operation
®
The available battery capacity for the SNAPHAT of your choice can then be divided by this
current to determine the amount of data retention available (see Table 11 on page 19). For
more information on Battery Storage Life refer to the Application Note AN1012.
Figure 4.
Power down timing
V
V
CC
(max)
(min)
PFD
PFD
PFD
V
V
V
SO
tF
tFB
E
E
tWPT
V
OHB
CON
AI02396
Figure 5.
Power up timing
V
V
CC
(max)
(min)
PFD
PFD
PFD
V
V
V
SO
tR
tRB
tER
E
E
tEDH
tEDL
V
OHB
CON
AI02397
9/21
Operation
M40Z111, M40Z111W
Table 2.
Symbol
Power down/up AC characteristics
Parameter(1)
Min
Max
Unit
(2)
tF
VPFD (max) to VPFD (min) VCC fall time
VPFD (min) to VSS VCC fall time
300
10
10
1
µs
µs
µs
µs
ns
ns
ns
ns
ms
µs
µs
(3)
tFB
tR
VPFD (min) to VPFD (max) VCC rise time
VSS to VPFD (min) VCC rise time
tRB
M40Z111
M40Z111W
M40Z111
15
20
tEDL
Chip enable propagation delay
10
tEDH
Chip enable propagation delay
Chip enable recovery
Write protect time
M40Z111W
20
(4)
tER
40
40
40
200
150
250
M40Z111
tWPT
M40Z111W
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring
until 200 µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. tER (min) = 20ms for industrial temperature range - grade 6 device.
2.2
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in
Figure 6) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from V to V (cathode connected to V , anode to V ).
CC
SS
CC
SS
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
10/21
M40Z111, M40Z111W
Figure 6.
Operation
Supply voltage protection
V
CC
V
V
CC
0.1μF
DEVICE
SS
AI00622
11/21
Maximum rating
M40Z111, M40Z111W
3
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient operating temperature
Grade 6
SNAPHAT®
SOIC
–40 to 85
–40 to 85
–55 to 125
260
°C
°C
°C
°C
V
TSTG
Storage temperature (VCC off)
(1)
TSLD
VIO
Lead solder temperature for 10 seconds
Input or output voltages
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to 4.6
20
Supply voltage
M40Z111
V
VCC
M40Z111W
V
IO
Output current
mA
W
PD
Power dissipation
1
1. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260°C (total thermal budget
not to exceed 245°C for greater than 30 seconds).
Caution:
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up
mode.
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
12/21
M40Z111, M40Z111W
DC and AC parameters
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in Table 4:
DC and AC measurement conditions. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 4.
DC and AC measurement conditions
Parameter
M40Z111
M40Z111W
VCC supply voltage
4.5 to 5.5V
–40 to 85°C
100pF
2.7 to 3.6V
–40 to 85°C
50pF
Ambient operating temperature
Load capacitance (CL)
Input rise and fall times
Input pulse voltages
≤ 5ns
≤ 5ns
0 to 3V
1.5V
0 to 3V
1.5V
Input and output timing ref. voltages
Note:
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 7.
AC testing load circuit
645Ω
DEVICE
UNDER
TEST
(1)
1.75V
C
= 100pF
or 5pF
L
C
includes JIG capacitance
L
AI02326
1. 50pF for M40Z111W.
Table 5.
Symbol
CIN
Capacitance
Parameter(1)(2)
Input capacitance
Output capacitance
Min
Max
Unit
8
pF
pF
(3)
COUT
10
1. Effective capacitance measured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only,
not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected
13/21
DC and AC parameters
M40Z111, M40Z111W
Table 6.
Sym
DC characteristics
Parameter
Supply current
M40Z111
Min Typ Max
M40Z111W
Unit
Test condition(1)
Min
Typ
Max
ICC
ICCDR
ILI
Outputs open
3
6
2
4
mA
nA
Data retention mode
current
150
150
Input leakage current
Output leakage current
0V ≤ VIN ≤ VCC
1
1
1
1
µA
µA
(2)
ILO
0V ≤ VOUT ≤ VCC
V
OUT > VCC –0.3
OUT > VCC –0.2
160
100
100
65
mA
mA
IOUT1 VOUT current (active)
V
VOUT current (battery
back-up)
IOUT2
VOUT > VBAT –0.3
100
2.0 3.0
2.2
100
3.0
µA
V
VBAT Battery voltage
3.5
2.0
3.5
VCC
0.3
+
VIH
Input high voltage
VCC + 0.3 2.0
V
VIL
Input low voltage
–0.3
0.8
–0.3
2.4
0.8
V
V
V
V
V
VOH Output high voltage
VOHB VOH battery back-up
VOL Output low voltage
THS Threshold select voltage
Power-fail deselect
IOH = –2.0mA
IOUT2 = –1.0µA
IOL = 4.0mA
2.4
2.0 2.9
3.6
0.4
2.0
2.9
3.6
0.4
VSS
VOUT
VSS
VOUT
4.50 4.60
4.75
4.50
2.80
2.90
3.00
2.70
V
V
V
voltage (THS = VSS
)
VPFD
Power-fail deselect
voltage (THS = VOUT
4.20 4.35
3.0
2.50
2.60
)
Battery back-up
switchover voltage
VPFD –
100mV
VSO
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Outputs deselected.
14/21
M40Z111, M40Z111W
Package mechanical data
5
Package mechanical data
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 8.
SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT,
package outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
15/21
Package mechanical data
M40Z111, M40Z111W
Table 7.
Symbol
SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
B
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
a
N
28
28
CP
0.10
0.004
16/21
M40Z111, M40Z111W
Figure 9.
Package mechanical data
4-pin SNAPHAT housing for 48mAh battery, package outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Note:
Drawing is not to scale.
Table 8. 4-pin SNAPHAT housing for 48mAh battery, package mechanical data
Symbol
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
A3
B
9.78
7.24
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
6.99
0.38
0.46
21.21
14.22
15.55
3.20
0.56
0.018
0.835
0.560
0.612
0.126
0.080
D
21.84
14.99
15.95
3.61
E
eA
eB
L
2.03
2.29
17/21
Package mechanical data
M40Z111, M40Z111W
Figure 10. 4-pin SNAPHAT housing for 120mAh battery, package outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Note:
Drawing is not to scale.
Table 9. 4-pin SNAPHAT housing for 120mAh battery, package mechanical data
Symbol
mm
Min
inches
Min
Typ
Max
Typ
Max
A
A1
A2
A3
B
10.54
8.51
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
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M40Z111, M40Z111W
Part numbering
6
Part numbering
Table 10. Ordering information scheme
Example:
M40Z
111W
MH
6
E
Device type
M40Z
Supply voltage and write protect voltage
111 = VCC = 4.5 to 5.5V; VPFD = 4.3 to 4.5V
THS = VSS = 4.5 ≤ VPFD ≤ 4.75V
THS = VOUT = 4.2 ≤ VPFD ≤ 4.5V
111W = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7V
THS = VSS = 2.8 ≤ VPFD ≤ 3.0V
VCC = 2.7 to 3.3V
THS = VOUT = 2.5 ≤ VPFD ≤ 2.7V
Package
MH(1) = SOH28
Temperature range
6 = –40 to 85°C
Shipping method for SOIC
E = Lead-free ECOPACK® package, tubes
F = Lead-free ECOPACK® package, tape & reel
1. The SOIC package (SOH28) requires the battery package (SNAPHAT®) which is ordered separately under
the part number “M4ZXX-BR00SHX” in plastic tubes or “M4ZXX-BR00SHXTR” in tape & reel form.
Caution:
Do not place the SNAPHAT battery package “M4ZXX-BR00SH” in conductive foam as this
will drain the lithium button-cell battery.
For a list of available options (e.g., speed, package) or for further information on any aspect
of this device, please contact the ST sales office nearest to you.
Table 11. Battery table
Part number
Description
Package
M4Z28-BR00SH1 SNAPHAT housing for 48mAh battery
M4Z32-BR00SH1 SNAPHAT housing for 120mAh battery
SH
SH
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Revision history
M40Z111, M40Z111W
7
Revision history
Table 12. Document revision history
Date
Revision
Changes
Sep-2000
1
First Draft Issue
Reformatted, TOC added, changed DC Characteristics (Table 6);
changed battery, ind. temperature information (Table 3, 2, 10, 11,
Figure 9, 10); Corrected SOIC label (Figure 2); added E2 to Hookup
(Figure 3)
14-Sep-2001
2
13-May-2002
12-Nov-2007
3
4
Modify reflow time and temperature footnote (Table 3)
Reformatted document; added lead-free second level interconnect
information to cover page and Section 5: Package mechanical data;
updated Figure 5, Table 3, 10, 11.
20/21
M40Z111, M40Z111W
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