M40Z111MH6TR [STMICROELECTRONICS]
5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs; 5V或3V NVRAM主管长达两个LPSRAMs
| 型号： | M40Z111MH6TR |
| 厂家： | 
ST |
| 描述： | 5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| 文件： | 总15页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M40Z111
M40Z111W
5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs
FEATURES SUMMARY
■ CONVERT LOW POWER SRAMs INTO
Figure 1. 28-pin SOIC Package
NVRAMs
■ PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
SNAPHAT (SH)
Battery
■ AUTOMATIC WRITE-PROTECTION WHEN
V
IS OUT-OF-TOLERANCE
CC
■ CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40Z111: V = 4.5 to 5.5V
CC
THS = V ; 4.5 ≤ V
≤ 4.75V
≤ 4.5V
PFD
SS
PFD
THS = V
; 4.2 ≤ V
OUT
– M40Z111W: V = 3.0 to 3.6V
CC
28
THS = V ; 2.8 ≤ V
≤ 3.0V
PFD
SS
1
V
= 2.7 to 3.3V
CC
SOH28 (MH)
THS = V
; 2.5 ≤ V
OUT
≤ 2.7V
PFD
■ LESS THAN 15ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device)
■ PACKAGING INCLUDES A 28-LEAD SOIC and
®
SNAPHAT TOP (to be ordered separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP WHICH
CONTAINS THE BATTERY
May 2002
1/15
M40Z111, M40Z111W
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SOIC28 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Hardware Hookup (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC Testing Load Circuit (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Down Timing (Figure 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Up Timing (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply Voltage Protection (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Battery Table (Table 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
M40Z111, M40Z111W
SUMMARY DESCRIPTION
The M40Z111/W NVRAM SUPERVISOR is a self-
contained device which converts a standard low-
power SRAM into a non-volatile memory.
nection to a separate SNAPHAT housing contain-
ing the battery. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process.
A precision voltage reference and comparator
monitors the V input for an out-of-tolerance con-
CC
dition.
Insertion of the SNAPHAT housing after reflow
prevents potential battery damage due to the high
temperatures required for device surface-mount-
ing. The SNAPHAT housing is keyed to prevent
reverse insertion.
When an invalid V
tioned chip enable (E
to write-protect the stored data in the SRAM.
During a power failure, the SRAM is switched from
condition occurs, the condi-
CC
) output is forced inactive
CON
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form. For the 28-lead SOIC, the battery package
(e.g., SNAPHAT) part number is “M4Z28-
BR00SH” or “M4Z32-BR00SH” (See Table 8,
page 10).
the
V
pin to the lithium cell within the
CC
®
SNAPHAT to provide the energy required for
data retention. On a subsequent power-up, the
SRAM remains write protected until a valid power
condition returns.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
Figure 2. Logic Diagram
Table 1. Signal Names
THS
E
Threshold Select Input
Chip Enable Input
V
CC
E
Conditioned Chip Enable Output
Supply Voltage Output
Supply Voltage
CON
V
OUT
THS
E
V
E
OUT
M40Z111
M40Z111W
V
CC
SS
V
Ground
CON
NC
Not Connected Internally
Figure 3. SOIC28 Connections
V
V
1
28
V
E
SS
OUT
NC
CC
AI02238B
2
27
NC
NC
NC
3
26
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E
4
25
5
24
23
V
V
6
CC
NC
7
M40Z111 22
M40Z111W
8
21
20
19
18
17
16
15
CC
NC
9
NC
NC
NC
10
11
12
13
14
THS
CON
V
NC
SS
AI02239B
3/15
M40Z111, M40Z111W
Figure 4. Hardware Hookup
3.0, 3.3, or 5V
V
V
V
CC
CC
OUT
E2
CMOS
SRAM
1N5817 or
MBR5120T3
0.1µF
0.1µF
M40Z111/W
E
E
CON
E
x8 or x16
Thereshold
THS
V
SS
AI02394
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
Grade 6
–40 to 85
°C
®
–40 to 85
–55 to 125
260
°C
°C
°C
SNAPHAT
SOIC
T
Storage Temperature (V Off)
STG
CC
(1)
SLD
Lead Solder Temperature for 10 seconds
T
V
–0.3 to V +0.3
Input or Output Voltages
Supply Voltage
V
V
IO
CC
M40Z111
–0.3 to 7.0
V
CC
M40Z111W
–0.3 to 4.6
V
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
4/15
M40Z111, M40Z111W
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. DC and AC Measurement Conditions
Parameter
M40Z111
4.5 to 5.5V
–40 to 85°C
100pF
M40Z111W
2.7 to 3.6V
–40 to 85°C
50pF
V
CC
Supply Voltage
Ambient Operating Temperature
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 5ns
≤ 5ns
0 to 3V
0 to 3V
Input Pulse Voltages
1.5V
1.5V
Input and Output Timing Ref. Voltages
Note: Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
(1)
1.75V
C
= 100pF
or 5pF
L
C
includes JIG capacitance
L
AI02326
Note: 1. 50pF for M40Z111W.
Table 4. Capacitance
Symbol
(1,2)
Min
Max
8
Unit
Parameter
C
Input Capacitance
Output Capacitance
pF
pF
IN
(3)
10
C
OUT
Note: 1. Effective capacitance measured with power supply at 5V (M40Z111) or 3.3V (M40Z111W); sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected
5/15
M40Z111, M40Z111W
Table 5. DC Characteristics
M40Z111
M40Z111W
Test
Sym
Parameter
Unit
(1)
Condition
Min
Typ
Max
Min
Typ
Max
I
Supply Current
Outputs open
3
6
2
4
mA
nA
CC
Data Retention Mode
Current
I
150
±1
150
±1
CCDR
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
µA
I
IN
CC
LI
(2)
0V ≤ V
≤ V
CC
±1
±1
100
65
µA
mA
mA
I
OUT
LO
V
V
> V –0.3
160
100
OUT
OUT
CC
I
I
V
V
Current (Active)
Current (Battery
OUT1
OUT
> V –0.2
CC
OUT
V
> V
–0.3
100
100
µA
OUT2
OUT
BAT
Back-up)
V
Battery Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
2.0
2.2
3.0
V
3.5
2.0
2.0
3.0
V
3.5
V
V
V
V
V
V
V
BAT
V
+ 0.3
+ 0.3
CC
IH
CC
V
–0.3
2.4
0.8
–0.3
2.4
0.8
IL
V
V
I
= –2.0mA
= –1.0µA
OH
OH
V
OH
Battery Back-up
I
OUT2
2.0
2.9
3.6
0.4
2.0
2.9
3.6
0.4
OHB
V
I
OL
= 4.0mA
Output Low Voltage
OL
V
V
OUT
V
V
OUT
THS Threshold Select Voltage
Power-fail Deselect
SS
SS
4.50
4.20
4.60
4.35
3.0
4.75
2.80
2.50
2.90
2.60
3.00
V
V
V
Voltage (THS = V
)
SS
V
PFD
Power-fail Deselect
4.50
2.70
Voltage (THS = V
)
OUT
V
–
Battery Back-up
Switchover Voltage
PFD
V
SO
100mV
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
A
CC
2. Outputs deselected.
6/15
M40Z111, M40Z111W
OPERATION
The M40Z111/W, as shown in Figure 4, page 4,
can control up to two standard low-power SRAMs.
These SRAMs must be configured to have the
chip enable input disable all other input signals.
Most slow, low-power SRAMs are configured like
this, however many fast SRAMs are not. During
normal operating conditions, the conditioned chip
above V , V
voltage. Output E
is switched back to the supply
SO
OUT
is held inactive for t
ER
CON
(200ms maximum) after the power supply has
reached V , independent of the E input, to allow
PFD
for processor stabilization (see Figure 7, page 8).
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40Z111/W NVRAM SUPERVI-
SOR. There are, however some criteria which
should be used in making the final choice of which
SRAM to use. The SRAM must be designed in a
way where the chip enable input disables all other
inputs to the SRAM. This allows inputs to the
M40Z111/W and SRAMs to be “Don't Care” once
enable (E
) output pin follows the chip enable
CON
(E) input pin with timing shown in Table 6, page 9.
An internal switch connects V to V . This
CC
OUT
switch has a voltage drop of less than 0.3V
(I ).
OUT1
When V degrades during a power failure, E
CC
CON
is forced inactive independent of E. In this situa-
tion, the SRAM is unconditionally write protected
V
falls below V
(min). The SRAM should
CC
PFD
as V
falls below an out-of-tolerance threshold
). The power fail detection value associated
CC
also guarantee data retention down to V = 2.0V.
CC
(V
PFD
The chip enable access time must be sufficient to
meet the system needs with the chip enable prop-
agation delays included. If the SRAM includes a
second chip enable pin (E2), this pin should be
with V
is selected by the THS pin and is shown
PFD
in Table 5, page 6.
Note: The THS pin must be connected to either
V
or V
.
tied to V
. If data retention lifetime is a critical
SS
OUT
OUT
parameter for the system, it is important to review
the data retention current specifications for the
particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0V.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
,
WP
E
is unconditionally driven high, write protect-
Manufacturers generally specify a typical condi-
tion for room temperature along with a worst case
condition (generally at elevated temperatures).
The system level requirements will determine the
choice of which value to use. The data retention
current value of the SRAMs can then be added to
CON
ing the SRAM.
A power failure during a write cycle may corrupt
data at the currently addressed location, but does
not jeopardize the rest of the SRAM's contents. At
voltages below V
sured the memory will be write protected provided
the V fall time exceeds t .
As V
disconnects V and connects the internal battery
to V
(min), the user can be as-
PFD
the I
value of the M40Z111/W to determine
CCDR
the total current requirements for data retention.
CC
F
®
The available battery capacity for the SNAPHAT
continues to degrade, the internal switch
CC
of your choice can then be divided by this current
to determine the amount of data retention avail-
able (see Table 8, page 10). For more information
on Battery Storage Life refer to the Application
Note AN1012.
CC
. This occurs at the switchover voltage
OUT
(V ). Below the V , the battery provides a volt-
age V
SO
SO
to the SRAM and can supply current
OHB
I
(see Table 5, page 6). When V
rises
OUT2
CC
7/15
M40Z111, M40Z111W
Figure 6. Power Down Timing
V
CC
V
V
V
(max)
(min)
PFD
PFD
PFD
V
SO
tF
tFB
E
E
tWPT
V
OHB
CON
AI02396
Figure 7. Power Up Timing
V
CC
V
V
V
(max)
(min)
PFD
PFD
PFD
V
SO
tR
tRB
tER
E
E
tEDH
tEDL
V
OHB
CON
AI02397
8/15
M40Z111, M40Z111W
Table 6. Power Down/Up AC Characteristics
(1)
Symbol
Min
Max
Unit
µs
Parameter
(2)
V
V
(max) to V
(min) to V
(min) V Fall Time
300
t
PFD
PFD
CC
F
(3)
V
Fall Time
10
10
1
µs
t
PFD
PFD
SS CC
FB
t
V
V
(min) to V
(max) V Rise Time
µs
µs
ns
ns
ns
ns
R
PFD CC
t
to V
(min) V Rise Time
PFD CC
RB
SS
M40Z111
M40Z111W
M40Z111
15
20
10
20
t
Chip Enable Propagation Delay
EDL
t
Chip Enable Propagation Delay
Chip Enable Recovery
Write Protect Time
EDH
M40Z111W
(4)
40
200
ms
t
ER
M40Z111
40
40
150
250
µs
µs
t
WPT
M40Z111W
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after V
PFD CC
PFD
passes V
(min).
PFD
3. V
(min) to V fall time of less than tFB may cause corruption of RAM data.
PFD
SS
4. t (min) = 20ms for Industrial Temperature Range - Grade 6 device.
ER
V
Noise And Negative Going Transients
Figure 8. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
8) is recommended in order to provide the needed
filtering.
V
CC
V
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
AI00622
mends connecting a schottky diode from V
to
CC
V
(cathode connected to V , anode to V ).
SS
CC SS
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
9/15
M40Z111, M40Z111W
PART NUMBERING
Table 7. Ordering Information Scheme
Example:
M40Z
111W
MH
6
TR
Device Type
M40Z
Supply Voltage and Write Protect Voltage
111 = V
= 4.5 to 5.5V; V
= 4.3 to 4.5V
CC
PFD
PFD
THS = V = 4.5 ≤ V
≤ 4.75V
SS
THS = V
= 4.2 ≤ V
≤ 4.5V
OUT
PFD
111W = V = 2.7 to 3.6V; V
= 2.6 to 2.7V
≤ 3.0V
CC
PFD
THS = V = 2.8 ≤ V
SS
PFD
V
= 2.7 to 3.3V
CC
THS = V
= 2.5 ≤ V
≤ 2.7V
PFD
OUT
Package
(1)
MH = SOH28
Temperature Range
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
®
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT ) which is ordered separately under the part number
“M4ZXX-BR00SHX” in plastic tube or “M4ZXX-BR00SHXTR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package “M4ZXX-BR00SH” in conductive foam as this will drain the lithium button-cell
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 8. Battery Table
Part Number
M4Z28-BR00SH
M4Z32-BR00SH
Description
Package
SH
SNAPHAT Housing for 48mAh Battery
SNAPHAT Housing for 120mAh Battery
SH
10/15
M40Z111, M40Z111W
PACKAGE MECHANICAL INFORMATION
Figure 9. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 9. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
11/15
M40Z111, M40Z111W
Figure 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Note: Drawing is not to scale.
Table 10. 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
12/15
M40Z111, M40Z111W
Figure 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A2
A3
A1
A
eA
D
B
L
eB
E
SHZP-A
Note: Drawing is not to scale.
Table 11. 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
13/15
M40Z111, M40Z111W
REVISION HISTORY
Table 12. Document Revision History
Date
Revision Details
September 2000 First Draft Issue
Reformatted, TOC added, changed DC Characteristics (Table 5); changed battery, ind.
temperature information (Tables 2, 6, 7, 8, Figures 10, 11); Corrected SOIC label (Figure 3); added
E2 to Hookup (Figure 4)
09/14/01
05/13/02
Modify reflow time and temperature footnote (Table 2)
14/15
M40Z111, M40Z111W
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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