M41ST85W [STMICROELECTRONICS]
5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR; 5.0或3.0V , 512位64 ×8串行实时时钟和NVRAM监控型号: | M41ST85W |
厂家: | ST |
描述: | 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR |
文件: | 总33页 (文件大小:455K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M41ST85Y
M41ST85W
5.0 OR 3.0V, 512 bit (64 x 8) SERIAL
RTC and NVRAM SUPERVISOR
FEATURES SUMMARY
■ 5.0 OR 3.0V OPERATING VOLTAGE
■ PACKAGING INCLUDES A 28-LEAD SOIC and
®
2
SNAPHAT TOP (to be Ordered Separately)
■ SERIAL INTERFACE SUPPORTS I C BUS
(400 KHz)
■ SOIC SNAPHAT PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY and
CRYSTAL
■ NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
■ OPTIMIZED FOR MINIMAL INTERCONNECT
■ SOIC EMBEDDED CRYSTAL PACKAGE (MX)
TO MCU
OPTION
■ 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
Figure 1. 28-pin SOIC Package
■ AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
SNAPHAT (SH)
Battery & Crystal
■ CHOICE OF POWER-FAIL DESELECT
VOLTAGES
– M41ST85Y: V = 4.5 to 5.5V;
CC
4.20V ≤ V
≤ 4.50V
PFD
– M41ST85W: V = 2.7 to 3.6V;
CC
2.55V ≤ V
≤ 2.70V
PFD
■ 1.25V REFERENCE (for PFI/PFO)
■ COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
28
1
SOH28 (MH)
■ 44 BYTES OF GENERAL PURPOSE RAM
■ PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
Figure 2. 28-pin (300mil) SOIC Package
EMBEDDED Crystal
■ WATCHDOG TIMER
■ MICROPROCESSOR POWER-ON RESET
■ BATTERY LOW FLAG
■ POWER-DOWN TIMESTAMP (HT BIT)
■ ULTRA-LOW BATTERY SUPPLY CURRENT
SOX28 (MX)
OF 500nA (MAX)
May 2003
1/33
Rev. 4.0
M41ST85Y, M41ST85W
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. 28-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. AC Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Serial Bus Data Transfer Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. WRITE Cycle Timing: RTC & External SRAM Control Signals . . . . . . . . . . . . . . . . . . . 12
Figure 12. Bus Timing Requirements Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. Alternate READ Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. WRITE Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/33
M41ST85Y, M41ST85W
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
t
Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REC
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. t Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REC
Table 13. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. Crystal Accuracy Across Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22. Calibration Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
M41ST85Y, M41ST85W
SUMMARY DESCRIPTION
The M41ST85Y/W Serial TIMEKEEPER /Con-
troller SRAM is a low power 512-bit, static CMOS
SRAM organized as 64 words by 8 bits. A built-in
32.768 kHz oscillator (external crystal controlled)
and 8 bytes of the SRAM (see Table 8, page 18)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
®
29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.
The M41ST85Y/W is supplied in a 28-lead SOIC
®
SNAPHAT package (which integrates both crys-
tal and battery in a single SNAPHAT top) or a 28-
pin, 300mil SOIC package (MX) which includes an
embedded 32kHz crystal.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
An additional 12 bytes of RAM provide status/con-
trol of Alarm, Watchdog and Square Wave func-
tions. Addresses and data are transferred serially
2
via a two line, bi-directional I C interface. The
built-in address register is incremented automati-
cally after each WRITE or READ data byte. The
M41ST85Y/W has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button-cell supply when a power fail-
ure occurs.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table 15, page 27).
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Functions available to the user include a non-vol-
atile, time-of-day clock/calendar, Alarm interrupts,
Watchdog Timer and programmable Square
Wave output. Other features include a Power-On
Reset as well as two additional debounced inputs
(RSTIN1 and RSTIN2) which can also generate an
output Reset (RST). The eight clock address loca-
tions contain the century, year, month, date, day,
hour, minute, second and tenths/hundredths of a
second in 24 hour BCD format. Corrections for 28,
The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile op-
eration.
4/33
M41ST85Y, M41ST85W
Figure 3. Logic Diagram
Table 1. Signal Names
E
Conditioned Chip Enable Output
External Chip Enable
CON
(1)
V
V
BAT
EX
CC
Interrupt/Frequency Test/Out Output
(Open Drain)
IRQ/FT/OUT
PFI
Power Fail Input
Power Fail Output
Reset Output (Open Drain)
Reset 1 Input
SCL
SDA
E
CON
PFO
RST
RST
EX
RSTIN1
RSTIN2
SCL
M41ST85Y
M41ST85W
IRQ/FT/OUT
SQW
Reset 2 Input
RSTIN1
RSTIN2
WDI
Serial Clock Input
Serial Data Input/Output
Square Wave Output
Watchdog Input
Supply Voltage
SDA
PFO
SQW
WDI
V
OUT
PFI
V
CC
V
Voltage Output
OUT
V
Ground
SS
V
SS
AI03658
(1)
Battery Supply Voltage
V
BAT
Note: 1. For 28-pin, 300mil embedded crystal SOIC only.
Note: 1. For 28-pin, 300mil embedded crystal SOIC only.
Figure 4. 28-pin SOIC Connections
Figure 5. 28-pin, 300mil SOIC (MX)
Connections
SQW
NC
1
2
3
4
5
6
28
27
26
25
24
23
V
CC
EX
NC
NC
1
2
3
4
5
6
28
27
26
25
24
23
V
CC
EX
IRQ/FT/OUT
NC
IRQ/FT/OUT
NC
NC
V
OUT
NC
NC
V
V
OUT
SS
NC
NC
NC
NC
NC
PFI
SCL
NC
NC
7 M41ST85Y 22
PFI
NC
NC
7 M41ST85Y 22
M41ST85W
WDI
RSTIN1
RSTIN2
NC
8
21
20
19
18
17
16
15
M41ST85W
SQW
WDI
8
21
20
19
18
17
16
15
9
SCL
NC
9
NC
10
11
12
13
14
10
11
12
13
14
RST
NC
RSTIN1
RSTIN2
PFO
RST
NC
NC
SDA
PFO
SDA
NC
E
V
CON
BAT
V
E
CON
SS
V
SS
AI03659
AI06370c
5/33
M41ST85Y, M41ST85W
Figure 6. Block Diagram
REAL TIME CLOCK
CALENDAR
SDA
SCL
44 BYTES
2
USER RAM
I C
INTERFACE
AFE
RTC w/ALARM
& CALIBRATION
(1)
IRQ/FT/OUT
SQW
WDS
WATCHDOG
(2)
32KHz
OSCILLATOR
Crystal
SQUARE WAVE
WDI
V
V
CC
OUT
V
BAT
BL
COMPARE
COMPARE
V
= 2.5V
= 2.5V
BL
V
SO
POR
COMPARE
V
= 4.4V
PFD
(2.65V for ST85W)
(1)
RST
RSTIN1
RSTIN2
E
CON
EX
PFI
PFO
COMPARE
1.25V
(Internal)
AI03932
Note: 1. Open drain output
2. Integrated into SOIC package for MX package option.
6/33
M41ST85Y, M41ST85W
Figure 7. Hardware Hookup
M41ST85Y/W
Regulator
Unregulated
Voltage
V
V
V
V
V
IN
CC
CC
OUT
CC
E
E
CON
M68Z128Y/W
or
EX
M68Z512Y/W
SCL
WDI
SDA
RST
RSTIN1
RSTIN2
To RST
SQW
PFO
To LED Display
To NMI
Pushbutton
Reset
R1
R2
PFI
(1)
IRQ/FT/OUT
To INT
V
BAT
V
SS
AI03660
Note: 1. Required for embedded crystal (MX) package only.
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 85
–55 to 125
260
Unit
°C
®
SNAPHAT
SOIC
Storage Temperature (V
Off, Oscillator Off)
T
CC
STG
°C
(1)
Lead Solder Temperature for 10 seconds
Input or Output Voltage
°C
T
SLD
–0.3 to V +0.3
CC
V
IO
V
V
M41ST85Y
M41ST85W
–0.3 to 7
V
Supply Voltage
CC
–0.3 to 4.6
V
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
7/33
M41ST85Y, M41ST85W
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. DC and AC Measurement Conditions
Parameter
M41ST85Y
4.5 to 5.5V
–40 to 85°C
100pF
M41ST85W
2.7 to 3.6V
–40 to 85°C
50pF
V
Supply Voltage
CC
Ambient Operating Temperature
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
≤ 50ns
0.2 to 0.8V
0.2 to 0.8V
CC
CC
0.3 to 0.7V
0.3 to 0.7V
CC
Input and Output Timing Ref. Voltages
CC
Note: Output High Z is defined as the point where data is no longer driven.
Figure 8. AC Testing Input/Output Waveforms
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Note: 50pF for M41ST85W.
Table 4. Capacitance
(1,2)
Symbol
Min
Max
Unit
Parameter
C
Input Capacitance
Output Capacitance
7
pF
pF
ns
IN
(3)
10
50
C
OUT
t
Low-pass filter input time constant (SDA and SCL)
LP
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs are deselected.
8/33
M41ST85Y, M41ST85W
Table 5. DC Characteristics
M41ST85Y
Typ
M41ST85W
Unit
Test
Sym
Parameter
(1)
Condition
Min
Max
Min
Typ
Max
Battery Current OSC
ON
400
50
500
400
500
nA
T
V
V
= 25°C,
A
(2)
= 0V,
= 3V
I
CC
BAT
Battery Current OSC
OFF
BAT
50
nA
mA
mA
I
Supply Current
f = 400kHz
1.4
1
0.75
0.50
CC1
SCL, SDA =
Supply Current
(Standby)
I
CC2
V
– 0.3V
CC
0V ≤ V
≤
IN
Input Leakage Current
±1
25
±1
25
µA
nA
µA
mA
µA
V
CC
(3)
LI
I
Input Leakage Current
(PFI)
–25
2
–25
2
0V ≤ V
≤
Output Leakage
Current
IN
(4)
±1
±1
I
LO
V
CC
V
>
OUT1
(5)
V
OUT
Current (Active)
175
100
100
100
I
OUT1
V
V
– 0.3V
CC
V
>
V
OUT
Current (Battery
OUT2
– 0.3V
I
OUT2
Back-up)
BAT
0.7V
V
+ 0.3 0.7V
CC
V
+ 0.3
V
Input High Voltage
Input Low Voltage
Battery Voltage
V
V
V
V
IH
CC
CC
CC
0.3V
0.3V
V
–0.3
2.5
–0.3
2.5
IL
CC
CC
(9)
(9)
V
BAT
3.0
2.9
3.0
2.9
3.5
3.5
(6)
V
OH
I
= –1.0mA
2.4
2.4
OH
Output High Voltage
I
=
OUT2
(7)
V
OH
(Battery Back-up)
2.5
3.5
2.5
3.5
V
V
V
V
OHB
–1.0µA
I
= 3.0mA
Output Low Voltage
Output Low Voltage
0.4
0.4
0.4
0.4
OL
V
OL
I
= 10mA
OL
(8)
(Open Drain)
V
Power Fail Deselect
PFI Input Threshold
PFI Hysteresis
4.20
4.40
1.250
20
4.50
1.275
70
2.55
2.60
2.70
1.275
70
V
V
PFD
V
V
= 5V(Y)
= 3V(V)
CC
1.225
1.225 1.250
CC
V
PFI
PFI Rising
20
mV
V
Battery Back-up
Switchover
V
2.5
2.5
SO
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
A
CC
2. Measured with V
and E
open.
OUT
CON
3. RSTIN1 and RSTIN2 internally pulled-up to V through 100KΩ resistor. WDI internally pulled-down to V through 100KΩ resistor.
CC
SS
4. Outputs Deselected.
5. External SRAM must match RTC SUPERVISOR chip V specification.
CC
6. For PFO and SQW pins (CMOS).
7. Conditioned output (E
duce battery life.
) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will re-
CON
8. For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than V , this supply must be equal to, or less than 3.0V when
CC
V
= 0V (during battery back-up mode).
CC
9. For rechargeable back-up, V
(max) may be considered V
.
CC
BAT
9/33
M41ST85Y, M41ST85W
OPERATING MODES
The M41ST85Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 64 bytes con-
tained in the device can then be accessed sequen-
tially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
conserve battery life. As system power returns and
rises above V , the battery is disconnected,
V
CC
SO
and the power supply is switched to external V
.
CC
Write protection continues until V
reaches
CC
V
(min) plus t
PFD
(min).
REC
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
6. Date Register
7. Month Register
8. Year Register
9. Control Register
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
21 - 64. User RAM
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
The M41ST85Y/W clock continually monitors V
for an out-of-tolerance condition. Should V
CC
fall
CC
High.
below V
, the device terminates an access in
PFD
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
falls below V , the device automati-
CC
SO
cally switches over to the battery and powers
down into an ultra low current mode of operation to
10/33
M41ST85Y, M41ST85W
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Figure 9. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 10. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
1
2
8
9
MASTER
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
11/33
M41ST85Y, M41ST85W
Figure 11. WRITE Cycle Timing: RTC & External SRAM Control Signals
EX
tEXPD
tEXPD
E
CON
AI03663
Figure 12. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Table 6. AC Characteristics
Symbol
(1)
Min
0
Max
Unit
kHz
µs
Parameter
f
t
SCL Clock Frequency
400
SCL
BUF
Time the bus must be free before a new transmission can start
M41ST85Y
1.3
10
15
t
EX to E
Propagation Delay
ns
EXPD
CON
M41ST85W
t
SDA and SCL Fall Time
Data Hold Time
300
ns
µs
F
(2)
0
t
HD:DAT
START Condition Hold Time
(after this period the first clock pulse is generated)
t
600
ns
HD:STA
t
Clock High Period
Clock Low Period
SDA and SCL Rise Time
Data Setup Time
600
1.3
ns
µs
ns
ns
HIGH
t
LOW
t
300
R
t
100
600
600
SU:DAT
START Condition Setup Time
(only relevant for a repeated start condition)
t
t
ns
ns
SU:STA
STOP Condition Setup Time
SU:STO
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
A
CC
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
12/33
M41ST85Y, M41ST85W
READ Mode
In this mode the master reads the M41ST85Y/W
slave after setting the slave address (see Figure
13, page 13). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 14,
page 13).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
The data byte which was addressed will be trans-
mitted and the master receiver will send an Ac-
knowledge Bit to the slave transmitter. The
address pointer is only incremented on reception
of an Acknowledge Clock. The M41ST85Y/W
slave transmitter will now place the data byte at
address An+1 on the bus, the master receiver
reads and acknowledges the new byte and the ad-
dress pointer is incremented to An+2.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41ST85Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 15, page 14).
Figure 13. Slave Address Location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
Figure 14. READ Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
13/33
M41ST85Y, M41ST85W
Figure 15. Alternate READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
WRITE Mode
In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 16, page 14. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
13, page 13) and again after it has received the
word address and each data byte.
Figure 16. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
14/33
M41ST85Y, M41ST85W
Data Retention Mode
With valid V applied, the M41ST85Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST85Y/W will automatically deselect,
write protecting itself (and any external SRAM)
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M41ST85Y/W and SRAMs to be “Don’t Care”
CC
once V
falls below V
(min). The SRAM
CC
PFD
when
V
falls between
V
(max) and
should also guarantee data retention down to
V =2.0 volts. The chip enable access time must
CC
CC
PFD
V
(min). This is accomplished by internally in-
PFD
hibiting access to the clock registers. At this time,
the Reset pin (RST) is driven active and will re-
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
main active until V returns to nominal levels. Ex-
CC
ternal RAM access is inhibited in a similar manner
this pin should be tied to V
.
OUT
by forcing E
0.2 volts of the V
as long as V remains at an out-of-tolerance con-
dition. When V
to a high level. This level is within
CON
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
. E
will remain at this level
BAT
CON
CC
falls below the Battery Back-up
CC
Switchover Voltage (V ), power input is switched
SO
®
from the V
pin to the SNAPHAT battery, and
CC
the clock registers and external SRAM are main-
tained from the attached battery supply.
All outputs become high impedance. The V
is capable of supplying 100 µA of current to the at-
tached memory with less than 0.3 volts drop under
pin
OUT
the SRAMs can then be added to the I
value of
BAT
this condition. On power up, when V
returns to
the M41ST85Y/W to determine the total current re-
CC
a nominal value, write protection continues for
by inhibiting E . The RST signal also re-
quirements for data retention. The available bat-
®
t
tery capacity for the SNAPHAT of your choice
REC
CON
mains active during this time (see Figure 17, page
16).
Note: Most low power SRAMs on the market to-
day can be used with the M41ST85Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
can then be divided by this current to determine
the amount of data retention available (see Table
15, page 27).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
15/33
M41ST85Y, M41ST85W
Figure 17. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
PFO
tDR
tREC
RECOGNIZED
RECOGNIZED
INPUTS
RST
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
E
CON
AI03661
Table 7. Power Down/Up AC Characteristics
(1)
Symbol
Min
300
10
Typ
Max
Unit
Parameter
(2)
V
V
(max) to V
(min) to V
(min) V
Fall Time
CC
µs
t
F
PFD
PFD
(3)
V
Fall Time
µs
µs
µs
µs
µs
t
PFD
SS CC
FB
t
PD
EX at V before Power Down
0
IH
t
PFI to PFO Propagation Delay
15
25
PFD
t
V
PFD
(min) to V
(max) V
Rise Time
CC
10
1
R
PFD
V to V
SS
(min) V Rise Time
CC
t
PFD
RB
(4)
Power up Deselect Time
40
200
ms
t
REC
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
A
CC
2. V
(max) to V
PFD
(min) fall time of less than t may result in deselection/write protection not occurring until
PFD F
200µs after V passes V
(min).
PFD
CC
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
PFD
SS FB
4. Programmable (see Table 12, page 25)
16/33
M41ST85Y, M41ST85W
CLOCK OPERATION
The eight byte clock register (see Table 8, page
18) is used to both set the clock and to read the
date and time from the clock, in a binary coded
decimal format. Tenths/Hundredths of Seconds,
Seconds, Minutes, and Hours are contained within
the first four registers.
Note: A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (de-
pending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h con-
tains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a '0' the oscillator restarts
within one second.
eight clock addresses are being read. If a clock ad-
dress is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Note: When a power failure occurs, the Halt Up-
date Bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the TIME-
®
KEEPER registers, and will allow the user to read
the exact time of the power-down event. Resetting
the HT Bit to a '0' will allow the clock to update the
TIMEKEEPER registers with the current time.
®
TIMEKEEPER Registers
The M41ST85Y/W offers 20 internal registers
which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
™
referred to as BiPORT TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary Format.
17/33
M41ST85Y, M41ST85W
®
Table 8. TIMEKEEPER Register Map
Data
Function/Range
BCD Format
Address
D7
D6
0.1 Seconds
10 Seconds
D5
D4
D3
D2
D1
D0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
0.01 Seconds
Seconds
Seconds
00-99
00-59
00-59
0-1/00-23
01-7
ST
0
Seconds
Minutes
Century/Hours
Day
10 Minutes
Minutes
CEB
TR
0
CB
0
10 Hours
Hours (24 Hour Format)
Day of Week
Date: Day of Month
Month
0
0
0
0
10 Date
Date
01-31
01-12
00-99
0
0
0
10M
Month
10 Years
Year
Year
OUT
WDS
AFE
RPT4
RPT3
RPT2
RPT1
WDF
0
FT
S
Calibration
Control
Watchdog
Al Month
Al Date
Al Hour
Al Min
BMB4 BMB3 BMB2 BMB1 BMB0
RB1
RB0
SQWE
RPT5
HT
ABE
AI 10 Date
AI 10 Hour
Al 10M
Alarm Month
Alarm Date
01-12
01-31
00-23
00-59
00-59
Alarm Hour
Alarm 10 Minutes
Alarm 10 Seconds
Alarm Minutes
Alarm Seconds
Al Sec
AF
0
0
BL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flags
0
0
0
0
Reserved
Reserved
Reserved
SQW
0
0
0
0
0
0
RS3
RS2
RS1
RS0
Keys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to zero
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
OUT = Output level
HT = Halt Update Bit
AFE = Alarm Flag Enable Flag
TR = t
Bit
REC
18/33
M41ST85Y, M41ST85W
Calibrating the Clock
The M41ST85Y/W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not exceed +/–35 PPM
(parts per million) oscillator frequency error at
uct is packaged in a non-user serviceable enclo-
sure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop Bit (ST, D7 of 01h) is '0,' the Fre-
quency Test Bit (FT, D6 of 08h) is '1,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 09h) is '1' or
the Watchdog Register (09h = 0) is reset.
o
25 C, which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than +1/–2
ppm at 25°C.
The oscillation rate of crystals changes with tem-
perature (see Figure 21, page 26). Therefore, the
M41ST85Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure 22, page 26.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration Bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
512.010124 Hz would indicate a +20 PPM oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequen-
cy.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register (08h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor to V for proper
CC
operation. A 500 to10k resistor is recommended in
order to control the rise time. The FT Bit is cleared
on power-down.
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M41ST85Y/W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5–RPT1 put the alarm in the repeat mode
of operation. Table 9, page 20 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5–RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT/OUT pin as shown in
Figure 18, page 20. To disable alarm, write '0' to
the Alarm Date Register and to RPT5–RPT1.
Two methods are available for ascertaining how
much calibration a given M41ST85Y/W may re-
quire.
Note: If the address pointer is allowed to incre-
ment to the Flag Register address, an alarm con-
dition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
dress. It should also be noted that if the last ad-
dress written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEP-
ER CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final prod-
®
19/33
M41ST85Y, M41ST85W
The IRQ/FT/OUT output is cleared by a READ to
the Flags Register. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Bat-
tery Back-up Mode Enable) and AFE are set. The
ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST85Y/W was in the de-
select mode during power-up. Figure 19, page 21
illustrates the back-up mode alarm timing.
Figure 18. Alarm Interrupt Reset Waveform
0Eh
0Fh
10h
ACTIVE FLAG
IRQ/FT/OUT
HIGH-Z
AI03664
Table 9. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per Month
Once per Year
20/33
M41ST85Y, M41ST85W
Figure 19. Back-Up Mode Alarm Waveform
V
V
CC
PFD
V
SO
tREC
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
HIGH-Z
HIGH-Z
AI03920
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds).
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over.
Note: The WDI pin should be tied to V
if not
SS
used.
In order to perform a software reset of the watch-
dog timer, the original time-out period can be writ-
ten into the Watchdog Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the frequency test func-
tion is activated, the watchdog function prevails
and the frequency test function is denied.
Note: The accuracy of the timer is within ± the se-
lected resolution.
If the processor does not reset the timer within the
specified period, the M41ST85Y/W sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for t
. The Watchdog register, FT, AFE, ABE
REC
and SQWE Bits will reset to a '0' at the end of a
Watchdog time-out when the WDS Bit is set to a
'1.'
21/33
M41ST85Y, M41ST85W
Square Wave Output
The M41ST85Y/W offers the user a programma-
ble square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish
the square wave output frequency. These fre-
quencies are listed in Table 10. Once the selection
of the SQW frequency has been completed, the
SQW pin can be turned on and off under software
control with the Square Wave Enable Bit (SQWE)
located in Register 0Ah.
Table 10. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
0
RS2
0
RS1
0
RS0
0
Frequency
None
32.768
8.192
4.096
2.048
1.024
512
Units
–
0
0
0
1
kHz
kHz
kHz
kHz
kHz
Hz
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
22/33
M41ST85Y, M41ST85W
Power-on Reset
Reset Inputs (RSTIN1 & RSTIN2)
The M41ST85Y/W continuously monitors V
.
The M41ST85Y/W provides two independent in-
puts which can generate an output reset. The du-
ration and function of these resets is identical to a
reset generated by a power cycle. Table 11 and
Figure 20 illustrate the AC reset characteristics of
CC
When V
falls to the power fail detect trip point,
CC
the RST pulls low (open drain) and remains low on
power-up for t after V passes V (max).
REC
CC
PFD
The RST pin is an open drain output and an appro-
priate pull-up resistor should be chosen to control
rise time.
this function. Pulses shorter than t
and
RLRH1
t
will not generate a reset condition. RSTIN1
RLRH2
and RSTIN2 are each internally pulled up to V
CC
through a 100kΩ resistor.
Figure 20. RSTIN1 & RSTIN2 Timing Waveforms
RSTIN1
tRLRH1
RSTIN2
tRLRH2
RST (1)
tR1HRH
tR2HRH
AI03665
Note: With pull-up resistor
Table 11. Reset AC Characteristics
(1)
Symbol
Min
200
100
40
Max
Unit
ns
Parameter
(2)
RSTIN1 Low to RSTIN1 High
RSTIN2 Low to RSTIN2 High
RSTIN1 High to RST High
RSTIN2 High to RST High
t
RLRH1
RLRH2
(3)
(4)
ms
ms
ms
t
200
200
t
R1HRH
R2HRH
(4)
40
t
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
A
CC
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. Programmable (see Table 12, page 25).
23/33
M41ST85Y, M41ST85W
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an in-
ternal reference voltage (1.25V). If PFI is less than
BL Bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
the power-fail threshold (V ), the Power-Fail
PFI
Output (PFO) will go low. This function is intended
for use as an undervoltage detector to signal a fail-
ing power supply. Typically PFI is connected
through an external voltage divider (see Figure 7,
page 7) to either the unregulated DC input (if it is
available) or the regulated output of the V regu-
CC
lator. The voltage divider can be set up such that
the voltage at PFI falls below V
onds before the regulated V
several millisec-
PFI
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
input to the
CC
M41ST85Y/W or the microprocessor drops below
the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This oc-
promised due to the fact that a nominal V
is
CC
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
curs after V drops below V
(min). When pow-
CC
PFD
er returns, PFO is forced high, irrespective of V
PFI
may be replaced while V
is applied to the de-
CC
for the write protect time (t
), which is the time
REC
vice.
from V
(max) until the inputs are recognized. At
PFD
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to V and PFO
SS
The M41ST85Y/W only monitors the battery when
left unconnected.
Century Bit
a nominal V is applied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to tog-
gle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Output Driver Pin
t
Bit
REC
When the FT Bit, AFE Bit and watchdog register
are not set, the IRQ/FT/OUT pin becomes an out-
put driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ/FT/OUT pin will be driven low.
Bit D7 of Clock Register 04h contains the t
Bit
REC
(TR). t
refers to the automatic continuation of
REC
the deselect time after V reaches V
. This al-
CC
PFD
lows for a voltage settling time before WRITEs
may again be performed to the device after a pow-
er-down condition. The t
Bit will allow the user
REC
Note: The IRQ/FT/OUT pin is an open drain which
requires an external pull-up resistor.
to set the length of this deselect time as defined by
Table 12, page 25.
Battery Low Warning
Initial Power-on Defaults
The M41ST85Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watch-
dog Register, FT, AFE, ABE, SQWE, and TR. The
following bits are set to a '1' state: ST, OUT, and
HT (see Table 13, page 25).
24/33
M41ST85Y, M41ST85W
Table 12. t
Definitions
REC
t
Time
REC
t
Bit (TR)
STOP Bit (ST)
Units
REC
Min
96
Max
0
0
1
0
1
98
ms
ms
µs
(1)
40
200
X
50
2000
Note: 1. Default Setting
Table 13. Default Values
Condition
WATCHDOG
TR
0
ST
1
HT
1
Out
FT
0
AFE
ABE SQWE
(1)
Register
(2)
1
0
0
0
0
0
0
0
0
Initial Power-up
Subsequent Power-up (with
UC
UC
1
UC
0
(3)
battery back-up)
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
25/33
M41ST85Y, M41ST85W
Figure 21. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 22. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
26/33
M41ST85Y, M41ST85W
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M41ST
85Y
MH
6
TR
Device Type
M41ST
Supply Voltage and Write Protect Voltage
85Y = V
CC
= 4.5 to 5.5V; 4.20V ≤ V
≤ 4.50V
≤ 2.70V
PFD
85W = V
CC
= 2.7 to 3.6V; 2.55V ≤ V
PFD
Package
(1)
MH = SOH28
(2)
MX = SOX28
Temperature Range
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
®
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT ) which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.
2. The SOX28 package includes an embedded 32,768Hz crystal.
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 15. SNAPHAT Battery Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Package
SH
Lithium Battery (48mAh) and Crystal SNAPHAT
Lithium Battery (120mAh) and Crystal SNAPHAT
SH
27/33
M41ST85Y, M41ST85W
PACKAGE MECHANICAL INFORMATION
Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 16. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Min
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
28/33
M41ST85Y, M41ST85W
Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Min
Max
A
A1
A2
A3
B
0.3850
0.2850
0.2752
0.0150
0.0220
0.8598
0.5902
0.6280
0.1421
0.0902
6.73
6.48
0.2650
0.2551
0.46
21.21
14.22
15.55
3.20
0.0181
0.8350
0.5598
0.6122
0.1260
0.0799
D
E
eA
eB
L
2.03
29/33
M41ST85Y, M41ST85W
Figure 25. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
10.54
7.24
Typ
Min
Max
A
A1
A2
A3
B
0.4150
0.2850
0.2752
0.0150
0.0220
0.8598
0.5902
0.6280
0.1421
0.0902
6.73
6.48
0.2650
0.2551
6.99
0.38
0.46
21.21
14.22
15.55
3.20
0.56
0.0181
0.8350
0.5598
0.6122
0.1260
0.0799
D
21.84
14.99
15.95
3.61
E
eA
eB
L
2.03
2.29
30/33
M41ST85Y, M41ST85W
Figure 26. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline
D
14
1
h x 45û
C
E
H
15
28
A2
A
ddd
A1
B
e
A1
α
L
SO-E
Note: Drawing is not to scale.
Table 19. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mechanical
millimeters
inches
Symbol
Typ
Min
Max
2.69
0.31
2.39
0.51
0.31
18.01
0.10
7.67
–
Typ
Min
Max
0.106
0.012
0.094
0.020
0.012
0.709
0.004
0.302
–
A
A1
A2
B
2.44
0.096
0.006
0.090
0.016
0.008
0.705
0.15
2.29
0.41
C
0.20
D
17.91
ddd
E
7.57
–
0.298
–
e
1.27
0.050
H
10.16
0.51
0°
10.52
0.81
8°
0.400
0.020
0°
0.414
0.032
8°
L
α
N
28
28
31/33
M41ST85Y, M41ST85W
REVISION HISTORY
Table 20. Document Revision History
Date
Rev. #
1.0
Revision Details
August 2000
24-Aug-00
12-Oct-00
18-Dec-00
First issue
1.1
Block Diagram added (Figure 3)
t
Table removed, cross references corrected
1.2
REC
2.0
Reformatted, TOC added, and PFI Input Leakage Current added (Table 5)
Addition of t information, table changed, one added (Tables 8, 12); changed PFI/PFO
REC
graphic (see Figure 6); change to DC and AC Characteristics, Order Information (Tables 5,
6, 14); note added to “Setting Alarm Clock Registers” section; added temp./voltage info. to
tables (Table 4, 5, 6, 6, 7); addition of Default Values (Table 13)
18-Jun-01
2.1
22-Jun-01
26-Jul-01
07-Aug-01
20-Aug-01
2.2
3.0
3.1
3.2
Note added to Clock Operation section
Change in Product Maturity
Improve text in “Setting the Alarm Clock” section
Change V
values in document
PFD
DC Characteristics V
added; and Crystal Electrical Characteristics table removed (Tables 5, 6)
changed; V
changed; PFI Hysteresis (PFI Rising) spec.
BAT
OHB
06-Sep-01
03-Dec-01
3.3
3.4
Changed READ/WRITE Mode Sequences (Figure 14, 16); change in V
5V (M41ST85Y) part only (Table 5, 14)
lower limit for
PFD
Change t
Definition (Table 12); modify reflow time and temperature footnote (Table 2)
01-May-02
03-Jul-02
3.5
3.6
REC
Modify DC Characteristics table footnote, Default Values (Tables 5, 13)
Added embedded crystal (MX) package option; corrected initial power-up condition (Figure
2, 3, 5, 6, 7, 26, Table 1, 13, 14, 19)
15-Nov-02
3.7
24-Jan-03
25-Feb-03
3.8
4.0
Update diagrams (Figure 6, 7, 26); update values (Table 7, 11, 12, 13, 19)
New Si changes (Table 7, 11, 12); corrected dimensions (Figure 26; Table 19)
32/33
M41ST85Y, M41ST85W
M41ST85, M41ST85Y, M41ST85W, 41ST85, ST85, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVI-
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sor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C,
I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator,
Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscil-
lator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Oscillator, Crystal, Crystal, Crystal, Crystal, Crystal,
Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal,
Crystal, Crystal, Crystal, Crystal, Crystal, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ,
IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, IRQ, PFI, PFI, PFI, PFI, PFI, PFI, PFI,
PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFI, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO,
PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, PFO, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset,
Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Reset, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover,
Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Back-
up, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail,
Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Com-
parator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V,
3V, 3V, 3V, 3V, 3V, 3V
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