M41T81MH6 [STMICROELECTRONICS]
1 TIMER(S), REAL TIME CLOCK, PDSO28, 0.330 INCH, PLASTIC, SOH-28;
| 型号： | M41T81MH6 |
| 厂家： | 
ST |
| 描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28, 0.330 INCH, PLASTIC, SOH-28 时钟 光电二极管 外围集成电路 |
| 文件： | 总29页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M41T81
SERIAL ACCESS RTC WITH ALARMS
FEATURES SUMMARY
■ 2.0 TO 5.5V CLOCK OPERATING VOLTAGE
Figure 1. 8-pin SOIC Package
■ COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
8
1
■ AUTOMATIC SWITCH-OVER and DESELECT
SO8 (M)
CIRCUITRY
2
■ SERIAL INTERFACE SUPPORTS I C BUS
(400KHz PROTOCOL)
Figure 2. 28-pin SOIC Package
■ PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (valid even during Battery Back-up
Mode)
SNAPHAT (SH)
Battery & Crystal
■ WATCHDOG TIMER
■ LOW OPERATING CURRENT OF 400µA
■ BATTERY BACK-UP NOT RECOMMENDED
FOR 3.0V APPLICATIONS (CAPACITOR
BACK-UP ONLY)
■ BATTERY OR SUPER-CAP BACK-UP
28
■ OPERATING TEMPERATURE OF –40 TO
85°C
1
■ ULTRA-LOW BATTERY SUPPLY CURRENT
OF 1µA
SOH28 (MH)
May 2002
1/29
M41T81
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8-pin SOIC Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
28-pin SOIC Connections (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Measurement I/O Waveform (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Crystal Electrical Characteristics (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Bus Data Transfer Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledgement Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Timing Requirements Sequence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Slave Address Location (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
READ Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Alternative READ Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE Mode Sequence (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down/Up Mode AC Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down/Up AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down/Up Trip Points DC Characteristics (Table 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/29
M41T81
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TIMEKEEPER Register Map (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Calibrating the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting Alarm Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Alarm Interrupt Reset Waveform (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Back-up Mode Alarm Waveform (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Alarm Repeat Modes (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Square Wave Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Square Wave Output Frequency (Table 12.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Preferred Default Values (Table 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Crystal Accuracy Across Temperature (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Calibration (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SNAPHAT Battery/Crystal Table (Table 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M41T81
SUMMARY DESCRIPTION
The M41T81 Serial Access TIMEKEEPER
SRAM is a low power Serial RTC with a built-in
32.768 KHz oscillator (external crystal controlled).
Eight bytes of the SRAM (see Table 10, page 16)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 12 bytes of SRAM provide status/
control of Alarm, Watchdog and Square Wave
functions. Addresses and data are transferred se-
28, 29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.
The M41T81 is supplied in either an 8-pin SOIC or
a 28-lead SOIC SNAPHAT package (which inte-
grates both crystal and battery in a single
SNAPHAT top). The 28-pin, 330mil SOIC provides
sockets with gold plated contacts at both ends for
direct connection to a separate SNAPHAT hous-
ing containing the battery and crystal. The unique
design allows the SNAPHAT battery/crystal pack-
age to be mounted on top of the SOIC package af-
ter the completion of the surface mount process.
2
rially via a two line, bi-directional I C interface. The
built-in address register is incremented automati-
cally after each WRITE or READ data byte.
The M41T81 has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button supply when a power failure
occurs. Functions available to the user include a
non-volatile, time-of-day clock/calendar, Alarm in-
terrupts, Watchdog Timer and programmable
Square Wave output. The eight clock address lo-
cations contain the century, year, month, date,
day, hour, minute, second and tenths/hundredths
of a secondin 24 hour BCD format. Corrections for
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
ber is “M4TXX-BR12SH” (see Table 15, page 23).
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
Figure 3. Logic Diagram
Table 1. Signal Names
(1)
(1)
Oscillator Input
XI
V
V
CC BAT
(1)
Oscillator Output
XO
IRQ/OUT/
FT/SQW
Interrupt / Output Driver / Frequency
Test / Square Wave (Open Drain)
(1)
(1)
XI
XO
SDA
SCL
(1)
Serial Data Input/Output
Serial Clock Input
M41T81
IRQ/FT/OUT/SQW
SCL
SDA
Battery Supply Voltage
V
BAT
V
Supply Voltage
Ground
CC
V
SS
V
Note: 1. For SO8 package only
SS
AI04613
Note: 1. For SO8 package only.
4/29
M41T81
Figure 4. 8-pin SOIC Connections
Figure 5. 28-pin SOIC Connections
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
NC
NC
NC
NC
CC
NC
IRQ/FT/OUT/SQW
NC
NC
NC
NC
NC
SCL
NC
NC
NC
SDA
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
1
2
3
4
8
7
6
5
XI
XO
CC
IRQ/FT/OUT/SQW
SCL
SDA
M41T81
M41T81
V
BAT
V
9
SS
10
11
12
13
14
AI04769
V
SS
AI04615
Figure 6. Block Diagram
REAL TIME CLOCK
CALENDAR
32KHz
OSCILLATOR
RTC W/ALARM
& CALIBRATION
CRYSTAL
AF
WDF
(1)
IRQ/FT/OUT/SQW
WATCHDOG
SDA
SCL
2
I C
INTERFACE
SQUARE WAVE
WRITE
PROTECT
INTERNAL
POWER
V
CC
V
BAT
(2)
SO
V
COMPARE
Note 1. Open drain output
Note 2. V = V – 0.5V (typ)
SO
BAT
AI04616
5/29
M41T81
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Sym
Parameter
Value
–40 to 85
–55 to 125
260
Unit
°C
SNAPHAT
SOIC
T
Storage Temperature (V Off, Oscillator Off)
STG
CC
°C
(1)
SLD
Lead Solder Temperature for 10 Seconds
°C
T
V
I
Input or Output Voltages
Output Current
–0.3 to Vcc+0.3
V
mA
W
IO
20
1
O
P
Power Dissipation
D
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-Up Mode
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT socket.
6/29
M41T81
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M41T81
–0.3 to 7.0V
–40 to 85°C
100pF
Supply Voltage (V
)
CC
Ambient Operating Temperature (T )
A
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.2V
0.3V
to 0.8 V
to 0.7 V
CC
CC
CC
CC
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 7. AC Measurement I/O Waveform
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Table 4. Capacitance
(1,2)
Symbol
Min
Max
7
Unit
pF
Parameter
C
IN
Input Capacitance
Output Capacitance
(3)
10
50
pF
C
OUT
t
Low-pass filter input time constant (SDA and SCL)
ns
LP
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
7/29
M41T81
Table 5. DC Characteristics
(1)
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±1
±1
µA
µA
µA
µA
V
LI
IN
CC
I
0V ≤ V ≤ V
OUT CC
LO
I
Switch Freq = 400kHz
SCL,SDA = V – 0.3V
400
100
CC1
CC2
I
Supply Current (standby)
Input Low Voltage
CC
V
V
0.3V
CC
–0.3
IL
0.7V
V
+ 0.5
CC
Input High Voltage
V
IH
CC
I
= 3.0mA
= 10mA
0.4
0.4
Output Low Voltage
V
OL
V
OL
I
Output Low Voltage (Open Drain)
V
OL
(2)
(3)
(4)
Battery Supply Voltage
Battery Supply Current
3
V
V
2.5
3.5
BAT
T = 25°C, V = 0V
A
CC
I
0.8
1
µA
BAT
Oscillator ON, V
= 3V
BAT
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
2. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
3. After switchover (V ), V (min) can be 2.0V for crystal with R = 40KΩ.
SO
BAT
S
4. For rechargeable back-up, V
(max) may be considered V
.
BAT
CC
Table 6. Crystal Electrical Characteristics
(1,2,3)
Sym
Min
Typ
Max
Units
kHz
kΩ
Parameter
Resonant Frequency
f
O
32.768
R
Series Resistance
Load Capacitance
S
60
C
12.5
pF
L
Note: 1. Externally supplied if using the SO8 package. ST Microelectronics recommends the KDS DT-38 Tuning Fork Type (thru-hole) or
DMX-26 (SMD) quartz crystal for industrial temperature conditions. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kd-
sj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T81. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
3. All SNAPHAT battery/crystal tops meet these specifications.
8/29
M41T81
OPERATION
The M41T81 clock operates as a slave device on
the serial bus. Accessis obtained by implementing
a start condition followed by the correct slave ad-
dress (D0h). The 20 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
4. Century/Hours Register
5. Day Register
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
6. Date Register
7. Month Register
8. Year Register
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
The M41T81 clock continually monitors V for an
CC
fall below
out-of-tolerance condition. Should V
CC
V
, the device terminates an access in progress
SO
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge relat-
ed clock pulse. A slave receiver which is ad-
dressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
and resets the device address counter. Inputs to
the device will not be recognized at this time to
prevent erroneous data from being written to the
device from a an out-of-tolerance system. The de-
vice also automatically switches over to the battery
and powers down into an ultra low current mode of
operation to conservebattery life. As system pow-
er returns and V rises above V , the battery is
CC
SO
disconnected, and the power supply is switched to
external V
.
CC
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different IC’s. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfermay be initiated only when the bus
is not busy.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in sucha way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
– During data transfer, the data line must remain
stable whenever the clock line is High.
9/29
M41T81
Figure 8. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 9. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
1
2
8
9
MASTER
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
10/29
M41T81
Figure 10. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Table 7. AC Characteristics
Sym
(1)
Min
0
Typ
Max
Units
kHz
µs
Parameter
f
SCL Clock Frequency
Clock Low Period
400
SCL
t
1.3
600
LOW
t
Clock High Period
ns
HIGH
t
SDA and SCL Rise Time
SDA and SCL Fall Time
START Condition Hold Time
300
300
ns
R
t
ns
F
t
600
600
ns
ns
HD:STA
(after this period the first clock pulse is generated)
START Condition Setup Time
(only relevant for a repeated start condition)
t
SU:STA
(2)
Data Setup Time
100
0
ns
µs
ns
t
SU:DAT
t
Data Hold Time
HD:DAT
t
STOP Condition Setup Time
600
SU:STO
Time the bus must be free before a new
transmission can start
t
1.3
µs
BUF
Note: 1. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
11/29
M41T81
READ Mode
In this mode the master reads the M41T81 slave
after setting the slave address (see Figure 12,
page 12). Following the WRITE Mode Control Bit
(R/W=0) and the Acknowledge Bit, the word ad-
dress ’An’ is written to the on-chip address pointer.
Next the START condition and slave address are
repeated followed by the READ Mode Control Bit
(R/W=1). At this point the master transmitter be-
comes the master receiver. The data byte which
was addressed will be transmitted and the master
receiver will send an Acknowledge Bit to the slave
transmitter. The address pointer is only increment-
ed on reception of an Acknowledge Clock. The
M41T81 slave transmitter will now place the data
byte at address An+1 on the bus, the master re-
ceiver reads and acknowledges the new byte and
the address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is aclock
address (00h to 07h). The update will resume due
to aStop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T81 slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 13, page 13).
Figure 11. Slave Address Location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
Figure 12. READ Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI00899
12/29
M41T81
Figure 13. Alternative READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
WRITE Mode
In this mode the master transmitter transmits to
the M41T81 slave receiver. Bus protocol is shown
in Figure 14, page 13. Following the START con-
dition and slave address, a logic ’0’ (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T81 slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 11, page 12 and again after it has re-
ceived the word address and each data byte.
Figure 14. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
WORD
ADDRESS (An)
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
13/29
M41T81
Data Retention Mode
With valid V
applied, the M41T81 can be ac-
time, and the clock registers are maintained from
the attached battery supply.
All outputs become high impedance. On power
CC
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the
M41T81 will automatically deselect, write protect-
ing itself when V falls below the Battery Back-up
Switchover Voltage (V ). Power input is also
switched from the V
up, when V
protection continues for t
returns to a nominal value, write
CC
CC
.
REC
SO
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
pin to the battery at this
CC
Figure 15. Power Down/Up Mode AC Waveforms
V
CC
V
SO
tPD
tREC
SDA
SCL
DON’T CARE
AI00596
Table 8. Power Down/Up AC Characteristics
(1,2)
Symbol
Min
0
Typ
Max
Unit
nS
Parameter
t
SCL and SDA at V before Power Down
PD
IH
t
SCL and SDA at V after Power Up
10
µS
REC
IH
Note: 1. V fall time should not exceed 5mV/µs.
CC
2. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
Table 9. Power Down/Up Trip Points DC Characteristics
(1,2)
(3)
Sym
Typ
– 0.50
Unit
Parameter
Min
– 0.80
Max
(4)
SO
V
V
V
– 0.30
BAT
Battery Back-up Switchover Voltage and Deselect
V
V
BAT
BAT
Note: 1. All voltages referenced to V
.
SS
2. Valid for Ambient Operating Temperature: T = –40 to 85°C; V = 2.0 to 5.5V (except where noted).
A
CC
3. In 3.3V application, if initial battery voltage is ≥ 3.4V, it may be necessary to reduce battery voltage (i.e., through wave soldering
the battery) in order to avoid inadvertent switchover / deselection for V – 10% operation.
CC
4. Switchover and deselect point
14/29
M41T81
CLOCK OPERATION
The 20-byteRegister Map (see Table 10, page 16)
is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal
format. Tenths/Hundredths of Seconds, Seconds,
Minutes, and Hours are contained within the first
four registers.
Note: A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
eight clock addresses are being read. If a clock ad-
dress is being read, an update of the clock regis-
ters will be halted. This will prevent a transition of
data during the READ.
Note: Upon power-up following a power failure,
the HT Bit will automatically be set to a ’1.’ This will
prevent the clock from updating the TIMEKEEP-
ER registers, and will allow the user to read the
exact time of the power-down event. Resetting the
HT Bit to a ’0’ will allow the clock to update the
TIMEKEEPER registers with the current time.
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a ’1’ will cause CB to toggle, either from ’0’
to ’1’ or from ’1’ to ’0’ at the turn of the century (de-
pending upon its initial state). If CEB is set to a ’0,’
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h con-
tains the STOP Bit (ST). Setting this bit to a ’1’ will
cause the oscillator to stop. If the device is expect-
ed to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce cur-
rent drain. When reset to a ’0’ the oscillator restarts
within one second.
TIMEKEEPER Registers
The M41T81 offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flag, Square
Wave and Control data. These registers are mem-
ory locations which contain external (user accessi-
ble) and internal copies of the data (usually
referred to as BiPORT TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is aclock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to any non-clock address (08h-13h).
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Reg-
isters store data in Binary Format.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed in-
dependently. Provision has been made to assure
that a clock update does not occur while any of the
15/29
M41T81
Table 10. TIMEKEEPER Register Map
Addr
Function/Range
BCD Format
D7
D6
0.1 Seconds
10 Seconds
10 Minutes
D5
D4
D3
D2
D1
D0
00h
01h
02h
0.01 Seconds
Seconds
Seconds
Seconds
Minutes
00-99
00-59
00-59
ST
0
Minutes
Century/
Hours
03h
CEB
CB
10 Hours
Hours (24 Hour Format)
0-1/00-23
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
0
0
0
0
0
0
0
0
0
Day of Week
Date: Day of Month
Month
Day
Date
01-7
01-31
01-12
00-99
10 Date
0
10M
Month
10 Years
Year
Year
OUT
0
FT
BMB4
SQWE
RPT5
HT
S
Calibration
Control
Watchdog
Al Month
Al Date
Al Hour
Al Min
BMB3
ABE
BMB2
BMB1
BMB0
RB1
RB0
AFE
RPT4
RPT3
RPT2
RPT1
WDF
0
Al 10M
Alarm Month
01-12
01-31
00-23
00-59
00-59
AI 10 Date
AI 10 Hour
Alarm Date
Alarm Hour
Alarm 10 Minutes
Alarm Minutes
Alarm Seconds
Alarm 10 Seconds
Al Sec
AF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Flags
Reserved
Reserved
Reserved
SQW
0
0
0
0
0
0
RS3
RS2
RS1
RS0
Keys: S = Sign Bit
AFE = Alarm Flag Enable Flag
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to ’0’
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
RB0-RB1 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
OUT = Output level
HT = Halt Update Bit
ABE = Alarm in Battery Back-up Mode Enable Bit
16/29
M41T81
Calibrating the Clock
The M41T81 is driven by a quartz controlled oscil-
lator with a nominal frequency of 32,768 Hz. The
devices are tested not exceed +/–35 PPM (parts
which correspondsto a totalrange of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41T81 may require.
o
per million) oscillator frequency error at 25 C,
which equates to about +/–1.53 minutes per
month (see Figure 18, page 22). When the Cali-
bration circuit is properly employed, accuracy im-
proves to better than +1/–2 PPM at 25°C.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEP-
ER CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final prod-
uct is packaged in a non-user serviceable enclo-
sure. The designer could provide a simple utility
that accesses the Calibration byte.
The oscillation rate of crystals changes with tem-
perature. The M41T81 design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 19,
page 22. The number of times pulses which are
blanked (subtracted, negative calibration) or split
(added, positive calibration) depends upon the
value loaded into the five Calibration Bits found in
the Control Register. Adding counts speeds the
clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register 08h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; ’1’ indi-
cates positive calibration, ’0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT/OUT/SQW pin. The pin will toggle at
512Hz, when the Stop Bit (ST, D7 of 01h) is ’0,’ the
Frequency Test Bit (FT, D6 of 08h) is ’1,’ the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is ’0,’ and the
Square Wave Enable Bit (SQWE, D6 of 0Ah) is ’0’
and the Watchdog Register (09h = 0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
512.010124 Hz would indicate a +20 PPM oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
The IRQ/FT/OUT/SQWpin is an open drainoutput
which requires a pull-up resistor to V for proper
CC
operation. A 500-10k resistor is recommended in
order to control the rise time. The FT Bit is cleared
on power-down.
17/29
M41T81
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M41T81 is in the bat-
tery back-up mode to serve as a system wake-up
call.
Note: If the address pointer is allowed to incre-
ment to the Flag Register address, an alarm con-
dition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different ad-
dress. It should also be noted that if the last ad-
dress written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 11, page 19 shows the possi-
ble configurations. Codes not listed in the table de-
fault to the once per second mode to quickly alert
the user of an incorrect alarm setting.
The IRQ/FT/OUT/SQW output is cleared by a
READ to the Flags Register as shown in Figure
16. A subsequent READ of the Flags Register is
necessary to see that the value of the Alarm Flag
has been reset to ’0.’
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set (and SQWE is ’0.’),
the alarm condition activates the IRQ/FT/OUT/
SQW pin.
The IRQ/FT/OUT/SQW pin can also be activated
in the battery back-up mode. The IRQ/FT/OUT/
SQW will go low if an alarm occurs and both ABE
(Alarm in Battery Back-up Mode Enable) and AFE
are set. Figure 17 illustrates the back-up mode
alarm timing.
Figure 16. Alarm Interrupt Reset Waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT/SQW
AI04617
Figure 17. Back-up Mode Alarm Waveform
V
CC
V
SO
tREC
ABE and AFE Bits
AF Bit in Flags
Register
IRQ/FT/OUT/SQW
HIGH-Z
HIGH-Z
AI05663
18/29
M41T81
Table 11. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per Month
Once per Year
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00 = 1/16 second, 01 = 1/4 second,
10 = 1 second, and 11 = 4 seconds. The amount
of time-out is then determined to be the multiplica-
tion of the five-bit multiplier value with the resolu-
tion. (For example: writing 00001110 in the
Watchdog Register = 3*1, or 3 seconds). If the
processor does not reset the timer within the spec-
ified period, the M41T81 sets the WDF (Watchdog
Flag) and generates a watchdog interrupt.
The watchdogtimer can be reset by having the mi-
croprocessor perform a WRITE of the Watchdog
Register. The time-out period then starts over.
Should the watchdog timer time-out, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT/SQW pin. This
will also disable the watchdog function until it is
again programmed correctly. A READ of the Flags
Register will reset the Watchdog Flag (Bit D7;
Register 0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set, the fre-
quency test function is activated, and the SQWE
Bit is ’0,’ the watchdog function prevails and the
frequency test function is denied.
19/29
M41T81
Square Wave Output
The M41T81 offers the user a programmable
square wave function which is output on the SQW
pin. RS3-RS0 bits located in 13h establish the
square wave output frequency. These frequencies
are listed in Table 12. Once the selection of the
SQW frequency has been completed, the IRQ/FT/
OUT/SQW pin can be turned on and off under soft-
ware control with the Square Wave Enable Bit
(SQWE) located in Register 0Ah.
Table 12. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
0
RS2
0
RS1
0
RS0
0
Frequency
None
32.768
8.192
4.096
2.048
1.024
512
Units
-
0
0
0
1
kHz
kHz
kHz
kHz
kHz
Hz
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
20/29
M41T81
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a ’1’ will cause CB to tog-
gle, either from a ’0’ to ’1’ or from ’1’ to ’0’ at the turn
of the century (depending upon its initial state). If
CEB is set to a ’0,’ CB will not toggle.
cation 08h are a ’0,’ then the IRQ/FT/OUT/SQW
pin will be driven low.
Note: The IRQ/FT/OUT/SQW pin is an open drain
which requires an external pull-up resistor.
Preferred Initial Power-on Default
Upon initial application of power to the device, the
following register bits are set to a ’0’state: Watch-
dog Register; AFE; ABE; SQWE; and FT. The fol-
lowing bits are set to a ’1’ state: ST; OUT; and HT
(see Table 13, page 21).
Output Driver Pin
When the FT Bit, AFE Bit, SQWE Bit, and Watch-
dog Register are not set, the IRQ/FT/OUT/SQW
pin becomes an output driver that reflects the con-
tents of D7 of the Control Register. In other words,
when D7 (OUT Bit) and D6 (FT Bit) of address lo-
Table 13. Preferred Default Values
WATCHDOG
Condition
ST
HT
Out
FT
AFE
SQWE
ABE
(1)
Register
(2)
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
0
Initial Power-up
(3)
Power-down
Note: 1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. Assuming these bits set to ’1’ prior to power-down (except for HT Bit).
21/29
M41T81
Figure 18. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 19. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
22/29
M41T81
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M41T
81
MH
6
TR
Device Type
M41T
Supply Voltage and Write Protect Voltage
81 = V = 2.0 to 5.5V
CC
Package
M = SO8
(1)
MH = SOH28
Temperature Range
6 = –40°C to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (e.g., SNAPHAT ) which is ordered separately under the
part number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.
Caution: Do NOT place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 15. SNAPHAT Battery/Crystal Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Package
SH
Lithium Battery (48mAh)/Crystal SNAPHAT
Lithium Battery (120mAh)/Crystal SNAPHAT
SH
23/29
M41T81
PACKAGE MECHANICAL INFORMATION
Figure 20. SO8 – 8-lead Plastic Small Package Outline
A2
A
C
B
CP
e
D
N
1
E
H
A1
α
L
SO-b
Note: Drawing is not to scale.
Table 16. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mechanical Data
mm
Min
1.35
0.10
0.33
0.19
4.80
3.80
–
inches
Min
Symb
Typ
Max
1.75
0.25
0.51
0.25
5.00
4.00
–
Typ
Max
0.069
0.010
0.020
0.010
0.197
0.157
–
A
A1
B
0.053
0.004
0.013
0.007
0.189
0.150
–
C
D
E
e
1.27
0.050
H
h
5.80
0.25
0.40
0°
6.20
0.50
0.90
8°
0.228
0.010
0.016
0°
0.244
0.020
0.035
8°
L
α
N
CP
8
8
0.10
0.004
24/29
M41T81
Figure 21. SOH28 – 28-lead Plastic Small Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-B
Note: Drawing is not to scale.
Table 17. SOH28 – 28-lead Plastic Small Outline, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Min
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
a
N
28
28
CP
0.10
0.004
25/29
M41T81
Figure 22. SH – 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0
0.385
0.285
0.275
0.015
0.022
0.860
0.590
.6280
0.142
0.090
6.73
6.48
0.265
0.255
0
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
.6122
0.126
0.080
D
E
eA
eB
L
2.03
26/29
M41T81
Figure 23. SH – 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 19. SH – 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0
0.415
0.335
0.315
0.015
0.022
0.860
0.710
.6280
0.142
0.090
8.00
7.24
0.315
0.285
0
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
.6122
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
27/29
M41T81
REVISION HISTORY
Table 20. Document Revision History
Date
Revision Details
December 2001 First Issue
01/21/02
05/01/02
Fix table footnotes (Table 5, 6)
Modify reflow time and temperature footnote (Table 2)
28/29
M41T81
M41T81, 41T81, T81Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,
Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,
Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-
cess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access,
Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Ac-
cess, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Interface,Interface, Inter-
face, Interface, Interface ,Interfa ce,Interface ,Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interfa ce,Interface, Interface ,
Interface ,Interface, Interfa ce,Interface, Interface, Interface ,Interface, Interface, Interfa ce,Interface, Interface, Interface, Interface, Interfa ce,Interfa ce,Interface, Inter-
face, Interface, Interface ,Interfa ce,Interface ,Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interfa ce,Interface, Interface ,
Interface ,Interface, Interfa ce,Interface, Interface, Interface ,Interface, Interface, Interfa ce,Interface, Interface, Interface, Interface, Interfa ce,Interfa ce,Interface, Inter-
face, Interface, Interface ,Interfa ce,Interface ,Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interfa ce,Interface, Interface ,
Interface ,Interfac e,Interface, Interface, Interface ,Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,
Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,
Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,
Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,
Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,
RTC, RTC, RTC, RTC, RTC, Programmable ,Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Program-
mable, Programmable, Programmable, Programmable, Programmable,Programmable, Programmable, Programmable, Programmable, Programmable ,Programmable,
Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Pro-
grammable ,Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Program-
mable, Programmable, Programmable, Programmable, Programmable,Programmable, Programmable, Programmable, Programmable, Programmable ,Programmable,
Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable
Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm,
Alarm, Alarm, Alarm, Alarm, Alarm, Interrupt, Interrupt ,Interrupt,Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrup t,Interrupt, Interrupt, Interrupt, Inter-
rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interru pt, Interrupt, Interrupt ,Interrupt, Interrupt, Interrup t,Interrupt, Interrupt, Interrupt, Interrupt ,Interrupt,Interrupt,Interrupt,Interrupt, Interrup t,Interru pt,Interrupt, In-
terrup t,Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,Interrupt, Interrupt, Interrupt, Interru pt,Interrupt, Interrupt, Interrupt, Interrupt, Interru pt,Interrupt, Interrupt, Inter-
rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interru pt, Interrupt, Interrupt ,Interrupt, Interrupt, Interrup t,Interrupt, Interrupt, Interrupt, Interrupt ,Interrupt,Interrupt,Interrupt,Interrupt, Interrup t,Interru pt,Interrupt, In-
terrup t,Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,Interrupt, Interrupt, Interrupt, Interru pt,Interrupt, Interrupt, Interrupt, Interrupt, Interru pt,Interrupt, Interrupt, Inter-
rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interru pt, Interrupt, Interrupt ,Interrupt, Interrupt, Interrup t,Interrupt, Interrupt, Interrupt, Interrupt ,Interrupt,Interrupt,Interrupt,Interrupt, Interrup t,Interru pt,Interrupt, In-
terrup t,Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,Interrupt, Interrupt, Interrupt, Interru pt,Interrupt, Interrupt, Interrupt, Interrupt, Interru pt,Interrupt, Interrupt, Inter-
rupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog ,Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,Watchdog, Watchdog, Watchdog, Watch-
dog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,
Watchdog ,Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog,Watchdog, Watchdog, Watchdog, Watch-
dog, Watchdog, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,Battery, Battery, Battery, Battery, Battery,Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,Battery, Battery,
Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Back-
up, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write Protect, Write
Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect,
Write Protect, Write Protect, Write Protect, WriteProtect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Industri al,
Industrial, Industrial, Industrial, Industrial, Industr ial, Industrial, Industrial, Industrial, Industrial, Industrial, vIndustr ial, Indust rial, Industrial, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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