M41T83_12_技术文档

M41T82

M41T83

Serial I²C bus real-time clock (RTC) with battery switchover

Datasheet − production data

Features

■ Ultra-low battery supply current of 365 nA

■ Factory-calibrated accuracy of 5 ppm typical

after 2 reflows (SOX18)

QFN16 (4 mm x 4 mm)

– Much better accuracies achievable using

built-in programmable analog and digital

calibration circuits

■ 2.0 V to 5.5 V clock operating voltage

■ Counters for tenths/hundredths of seconds,

seconds, minutes, hours, day, date, month,

year, and century

SO8 (150 mil)

■ Automatic switchover and reset output circuitry

(fixed reference)

18

– M41T83S

V

= 3.00 V to 5.50 V

CC

(2.85 V ≤ V

– M41T83R

≤ 3.00 V)

RST

1

V

= 2.70 V to 5.50 V

CC

SOX18, embedded crystal (300 mil)

(2.55 V ≤ V

≤ 2.70 V)

RST

– M41T83Z

V

= 2.38 V to 5.50 V

CC

■ Oscillator stop detection

(2.25 V ≤ V

≤ 2.38 V)

RST

■ Battery or SuperCap™ backup

■ Operating temperature of –40 °C to 85 °C

2

■ Serial interface supports I C bus (400 kHz

protocol)

■ Package options

■ Programmable alarm with interrupt function

– a 16-lead QFN (M41T83),

– an 8-lead SOIC (M41T82), or

(valid even during battery backup mode)

nd

■ Optional 2 programmable alarm available

– an 18-lead embedded crystal SOIC

(M41T83)

■ Square wave output defaults to 32 KHz on

power-up (M41T83 only)

■ RoHS compliance: lead-free components are

■ RESET (RST) output

compliant with the RoHS directive

■ Watchdog timer

■ Programmable 8-bit counter/timer

■ 7 bytes of battery-backed user SRAM

■ Battery low flag

■ Low operating current of 80 µA

October 2012

Doc ID 12578 Rev 15

1/62

This is information on a product in full production.

www.st.com

1

Contents

M41T82-M41T83

Contents

1

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1

2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.1

2.1.2

2.1.3

2.1.4

2.1.5

Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2

2.3

2.4

2.5

Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Data retention and battery switchover (V_SO= V_RST) . . . . . . . . . . . . . . . . 18

Power-on reset (t_rec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3

Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1

3.2

Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.1

3.1.2

Example of incoherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Accessing the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Halt bit (HT) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2.1

Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

3.4

Real-time clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.4.1

3.4.2

Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 28

Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 31

3.5

3.6

3.7

3.8

Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Optional second programmable alarm and user SRAM . . . . . . . . . . . . . . 36

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.8.1

3.8.2

3.8.3

3.8.4

3.8.5

M41T83 timer interrupt/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Timer flag (TF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Timer interrupt enable (TIE, M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 39

Timer enable (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Contents

3.9

Square wave output (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.10 Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.11 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.12 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.13 Oscillator fail interrupt enable (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 43

3.14 IRQ1/FT/OUT pin, frequency test, interrupts and the OUT bit

(M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.14.1 Active mode operation on V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

CC

3.14.2 Backup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.15 FT/RST pin, frequency test and reset output pin (M41T82 only) . . . . . . . 46

3.16 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.17 OTP bit operation (M41T83 in SOX18 package only) . . . . . . . . . . . . . . . 47

4

5

6

7

8

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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List of tables

M41T82-M41T83

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

M41T82 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Key to Table 2: M41T82 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 24

M41T83 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Key to Table 4: M41T83 clock/control register map (32 bytes). . . . . . . . . . . . . . . . . . . . . . 26

Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Watchdog register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timer interrupt operation in free-running mode (with TI/TP = 1). . . . . . . . . . . . . . . . . . . . . 38

Timer source clock frequency selection (244.1 µs to 4.25 hrs). . . . . . . . . . . . . . . . . . . . . . 39

Square wave output frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Priority for IRQ1/FT/OUT pin when operating on V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Priority for IRQ1/FT/OUT pin when operating in backup mode . . . . . . . . . . . . . . . . . . . . . 45

Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm pack. mech. data . . . . . . . . . . . 55

SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, package mech. data 57

SO8 – 8-lead plastic small outline (150 mils body width), package mech. data . . . . . . . . . 58

Carrier tape dimensions for QFN16, SOX18, and SO8 packages . . . . . . . . . . . . . . . . . . . 59

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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M41T82-M41T83

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

M41T83 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SO8 (M) connections (M41T82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

QFN16 (QA) connections (M41T83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SOX18 (MY) connections (M41T83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

M41T82 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

M41T82 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

M41T83 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

M41T83 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 10. Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11. Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12. Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14. Alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 15. Write mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 16. Clock data coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18. Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19. Clock accuracy vs. on-chip load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 20. Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 21. Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 22. Timer output waveform in free-running mode (with TI/TP = 1) . . . . . . . . . . . . . . . . . . . . . . 38

Figure 23. Battery check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 24. IRQ1/FT/OUT output pin circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 25. Measurement AC I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 26.

I

vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

CC2

Figure 27. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 28. Bus timing requirement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline . . . . . . . . . . . 55

Figure 30. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint . . . . . . 56

Figure 31. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 32. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline . . . . . . . . . . . 57

Figure 33. SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 34. Carrier tape for QFN16, SOX18, and SO8 packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Description

M41T82-M41T83

1

Description

2

The M41T8x are low-power serial I C real-time clocks (RTCs) with a built-in 32.768 kHz

oscillator (external crystal-controlled for the QFN16 and SO8 packages, embedded crystal

for the SOX18 package). Eight bytes of the register map (see Table 2 on page 23) are used

for the clock/calendar function and are configured in binary-coded decimal (BCD) format. An

additional 17 bytes of the register map provide status/control of the two alarms, watchdog,

8-bit counter, and square wave functions. An additional seven bytes are made available as

user SRAM.

2

Addresses and data are transferred serially via a two-line, bidirectional I C interface. The

built-in address register is incremented automatically after each WRITE or READ data byte.

The M41T8x has a built-in power sense circuit which detects power failures and

automatically switches to the battery supply when a power failure occurs. The energy

needed to sustain the clock operations can be supplied by a small lithium button battery

when a power failure occurs.

Functions available to the user include a non-volatile, time-of-day clock/calendar, two alarm

interrupts, watchdog timer, programmable 8-bit counter, and square wave outputs. The eight

clock address locations contain the century, year, month, date, day, hour, minute, second,

and tenths/hundredths of a second in 24-hour BCD format. Corrections for 28, 29 (leap

year), 30, and 31 day months are made automatically. The M41T83 is supplied in either a

QFN16 or an SOX18, 300 mil SOIC which includes an embedded 32 KHz crystal. The

SOX18 package requires only a user-supplied battery to provide non-volatile operation. The

M41T82 is available only in an SO8 package.

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M41T82-M41T83

Figure 1.

Description

M41T82 logic diagram

V

CC

BAT

XI

XO

(1)

FT/RST

SDA

SCL

V

SS

AI11196

1. Open drain

Figure 2.

M41T83 logic diagram

V

BAT CC

(2)

(1)

XI

SQW

(3)

(1)

IRQ1/OUT/FT

XO

(3)

RST

SDA

SCL

(3)

IRQ2

V

SS

AI11195

1. For QFN16 package only

2. Defaults to 32 KHz on power-up

3. Open drain

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Description

M41T82-M41T83

Table 1.

Signal names

Symbol

Description

XI⁽¹⁾

XO⁽¹⁾

32 KHz oscillator input

32 KHz oscillator output

IRQ1/OUT/FT⁽²⁾

SQW⁽³⁾

RST

Interrupt 1/output driver/frequency test output (open drain)

32 KHz programmable square wave output

Power-on reset output (open drain)

Frequency test output/power-on reset (open drain - M41T82 only)

Interrupt for alarm 2 (open drain)

Serial data address input/output

Serial clock input

FT/RST

IRQ2⁽²⁾

SDA

SCL

V_BAT

Battery supply voltage (tie V_BATto V_SSif no battery is connected.)

Do not use

DU⁽⁴⁾

V_CC

Supply voltage

V_SS

Ground

1. For SO8 and QFN16 packages only.

2. For SOX18 and QFN16 packages only.

3. Defaults to 32 KHz on power-up.

4. DU pin must be tied to V_CC

.

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Figure 3.

Description

SO8 (M) connections (M41T82)

XI

XO

V_BAT

V_SS

1

2

3

4

8

7

6

5

V_CC

FT/RST⁽¹⁾

SCL

M41T82

SDA

AI11199

1. Open drain output

Figure 4.

QFN16 (QA) connections (M41T83)

16

14

15

13

(1)

IRQ2

RST

1

2

3

4

12

11

(1)

NC

IRQ1/FT/OUT

M41T83

NC

(2)

10 SCL

SDA

9

SQW

6

7

5

8

AI11197

1. Open drain output.

2. Defaults to 32 KHz on power-up.

Figure 5.

SOX18 (MY) connections (M41T83)

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

NC

NF⁽¹⁾

NC

NF⁽¹⁾

V

CC

RST⁽²⁾

IRQ2⁽²⁾

NC

M41T83

DU⁽³⁾

SQW⁽⁴⁾

IRQ1/FT/OUT⁽²⁾

V

BAT

SS

SCL

SDA

AI11198

1. NF pins must be tied to V_SS. Pins 2 and 3, and 16 and 17 are internally shorted together.

2. Open drain output.

3. Do not use (must be tied to V_CC).

4. Defaults to 32 KHz on power-up.

Doc ID 12578 Rev 15

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Description

M41T82-M41T83

Figure 6.

M41T82 block diagram

REAL TIME CLOCK

CALENDAR

OSCILLATOR FAIL

XI

CIRCUIT

32KHz

OSCILLATOR

XO

CRYSTAL

ALARM1

ALARM2

WATCHDOG

SDA

SCL

2

I C

FT

INTERFACE

FREQUENCY TEST

OUTPUT DRIVER

WRITE

PROTECT

8-BIT COUNTER

V

< V

CC

RST

USER SRAM (7 Bytes)

INTERNAL

POWER

V

CC

V

BAT

COMPARE

t

(1)

rec

V

/V

RST SO

(2)

RST

TIMER

AI11812

1. V_RST= V_SO= 2.93 V (S), 2.63 V (R), and 2.32 V (Z).

2. Open drain output.

Figure 7.

M41T82 hardware hookup

V

CC

MCU

M41T82

V

CC

XI

(1)

Reset Input

FT/RST

XO

Serial Clock Line

Serial Data Line

SCL

SDA

V

BAT

SS

AI11813

1. Open drain output.

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Doc ID 12578 Rev 15

M41T82-M41T83

Figure 8.

Description

M41T83 block diagram

REAL TIME CLOCK

CALENDAR

OSCILLATOR FAIL

OFIE

XI

CIRCUIT

32KHz

OSCILLATOR

XO

A1IE

A2IE

CRYSTAL

ALARM1

ALARM2

(1)

IRQ2

(1)

WATCHDOG

IRQ1/FT/OUT

SDA

SCL

2

I C

FT

INTERFACE

FREQUENCY TEST

OUT

TIE

OUTPUT DRIVER

8-BIT COUNTER

SQUARE WAVE

WRITE

PROTECT

V

< V

CC

RST

SQWE

SQW

8 BITS OF OTP

USER SRAM (7 Bytes)

INTERNAL

POWER

V

CC

V

BAT

COMPARE

t

(2)

rec

V

/V

RST SO

(1)

RST

TIMER

AI11800

1. Open drain output.

2. V_RST= V_SO= 2.93 V (S), 2.63 V (R), and 2.32 V (Z).

Figure 9.

M41T83 hardware hookup

V

CC

MCU

M41T83

V

CC

INT

(1)

IRQ1/FT/OUT

XI

(1)

Reset Input

Port

RST

(1)

XO

V

IRQ2

Serial Clock Line

Serial Data Line

32KHz CLKIN

SCL

BAT

SDA

V

SS

SQW

AI11801

1. Open drain output.

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Operation

M41T82-M41T83

2

Operation

The M41T8x clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 32 bytes

contained in the device can then be accessed sequentially in the following order:

st

●

1 byte: tenths/hundredths of a second register

nd

2

3

byte: seconds register

byte: minutes register

rd

th

4 byte: century/hours register

th

5 byte: day register

th

6 byte: date register

th

7 byte: month register

th

8 byte: year register

th

9 byte: digital calibration register

th

10 byte: watchdog register

th

11 - 15 bytes: alarm 1 registers

th

16 byte: flags register

th

17 byte: timer value register

th

18 byte: timer control register

th

19 byte: analog calibration register

th

20 byte: square wave register

st

th

21 - 25 bytes: alarm 2 registers

th

nd

26 - 32 bytes: user RAM

The M41T8x clock continually monitors V for an out-of-tolerance condition. Should V

CC

fall below V , the device terminates an access in progress and resets the device address

RST

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from an out-of-tolerance system. The power input will also

be switched from the V pin to the battery when V falls below the battery back-up

CC

switchover voltage (V = V

). At this time the clock registers will be maintained by the

SO

RST

attached battery supply. As system power returns and V rises above V , the battery is

CC

SO

disconnected, and the power supply is switched to external V

.

CC

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Doc ID 12578 Rev 15

M41T82-M41T83

Operation

2.1

2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-

directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be

connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

●

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is high.

Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1

2.1.2

Bus not busy

Both data and clock lines remain high.

Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

2.1.3

2.1.4

Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

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Operation

M41T82-M41T83

2.1.5

Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low

level put on the bus by the receiver whereas the master generates an extra acknowledge

related clock pulse. A slave receiver which is addressed is obliged to generate an

acknowledge after the reception of each byte that has been clocked out of the slave

transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable low during the high period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case the transmitter must leave the data line high to enable the master to generate the

STOP condition.

Figure 10. Serial bus data transfer sequence

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CHANGE OF

STOP

CONDITION

DATA ALLOWED

CONDITION

AI00587

Figure 11. Acknowledgement sequence

CLOCK PULSE FOR

ACKNOWLEDGEMENT

START

SCL FROM

1

2

8

9

MASTER

DATA OUTPUT

MSB

LSB

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

AI00601

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Doc ID 12578 Rev 15

M41T82-M41T83

Operation

2.2

Read mode

In this mode the master reads the M41T8x slave after setting the slave address (see

Figure 13 on page 16). Following the WRITE mode control bit (R/W = 0) and the

acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the

START condition and slave address are repeated followed by the READ mode control bit

(R/W = 1). At this point the master transmitter becomes the master receiver. The data byte

which was addressed will be transmitted and the master receiver will send an acknowledge

bit to the slave transmitter. The address pointer is only incremented on reception of an

acknowledge clock. The M41T8x slave transmitter will now place the data byte at address

An+1 on the bus, the master receiver reads and acknowledges the new byte and the

address pointer is incremented to An+2.

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter. Most of the registers and memory locations are

accessed directly, but the RTC counters are accessed via a set of buffer/transfer registers at

addresses 00h to 07h. The counters are not directly read nor written. Instead, at the start of

a read or write cycle, the counters are copied into the eight buffer/transfer registers so that

the user can read them out sequentially, receiving a coherent set of data, copied from the

same instant in time.

An alternate READ mode may also be implemented whereby the master reads the M41T8x

slave without first writing to the (volatile) address pointer. The first address that is read is the

last one stored in the pointer (see Figure 14 on page 16).

Figure 12. Slave address location

R/W

START

SLAVE ADDRESS

A

1

0

1

0

AI00602

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Operation

M41T82-M41T83

Figure 13. Read mode sequence

BUS ACTIVITY:

MASTER

WORD

ADDRESS (An)

SDA LINE

S

DATA n

DATA n+1

BUS ACTIVITY:

SLAVE

ADDRESS

SLAVE

ADDRESS

DATA n+X

P

AI00899

Figure 14. Alternative read mode sequence

BUS ACTIVITY:

MASTER

SDA LINE

S

DATA n

DATA n+1

DATA n+X

P

BUS ACTIVITY:

SLAVE

ADDRESS

AI00895

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Doc ID 12578 Rev 15

M41T82-M41T83

Operation

2.3

Write mode

In this mode the master transmitter transmits to the M41T8x slave receiver. Bus protocol is

shown in Figure 15. Following the START condition and slave address, a logic 0 (R/W = 0) is

placed on the bus and indicates to the addressed device that word address “An” will follow

and is to be written to the on-chip address pointer. The data word to be written to the

memory is strobed in next and the internal address pointer is incremented to the next

address location on the reception of an acknowledge clock. The M41T8x slave receiver will

send an acknowledge clock to the master transmitter after it has received the slave address

see Figure 12 on page 15 and again after it has received the word address and each data

byte.

Figure 15. Write mode sequence

BUS ACTIVITY:

MASTER

WORD

ADDRESS (An)

SDA LINE

S

DATA n

DATA n+1

DATA n+X

P

BUS ACTIVITY:

SLAVE

ADDRESS

AI00591

As in the case of reading, some registers and memory locations are written directly, but the

RTC counters are written via a set of eight buffer/transfer registers at addresses 00h to 07h.

2

The user will write the date and time information sequentially, and then, at the end of the I C

write cycle or when the address pointer increments beyond 07h, the buffer/transfer registers

will be copied into the RTC counters. All the time parameters - fractions, seconds, minutes,

hours, day, date, month, year, and century bits - are copied simultaneously.

Whatever value is in the buffer/transfer registers will be copied to the counters, so if the user

only changes one of the eight bytes, the remaining seven bytes will receive the unchanged

contents of the buffer/transfer registers, which will contain whatever was in the counters at

the start of the write access.

For example, if the user starts a write cycle on Monday, November 16, 2009, at 17:52:27.03,

and writes a 22 to the minutes registers, the value Monday, November 16, 2009,

17:52:22.03 will be written back into the counters. At the start of the write cycle, the eight

bytes of counters were copied into the buffer/transfer registers. Then, the seconds register

was overwritten. Finally, the eight bytes were copied back into the counters with the result

that the seconds value was changed.

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Operation

M41T82-M41T83

2.4

Data retention and battery switchover (V_SO= V_RST

)

Once V falls below the switchover voltage (V = V ), the device automatically

RST

CC

SO

switches over to the battery and powers down into an ultra low current mode of operation to

preserve battery life. If V is less than, or greater than V , the device power is switched

BAT

RST

from V to V

when V drops below V

(see Figure 27 on page 52). At this time the

CC

BAT

CC

RST

clock registers and user RAM will be maintained by the attached battery supply.

When it is powered back up, the device switches back from battery to V at V

+

SO

CC

hysteresis. When V rises above V , it will recognize the inputs. For more information

CC

RST

on battery storage life refer to Application Note AN1012.

2.5

Power-on reset (t_rec)

The M41T8x continuously monitors V . When V falls to the power fail detect trip point,

CC

the RST output pulls low (open drain) and remains low after power-up for t (210 ms

rec

typical) after V rises above V

(max).

CC

RST

Note:

The t period does not affect the RTC operation. Write protect only occurs when V is

rec CC

below V . When V rises above V , the RTC will be selectable immediately. Only the

RST

CC

RST

RST output is affected by the t period.

rec

The RST pin is an open drain output and an appropriate pull-up resistor to V should be

CC

chosen to control the rise time.

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Doc ID 12578 Rev 15

M41T82-M41T83

Clock operation

3

Clock operation

The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of

32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz

crystal that is used as the time-base for the RTC.

The 8-byte clock register (see Table 2 on page 23 and Table 4 on page 25) is used to both

set the clock and to read the date and time from the clock, in binary coded decimal format.

Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first

four registers.

Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the

oscillator to stop. When reset to a 0 the oscillator restarts within one second (typical).

Note:

Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST

bit to 0. This provides an additional “kick-start” to the oscillator circuit.

Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0

(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of

week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The

ninth clock register is the digital calibration register, while the analog calibration register is

found at address 12h (these are both described in Section 3.4: Clock calibration). The RTC

includes an oscillator fail detect circuit which sets the OF bit in the flags register (bit 2,

register 0fh). For the M41T83, bit D7 of register 09h (watchdog register) contains the

oscillator fail interrupt enable bit (OFIE) which can be used to enable an interrupt when the

OF bit is set (see Section 3.12: Oscillator fail detection on page 42) will also generate an

interrupt output.

Note:

A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),

including the ST bit and CB0-CB1 bits will result in an update of the RTC counters and a

reset of the divider chain. This could result in an inadvertent change of the current time. For

example, the ST bit is in the seconds register (address 01h) and the century bits (CB0-CB1)

are in the hours register (address 03h), so the user should take care to not alter these other

parameters when changing the ST bit or the century bits.

The eight clock registers may be read one byte at a time or in a sequential block. At the start

of a read cycle, a copy of the time/date counters is placed in the buffer/transfer registers and

can then be transferred out sequentially without concern that the time/date increments

during the transfer and thus yields a corrupt value. For example, if the user were to read the

seconds register, then start another bus cycle to read the minutes register, the minutes

counter could have incremented during the time between the two read cycles. The seconds

and minutes values would not be from the same instant in time; they would not be coherent.

By using the sequential read feature, the values shifted out are from the same instant in time

and are thus coherent.

Similarly, when writing to the RTC registers, during one write cycle, the user can

sequentially transfer all eight bytes of time/date into the buffer/transfer registers whereupon

they will be loaded simultaneously into the RTC counters thus ensuring a coherent update

of the time/date.

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Clock operation

M41T82-M41T83

3.1

Clock data coherency

In order to synchronize the data during reads and writes of the real-time clock device, a set

2

of buffer transfer registers resides between the I C serial interface on the user side, and the

clock/calendar counters in the part. While the read/write data is transferred in and out of the

device one bit at a time to the user, the transfers between the buffer registers and counters

occur such that all the bits are copied simultaneously. This keeps the data coherent and

ensures that none of the counters are incremented while the data is being transferred.

Figure 16. Clock data coherency

32KHz

OSC

RTC

AT START OF READ OR WRITE,

DATA IN COUNTERS IS COPIED TO

BUFFER/TRANSFER REGISTERS.

COUNTERS

DIVIDE BY 32768

1 Hz

COUNTER

READ / WRITE

BUFFER-TRANSFER

REGISTERS

COUNTER

SECONDS

MINUTES

HOURS

DAY-OF-WEEK

DATE

2

I C

COUNTER

2

I C

COUNTER

INTERFACE

MONTHS

YEARS

CENTURIES

COUNTER

AFTER A WRITE, DATA IS TRANSFERRED

FROM BUFFERS TO COUNTERS

NON-CLOCK

REGISTERS

SQUAREWAVE

CALIBRATION

HALT BIT SET AT POWER-DOWN

ALARM / HALT

WATCHDOG

3.1.1

Example of incoherency

Without having the intervening buffer/transfer registers, if the user began directly reading the

counters at 23:59:59, a read of the seconds register would return 59 seconds. After the

address pointer incremented, the next read would return 59 minutes. Then the next read

should return 23 hours, but if the clock happened to increment between the reads, the user

would see 00 hours. When the time was re-assembled, it would appear as 00:59:59, and

thus be incorrect by one hour.

By using the buffer/transfer registers to hold a copy of the time, the user is able to read the

entire set of registers without any values changing during the read.

Similarly, when the application needs to change the time in the counters, it is necessary that

all the counters be loaded simultaneously. Thus, the user writes sequentially to the various

buffer/transfer registers, then they are copied to the counters in a single transfer thereby

coherently loading the counters.

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M41T82-M41T83

Clock operation

3.1.2

Accessing the device

The M41T82/83 is comprised of 32 addresses which provide access to registers for time

and date, digital and analog calibration, two alarms, watchdog, flags, timer, squarewave

(M41T83 only) and NVRAM. The clock and alarm parameters are in binary coded decimal

(BCD) format. The calibration, timer, watchdog, and squarewave parameters are in a binary

format.

In the case of the M41T82 and M41T83, at the start of each read or write serial transfer, the

counters are automatically copied to the buffer registers. In the event of a write to any

register in the range 0-7, at the end of the serial transfer, the buffer registers are copied back

into the counters thus revising the date/time. Any of the eight clock registers (addresses 0-

7) not updated during the transfer will have its old value written back into the counters. For

example, if only the seconds value is revised, the other seven counters will end up with the

same values they had at the start of the serial transfer.

However, writes which do not affect the clock registers - that is, a write only to the non-clock

registers (addresses 0x08 to 0x1F) - will not cause the buffer registers to be copied back to

the counters. The counters are only updated if a register in the range 0-7 was written.

Whenever the RTC registers (addresses 0-7) are written, the divider chain from the

oscillator is reset.

3.2

Halt bit (HT) operation

When the part is powered down into battery backup mode, a control bit, called the Halt or

HT bit, is set automatically. This inhibits any subsequent transfers from the counters to the

buffer registers thereby freezing in the buffer registers the time/date of the last access of the

part.

Repeated reads of the clock registers will return the same value. After the HT bit is cleared,

by writing bit 6 of address 0x0C to 0, the next read of the RTC will return the present time.

Note:

Writes to the RTC registers (addresses 0-7) with the HT bit set can cause time corruption.

Since the buffer registers contain the time of the last access prior to the HT bit being set, any

write in the address range 0-7 will result in the time of the last access being copied back into

the counters.

Example: The last access was November 17, 2009, at 16:15:07.77. The system later

powered down thus setting the HT bit and freezing that value in the buffers. Later, on

December 18, 2009, at 03:22:43.35, the system is powered up and the user writes the

seconds to 46 without first clearing the HT bit. At the end of the serial transfer, the old

time/date, with the seconds modified to 46, will be written back into the clock registers

thereby corrupting them. The new, wrong time will be November 17, 2009, at 16:15:46.77.

This makes it appear the RTC lost time during the power outage.

Thus, at power-up, the user should always clear the HT bit (write bit 6 to 0 at address 0x0C)

before writing to any address in the range 0-7.

A typical power-up flow is to read the time of last access, then clear the HT bit, then read the

current time.

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Clock operation

M41T82-M41T83

3.2.1

Power-down time-stamp

Some applications may need to determine the amount of time spent in backup mode. That

can be calculated if the time of power-down and the time of power-up are known. The latter

is straightforward to obtain. But the time of power-down is only available if an access

occurred just prior to power-down. That is, if there was an access of the device just prior to

power-down, the time of the access would have been frozen in the buffer transfer registers

and thus the approximate time of power-down could be obtained.

If an application requires the time of power-down, the best way to implement it is to set up

the software to do frequent reads of the clock, such as once every 1 or 5 seconds. That

way, at power-up, the buffer-transfer registers will contain a time value within 1 (or 5)

seconds of the actual time of power-down. For more information, please refer to AN1572,

“Power-down time-stamp function in serial real-time clocks (RTCs)”.

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M41T82-M41T83

Clock operation

(1)

Table 2.

Addr

M41T82 clock/control register map (32 bytes)

Function/range BCD

format

D7

D6

0.1 seconds

10 seconds

D5

D4

D3

D2

D1

D0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h-1Fh

0.01 seconds

seconds

minutes

00-99

00-59

0-3/00-23

01-7

ST

0

10 minutes

minutes

CB1

0

CB0

10 hours

Hours (24 hour format)

Day of week

Date: day of month

Month

Century/hours

Day

0

10 date

Date

01-31

01-12

00-99

0

10M

Month

10 years

Year

0

FT

BMB4

0

DCS

BMB3

ABE

DC4

BMB2

DC3

DC2

DC1

RB1

DC0

RB0

Digital calibration

Watchdog

Al1 month

Al1 date

Al1 hour

Al1 min

BMB1 BMB0

Al1 10M

Alarm1 month

Alarm1 date

01-12

01-31

00-23

00-59

RPT14 RPT15

AI1 10 date

AI1 10 hour

RPT13

RPT12

RPT11

WDF

HT

Alarm1 hour

Alarm1 10 minutes

Alarm1 10 seconds

Alarm1 minutes

Alarm1 seconds

Al1 sec

AF1

AF2⁽²⁾

Timer countdown value

BL

TF

OF

0

Flags

Timer value

Timer control

TE

ACS

0

AC6

0

AC5

0

AC4

0

AC3

0

AC2

0

TD1

AC1

TD0

AC0 Analog calibration

AL2E

0

SQW

0⁽³⁾

Al2 10M

Alarm2 month

Alarm2 date

SRAM/Al2 month

SRAM/Al2 date

SRAM/Al2 hour

SRAM/Al2 min

SRAM/Al2 sec

SRAM

01-12

01-31

00-23

00-59

RPT24 RPT25

AI2 10 date

AI2 10 hour

RPT23

RPT22

RPT21

0⁽³⁾

Alarm2 10 minutes

Alarm2 10 seconds

Alarm2 minutes

Alarm2 seconds

User SRAM (7 bytes)

1. See Table 3: Key to Table 2: M41T82 clock/control register map (32 bytes)

2. AF2 will always read 0, if the AL2E bit is set to 0.

3. As indicated in Table 3, the 0 bits should be written to 0. But in the case of these four bits, when AL2E is 0, registers 14-18h

are SRAM locations and these bits become SRAM cells which are thus excluded from that restriction.

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Clock operation

M41T82-M41T83

Table 3.

Key to Table 2: M41T82 clock/control register map (32 bytes)

Code Explanation

Must be set to zero

0

ABE

Alarm in battery backup enable bit

Analog calibration bits

Analog calibration sign bit

Alarm flag bits

AC0-AC6

ACS

AF1, AF2

AL2E

Alarm 2 enable bit

Battery low bit

BL

BMB0-BMB4

CB0, CB1

DC0-DC4

DCS

Watchdog multiplier bits

Century bits

Digital calibration bits

Digital calibration sign bit

Frequency test bit

Halt update bit

FT

HT

OF

Oscillator fail bit

RB0-RB2

RPT11-RPT15

RPT21-RPT25

ST

Watchdog resolution bits

Alarm 1 repeat mode bits

Alarm 2 repeat mode bits

Stop bit

TD0, TD1

TE

Timer frequency bits

Timer enable bit

TF

Timer flag

WDF

Watchdog flag

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M41T82-M41T83

Clock operation

(1)

Table 4.

Addr

M41T83 clock/control register map (32 bytes)

Function/range BCD

format

D7

D6

0.1 seconds

10 seconds

D5

D4

D3

D2

D1

D0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0.01 seconds

seconds

Minutes

Century/hours

Day

00-99

00-59

0-3/00-23

01-7

ST

0

10 minutes

Minutes

CB1

0

CB0

10 hours

Hours (24 hour format)

Day of week

Date: day of month

Month

0

10 date

Date

01-31

01-12

00-99

0

10M

Month

10 years

Year

OUT

FT

DCS

DC4

DC3

DC2

DC1

RB1

DC0 Digital calibration

OFIE

BMB4

BMB3

BMB2

BMB1

BMB0

RB0

Watchdog

Al1 month

Al1

10M

0Ah

A1IE

SQWE

ABE

Alarm 1month

01-12

0Bh RPT14 RPT15

AI1 10 date

AI1 10 hour

Alarm1 date

Alarm1 hour

Al1 date

Al1 hour

Al1 min

01-31

00-23

00-59

0Ch RPT13

0Dh RPT12

0Eh RPT11

HT

Alarm1 10 minutes

Alarm1 10 seconds

Alarm1 minutes

Alarm1 seconds

Al1 sec

0Fh

10h

11h

WDF

AF1

AF2⁽²⁾

BL

TF

OF

0

Flags

Timer countdown value

Timer value

Timer control

TE

TI/TP

AC6

RS2

0⁽³⁾

TIE

AC5

RS1

0⁽³⁾

0

AC3

0

AC2

0

TD1

AC1

TD0

AC0

OTP

Analog

calibration

12h

13h

14h

ACS

RS3

A2IE

AC4

RS0

AL2E

SQW

Al2

10M

Alarm2 month

SRAM/Al2 month

01-12

15h RPT24 RPT25

AI2 10 date

AI2 10 hour

Alarm2 date

Alarm2 hour

SRAM/Al2 date

SRAM/Al2 hour

SRAM/Al2 min

SRAM/Al2 sec

01-31

00-23

00-59

16h RPT23

17h RPT22

18h RPT21

0⁽³⁾

Alarm2 10 minutes

Alarm2 10 seconds

Alarm2 minutes

Alarm2 seconds

19h-

1Fh

User SRAM (7 bytes)

SRAM

1. See Table 5: Key to Table 4: M41T83 clock/control register map (32 bytes).

2. AF2 will always read 0, if the AL2E bit is set to 0.

3. As indicated in Table 5, the 0 bits should be written to 0. But in the case of these three bits, when AL2E is 0, registers

14-18h are SRAM locations and these bits become SRAM cells which are thus excluded from that restriction.

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Clock operation

M41T82-M41T83

Table 5.

Key to Table 4: M41T83 clock/control register map (32 bytes)

Code Explanation

Must be set to zero

0

ABE

Alarm in battery back-up enable bit

Alarm interrupt enable bits

Analog calibration bits

Analog calibration sign bit

Alarm flag

A1IE, A2IE

AC0-AC6

ACS

AF1, AF2

AL2E

Alarm 2 enable bit

Battery low bit

BL

BMB0-BMB4

CB0, CB1

DC0-DC4

DCS

Watchdog multiplier bits

Century bits

Digital calibration bits

Digital calibration Sign bit

Frequency test bit

Halt update bit

FT

HT

OF

Oscillator fail bit

OUT

Output level

OFIE

Oscillator fail interrupt enable

OTP control bit

OTP

RB0-RB2

RPT11-RPT15

RPT21-RPT25

RS0-RS3

SQWE

SRAM/ALM2

ST

Watchdog resolution bits

Alarm 1 repeat mode bits

Alarm 2 repeat mode bits

SQW frequency

Square wave enable

SRAM/alarm 2 bit

Stop bit

TD0, TD1

TE

Timer frequency bits

Timer enable bit

TF

Timer flag

TI/TP

Timer interrupt or pulse

Timer interrupt enable

Watchdog flag

TIE

WDF

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M41T82-M41T83

Clock operation

3.3

Real-time clock accuracy

The M41T8x is driven by a quartz controlled oscillator with a nominal frequency of

32,768 Hz. The accuracy of the real-time clock is dependent upon the accuracy of the

crystal, and the match between the capacitive load of the oscillator circuit and the capacitive

load for which the crystal was trimmed. Temperature also affects the crystal frequency,

causing additional error (see Figure 18 on page 32).

The M41T8x provides the option of clock correction through either manufacturing calibration

or in-application calibration. The total possible compensation is typically –93 ppm to

+156 ppm. The two compensation circuits that are available are:

1. An analog calibration register (12h) can be used to adjust internal (on-chip) load

capacitors for oscillator capacitance trimming. The individual load capacitors C and

XI

C

(see Figure 17), are selectable from a range of –18 pF to +9.75 pF in steps of

XO

0.25 pF. This translates to a calculated compensation of approximately 30 ppm (see

Section 3.4.2: Analog calibration (programmable load capacitance) on page 31).

2. A digital calibration register (08h) can also be used to adjust the clock counter by

adding or subtracting a pulse at the 512 Hz divider stage. This approach provides

periodic compensation of approximately –63 ppm to +126 ppm (see Section 3.4.1:

Digital calibration (periodic counter correction) on page 28).

Figure 17. Internal load capacitance adjustment

XI

C

XI

Crystal Oscillator

XO

C

XO

AI11804

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Clock operation

M41T82-M41T83

3.4

Clock calibration

The M41T8x oscillator is designed for use with a 12.5 pF crystal load capacitance. When

the calibration circuit is properly employed, accuracy improves to better than 1 ppm at

25 °C.

The M41T8x design provides the following two methods for clock error correction.

3.4.1

Digital calibration (periodic counter correction)

This method employs the use of periodic counter correction by adjusting the ratio of the

100 Hz divider stage to the 512 Hz divider stage. Under normal operation, the 100 Hz

divider stage outputs precisely 100 pulses for every 512 pulses of the 512 Hz input stage to

provide the input frequency to the fraction of seconds clock register. By adjusting the

number of 512 Hz input pulses used to generate 100 output pulses, the clock can be sped

up or slowed down, as shown in Figure 20 on page 34.

When a non-zero value is loaded into the five calibration bits (DC4 – DC0) found in the

digital calibration register (08h) and the sign bit is 1, (indicating positive calibration), the

100 Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512.

Since the 100 pulses are now being output in a shorter window, this has the effect of

speeding up the clock by 1/512 seconds for each second the circuit is active. Similarly, when

the sign bit is 0, indicating negative calibration, the block outputs 100 pulses for every 513

input pulses. Since the 100 pulses are then being output in a longer window, this has the

effect of slowing down the clock by 1/512 seconds for each second the circuit is active.

The amount of calibration is controlled by using the value in the calibration register (N) to

generate the adjustment in one second increments. This is done for the first N seconds once

every eight minutes for positive calibration, and for N seconds once every sixteen minutes

for negative calibration (see Table 6 on page 30).

For example, if the calibration register is set to 100010, then the adjustment will occur for

two seconds in every minute. Similarly, if the calibration register is set to 000011, then the

adjustment will occur for 3 seconds in every alternating minute.

The digital calibration bits (DC4 – DC0) occupy the five lower order bits in the digital

calibration register (08h). These bits can be set to represent any value between 0 and 31 in

binary form. The sixth bit (DCS) is a sign bit; 1 indicates positive calibration, 0 indicates

negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative)

cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or

–2.034 ppm. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31

increments in the calibration byte would represent +10.7 or –5.35 seconds per month, which

corresponds to a total range of +5.5 or –2.75 minutes per month.

One method of determining the amount of digital calibration required is to use the frequency

test output (FT) of the device (see Section 3.14: IRQ1/FT/OUT pin, frequency test,

interrupts and the OUT bit (M41T83 only) on page 43 for more information on enabling the

FT output).

When FT is enabled, a 512 Hz signal is output in the IRQ1/FT/OUT pin on the M41T83, and

on the FT/RST pin on the M41T82. This signal can be measured using a highly accurate

timing device such as a frequency counter. The measured value is then compared to 512 Hz

and the oscillator error in ppm is then determined.

The user should keep in mind that changes in the digital calibration value will not affect the

signal measured on the FT pin. While the analog calibration circuit does affect the oscillator,

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M41T82-M41T83

Clock operation

the digital calibration circuitry uses periodic counter correction which occurs downstream of

the 512 Hz divider chain and hence has no effect on the FT pin.

Note:

1

2

The modified pulses are not observable on the frequency test (FT) output, nor will the effect

of the calibration be measurable real-time, due to the periodic nature of the error

compensation.

Positive digital calibration is performed on an eight minute cycle, therefore the value in the

calibration register should not be modified more frequently than once every eight minutes for

positive values of calibration. Negative digital calibration is performed on a sixteen minute

cycle, therefore negative values in the calibration register should not be modified more

frequently than once every sixteen minutes.

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Clock operation

M41T82-M41T83

Table 6.

Digital calibration values

Calibration value rounded to the nearest ppm

Calibration value (binary)

Negative calibration (DCS = 0)

to slow a fast clock

Positive calibration (DCS = 1)

to speed up a slow clock

DC4 – DC0

0 (00000)

1 (00001)

2 (00010)

3 (00011)

4 (00100)

5 (00101)

6 (00110)

7 (00111)

8 (01000)

9 (01001)

10 (01010)

11 (01011)

12 (01100)

13 (01101)

14 (01110)

15 (01111)

16 (10000)

17 (10001)

18 (10010)

19 (10011)

20 (10100)

21 (10101)

22 (10110)

23 (10111)

24 (11000)

25 (11001)

26 (11010)

27 (11011)

28 (11100)

29 (11101)

30 (11110)

31 (11111)

0

4

–2

–4

8

–6

12

16

20

24

28

33

37

41

45

49

53

57

61

65

69

73

77

81

85

90

94

98

102

106

110

114

118

122

126

–8

–10

–12

–14

–16

–18

–20

–22

–24

–26

–28

–31

–33

–35

–37

–39

–41

–43

–45

–47

–49

–51

–53

–55

–57

–59

–61

–63

N

N/491520 (per minute)

N/245760 (per minute)

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M41T82-M41T83

Clock operation

3.4.2

Analog calibration (programmable load capacitance)

A second method of calibration employs the use of programmable internal load capacitors to

adjust (or trim) the oscillator frequency. As discussed in Section 3.4.1, the 512 Hz frequency

test output can be used to determine the amount of frequency error in the oscillator.

Changes in the analog calibration value will affect the frequency test output, thus the user

can immediately see the effects of these changes (see Section 3.14 on page 43 for more

information on enabling the FT output).

By design, the oscillator is intended to be 0 ppm crystal accuracy at room temperature

(25 °C, see Figure 18 on page 32). For a 12.5 pF crystal, the default loading on each side of

the crystal will be 25 pF. For incrementing or decrementing the calibration value,

capacitance will be added or removed in increments of 0.25 pF to each side of the crystal.

Internally, C

of the oscillator is changed via two digitally controlled capacitors, C and

XI

LOAD

C

, connected from the XI and XO pins to ground (see Figure 17 on page 27). The

XO

effective on-chip series load capacitance, C

nominal value of 12.5 pF (AC0 – AC6 = 0).

, ranges from 3.5 pF to 17.4 pF, with a

LOAD

The effective series load capacitance (C

) is the combination of C and C

:

XO

LOAD

XI

C

= 1 ⁄ (1 ⁄ C + 1 ⁄ C

)

XO

LOAD

XI

Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load

capacitance value for frequency compensation of the RTC. Each bit has a different weight

for capacitance adjustment. An analog calibration sign (ACS) bit determines if capacitance

is added (ACS bit = 0, negative calibration) or removed (ACS bit = 1, positive calibration).

The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency

by removing capacitance) due to the typical characteristic of quartz crystals to slow down

due to changes in temperature, but negative calibration is also available.

Since the analog calibration register adjustment is essentially pulling the frequency of the

oscillator, the resulting frequency changes will not be linear with incremental capacitance

changes. The equations which govern this mechanism indicate that smaller capacitor values

of analog calibration adjustment will provide larger increments. Thus, the larger values of

analog calibration adjustment will produce smaller incremental frequency changes. These

values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the highest

capacitance settings. The range provided by the analog calibration register adjustment with

a typical surface mount crystal is approximately 30 ppm around the AC6-AC0 = 0 default

setting because of this property (see Table 7 on page 32).

Pre-programmed calibration value

Users of the M41T83 in the embedded crystal package have the option of using the factory

programmed analog calibration value (refer to Section 3.17: OTP bit operation (M41T83 in

SOX18 package only) on page 47).

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Clock operation

M41T82-M41T83

Figure 18. Crystal accuracy across temperature

Frequency (ppm)

20

0

–20

–40

–60

2

ΔF

F

= K x (T – T_O)

–80

–100

–120

–140

–160

= –0.036 ppm/°C²0.006 ppm/°C²

T_O= 25°C 5°C

K

–40

–30

–20

–10

0

10

20

30

40

50

60

70

80

Temperature °C

AI07888

Table 7.

Analog calibration values

Analog

(1)

calibration D7

value

D6

D5

D4

D3

D2

D1

D0

C_XI, C_XO

C_LOAD

Addr

ACS

AC6

AC5

AC4

AC3

AC2

AC1

AC0

½(C_XI, C_XO

)

( ) (16 pF) (8 pF) (4 pF) (2 pF) (1 pF) (0.5 pF) (0.25 pF)

0 pF

3 pF

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

25 pF

28 pF

30 pF

18 pF

34.75 pF

7 pF

12.5 pF

14 pF

15 pF

9 pF

5 pF

12h

–7 pF

9.75 pF⁽²⁾

–18 pF⁽³⁾

17.4 pF

3.5 pF

1. C_LOAD= 1/(1/C_XI+ 1/C_XO).

2. Maximum negative calibration value.

3. Maximum positive calibration value.

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M41T82-M41T83

The on-chip capacitance can be calculated as follows:

Clock operation

where ACS is the sign.

For example:

●

C

(12h = x0000000) = 12.5 pF

LOAD

(12h =11001000) = 3.5 pF (sign is negative)

(12h = 00100111) = 17.4 pF

With the analog calibration adjusted to its lowest value, the oscillator will see a minimum of

3.5 pF load capacitance as shown on the bottom row of Table 7.

Note:

These are typical values, and the total load capacitance seen by the crystal will include

approximately 1-2 pF of package and board capacitance in addition to the analog calibration

register value.

Any invalid value of analog calibration will result in the default capacitance of 25 pF.

The combination of analog and digital trimming can give up to –93 to +156 ppm of the total

adjustment.

Figure 19 represents a typical curve of clock ppm adjustment versus the analog calibration

value. This curve may vary with different crystals, so it is good practice to evaluate the

crystal to be used with an M41T8x device before establishing the adjustment values for the

application in question.

Figure 19. Clock accuracy vs. on-chip load capacitance

100.0

XI

XO

80.0

60.0

40.0

Crystal

Oscillator

C_XI

C_XO

C_XIC_XO

*

C_LOAD

=

C

_XI+ C_XO

20.0

On-Chip

FASTER

DECREASING LOAD CAP.

INCREASING LOAD CAP.

0.0

SLOWER

-20.0

OFFSET TO

-18.0 -15.0

3.5 5.0

0xC8 0xBC

-10.0

7.5

-5.0

10

0.0

12.5

0x00

5.0

15

9.75

C , C (pF)

XI

XO

NET EQUIV. LOAD

CAP., C , (pF)

17.4

LOAD

Analog Calibration

Value, AC,

0xA8

0x94

0x14

0x27

ai13906

register 0x12

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Clock operation

M41T82-M41T83

Two methods are available for ascertaining how much calibration a given M41T8x may

require:

The first involves setting the clock, letting it run for a month and comparing it to a known

●

accurate reference and recording deviation over a fixed period of time. This allows the

designer to give the end user the ability to calibrate the clock as the environment

requires, even if the final product is packaged in a non-user serviceable enclosure. The

designer could provide a simple utility that accesses either or both of the calibration

bytes.

●

The second approach is better suited to a manufacturing environment, and uses the

512 Hz frequency test output. This is the IRQ1/FT/OUT pin on the M41T83, and the

FT/RST pin on the M41T82 (see Section 3.14 and Section 3.15 for more information on

enabling the FT output). The 512 Hz frequency test signal can be measured using a

highly accurate timing device such as a frequency counter. The measured value is then

compared to 512 Hz and the oscillator error in ppm is then determined.

Any deviation from 512 Hz indicates the degree and direction of oscillator frequency

shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a

+20 ppm oscillator frequency error, requiring either a –10 (xx001010) to be loaded into

the digital calibration byte, or +6 pF (00011000) into the analog calibration byte for

correction.

Note:

Setting or changing the digital calibration byte does not affect the frequency test, square

wave, or watchdog timer frequency, but changing the analog calibration byte DOES affect all

functions derived from the low current oscillator (see Figure 20).

Figure 20. Clock divider chain and calibration circuits

512Hz Output

Frequency Test

Remainder of

Divider Circuit

Square Wave

Watchdog Timer

8-bit Timer

÷64

÷2

C

XI

Low Current

Oscillator

32KHz

Digital Calibration Circuitry

(divide by 511/512/513)

Clock

Counters

C

XO

1Hz Signal

Analog Calibration

Circuitry

AI11806c

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M41T82-M41T83

Figure 21. Crystal isolation example

Clock operation

Crystal

Local Grounding

Plane (Layer 2)

XO

XI

V

SS

AI11814

1. Substrate pad should be tied to V_SS

.

3.5

Setting the alarm clock registers

Codes not listed in the table default to the once-per-second mode to quickly alert the user of

an incorrect alarm setting. When the clock information matches the alarm clock settings

based on the match criteria defined by RPTx5–RPTx1 (x = 1 for alarm 1 or 2 for alarm 2),

the alarm flag, AFx, is set. Reading the flags register clears the alarm flags. A subsequent

read of the flags register is necessary to see that the value of the alarm flag has been reset

to 0.

M41T83 interrupts on alarm

In the M41T83, for alarm 1, setting the alarm interrupt enable, A1IE, allows an interrupt

output to be asserted upon AF1 being set provided that other configuration bits are set

accordingly (see Section 3.14 for more information on the IRQ/FT/OUT output).

Likewise for alarm 2, with A2IE set, IRQ2 will be asserted upon AF2 going high. To disable

either of the alarms, write a 0 to the alarm date registers and to the RPTx5–RPTx1 bits.

Note:

If the address pointer is allowed to increment to the flag register address, or the last address

written is “Alarm Seconds,” the address pointer will increment to the flag address, and an

alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to

a different address.

Alarm IRQ outputs are de-asserted when the alarm flags are cleared by reading the flags

register (0Fh).

The IRQ1/FT/OUT pin can also be activated in the battery backup mode. This requires the

ABE bit (alarm in backup enable) to be set (see Section 3.14.2: Backup mode for additional

conditions which apply). Once an interrupt is asserted in backup mode, it will remain true

until V is restored and a subsequent read of the flags register occurs.

CC

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Clock operation

M41T82-M41T83

3.6

Optional second programmable alarm and user SRAM

When the alarm 2 enable (AL2E) bit (D1 of address 13h) is set to a logic 1, registers 14h

through 18h provide control for a second programmable alarm which operates in the same

manner as the alarm function described in Section 3.5. The AL2E bit defaults on initial

power-up to a logic 0 (alarm 2 disabled). In this mode, the five alarm 2 bytes (14h-18h)

function as additional user SRAM, for a total of 12 bytes of user SRAM.

With AL2E set to 1, the alarm is enabled, and will cause the AF2 bit to be set when the

alarm condition is met. On the M41T83, if the A2IE (alarm 2 interrupt enable) bit is set, an

interrupt will be asserted on IRQ2. The interrupt is de-asserted when the alarm flags are

cleared by reading the flags register (0Fh).

IRQ2 can be enabled in backup mode by setting ABE to 1 (in conjuction with setting A2IE).

Table 8.

RPT5

Alarm repeat modes

RPT4

RPT3

RPT2

RPT1

Alarm setting

1

0

1

0

1

0

1

0

1

0

Once per second

Once per minute

Once per hour

Once per day

Once per month

Once per year

3.7

Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the watchdog

register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits

RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,

and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For example: writing 00001110 in the

watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the

specified period, the M41T8x sets the WDF (watchdog flag).

The watchdog timer is reset by writing to the watchdog register. The time-out period then

starts over.

M41T83 watchdog interrupt

On the M41T83, provided that the necessary configuration bits are set, the IRQ/FT/OUT

output will be asserted when the watchdog times out (see Section 3.14 for additional

conditions which apply).

Should the watchdog time out, to de-assert the IRQ1/FT/OUT output, the lower seven bits of

the watchdog register (09h) must be written. This will de-assert the output and re-initialize

the watchdog. Writing these seven bits to 0 will de-assert the output and disable the

watchdog.

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M41T82-M41T83

Clock operation

A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh) but not de-

assert the IRQ1/FT/OUT output. The watchdog function is automatically disabled upon

power-up and the watchdog register is cleared.

Table 9.

Watchdog register

Addr

D7

D6

D5

D4

D3

D2

D1

D0

Function

09h

OFIE

BMB4

BMB3

BMB2

BMB1

BMB0

RB1

RB0

Watchdog

3.8

8-bit (countdown) timer

The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the

timer control register (11h) TE bit. Other timer properties such as the source clock, or

interrupt generation are also selected in the timer control register (see Table 10). For

2

accurate read back of the countdown value, the I C-bus clock (SCL) must be operating at a

frequency of at least twice the selected timer clock.

The timer control register selects one of four source clock frequencies for the timer (4096,

64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a software-

loaded 8-bit binary value (register 10h) and decrements to 1. On the next tick of the counter,

it reloads the timer countdown value and sets the timer flag (TF) bit. The TF bit can only be

cleared by software. When asserted, the timer flag (TF) can also be used to generate an

interrupt (IRQ1/FT/OUT) on the M41T83. Writing the timer countdown value (10h) has no

effect on the TF bit or the IRQ1/FT/OUT output.

3.8.1

M41T83 timer interrupt/output

On the M41T83, there are two choices for the output depending on the TI/TP configuration

bit (timer interrupt/timer pulse, bit 6, register 11h).

Normal interrupt mode

With TI/TP = 0, the output will assert like a normal interrupt, staying low until the TF bit is

cleared by software by reading the flags register (0Fh).

Free-running mode

When TI/TP is a 1, the output is a free-running waveform as depicted in Figure 22. After

being low for the specified time (as shown in Table 11), the output automatically goes high

without need of software clearing any bits. The TF bit will still be set each time the timer

reloads, but it is not necessary for the software to clear it in this mode. Furthermore, clearing

the TF bit has no effect on the output in this mode.

While writes to the timer countdown register (10h) control the reload value, reads of this

register return the current countdown timer value.

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Clock operation

M41T82-M41T83

Function

(1)

Table 10. Timer control register map

Addr

D7

D6

D5

D4

D3

TF

D2

D1

D0

0Fh

10h

11h

WDF

AF1

AF2

BL

OF

0

Flags

Timer countdown value⁽²⁾

Timer value

Timer control

TE

TI/TP

TIE

0

TD1

TD0

1. Bit positions labeled with 0 should always be written with logic 0.

2. Writing to the timer register will not reset the TF bit nor clear the interrupt.

When the timer is in the free-running mode, with a value of n programmed into the timer

countdown value, the output will nominally be low for one cycle of the specified clock source

and high for n-1 cycles with an overal period of n cycles. Thus, the countdown period is

n/source clock frequency.

For the special case of n = 1, as shown in Table 11, when the clock source is 4096 or 64 Hz,

the low time (T ) is half the clock period instead of a full clock period.

L

Table 11. Timer interrupt operation in free-running mode (with TI/TP = 1)

IRQ low time – T_L(seconds)⁽¹⁾

IRQ period – T_IRQ(seconds)

Source clock (Hz)

n = 1⁽²⁾

n > 1

n = 1

n > 1

4096

64

1/8192 = 122 µs 1/4096 = 244 µs

1/128 = 7.8 ms 1/64 = 15.6 ms

1/4096 = 244 µs

1/64 = 15.6 ms

1

n / 4096

n / 64

1

1/64

n

1/60

1 minute

n minutes

1. IRQ1/FT/OUT is asserted coincident with TF going true.

2. n = loaded countdown timer value (0 < n < 255). The timer is stopped when n = 0.

Figure 22. Timer output waveform in free-running mode (with TI/TP = 1)

T

IRQ

T

L

IRQ1/FT/OUT

AM03012v1

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Clock operation

3.8.2

Timer flag (TF)

At the end of a timer countdown, when the timer reloads, TF is set to logic '1.' Regardless of

the state of TF bit (or TI/TP bit), the timer will continue decrementing and reloading.

If both timer and alarm interrupts are used in the application, the source of the interrupt can

be determined by reading the flag bits. Refer to Section 3.14 for more information on the

interaction of these bits. The TF bit is cleared by reading the flags register. This will de-

assert an interrupt output due to the timer.

3.8.3

3.8.4

Timer interrupt enable (TIE, M41T83 only)

In normal interrupt mode (TI/TP = 0), when TF is asserted, the interrupt output is asserted (if

TIE = 1). To de-assert the interrupt, the TF bit or the TIE bit must be reset. Disabling the

interrupt by clearing the TIE bit will de-assert the output, but does not clear the TF bit. Thus,

if TIE is re-enabled prior to clearing TF, the interrupt will assert immediately.

Timer enable (TE)

●

TE = 0

When the timer register (10h) is set to 0, the timer is disabled.

TE = 1

●

The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the

counter will begin counting from the same value as when it was disabled.

3.8.5

TD1/0

These are the timer source clock frequency selection bits (see Table 12). These bits

determine the source clock for the countdown timer (see Table 10 on page 38). When not in

use, the TD1 and TD0 bits should be set to 11 (1/60 Hz) for power saving.

Table 12. Timer source clock frequency selection (244.1 µs to 4.25 hrs)

TD1

TD0

Timer source clock frequency (Hz)

0

1

0

1

0

1

4096 (244.1 µs)

64 (15.6 ms)

1 (1 s)

1/60 (60 s)

3.9

Square wave output (M41T83 only)

The M41T83 offers the user a programmable square wave function which is output on the

SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These

frequencies are listed in Table 13. Once the selection of the SQW frequency has been

completed, the SQW pin can be turned on and off under software control with the square

wave enable bit (SQWE) located in register 0Ah.

Note:

If the SQWE bit is set to '1' and V falls below the switchover (V ) voltage, the square

CC SO

wave output will be disabled.

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Clock operation

M41T82-M41T83

Table 13. Square wave output frequency

Square wave bits

Square wave

RS3

RS2

RS1

RS0

Frequency

Units

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

None

32.768

8.192

4.096

2.048

1.024

512

256

128

64

–

0

1

0

1

0

1

0

1

0

1

0

1

kHz

Hz

32

Hz

16

Hz

8

Hz

4

Hz

2

Hz

1

Hz

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M41T82-M41T83

Clock operation

3.10

Battery low warning

The M41T8x automatically checks the battery each time V powers up and each time the

CC

clock rolls over at midnight.

V

is compared to V (approximately 2.5 V), then the battery low (BL) bit, D4 of flags

BL

BAT

register 0Fh, is set if the battery voltage is found to be less than V . Similarly, if V

is

BL

BAT

greater than V , the BL bit is cleared during battery check.

BL

The BL bit retains its state until the next battery check occurs. This means the BL bit will not

clear immediately upon battery replacement, but only after the next battery check occurs at

the next power-up or midnight rollover.

If a battery low is generated during a power-up sequence, this indicates that the battery is

below approximately 2.5 volts and may not be able to maintain data integrity. Clock data

should be considered suspect and verified as correct. A fresh battery should be installed.

If a battery low indication is generated during the 24-hour interval check, this indicates that

the battery is near end of life. However, data is not compromised due to the fact that a

nominal V is supplied. In order to ensure data integrity during subsequent periods of

CC

battery backup mode, the battery should be replaced.

Midnight rollover check

As shown in Figure 23, during the midnight rollover check, the M41T8x applies a load to the

battery, then compares V

to V and updates the BL bit accordingly. Because a load is

BAT

BL

present, an open condition on the V

pin will result in the BL bit being set. After the check

BAT

is performed, the RTC removes the load.

Power-up battery check

During the power-up check, no load is applied to the battery under the assumption the

battery has already been stressed to its working level by having powered the RTC in backup

mode. If no battery is present, V

indeterminate.

will be floating and the battery check result will be

BAT

Figure 23. Battery check

At power-up

and at rollover

V_BAT

Only at

rollover

V_BL=2.5V

BL

S

Q

FF

R

L

R

AM03009v1

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Clock operation

M41T82-M41T83

The M41T8x only checks the battery when powered by V . It does not check the battery

CC

while in backup mode. Thus, users are advised that during long periods in backup mode,

the battery can drop to a level at which timekeeping may fail or data becomes corrupted. If,

at power-up, a battery low is indicated, data integrity should be verified.

Forcing a battery check

If it is desired to check the battery at an arbitrary time, one common technique is for the

application software to write the time to just before midnight, 23:59:59, and then wait two

seconds thereby letting the clock rollover and causing the BL bit to update. The application

then restores the time back to its previous value plus two seconds.

3.11

Century bits

These two bits will increment in a binary fashion at the turn of the century, and handle all

leap years correctly. See Table 14 for additional explanation.

Table 14. Century bits examples

CB0

CB1

Leap Year?

Example⁽¹⁾

0

1

0

1

0

1

Yes

No

2000

2100

2200

2300

1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by

100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year

2100 is not).

3.12

Oscillator fail detection

If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either

stopped, or was stopped for some period of time. This bit can be used to judge the validity of

the clock and date data. This bit will be set to '1' any time the oscillator stops.

In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the

STOP bit (ST) should be written to a '1,' then immediately reset to 0. This will restart the

oscillator. The following conditions can cause the OF bit to be set:

●

The first time power is applied (defaults to a '1' on power-up).

Note:

If the OF bit cannot be written to '0' four seconds after the initial power-up, the STOP bit (ST)

should be written to a '1,' then immediately reset to 0.

●

The voltage present on V_CCor battery is insufficient to support oscillation.

The ST bit is set to '1.'

External interference of the crystal

For the M41T83, if the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the

IRQ1/FT/OUT pin will also be asserted (see Section 3.13 and Section 3.14 for additional

conditions which apply). The IRQ1/FT/OUT output is de-asserted by resetting the OF bit to

0, NOT by reading the flags register. The OF bit will remain a '1' until written to 0. Reading

the flags register has no effect on OF.

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M41T82-M41T83

Clock operation

The oscillator must start and have run for at least 4 seconds before attempting to reset the

OF bit to 0.

The oscillator fail detect circuit funtions during backup mode. If a triggering event occurs to

disrupt the oscillator during a power-down condition, the OF bit will be set accordingly.

3.13

Oscillator fail interrupt enable (M41T83 only)

With the OFIE bit set, the OF bit will cause the IRQ1/FT/OUT output to be asserted (see

Section 3.14.1 and 3.14.2 for additional conditions that apply). The IRQ1/FT/OUT output is

cleared by resetting the OF bit to 0 (NOT by reading the flags register). Clearing the OFIE bit

will also cause the IRQ1/FT/OUT output to de-assert, but if OFIE is subsequently set prior to

clearing OF, the IRQ1/FT/OUT output will assert immediately upon setting OFIE. Clearing

the OF bit is necessary to prevent such an inadvertent interrupt.

If the alarm in backup enable bit, ABE, is set (along with OFIE), the oscillator fail detect will

cause an interrupt in the IRQ1/FT/OUT pin during backup mode. For additional information

on this, refer to Section 3.14.2.

3.14

IRQ1/FT/OUT pin, frequency test, interrupts and the OUT bit

(M41T83 only)

Four interrupt sources, the frequency test function, and the discrete output bit OUT all share

the IRQ1/FT/OUT pin. Priority is built into the part such that some functions dominate

others. Additionally, the priority depends on configuration bits such as OUT and ABE, and

on whether the part is operating on V or is in the backup mode. This pin is an open drain

CC

output and requires an external pull-up resistor.

Figure 24 shows the various signal sources and controlling bits for the IRQ1/FT/OUT output

pin.

Figure 24. IRQ1/FT/OUT output pin circuit

TIMER

TI/TP

reload

TE

TF

TIE

IRQ1/OUT/FT

LOGIC

OUT

FT

IRQ1/OUT/FT

ABE

A1IE

OFIE

TIE

OF

AF1

Write OF to 0

to clear

OFIE

AI1E

w-dog running

Read FLAGS register

to clear

WDF

PRE

Q

Write watchdog register

to clear

WDOG

AM03013v1

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Clock operation

M41T82-M41T83

The timer, oscillator fail detect circuit, alarm 1, and watchdog are ORed together as the

primary interrupt sources. The frequency test signal, FT, is used to enable a 512 Hz output

on the IRQ1/FT/OUT pin for calibrating the RTC. When not used as an interrupt or

frequency test output, the pin can be used as a discrete logic output controlled by the OUT

bit. The ABE bit is used to enable interrupts during backup mode.

Operating on V , all four interrupt sources are available. During backup, the timer and

CC

watchdog are disabled, and the only interrupt sources are alarm 1 and the oscillator fail

detect circuit.

3.14.1

Active mode operation on V

CC

On V , the operation of the output circuit is as shown in Table 15.

CC

Table 15. Priority for IRQ1/FT/OUT pin when operating on V

CC

A1IE⁽³⁾

+ OFIE⁽⁴⁾

OUT⁽¹⁾

FT⁽²⁾

+ TIE⁽⁵⁾

+ watchdog⁽⁶⁾

running

Comment

When OUT is 0 and FT is not enabled, OUT dominates

and none of the interrupt sources have any effect.

0

x

0

x

1

x

When FT = 1 and OUT = 1 and no interrupts are enabled,

the output will be the 512 Hz frequency test (FT) signal.

512 Hz

0

When one or more interrupts are enabled, and OUT is a 1,

the pin stays high until one of the interrupts is asserted.

1

x

1

0

IRQ

1

When OUT is 1, FT is 0 and no interrupts are enabled, the

pin is high.

0

1. OUT is bit 7 of register 08h (digital calibration).

2. FT is bit 6 of register 08h (digital calibration).

3. A1IE is bit 7 of register 0Ah (alarm 1, month).

4. OFIE is bit 7 of register 09h (watchdog).

5. TIE is bit 5 of register 11h (timer control).

6. The watchdog is controlled by register 09h (watchdog).

When OUT is 0 and FT is 0, the pin will be 0 regardless of whether any interrupts are

enabled.

When FT is a 1, the 512 Hz signal will be output if OUT is 0 or if no interrupts are enabled.

The interrupt sources control the pin when OUT is 1 and one or more of the interrupts are

enabled.

If OUT is 1, FT is 0 and no interrupts are enabled, then the pin will be 1.

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Clock operation

3.14.2

Backup mode

In backup mode, the operation of the output circuit is as shown in Table 16.

Table 16. Priority for IRQ1/FT/OUT pin when operating in backup mode

A1IE⁽³⁾

OUT⁽¹⁾

ABE⁽²⁾

Comment

+ OFIE⁽⁴⁾

When ABE is 0, the pin is 1 regardless of OUT or

the interrupt sources.

x

0

x

1

When OUT is 1 and no interrupts are enabled,

the pin is 1. (A1IE and OFIE are the only

interrupts applicable in this mode).

1

0

1

x

1

0

x

1

0

When ABE is 1 and OUT is 0, OUT dominates

and regardless of the interrupt sources.

When one or more interrupts are enabled, ABE is

a 1, and OUT is a 1, the pin stays high until one of

the interrupts is asserted.

IRQ

1. OUT is bit 7 of register 08h (digital calibration).

2. ABE is bit 5 of register 0Ah (alarm 1, month).

3. A1IE is bit 7 of register 0Ah (alarm 1, month).

4. OFIE is bit 7 of register 09h (watchdog).

In backup mode, frequency test is disabled. Thus, the FT bit is a ‘don’t care’.

ABE enables interrupts in backup. If it is 0, the output pin is a 1 regardless of the other bits.

The pin is also a 1 when OUT is a 1 and no interrupts are enabled.

When OUT is 0 and ABE is a 1, the pin is 0 regardless of the interrupts.

Thus, in order to enable interrupts in backup mode, OUT must be a 1 and ABE must be a 1,

and one or more of the interrupt enables must be a 1.

Simultaneous interrupts

Since more than one interrupt source can cause the IRQ1/FT/OUT pin to go low, more than

one interrupt may be pending when the microprocessor services the interrupt. Therefore,

the application software should read the flags register (0Fh) to discern which condition or

conditions are causing the pin to be asserted.

Also be aware that once a flag causes the pin to assert, other flags could subsequently also

go true. Since the pin is already low due to the first, no additional output transition will occur.

That is why the software must check the flags register.

Example: If the watchdog is in use and the oscillator fail detect interrupt is enabled, and the

watchdog times out, the IRQ1/FT/OUT pin will go low. If, in the intervening time before the

processor services the interrupt, something disturbs the oscillator, such as a drop of

moisture landing on the crystal pins, the OF bit will also be set. Thus, when the software

services the interrupt, it must service both sources: it must re-initialize the watchdog and

clear the OF bit in order to de-assert the IRQ1/FT/OUT pin. By reading the flags register, the

software will know both flags were set and that both need service.

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Clock operation

M41T82-M41T83

3.15

FT/RST pin, frequency test and reset output pin (M41T82

only)

On the M41T82, the 512 Hz frequency test signal and the reset output share the same pin,

FT/RST. When the FT bit (bit 6 of register 08h) is a 1, the 512 Hz test signal is activated on

the pin. With FT a 0 and V good (above V

), the output will be high. If the 512 Hz is

CC

RST

enabled when V fails, the FT bit will be cleared and the output will go low to assert reset.

CC

At power-up, FT will be 0 leaving the pin functioning as the reset output.

3.16

Initial power-on defaults

Upon initial application of power to the device, the register bits will initially power-on in the

state indicated in Table 17 and Table 18.

Table 17. Initial power-on default values (part 1)

DCS Digital Analog

ACS calib. calib.

Watch-

dog⁽³⁾

Condition⁽¹⁾ST CB1 CB0 OUT FT

OFIE⁽²⁾

A1IE ⁽²⁾SQWE⁽²⁾ABE

Initial

0

1

0

1

0

power-up

Subsequent

UC UC UC UC

UC

power-up⁽⁴⁾⁽⁵⁾

1. All other control bits power-up in an undetermined state.

2. M41T83 only

3. BMB0-BMB4, RB0, RB1

4. With battery backup

5. UC = unchanged

Table 18. Initial power-up default values (part 2)

RPT11

-15

TI/TP

OTP

RPT21-

25

Condition⁽¹⁾

HT OF TE

TIE⁽²⁾TD1 TD0 RS0 RS1-3

A2IE⁽²⁾

AL2E

(2)

Initial

0

1

0

1

0

power-up

Subsequent

UC

UC UC UC

UC

power-up⁽³⁾⁽⁴⁾

1. All other control bits power-up in an undetermined state.

2. M41T83 only

3. With battery backup

4. UC = unchanged

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Clock operation

3.17

OTP bit operation (M41T83 in SOX18 package only)

When the OTP (one time programmable) bit is set to a '1,' the value in the internal OTP

registers will be transferred to the analog calibration register (12h) and are “Read only.” The

OTP value is programmed by the manufacturer, and will contain the calibration value

necessary to achieve typically 5 ppm (V only) at room temperature after two SMT

CC

reflows. This clock accuracy can then be guaranteed to drift no more than 3 ppm the first

year, and 1 ppm for each following year due to crystal aging.

If the OTP bit is set to 0, the analog calibration register will become a WRITE/READ register

and function like standard SRAM memory cells, allowing the user to implement any desired

value of analog calibration.

When the user sets the OTP bit, they need to wait for approximately 8 ms before the analog

registers transfer the value from the OTP to the analog registers due to the OTP read

operation.

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Maximum ratings

M41T82-M41T83

4

Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 19. Absolute maximum ratings

Sym

Parameter

Value⁽¹⁾

Unit

T_STG

V_CC

T_SLD

V_IO

I_O

Storage temperature (V_CCoff, oscillator off)

Supply voltage

–55 to 125

°C

V

–0.3 to 7.0

Lead solder temperature for 10 seconds

Input or output voltages

Output current

260⁽²⁾

°C

V

–0.2 to V_CC+0.3

20

1

mA

W

P_D

Power dissipation

QFN16

SO8

35.7

128.4

θ_JA

Thermal resistance, junction to ambient

°C/W

SOX18

1. Data based on characterization results, not tested in production.

2. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.

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DC and AC parameters

5

DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the dc and

ac characteristics of the device. The parameters in the following DC and AC Characteristic

tables are derived from tests performed under the measurement conditions listed in the

relevant tables. Designers should check that the operating conditions in their projects match

the measurement conditions when using the quoted parameters.

Table 20. Operating and AC measurement conditions

Parameter⁽¹⁾

M41T8x

Supply voltage (V_CC

)

2.38 V to 5.5 V

–40 to 85 °C

50 pF

Ambient operating temperature (T_A)

Load capacitance (C_L)

Input rise and fall times

≤ 5 ns

Input pulse voltages

0.2 V_CCto 0.8 V_CC

0.3 V_CCto 0.7 V_CC

Input and output timing ref. voltages

1. Output Hi-Z is defined as the point where data is no longer driven.

Figure 25. Measurement AC I/O waveform

0.8V

CC

0.7V

CC

0.3V

0.2V

CC

AI02568

Table 21. Capacitance

Symbol

Parameter⁽¹⁾⁽²⁾

Min

Max

Unit

C_IN

Input capacitance

7

pF

ns

(3)

C_OUT

Output capacitance

10

50

t_LP

Low-pass filter input time constant (SDA and SCL)

1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested.

2. At 25 °C, f = 1 MHz

3. Outputs deselected

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DC and AC parameters

M41T82-M41T83

Table 22. DC characteristics

Sym

Parameter

Test condition⁽¹⁾

Min

Typ

Max

Unit

Operating voltage (S)

–40 to 85 °C

3.00

2.70

2.38

5.50

1

V

V_CCOperating voltage (R)

Operating voltage (Z)

V

–40 to 85 °C

V

I_LIInput leakage current

I_LOOutput leakage current

0V ≤ V_IN≤ V_CC

0V ≤ V_OUT≤ V_CC

µA

1

5.5 V

3.0 V

125

55

45

8

150

SCL = 400 kHz

I_CC1Supply current

(No load)

2.5 (Z only)

5.5 V

SCL = 0 Hz;

10

All inputs ≥ V_CC– 0.2 V or

≤ V_SS+ 0.2 V

I_CC2Supply current (standby)

3.0 V

6.5

µA

(SQWE bit = 0)

V_ILInput low voltage

V_IHInput high voltage

–0.3

0.3V_CC

V

0.7V_CC

V_CC+0.3

V_CC/V_BAT= 3.0 V,

I_OL= 1.0 mA

RST, FT/RST

SQW, IRQ1/FT/OUT, IRQ2

SCL, SDA

0.4

V

V_CC= 3.0 V,

I_OL= 1.0 mA

V_OLOutput low voltage

V_OHOutput high voltage

V_CC= 3.0 V,

V

I_OL= 3.0 mA

V_CC= 3.0 V, I_OH= –1.0 mA (push-pull)

IRQ1/FT/OUT, IRQ2, FT/RST, RST

2.4

2.0

Pull-up supply voltage

(open drain)

5.5

Backup supply voltage

V_BAT

V

(battery or capacitor)

Battery low (BL bit)

threshold

V_BL

2.5

25 °C; V_CC= 0 V; OSC on;

V_BAT= 3 V; SQW off

I_BATBattery supply current

365

450

nA

1. Valid for ambient operating temperature: T_A= –40 to 85 °C; V_CC= 2.38 V to 5.5 V (except where noted)

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M41T82-M41T83

Figure 26. I

DC and AC parameters

vs. temperature

CC2

10.000

9.000

8.000

7.000

6.000

5.000

4.000

3.000

2.000

(3.0V)

(5.0V)

-40

-20

0

20

40

60

80

Temperature (°C)

ai 13909

Table 23. Crystal electrical characteristics

Symbol

Parameter⁽¹⁾⁽²⁾

Min

Typ

Max

Units

f_O

R_S

C_L

Resonant frequency

32.768

kHz

kΩ

pF

Series resistance

Load capacitance

65⁽³⁾

12.5

1. Externally supplied if using the QFN16 or SO8 package. STMicroelectronics recommends the Citizen CFS-

145 (1.5 x 5 mm) and the KDS DT-38 (3 x 8 mm) for thru-hole, or the KDS DMX-26S (3.2 x 8 mm) or Micro

Crystal MS3V-T1R (1.5 x 5 mm) for surface-mount, tuning fork-type quartz crystals.

2. Load capacitors are integrated within the M41T8x. Circuit board layout considerations for the 32.768 kHz

crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.

3. Guaranteed by design.

Table 24. Oscillator characteristics

Symbol

Parameter⁽¹⁾⁽²⁾

Conditions Min Typ Max Units

V_STA

t_STA

Oscillator start voltage

≤ 4 s

2.0

V

s

Oscillator start time

V_CC= V_SO

1

(1)

C

_XI,C_XO

Capacitor input, capacitor output

IC-to-IC frequency variation⁽²⁾⁽³⁾

25

pF

–10

+10 ppm

1. With default analog calibration value ( = 0)

2. Reference value

3. T_A= 25 °C, V_CC= 5.0 V

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DC and AC parameters

Figure 27. Power down/up mode AC waveforms

M41T82-M41T83

V

CC

V

SO

RST

t

rec

SDA, SCL

RST

DON'T CARE

t_RD

AI00596

Table 25. Power down/up trip points DC characteristics

Sym

Parameter⁽¹⁾⁽²⁾

Min

Typ

Max

Unit

S

R

Z

2.85

2.55

2.25

2.93

2.63

2.32

V_RST

25

3.0

2.7

V

V_RST

Reset threshold voltage

2.38

V

Battery backup switchover

Hysteresis

V

V_SO

mV

ms

µs

t_rec

t_RD

RST duration after V_CChigh

V_CCto reset delay⁽³⁾

140

280

2.5

1. All voltages referenced to V_SS

2. Valid for ambient operating temperature: T_A= –40 to 85 °C; V_CC= 2.38 to 5.5 V (except where noted)

3. Measured with V_CCfalling slew rate of 10 mV/µs for V_CCin the range V_RST+ 100 mV to V_RST– 100 mV

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M41T82-M41T83

Figure 28. Bus timing requirement sequence

DC and AC parameters

SDA

SCL

t

BUF

HD:STA

t

R

F

t

HIGH

t

SU:STO

SU:DAT

HD:DAT

SU:STA

P

S

t

SR

P

LOW

AI00589

Table 26. AC characteristics

Sym

Parameter⁽¹⁾

Min

Typ

Max

Units

f_SCL

t_LOW

t_HIGH

t_R

SCL clock frequency

0

400

kHz

µs

Clock low period

1.3

600

Clock high period

ns

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

300

ns

t_F

ns

t_HD:STA

t_SU:STA

600

ns

(after this period the first clock pulse is generated)

START condition setup time

(only relevant for a repeated start condition)

(2)

t_SU:DAT

Data setup time

100

0

ns

µs

ns

t_HD:DATData hold time

t_SU:STOSTOP condition setup time

600

Time the bus must be free before a new transmission

can start

t_BUF

1.3

µs

1. Valid for ambient operating temperature: T_A= –40 to 85 °C; V_CC= 2.38 to 5.5 V (except where noted).

2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling

edge of SCL.

Doc ID 12578 Rev 15

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Package mechanical data

M41T82-M41T83

6

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

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M41T82-M41T83

Package mechanical data

Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline

D

E

A3

A

A1

ddd C

e

b

L

1

2

3

E2

D2

QFN16-A

Note:

Drawing is not to scale.

Table 27. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm pack. mech. data

mm

Min

inches

Min

Sym

Typ

Max

Typ

Max

A

A1

A3

b

0.90

0.02

0.20

0.30

4.00

–

0.80

0.00

–

1.00

0.05

–

0.035

0.001

0.008

0.012

0.157

–

0.031

0.000

–

0.039

0.002

–

0.25

3.90

2.50

3.90

2.50

–

0.35

4.10

2.80

4.10

2.80

–

0.010

0.154

0.098

0.154

0.098

–

0.014

0.161

0.110

0.161

0.110

–

D

D2

E

4.00

–

0.157

–

E2

e

0.65

0.40

–

0.026

0.016

–

L

0.30

0.08

0.50

–

0.012

0.003

0.020

–

ddd

Doc ID 12578 Rev 15

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Package mechanical data

M41T82-M41T83

Figure 30. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended

footprint

2.70

0.70

0.20

4.50

2.70

0.35

0.325

0.65

AI11815

Note:

Dimensions are shown in millimeters (mm).

Figure 31. 32 KHz crystal + QFN16 vs. VSOJ20 mechanical data

6.0 0.2

3.2

VSOJ20

SMT

CRYSTAL

1.5

7.0 0.3

1

2

3

4

3.9

ST QFN16

3.9

AI11816

Note:

Dimensions shown are in millimeters (mm).

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M41T82-M41T83

Package mechanical data

Figure 32. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline

SOX18

Note:

Drawing is not to scale.

Table 28. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal,

package mech. data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

B

2.57

0.23

2.34

0.46

0.25

11.61

7.62

10.34

1.27

0.66

2.44

0.15

2.29

0.41

0.20

11.56

7.57

10.16

–

2.69

0.31

2.39

0.51

0.31

11.66

7.67

10.52

–

0.101

0.009

0.092

0.018

0.010

0.457

0.300

0.407

0.050

0.026

0.096

0.006

0.090

0.016

0.008

0.455

0.298

0.400

–

0.106

0.012

0.094

0.020

0.012

0.459

0.302

0.414

–

c

D

E

E1

e

L

0.51

0.81

0.020

0.032

Doc ID 12578 Rev 15

57/62

Package mechanical data

Figure 33. SO8 – 8-lead plastic small package outline

M41T82-M41T83

h x 45°

c

A2

A

ccc

b

e

0.25 mm

D

GAUGE PLANE

k

8

E1

E

L

1

A1

L1

SO-A

Note:

Drawing is not to scale.

Table 29. SO8 – 8-lead plastic small outline (150 mils body width), package mech.

data

mm

Min

inches

Min

Symb

Typ

Max

Typ

Max

A

A1

A2

b

1.75

0.25

0.069

0.010

0.10

1.25

0.28

0.17

0.004

0.049

0.011

0.007

0.48

0.23

0.10

5.00

6.20

4.00

-

0.019

0.009

0.004

0.197

0.244

0.157

-

c

ccc

D

4.90

6.00

3.90

1.27

4.80

5.80

3.80

-

0.193

0.236

0.154

0.050

0.189

0.228

0.150

-

E

E1

e

h

0.25

0°

0.50

8°

0.010

0°

0.020

8°

k

L

0.40

0.127

0.016

0.050

L1

1.04

0.041

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M41T82-M41T83

Package mechanical data

Figure 34. Carrier tape for QFN16, SOX18, and SO8 packages

P

0

E

P

D

2

T

A

0

F

TOP COVER

TAPE

W

B

0

P

1

CENTER LINES

OF CAVITY

K

0

USER DIRECTION OF FEED

AM03073v1

Table 30. Carrier tape dimensions for QFN16, SOX18, and SO8 packages

Bulk

Qty

Package

W

D

E

P₀

P₂

F

A₀

B₀

K₀

P₁

T

Unit

1.50

+0.10/

–0.00

12.00

0.30

1.75

0.10

4.00

0.10

2.00

0.10

5.50

0.05

4.30

0.10

4.30

0.10

1.10

0.10

8.00

0.10

0.30

0.05

QFN16

mm 1000

mm 2500

1.50

+0.10/

–0.00

24.00

0.30

1.75

0.10

4.00

0.10

2.00 11.50 12.70 11.90 3.20 16.00 0.30

0.10

SOX18

SO8

0.10

0.05

1.50

+0.10/

–0.00

12.00

0.30

1.75

0.10

4.00

0.10

2.00

0.10

5.50

0.05

6.50

0.10

5.30

0.10

2.20

0.10

8.00

0.10

0.30

0.05

Doc ID 12578 Rev 15

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Part numbering

M41T82-M41T83

7

Part numbering

Table 31. Ordering information

Example:

M41T

83

S

QA

6

F

Device family

M41T

Device type

82 (SO8 package only)

83

Operating voltage

S = V_CC= 3.00 to 5.5 V

R = V_CC= 2.70 to 5.5 V

Z = V_CC= 2.38 to 5.5 V

Package

QA = QFN16 (4 mm x 4 mm)

M⁽¹⁾= SO8

MY⁽²⁾= SOX18

Temperature range

6 = –40 °C to 85 °C

Shipping method

F = ECOPACK^®package, tape & reel

1. M41T82 only

2. The SOX18 package includes an embedded 32,768 Hz crystal.

For other options, or for more information on any aspect of this device, please contact the

ST sales office nearest you.

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Revision history

8

Revision history

Table 32. Document revision history

Date

Revision

Changes

Updated Table 1, 2, 4, 6, 10, 11, 22, Figure 20, 27, Section 3, Section 3.4.1,

Section 3.4.2, Section 3.5, Section 3.6, Section 3.7, Section 3.8,

Section 3.8.2, Section 3.8.3, Section 3.8.4, Section 3.8.5, Section 3.12,

Section 3.13, Section 6; added Section 3.8.1, Section 3.14, Section 3.15,

Table 9, 15, 16, Figure 22, 24; removed “output driver pin” section, “alarm

interrupt reset waveform” figure, “backup mode alarm waveform” figure, “timer

countdown value register bits (addr 11h)” table; added tape and reel

information Figure 34, Table 30.

09-Apr-2009

9

Updated Section 2.2: Read mode, Section 2.3: Write mode, Section 3: Clock

operation, Section 3.1, Section 3.2, Table 26.

05-Jan-2010

10

25-Mar-2010

19-Oct-2010

11

12

Updated Figure 27; Table 25.

Updated Note in Section 3.12: Oscillator fail detection.

Updated Features, title, Section 3.1: Clock data coherency, Section 3.2: Halt

bit (HT) operation; added Figure 16, added footnote 3 to Table 31: Ordering

information.

12-Oct-2011

13

Added reference to AN1572 in Section 3.2.1: Power-down time-stamp; textual

update to Section 3.17: OTP bit operation (M41T83 in SOX18 package only);

updated test condition for I_BATin Table 22: DC characteristics; removed

shipping method in tubes from Table 31: Ordering information.

16-May-2012

26-Oct-2012

14

15

Textual update concerning reflow (Features, Section 3.17); removed footnote

3 of Table 19; updated footnote 1 of Table 23; removed Section 8: References.

Doc ID 12578 Rev 15

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M41T82-M41T83

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62/62

Doc ID 12578 Rev 15


型号：	M41T83_12
厂家：	ST
描述：	Serial I2C bus real-time clock (RTC) with battery switchover 串行I2C总线的实时时钟（ RTC ）与电池切换电池时钟
文件：	总62页 (文件大小：1001K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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