M48T59V [STMICROELECTRONICS]
64 Kbit 8Kb x8 TIMEKEEPER SRAM; 64 Kbit的是8K ×8 TIMEKEEPER SRAM
| 型号： | M48T59V |
| 厂家： | 
ST |
| 描述： | 64 Kbit 8Kb x8 TIMEKEEPER SRAM |
| 文件： | 总21页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T59
M48T59Y/M48T59V
®
64 Kbit (8Kb x8) TIMEKEEPER SRAM
PRELIMINARY DATA
■ INTEGRATED ULTRA LOW POWER SRAM,
SNAPHAT (SH)
Battery/Crytstal
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
■ FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
28
■ WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
1
28
PCDIP28 (PC)
Battery/Crystal
CAPHAT
– M48T59: 4.5V ≤ V
≤ 4.75V
PFD
1
– M48T59Y: 4.2V ≤ V
≤ 4.5V
≤ 3.0V
PFD
PFD
SOH28 (MH)
– M48T59V: 2.7V ≤ V
■ SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
■ PACKAGING INCLUDES a 28-LEAD SOIC and
Figure 1. Logic Diagram
®
SNAPHAT TOP
(to be Ordered Separately)
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
■ MICROPROCESSOR POWER-ON RESET
V
CC
(Valid even during battery back-up mode)
■ PROGRAMMABLE ALARM OUTPUT ACTIVE
13
8
in the BATTERY BACK-UP MODE
A0-A12
W
DQ0-DQ7
■ BATTERY LOW FLAG
Table 1. Signal Names
M48T59
M48T59Y
M48T59V
A0-A12
Address Inputs
E
IRQ/FT
RST
DQ0-DQ7
Data Inputs / Outputs
Interrupt / Frequency Test
Output (Open Drain)
G
IRQ/FT
RST
Power Fail Reset Output
(Open Drain)
E
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
V
SS
AI01380E
G
W
V
CC
V
SS
October 1999
1/21
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M48T59, M48T59Y, M48T59V
Figure 2A. DIP Connections
Figure 2B. SOIC Connections
RST
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
RST
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
W
2
26 IRQ/FT
25 A8
3
IRQ/FT
A8
A6
A6
4
A5
24 A9
A5
5
A9
A4
23 A11
A4
6
A11
G
A3
22
G
A3
7
M48T59
M48T59Y
M48T59Y
M48T59V
A2
21 A10
A2
8
A10
E
A1
20
E
A1
9
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
14
V
SS
SS
AI01381D
AI01382E
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
Grade 1
T
Ambient Operating Temperature
°C
A
Grade 6
–40 to 85
–40 to 85
T
Storage Temperature (V Off, Oscillator Off)
°C
°C
V
STG
CC
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
T
SLD
V
–0.3 to 7
–0.3 to 7
–0.3 to 4.6
20
IO
M48T59/M48T59Y
M48T59V
V
CC
Supply Voltage
V
I
O
Output Current
mA
W
P
D
Power Dissipation
1
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
(1)
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ7-DQ0
Power
Standby
CC
V
X
High Z
IH
4.75V to 5.5V
or
4.5V to 5.5V
V
IL
V
IL
V
IL
V
D
Active
IL
IH
IH
IN
V
IL
V
V
D
Read
Active
OUT
or
3.0V to 3.6V
V
IH
Read
High Z
High Z
High Z
Active
(2)
Deselect
Deselect
X
X
X
CMOS Standby
Battery Back-up Mode
V
to V
(min)
PFD
SO
≤ V
X
X
X
SO
Note: 1. X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
2. See Table 7 for details.
2/21
M48T59, M48T59Y, M48T59V
Figure 3. Block Diagram
IRQ/FT
OSCILLATOR AND
CLOCK CHAIN
16 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A12
POWER
DQ0-DQ7
8176 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
W
G
V
PFD
SWITCHING
CIRCUITRY
V
RST
V
CC
SS
AI01383D
DESCRIPTION
Table 4. AC Measurement Conditions
®
The M48T59/59Y/59V TIMEKEEPER RAM is an
8Kb x8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.
The M48T59/59Y/59V is a non-volatile pin and
function equivalent to any JEDEC standard 8Kb x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed.
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Figure 4. AC Testing Load Circuit
The 28 pin 600mil DIP CAPHAT™ houses the
M48T59/59Y/59V silicon with a quartz crystal and
a long life lithium button cell in a single package.
645Ω
DEVICE
UNDER
TEST
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Inser-
tion of the SNAPHAT housing after reflow pre-
vents potential battery and crystal damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
1.75V
C
= 100pF
L
C
includes JIG capacitance
L
AI02325
Note: Excluding open-drain output pins.
3/21
M48T59, M48T59Y, M48T59V
(1, 2)
Table 5. Capacitance
(T = 25 °C)
A
Symbol
Parameter
Input Capacitance
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
10
pF
IN
IN
(3)
V
OUT
Input / Output Capacitance
10
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
CC
M48T59/Y
M48T59V
Symbol
Parameter
Test Condition
Unit
Min
Max
Min
Max
(1)
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±1
±1
50
±1
±1
30
µA
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
I
LO
OUT
I
Outputs open
mA
CC
Supply Current (Standby)
TTL
I
E = V
3
2
mA
mA
CC1
IH
Supply Current (Standby)
CMOS
I
E = V – 0.2V
3
1
CC2
(2)
CC
Input Low Voltage
–0.3
2.2
0.8
–0.3
2
0.8
V
V
V
V
IL
V
V
CC
+ 0.3
V
CC
+ 0.3
Input High Voltage
IH
I
I
= 2.1mA
= 10mA
= –1mA
Output Low Voltage
0.4
0.4
0.4
0.4
OL
V
V
OL
Output Low Voltage (IRQ/FT
I
V
V
OL
(3)
and RST)
Output High Voltage
2.4
2.4
OH
OH
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
3. The IRQ/FT and RST pins are Open Drain.
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
Symbol
Parameter
Min
4.5
4.2
2.7
Typ
4.6
Max
4.75
4.5
Unit
M48T59
M48T59Y
M48T59V
M48T59/Y
M48T59V
V
V
V
V
V
V
PFD
Power-fail Deselect Voltage
4.35
2.9
3.0
3.0
V
Battery Back-up Switchover Voltage
ExpectedDataRetentionTime(at25°C)
SO
V
–100mV
PFD
Grade 1
Grade 6
YEARS
YEARS
7
t
DR
(2)
10
Note: 1. All voltages referenced to V
.
SS
2. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
4/21
M48T59, M48T59Y, M48T59V
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C)
A
Symbol
Parameter
Min
Max
Unit
t
E or W at V before Power Down
0
µs
PD
(1)
IH
V
V
(max) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
M48T59/Y
M48T59V
10
150
10
1
µs
µs
µs
µs
(2)
(min) to V
V
Fall Time
t
PFD
PFD
SS CC
FB
t
R
V
V
V
(min) to V
(max) V Rise Time
PFD CC
t
to V (min) V Rise Time
PFD CC
RB
SS
(3)
(max) to RST High
40
200
ms
t
PFD
REC
Note: 1. V
(max) to V
(min) fall time of less than t may result in deselection/write protection not occurring until 200µs after V pass-
F CC
PFD
PFD
es V
(min).
PFD
2. V
3. t
(min) to V fall time of less than t may cause corruption of RAM data.
(min) = 20ms for industrial temperature grade 6 device.
PFD
REC
SS FB
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tPD
tFB
tRB
tDR
tREC
RST
RECOGNIZED
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI03258
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28 lead SOIC, the bat-
tery/crystal package (i.e. SNAPHAT) part number
is "M4T28-BR12SH" or “M4T32-BR12SH”.
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T59/59Y/59V are integrated on one silicon
chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, month, date, day, hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year),
30, and 31 day months are made automatically.
Byte 1FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
5/21
M48T59, M48T59Y, M48T59V
Table 9. Read Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
CC
M48T59/M48T59Y/M48T59V
-70
Symbol
Parameter
Unit
Min
Max
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
(1)
Address Valid to Output Valid
70
70
35
t
t
AVQV
ELQV
GLQV
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
5
5
t
ELQX
GLQX
EHQZ
GHQZ
t
t
25
25
t
10
t
AXQX
Note: 1. C = 100pF (see Fig 4).
L
2. C = 5pF (see Fig 4).
L
Figure 6. Read Mode AC Waveforms.
tAVAV
VALID
A0-A12
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01385
Note: Write Enable (W) = High.
6/21
M48T59, M48T59Y, M48T59V
Table 10. Write Mode AC Characteristics
(T = 0 to 70 °C or –40 to 85 °C; V = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
CC
M48T59/M48T59Y/M48T59V
-70
Symbol
Parameter
Unit
Min
70
0
Max
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
AVEL
t
50
55
0
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
EHAX
t
30
30
5
DVWH
t
DVEH
t
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
WHDX
t
5
EHDX
(1, 2)
25
t
WLQZ
t
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
60
60
5
ns
ns
ns
AVWH
t
AVE1H
(1, 2)
t
WHQX
Note: 1. C = 5pF (see Fig 4).
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ read/write memory cells.
The M48T59/59Y/59V includes a clock control cir-
cuit which updates the clock bytes with current in-
formation once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
READ MODE
The M48T59/59Y/59V is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
) after the last address input signal is
AVQV
The M48T59/59Y/59V also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
stable, providing that the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
condition. When V is out of tolerance, the circuit
of the Chip Enable Access time (t
) or Output
ELQV
CC
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
Enable Access time (t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
).
GLQV
tem operation brought on by low V . As V falls
CC
CC
below approximately 3V, the control circuitry con-
nects the battery which maintains data and clock
operation until valid power returns.
ed before t
, the data lines will be driven to an
AVQV
indeterminate state until t
puts are changed while E and G remain active,
. If the Address In-
AVQV
output data will remain valid for Output Data Hold
time (t
) but will go indeterminate until the next
AXQX
Address Access.
7/21
M48T59, M48T59Y, M48T59V
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV
A0-A12
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01386
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
8/21
M48T59, M48T59Y, M48T59V
WRITE MODE
The M48T59/59Y/59V is in the Write Mode when-
ever W and E are low. The start of a write is refer-
enced from the latter occurring falling edge of W or
E. A write is terminated by the earlier rising edge
of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
CC
a minimum of t
from Chip Enable or t
EHAX
WHAX
from Write Enable prior to the initiation of another
Note: A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
read or write cycle. Data-in must be valid t
prior to the end of write and remain valid for t
DVWH
WHDX
afterward. G should be kept high during write cy-
cles to avoid bus contention; although, if the output
bus has been activated by a low on E and G a low
At voltages below V
(min), the user can be as-
PFD
sured the memory will be in a write protected state,
provided the V fall time is not less than t . The
CC
F
on W will disable the outputs t
after W falls.
WLQZ
M48T59/59Y/59V may respond to transient noise
spikes on V that reach into the deselect window
CC
Table 11. Register Map
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
1FFFh
1FFEh
1FFDh
1FFCh
1FFBh
1FFAh
1FF9h
1FF8h
1FF7h
1FF6h
1FF5h
1FF4h
1FF3h
1FF2h
1FF1h
1FF0h
10 Years
Year
Month
Date
Year
Month
00-99
01-12
0
0
0
0
0
10 M
10 Date
Date
01-31
0
FT
0
CB
CEB
0
Day
Hours
Century/Day
Hour
00-01/01-07
00-23
0
10 Hours
0
10 Minutes
10 Seconds
S
Minutes
Minutes
00-59
ST
W
Seconds
Seconds
Control
00-59
R
Calibration
WDS BMB4 BMB3 BMB2 BMB1 BMB0
RB1
Y
RB0
Y
Watchdog
Interrupts
Alarm Date
Alarm Hours
Alarm Minutes
Alarm Seconds
Unused
AFE
RPT4
RPT3
RPT2
RPT1
Y
Y
Y
Y
ABE
Y
Y
Y
Al. 10 Date
Alarm Date
Alarm Hours
01-31
00-23
00-59
00-59
Al. 10 Hours
Alarm 10 Minutes
Alarm 10 Seconds
Alarm Minutes
Alarm Seconds
Y
Y
Z
Y
Y
Z
Y
Z
Y
Z
Y
Z
WDF
AF
BL
Flags
Keys: S = SIGN Bit
WDS = Watchdog Steering Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ST = STOP Bit
0 = Must be set to zero
Y = ’1’ or ’0’
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT4 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
Z = ’0’ and are Read only
AF = Alarm Flag
CEB = Century Enable Bit
CB = Century Bit
BL = Battery Low
9/21
M48T59, M48T59Y, M48T59V
during the time the device is sampling V . There-
fore, decoupling of the power supply lines is rec-
ommended.
condition reset will not occur unless the addresses
are stable at the flag location for at least 15ns
while the divice is in the read mode as shown in
Figure 11.
CC
When V
drops below V , the control circuit
SO
CC
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T59/59Y/
59V for an accumulated period of at least 7 years
The IRQ/FT pin is an open drain output and re-
quires a pull-up resistor (10kΩ recommended) to
V
. The pin remains in the high impedance state
CC
unless an interrupt occurs or the frequency test
mode is enabled.
when V
is less than V . As system power re-
CC
SO
turns and V
rises above V , the battery is dis-
SO
CC
CLOCK OPERATIONS
Reading the Clock
connected, and the power supply is switched to
external V . Deselect continues for t after
CC
REC
V
reaches V
(max).
CC
PFD
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER-ON RESET
The M48T59/59Y/59V continuously monitors V
.
CC
When V
falls to the power fail detect trip point,
CC
the RST pulls low (open drain) and remains low on
power-up for 40ms to 200ms after V passes
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control register (1FF8h). As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
CC
V
. RST is valid for all V conditions. The RST
PFD
CC
pin is an open drain output and an appropriate re-
sistor to V should be chosen to control rise time.
CC
PROGRAMMABLE INTERRUPTS
The M48T59/59Y/59V provides two programma-
ble interrupts; an alarm and a watchdog. When an
interrupt condition occurs, the M48T59/59Y/59V
sets the appropriate flag bit in the flag register
1FF0h. The interrupt enable bits in (AFE and ABE)
in 1FF6h and the Watchdog Steering (WDS) bit in
1FF7h allow the interrupt to activate the IRQ/FT
pin.
Setting the Clock
Bit D7 of the Control register (1FF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
The interrupt flags and the IRQ/FT output are
cleared by a read to the flags register. An interrupt
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
10/21
M48T59, M48T59Y, M48T59V
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 12). Resetting the WRITE bit to
a ’0’ then transfers the values of all time registers
(1FF9h-1FFFh) to the actual TIMEKEEPER
counters and allows normal operation to resume.
After the WRITE bit is reset, the next clock update
will occur within approximately one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ‘0’.
Calibrating the Clock
The M48T59/59Y/59V is driven by a quartz con-
trolled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per million) oscillator frequency er-
ror at 25°C, which equates to about ±1.53 minutes
per month. With the calibration bits properly set,
the accuracy of each M48T59/59Y/59V improves
to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and tempera-
ture shift error with cumbersome trim capacitors.
The M48T59/59Y/59V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T59/59Y/59V in
the
DIP
package,
is
shipped
from
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T59/59Y/59V oscilla-
tor starts within one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT), the STOP bit (ST) or the CENTURY EN-
ABLE bit (CEB).
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indi-
cates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
11/21
M48T59, M48T59Y, M48T59V
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a bi-
nary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles; for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T59/59Y/59V may
require. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the fi-
nal product is packaged in a non-user serviceable
enclosure. All the designer has to do is provide a
simple utility that accesses the Calibration byte.
error, requiring a –10 (WR001010) to be loaded
into the Calibration Byte for correction. Note that
setting or changing the Calibration Byte does not
affect the Frequency test output frequency.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT bit is cleared on pow-
er-down.
For more information on calibration, see the Appli-
cation Note AN934 "TIMEKEEPER Calibration".
SETTING ALARM CLOCK
Registers 1FF5h-1FF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific day of the month or
repeat every month, day, hour, minute, or second.
It can also be programmed to go off while the
M48T59 is in the battery back-up mode of opera-
tion to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 12 shows the possible configura-
tions. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz when the
Stop bit (D7 of 1FF9h) is '0', the FT bit (D6 of
1FFCh) is '1', the AFE bit (D7 of 1FF6h) is '0', and
the Watchdog Steering bit (D7 of 1FF7h) is '1' or
the Watchdog Register is reset (1FF7h = 0).
Table 12. Alarm Repeat Mode
RPT4 RPT3
RPT2
RPT1 Alarm Activated
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Once per Second
Once per Minute
Once per Hour
Once per Day
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 ppm oscillator frequency
Once per Month
Figure 11. Interrupt Reset Waveforms
15ns Min
ADDRESS 1FF0h
A0-A12
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI01388B
12/21
M48T59, M48T59Y, M48T59V
Note: User must transition address (or toggle chip
WATCHDOG TIMER
enable) to see Flag bit change.
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight bit Watchdog Register (Ad-
dress 1FF7h). The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1-
RB0) select the resolution, where 00 = 1/16 sec-
ond, 01 = 1/4 second, 10 = 1 second, and 11 = 4
seconds. The amount of time-out is then deter-
mined to be the multiplication of the five bit multi-
plier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3 x 1
or 3 seconds).
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ‘0’ to the Alarm Date register and RPT1-4.
The alarm flag and the IRQ/FT output are cleared
by a read to the Flags register.
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T59 was in the deselect mode during
power-up. Figure 12 illustrates the back-up mode
alarm timing.
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T59 sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset.
WDF is reset by reading the Flags Register (Ad-
dress 1FFOh).
Figure 12. Back-up Mode Alarm Waveforms
tREC
V
V
V
CC
PFD
PFD
(max)
(min)
V
SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03254B
13/21
M48T59, M48T59Y, M48T59V
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a ’0’, the
watchdog will activate the IRQ/FT pin when timed-
out. When WDS is set to a ’1’, the watchdog will
output a negative pulse on the RST pin for a dura-
tion of 40ms to 200ms. The Watchdog register and
the FT bit will reset to a ’0’ at the end of a watchdog
time-out when the WDS bit is set to a ’1’.
power-up sequence or the next scheduled 24-hour
interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery voltage is
below 2.5V (approximately), which may be insuffi-
cient to maintain data integrity. Data should be
considered suspect and verified as correct. A fresh
battery should be installed.
The watchdog timer resets when the microproces-
sor performs a re-write of the Watchdog Register.
The time-out period then starts over. The watch-
dog timer is disabled by writing a value of
00000000 to the eight bits in the Watchdog Regis-
ter. The watchdog function is automatically dis-
abled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set
to output to the IRQ/FT pin and the frequency test
function is activated, the watchdog or alarm func-
tion prevails and the frequency test function is de-
nied.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data has not been
compromised due to the fact that a nominal VCC
is supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, it is
recommended that the battery be replaced. The
SNAPHAT top may be replaced while VCC is ap-
plied to the device.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T59/59Y/
59V only monitors the battery when a nominal
VCC is applied to the device. Thus applications
which require extensive durations in the battery
back-up mode should be powered-up periodically
(at least once every few months) in order for this
technique to be beneficial. Additionally, if a battery
low is indicated, data integrity should be verified
upon power-up via a checksum or other technique.
BATTERY LOW FLAG
The M48T59/59Y/59V automatically performs pe-
riodic battery voltage monitoring upon power-up
and at factory-programmed time intervals of 24
hours (at day rollover) as long as the device is
powered and the oscillator is running. The Battery
Low flag (BL), Bit D4 of the flags Register 1FF0h,
will be asserted high if the internal or SNAPHAT
battery is found to be less than approximately
2.5V. The BL flag will remain active until comple-
tion of battery replacement and subsequent bat-
tery low monitoring tests, either during the next
POWER-ON DEFAULTS
Upon application of power to the device, the fol-
lowing register bits are set to a ’0’ state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT.
(See Table 13).
Table 13. Default Values
WATCHDOG
Condition
W
R
FT
AFE
ABE
(1)
Register
Initial Power-up
(Battery Attach for SNAPHAT)
0
0
0
0
0
0
(2)
(3)
0
0
0
0
0
0
0
1
0
1
0
0
Subsequent Power-up / RESET
(4)
Power-down
Note: 1. WDS, BMB0-BMB4, RBO, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to ’1’ prior to power-down.
14/21
M48T59, M48T59Y, M48T59V
POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION
Figure 13. Supply Voltage Protection
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V
bus. The energy
CC
V
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering.
CC
V
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
SS
CC
below V by as much as one Volt. These nega-
SS
tive spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V (cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount
15/21
M48T59, M48T59Y, M48T59V
Table 14. Ordering Information Scheme
Example:
M48T59Y
-70 MH
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
(1)
59
= V = 4.75V to 5.5V; V
= 4.5V to 5.5V
PFD
CC
59Y = V = 4.5V to 5.5V; V
= 4.2V to 4.5V
= 2.7V to 3.0V
CC
PFD
PFD
59V = V = 3.0V to 3.6V; V
CC
Speed
-70 = 70ns
Package
PC = PCDIP28
(2)
MH
= SOH28
Temperature Range
1 = 0 to 70 °C
(3)
6
= –40 to 85 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The M48T59 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number
"M4TXX-BR12SH1" in plastic tube or "M4TXX-BR12SH1TR" in Tape & Reel form.
3. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery/crystal package "M4TXX-BR12SH1" in conductive foam since will drain the lithium button-
cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
16/21
M48T59, M48T59Y, M48T59V
Table 15. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.65
0.76
8.89
0.53
1.78
0.31
39.88
18.34
2.79
36.32
16.00
3.81
Typ
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
B1
C
D
E
e1
e3
eA
L
N
Figure 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Drawing is not to scale.
17/21
M48T59, M48T59Y, M48T59V
Table 16. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
Figure 15. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
18/21
M48T59, M48T59Y, M48T59V
Table 17. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
Figure 16. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
19/21
M48T59, M48T59Y, M48T59V
Table 18. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Figure 17. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
20/21
M48T59, M48T59Y, M48T59V
.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
1999 STMicroelectronics - All Rights Reserved
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
21/21
相关型号：
©2020 ICPDF网 联系我们和版权申明