M48Z128V-70CS1 [STMICROELECTRONICS]
128KX8 STANDARD SRAM, 70ns, PDSO32, TSOP-32;
| 型号： | M48Z128V-70CS1 |
| 厂家： | 
ST |
| 描述： | 128KX8 STANDARD SRAM, 70ns, PDSO32, TSOP-32 静态存储器 光电二极管 |
| 文件： | 总18页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48Z128
M48Z128Y, M48Z128V
1 Mbit (128Kb x8) ZEROPOWER SRAM
■ INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
■ CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
32
1
■ 10 YEARS of DATA RETENTION in the
ABSENCE of POWER
PMDIP32 (PM)
Module
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
SNAPHAT (SH)
Battery
■ WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
PFD
– M48Z128: 4.50V ≤ V
≤ 4.75V
PFD
– M48Z128Y: 4.20V ≤ V
≤ 4.50V
≤ 3.00V
PFD
PFD
– M48Z128V: 2.80V ≤ V
■ BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
■ PIN and FUNCTION COMPATIBLE with
TSOP32
(8 x 20mm)
JEDEC STANDARD 128K x 8 SRAMs
SOH28
■ SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
Surface Mount Chip Set Solution (CS)
Figure 1. Logic Diagram
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
V
CC
■ SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
17
8
A0-A16
W
DQ0-DQ7
DESCRIPTION
The M48Z128/128Y/128V ZEROPOWER RAM
is a 128 Kbit x8 non-volatile static RAM organized
as131,072 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic 32 pin DIP module. This
solution is available in two special packages to
provide a highly integrated battery backed-up
memory solution.
M48Z128
M48Z128Y
M48Z128V
E
G
V
SS
AI01194
July 2000
1/18
M48Z128, M48Z128Y, M48Z128V
Figure 2. DIP Connections
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
Chip Enable
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 A15
E
30 NC
G
W
Output Enable
Write Enable
29
W
28 A13
27 A8
26 A9
25 A11
A6
V
Supply Voltage
Ground
CC
A5
M48Z128
M48Z128Y
M48Z128V
A4
V
SS
A3
24
23 A10
22
G
NC
Not Connected Internally
A2 10
A1 11
A0 12
E
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Zxx-BR00SH1”.
The M48Z128/128Y/128V also has its own Power-
fail Detect circuit. The control circuitry constantly
DQ0
13
DQ1 14
DQ2 15
V
SS
16
AI01195
The M48Z128/128Y/128V is a non-volatile pin and
function equivalent to any JEDEC standard 128K
x8 SRAM. It also easily fits into many ROM,
EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement
for special writetiming or limitations on the number
of writes that can be performed. The 32 pin 600mil
DIP Module houses the M48Z128/128Y/128V sili-
con with a long life lithium button cell in a single
package.
monitors the single V supply for an out of toler-
CC
ance condition. When V is out of tolerance, the
CC
circuit write protects the SRAM, providing a high
degree of data security in the midst of unpredict-
For surface mount environments ST provides a
Chip Set solution consisting of a 28 pin 330mil
SOIC NVRAM Supervisor (M40Z300/W) and a 32
pin TSOP (8 x 20mm) LPSRAM (M68Z128/W)
packages. Both 5V and 3V versions are available
(see Table 5).
able system operation brought on by low V . As
CC
V
falls below the switchover voltage (V ), the
CC
SO
control circuitry connects the battery which main-
tains data until valid power returns.
2/18
M48Z128, M48Z128Y, M48Z128V
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
0 to 70
Unit
°C
T
A
Ambient Operating Temperature
T
T
Storage Temperature (V Off)
–40 to 70
–10 to 70
°C
STG
CC
Temperature Under Bias
°C
BIAS
(2)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
°C
T
SLD
V
–0.3 to 7
–0.3 to 7
V
IO
M48Z128/Y
M48Z128V
V
Supply Voltage
V
CC
–0.3 to 4.6
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.75V to 5.5V
or
4.5V to 5.5V
or
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
V
V
D
OUT
Read
Active
IL
3.0V to 3.6V
V
Read
High Z
High Z
High Z
Active
IH
Deselect
Deselect
X
X
X
CMOS Standby
V
to V
(min)
PFD
SO
≤ V
X
X
X
Battery Back-up Mode
SO
Note: 1. X = V or V ; V
= Battery Back-up Switchover Voltage.
IH
IL
SO
3/18
M48Z128, M48Z128Y, M48Z128V
Figure 3. Block Diagram
V
CC
A0-A16
DQ0-DQ7
POWER
E
131,072 x
8
VOLTAGE SENSE
SRAM ARRAY
AND
E
SWITCHING
CIRCUITRY
W
G
INTERNAL
BATTERY
V
SS
AI01196
Table 4. AC Measurement Conditions
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
650Ω
DEVICE
Note that Output Hi-Z is defined as the point where data is no longer
driven.
UNDER
TEST
READ MODE
1.75V
C
= 100pF
or 50pF
L
The M48Z128/128Y/128V is in the Read Mode
whenever W (Write Enable) is high and E (Chip
Enable) is low. The device architecture allows rip-
ple-through access of data from eight of 1,048,576
locations in the static storage array. Thus, the
unique address specified by the 17 Address Inputs
defines which one of the 131,072 bytes of data is
to be accessed. Valid data will be available at the
(1)
C
includes JIG capacitance
L
AI03630
Data I/O pins within Address Access time (t
)
AVQV
Note: 1. 50pF for M48Z128V (3.3V).
after the last address input signal is stable, provid-
ing that the E and G (Output Enable) access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the later
of Chip Enable Access time (t
able Access Time (t
data lines will be driven to an indeterminate state
until t . If the Address Inputs are changed
while E and G remain low, output data will remain
valid for Output Data Hold time (t ) but will go
AVQV
) or Output En-
). The state of the eight
ELQV
GLQV
AXQX
three-state Data I/O signals is controlled by E and
G. If the outputs are activated before t , the
indeterminate until the next Address Access.
AVQV
4/18
M48Z128, M48Z128Y, M48Z128V
(1)
Figure 5. Hardware Hookup for SMT Chip Set
THS(2,3)
V
V
OUT
CC
SNAPHAT
E2
BATTERY(4)
M40Z300/W
E1
M68Z128/W
DQ0-DQ7
E
E
CON
E2
E3
E4
CON
CON
CON
A0-A16
W
A
B
RST
BL
V
V
SS
SS
AI03625
Note: 1. For pin connections, see individual data sheets for M40Z300/W and M68Z128/W at www.st.com.
2. Connect THS pin to V if 4.2V ≤ V ≤ 4.5V (M48Z128Y) or connect THS pin to V if 4.5V ≤ V ≤ 4.75V (M48Z128).
PFD
OUT
PFD
SS
3. Connect THS pin to to V if 2.8V ≤ V
≤ 3.0V (M48Z128V).
PFD
SS
4. SNAPHAT ordered separately.
Table 5. ChipSet Solution
(1)
NVRAM
M48Z128
M48Z128Y
M48Z128V
LPSRAM
M68Z128
M68Z128
M68Z128W
SUPERVISOR
M40Z300
THS Pin
V
SS
V
M40Z300
OUT
V
M40Z300W
SS
Note: 1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/W).
5/18
M48Z128, M48Z128Y, M48Z128V
(1, 2)
Table 6. Capacitance
A
(T = 25 °C, f = 1MHz)
Symbol
Parameter
Input Capacitance
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
10
pF
IN
(3)
IN
V
Input / Output Capacitance
10
pF
C
IO
OUT
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 7A. DC Characteristics
(T = 0 to 70 °C; V = 4.75V to 5.5V or 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
±1
±1
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
µA
I
OUT
LO
I
Supply Current
E = V , Outputs open
105
7
mA
mA
mA
CC
IL
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC1
CC2
IH
I
E ≥ V – 0.2V
4
CC
Input Low Voltage
–0.3
2.2
0.8
V
V
IL
V
V
Input High Voltage
Output Low Voltage
Output High Voltage
V
+ 0.3
CC
V
V
V
IH
I
= 2.1mA
= –1mA
OH
0.4
OL
OL
V
OH
I
2.4
Note: 1. Outputs deselected.
Table 7B. DC Characteristics
(T = 0 to 70 °C; V = 3.0V to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
±1
µA
I
LI
IN
CC
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±1
50
4
µA
mA
mA
mA
V
I
OUT
LO
I
E = V , Outputs open
CC
IL
I
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
CC1
CC2
IH
E ≥ V – 0.2V
3
CC
–0.3
2.2
0.6
V
IL
V
V
V
+ 0.3
CC
Input High Voltage
V
IH
I
= 2.1mA
= –1mA
Output Low Voltage
0.4
V
OL
OL
V
I
OH
Output High Voltage
2.2
V
OH
Note: 1. Outputs deselected
6/18
M48Z128, M48Z128Y, M48Z128V
(1)
Table 8. Power Down/Up Trip Points DC Characteristics
A
(T = 0 to 70 °C)
Symbol
Parameter
Min
4.5
4.2
2.8
Typ
4.6
4.3
2.9
3
Max
4.75
4.5
Unit
V
M48Z128
V
Power-fail Deselect Voltage
M48Z128Y
M48Z128V
V
PFD
3.0
V
M48Z128/Y
M48Z128V
V
Battery Back-up Switchover Voltage
Data Retention Time
V
SO
2.5
(2)
10
YEARS
t
DR
Note: 1. All voltages referenced to V
.
SS
2. At 25 °C.
Table 9. Power Down/Up AC Characteristics
(T = 0 to 70 °C)
A
Symbol
Parameter
Min
Max
Unit
(1)
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
CC
F
V
V
V
V
V
Fall Time (M48Z128/Y)
Fall Time (M48Z128V)
10
150
10
1
PFD
PFD
PFD
SS CC
(2)
µs
t
FB
(min) to V
(min) to V
V
SS CC
t
(max) V
Rise Time
CC
µs
µs
R
PFD
t
to V
(min) V Rise Time
PFD CC
RB
SS
Write Protect Time (M48Z128/Y)
Write Protect Time (M48Z128V)
40
40
150
250
t
µs
WPT
E Recovery Time
40
120
ms
t
ER
Note: 1. V
(max) to V
(min) fall time of less than t may result indeselection/write protection not occurring until 200µs after V pass-
F CC
PFD
PFD
es V
(min).
PFD
2. V
(min) to V fall time of less than t may cause corruption of RAM data.
PFD
SS FB
Figure 6. Power Down/Up Mode AC Waveforms
tF
V
V
CC
PFD
(max)
(min)
V
PFD
V
V
SO
SS
tWP
tDR
tR
tFB
tRB
DON’T CARE
tER
INPUTS
RECOGNIZED
RECOGNIZED
(Including E)
HIGH-Z
OUTPUTS
VALID
VALID
AI02385
7/18
M48Z128, M48Z128Y, M48Z128V
Table 10. Read Mode AC Characteristics
(T = 0 to 70 °C; V = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
CC
M48Z128
M48Z128Y
M48Z128V
M48Z128
M48Z128Y
M48Z128V
M48Z128
M48Z128Y
Symbol
Parameter
Unit
-70
-85
-120
Min
Max
Min
Max
Min
Max
t
Read Cycle Time
70
85
120
ns
ns
AVAV
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Address Valid to Output Valid
70
70
35
85
85
45
120
120
60
t
AVQV
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
ns
ns
ns
ns
ns
ns
ns
t
ELQV
t
GLQV
5
3
5
3
5
3
t
ELQX
t
GLQX
30
20
35
25
45
35
t
EHQZ
GHQZ
t
5
5
10
t
AXQX
Note: 1. C = 100pF.
L
2. C = 5pF.
L
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DATA VALID
DQ0-DQ7
AI01078
Note:
Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
8/18
M48Z128, M48Z128Y, M48Z128V
Figure 10. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
VALID
A0-A16
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Note: Write Enable (W) = High.
WRITE MODE
tecting itself t
after V
falls below V
. All
PFD
WP
CC
outputs become high impedance, and all inputs
The M48Z128/128Y/128V is in the Write Mode
whenever W and E are active. The start of a write
is referenced from the latter occurring falling edge
of W or E. A write is terminated by the earlier rising
edge of W or E.
are treated as ”don’t care.”
If power fail detection occurs during a valid ac-
cess, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
t
, write protection takes place. When V drops
WP
CC
The addresses must be held valid throughout the
below V , the control circuit switches power to
SO
cycle. E or W must return high for minimum of t
E-
the internal energy source which preserves data.
from E or t
from W prior to the initiation
HAX
WHAX
of another read or write cycle. Data-in must be val-
The internal coin cell will maintain data in the
M48Z128/128Y/128V after the initial application of
V
id t prior to the end of write and remain valid
DVWH
for t
or t
afterward. G should be kept
for an accumulated period of at least 10 years
WHDX
EHDX
CC
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs
when V is less than V . As system power re-
CC SO
turns and V rises above V , the battery is dis-
CC
SO
connected, and the power supply is switched to
t
after W falls.
external V . Write protection continues for t af-
WLQZ
CC ER
ter V reaches V
to allow for processor stabi-
CC
PFD
DATA RETENTION MODE
With valid V applied, the M48Z128/128Y/128V
lization. After t , normal RAM operation can
ER
resume.
CC
TM
operates as a conventional BYTEWIDE
static
For more information on Battery Storage Life refer
to the Application Note AN1012.
RAM. Should the supply voltage decay, the RAM
will automatically power-fail deselect, write pro-
9/18
M48Z128, M48Z128Y, M48Z128V
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01198
Note: Output Enable (G) = High.
Figure 9. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01199
Note: Output Enable (G) = High.
10/18
M48Z128, M48Z128Y, M48Z128V
Table 11. Write Mode AC Characteristics
(T = 0 to 70 °C; V = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
CC
M48Z128
M48Z128Y
M48Z128V
M48Z128
M48Z128Y
M48Z128V
M48Z128
M48Z128Y
Symbol
Parameter
Unit
-70
-85
-120
Min
70
0
Max
Min
85
0
Max
Min
120
0
Max
t
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
0
AVEL
t
t
t
t
55
55
5
65
75
5
85
100
5
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
ELEH
WHAX
t
15
30
30
0
15
35
35
0
15
45
45
0
EHAX
DVWH
t
DVEH
WHDX
t
10
10
10
EHDX
(1, 2)
25
30
40
t
WLQZ
t
65
65
75
75
100
100
AVWH
t
AVEH
(1, 2)
Write Enable High to Output Transition
5
5
5
ns
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low after W going low, the outputs remain in the high impedance state.
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
Figure 11. Supply Voltage Protection
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V
bus. The energy
CC
V
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
11) is recommended in order to provide the need-
ed filtering.
V
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
SS
ative voltage spikes on V that drive it to values
CC
below V by as much as one Volt. These nega-
SS
tive spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V (cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
11/18
M48Z128, M48Z128Y, M48Z128V
Table 12. Ordering Information Scheme
Example:
M48Z128Y
-70 CS
1
Device Type
M48Z
Supply Voltage and Write Protect Voltage
128 = V = 4.75V to 5.5V; V
= 4.5V to 4.75V
= 4.2V to 4.5V
= 2.8V to 3.0V
CC
PFD
128Y = V
128V = V
= 4.5V to 5.5V; V
CC
CC
PFD
PFD
= 3.0V to 3.6V; V
Speed
-70 = 70ns
-85 = 85ns
-120 = 120ns
Package
PM = PMDIP32
(1)
CS = Surface Mount Chip Set solution M40Z300/W (SOH28) + M68Z128/W (TSOP32)
Temperature Range
1 = 0 to 70 °C
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
”M4Zxx-BR00SH1” in plastic tube or ”M4Zxx-BR00SH1TR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package ”M4Zxx-BR00SH1” in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 13. Revision History
Date
Revision Details
May 1999
First Issue
Document Layout changed
Surface Mount Chip Set solution added
04/13/00
t
changed (Table 10)
06/20/00
07/19/00
GLQX
M48Z128V added
12/18
M48Z128, M48Z128Y, M48Z128V
Table 14. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
B
9.27
9.52
0.365
0.015
0.017
0.008
1.670
0.710
0.090
1.350
0.590
0.120
0.075
32
0.375
0.38
0.43
0.59
0.33
0.023
0.013
1.700
0.740
0.110
1.650
0.630
0.150
0.110
C
0.20
D
42.42
18.03
2.29
43.18
18.80
2.79
E
e1
e3
eA
L
34.29
14.99
3.05
41.91
16.00
3.81
S
1.91
2.79
N
32
Figure 12. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1
e1
L
C
eA
S
B
e3
D
N
1
E
PMDIP
Drawing is not to scale.
13/18
M48Z128, M48Z128Y, M48Z128V
Table 15. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
28
28
CP
0.10
0.004
Figure 13. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
14/18
M48Z128, M48Z128Y, M48Z128V
Table 16. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
Figure 14. M4Z28-BR00SH SNAPHAT Housing for 48 mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Drawing is not to scale.
15/18
M48Z128, M48Z128Y, M48Z128V
Table 17. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Figure 15. M4Z32-BR00SH SNAPHAT Housing for 120 mAh Battery, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHZP-A
Drawing is not to scale.
16/18
M48Z128, M48Z128Y, M48Z128V
Table 18. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
20.200
18.500
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
–
A
A1
A2
B
0.050
0.950
0.150
0.100
19.800
18.300
–
0.0020
0.0374
0.0059
0.0039
0.7795
0.7205
–
C
D
D1
e
0.500
0.0197
E
7.900
0.500
0°
8.100
0.700
5°
0.3110
0.0197
0°
0.3189
0.0276
5°
L
α
CP
N
0.100
0.0039
32
32
Figure 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
17/18
M48Z128, M48Z128Y, M48Z128V
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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18/18
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