M4T32-BR12SHXTR [STMICROELECTRONICS]
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| 型号： | M4T32-BR12SHXTR |
| 厂家： | 
ST |
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M41T256Y
256 Kbit (32K x8) SERIAL RTC
FEATURES SUMMARY
■ 5V OPERATING VOLTAGE
Figure 1. 44-pin, Hatless SOIC Package
■ SERIAL INTERFACE SUPPORTS EXTENDED
2
I C BUS ADDRESSING (400 KHz)
■ AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
■ POWER-FAIL DESELECT VOLTAGES:
44
– M41T256Y: V = 4.5 to 5.5V;
CC
1
V
= 4.2 < V
< 4.5V
PFD
PFD
■ COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, and YEAR
SO44 (MT)
■ PROGRAMMABLE SOFTWARE CLOCK
CALIBRATION
■ 32,752 BYTES OF GENERAL PURPOSE RAM
■ MICROPROCESSOR POWER-ON RESET
Figure 2. 44-pin SOIC Package
■ HOLDS MICROPROCESSOR IN RESET
UNTIL SUPPLY VOLTAGE REACHES
STABLE OPERATING LEVEL
SNAPHAT (SH)
Crystal/Battery
■ AUTOMATIC ADDRESS-INCREMENTING
■ TAMPER INDICATION CIRCUIT with TIME-
STAMP
■ SLEEP MODE FUNCTION
■ PACKAGING INCLUDES A 44-LEAD SOIC and
®
SNAPHAT TOP (to be ordered separately)
44
■ SOIC PACKAGE PROVIDES DIRECT
1
®
CONNECTION FOR A SNAPHAT TOP
SOH44 (MH)
WHICH CONTAINS THE BATTERY and
CRYSTAL
March 2003
1/26
Rev. 2.2
M41T256Y
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Diagram (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
44-pin SOIC Connections (MT) (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Testing Input/Output Waveforms (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Crystal Electrical Characteristics (Externally Supplied) (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-Wire Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Serial Bus Data Transfer Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Acknowledgement Sequence (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Timing Requirements Sequence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Slave Address Location (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
READ Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Alternate READ Mode Sequence (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WRITE Mode Sequence (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Down/Up Mode AC Waveforms (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Down/Up AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TIMEKEEPER® Register Map (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/26
M41T256Y
Tamper Indication Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Tamper Event Time-Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Preferred Power-on/Battery Attach Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Preferred Default Values (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal Accuracy Across Temperature (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Calibration (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SNAPHAT® Battery Table (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
M41T256Y
SUMMARY DESCRIPTION
®
The M41T256Y Serial TIMEKEEPER SRAM is a
low power 256 Kbit static CMOS SRAM organized
as 32K words by 8 bits. A built-in 32.768 kHz os-
cillator (external crystal controlled) and 8 bytes of
the SRAM (see Figure 9, page 17) are used for the
clock/calendar function and are configured in bina-
ry coded decimal (BCD) format.
tion (7FF8h) stores the clock software calibration
settings as well as the Write Clock Bit.
The M41T256Y is supplied in a 44-lead SOIC
®
SNAPHAT package (MH - which integrates both
crystal and battery in a single SNAPHAT top) or a
44-pin “hatless” SOIC (MT). The 44-pin, 330mil
SOIC provides sockets with gold-plated contacts
at both ends for direct connection to a separate
SNAPHAT housing containing the battery and
crystal. The unique design allows the SNAPHAT
battery/crystal package to be mounted on top of
the SOIC package after the completion of the sur-
face-mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion. The 44-pin
SOIC and crystal/battery packages are shipped
separately in plastic, anti-static tubes or in Tape &
Reel form. For the 44-lead SOIC, the battery/crys-
tal package (e.g., SNAPHAT) part number is
“M4Txx-BR12SH” (see Table 15, page 24).
Addresses and data are transferred serially via a
two line, bi-directional I C interface. The built-in
address register is incremented automatically af-
ter each WRITE or READ data byte.
2
The M41T256Y has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power fail-
ure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
lithium button-cell supply when a power failure oc-
curs. Functions available to the user include a
non-volatile, time-of-day clock/calendar, and Pow-
er-on Reset. The eight clock address locations
contain the year, month, date, day, hour, minute,
second, and tenths/hundredths of seconds in 24-
hour BCD format. Corrections for 28, 29 (leap year
- valid until year 2100), 30 and 31 day months are
made automatically. The first clock address loca-
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium, button-cell battery.
Figure 3. Logic Diagram
Table 1. Signal Names
(1)
Oscillator Input
XI
(1)
V
V
CC BAT
(1)
Oscillator Output
XO
(1)
(1)
FT
Frequency Test (Open drain)
Reset Output (Open drain)
Serial Clock Input
XI
RST
SCL
SDA
XO
RST
FT
M41T256Y
SCL
SDA
TP
Serial Data Input/Output
Supply Voltage
V
CC
(1)
Battery Supply Voltage
V
V
BAT
SS
Ground
V
SS
TP
Tamper Input
AI04754b
Note: 1. For 44-pin SNAPHAT (MT) package only.
Note: 1. For 44-pin SNAPHAT (MT) package only.
4/26
M41T256Y
Figure 4. 44-pin SOIC Connections (MT)
Figure 5. 44-pin SOIC (MH - SNAPHAT)
V
V
CC
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
XO
XI
NF
NC
NC
NF
CC
NC
NC
NC
FT
NC
NC
NC
FT
RST
NF
NF
NF
NF
NF
NF
NF
TP
NC
NF
RST
NF
NF
NF
NF
NF
NF
NF
TP
NC
NF
NF
NF
NF
NF
NF
NF
NC
NC
NF
SCL
NC
NF
NF
NF
NF
NF
BAT+
NF
NF
NF
NF
NF
NF
NC
NC
NF
SCL
NC
NF
NF
NF
NF
NF
NC
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
M41T256Y
M41T256Y
NF
NF
NF
NF
NF
NF
SDA
SDA
V
V
V
V
SS
SS
SS
SS
NC
NC
V
V
SS
SS
AI04755b
AI07022
Note: No Function (NF) must be tied to V
.
SS
Figure 6. Block Diagram
PULL-UP TO
REAL TIME CLOCK
CALENDAR
CHIP V
CC
32,752 BYTES
USER RAM
SDA
SCL
2
I C
INTERFACE
RTC
& CALIBRATION
(1)
FT
TAMPER BIT
32KHz
OSCILLATOR
Crystal
TP
POWER
V
CC
V
BAT
BL
V
= 2.5V
COMPARE
COMPARE
BL
V
= V
SO
BAT
V
= 4.38V
PFD
(1)
POR
COMPARE
RST
AI04759
Note: 1. Open drain output
5/26
M41T256Y
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 85
–55 to 125
260
Unit
°C
°C
°C
V
®
SNAPHAT
SOIC
T
Storage Temperature (V Off, Oscillator Off)
STG
CC
(1)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
T
SLD
V
IO
–0.3 to V + 0.3
CC
V
–0.3 to 7.0
V
CC
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
6/26
M41T256Y
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. DC and AC Measurement Conditions
Parameter
M41T256Y
4.5 to 5.5V
–25 to 70°C
100pF
V
CC
Supply Voltage
Ambient Operating Temperature
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 50ns
0.2V to 0.8V
Input Pulse Voltages
CC
CC
0.3V to 0.7V
Input and Output Timing Ref. Voltages
CC
CC
Figure 7. AC Testing Input/Output Waveforms
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI02568
Table 4. Capacitance
(1,2)
Symbol
Min
Max
7
Unit
pF
Parameter
Input Capacitance
C
IN
Input Capacitance (Tamper Pin)
1000
pF
(3)
Input / Output Capacitance
10
50
pF
ns
C
IO
t
Low-pass filter input time constant (SDA and SCL)
LP
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
7/26
M41T256Y
Table 5. DC Characteristics
(1)
Sym
Parameter
Battery Current OSC ON
Battery Current OSC OFF
Supply Current
Min
Typ
1.5
1.0
1.4
1.0
Max
1.9
1.4
3.0
2.5
Unit
µA
Test Condition
T = 25°C, V = 0V, V = 3.0V
BAT
A
CC
I
I
BAT
µA
f = 400kHz
mA
mA
CC1
CC2
I
SCL, SDA = V – 0.3V
Supply Current (Standby)
CC
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Input High Voltage
±1
±1
µA
µA
V
I
IN
CC
LI
(2)
0V ≤ V
≤ V
CC
I
OUT
LO
V
0.7V
V
+ 0.3
IH
CC
CC
V
–
Input High Voltage in Battery Back-
up for Tamper Pin
BAT
V
V
BAT
V
IHB
Vdiode
V
0.3V
CC
Input Low Voltage
–0.3
V
V
V
V
V
V
V
Ω
IL
V
2.5
3.5
+ 0.3
BAT Battery Voltage
V
OH
V
CC
Output High Voltage
Output Low Voltage
I
= 3.0mA
= 10mA
0.4
0.4
OL
V
OL
(3)
I
OL
Output Low Voltage (Open Drain)
V
Power Fail Deselect
4.20
4.50
PFD
V
V
BAT
Battery Back-up Switchover
SO
R
SW
Switch Resistance on Tamper Pin
500
Note: 1. Valid for Ambient Operating Temperature: T = –25 to 70°C; V = 4.5 to 5.5V (except where noted).
A
CC
2. Outputs deselected.
3. For RST and FT pin (Open Drain).
Table 6. Crystal Electrical Characteristics (Externally Supplied)
(1,2)
Symbol
Typ
Min
Max
Unit
Parameter
Resonant Frequency
f
32.768
kHz
0
R
Series Resistance
Load Capacitance
35
kΩ
S
12.5
pF
C
L
Note: 1. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S:
1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or ht-
tp://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T256Y. Circuit board layout considerations for the 32.768 kHz crystal of minimum
trace lengths and isolation from RF generating signals should be taken into account.
8/26
M41T256Y
OPERATING MODES
The M41T256Y clock operates as a slave device
on the serial bus. Access is obtained by imple-
menting a start condition followed by the correct
slave address (D0h). The 256K bytes contained in
the device can then be accessed sequentially in
the following order:
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
0-7FEF = General Purpose RAM
7FF0-7FF6 = Reserved
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
7FF7h = Tenths/Hundredths Register
7FF8h = Control Register
7FF9h = Seconds Register
7FFAh = Minutes Register
7FFBh = Hour Register
7FFCh = Tamper/Day Register
7FFDh = Date Register
7FFEh = Month Register
7FFFh = Year Register
The M41T256Y clock continually monitors V for
CC
an out-of tolerance condition. Should V
fall be-
CC
low V
, the device terminates an access in
PFD
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from an out-of-tolerance system.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
When V
falls below V , the device automati-
CC
SO
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
V
rises above V , the battery is disconnected,
CC
SO
Acknowledge. Each byte of eight bits is followed
by one acknowledge clock pulse. This acknowl-
edge clock pulse is a low level put on the bus by
the receiver whereas the master generates an ex-
tra acknowledge related clock pulse. A slave re-
ceiver which is addressed is obliged to generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low dur-
ing the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must sig-
nal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
and the power supply is switched to external V
.
CC
Write protection continues until V reaches V
CC
PFD
plus t
.
REC
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
9/26
M41T256Y
Figure 8. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
(SCL) CLOCK
(SDA) DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI04756
Figure 9. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
1
2
8
9
MASTER
DATA OUTPUT
MSB
LSB
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
AI00601
10/26
M41T256Y
Figure 10. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
P
S
tLOW
SR
P
AI00589
Table 7. AC Characteristics
Symbol
(1)
Min
0
Max
Unit
kHz
µs
Parameter
f
t
SCL Clock Frequency
400
SCL
Time the bus must be free before a new transmission can start
SDA and SCL Fall Time
1.3
BUF
t
300
ns
F
t
Data Hold Time
0
µs
HD:DAT
START Condition Hold Time
(after this period the first clock pulse is generated)
t
600
ns
HD:STA
t
Clock High Period
Clock Low Period
SDA and SCL Rise Time
Data Setup Time
600
1.3
ns
µs
ns
ns
HIGH
t
LOW
t
300
R
(2)
100
t
SU:DAT
START Condition Setup Time
(only relevant for a repeated start condition)
t
600
600
ns
ns
SU:STA
t
STOP Condition Setup Time
SU:STO
Note: 1. Valid for Ambient Operating Temperature: T = –25 to 70°C; V = 4.5 to 5.5V (except where noted).
A
CC
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
11/26
M41T256Y
READ Mode
In this mode the master reads the M41T256Y
slave after setting the slave address (see Figure
11, page 12). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the byte ad-
dresses A(0) and A(1) are written to the on-chip
address pointer (MSB of address byte A(0) is a
“Don’t care”). Next the START condition and slave
address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an acknowledge bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T256Y slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to An+2.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T256Y slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 13, page 13).
WRITE Mode
In this mode the master transmitter transmits to
the M41T256Y slave receiver. Bus protocol is
shown in Figure Figure 14, page 13. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that byte addresses A(0) and A(1)
will follow and is to be written to the on-chip ad-
dress pointer (MSB of address byte A(0) is a
“Don’t care”). The data byte to be written to the
memory is strobed in next and the internal address
pointer is incremented to the next memory location
within the RAM on the reception of an acknowl-
edge bit. The M41T256Y slave receiver will send
an acknowledge bit to the master transmitter after
it has received the slave address (see Figure 11,
page 12) and again after it has received each ad-
dress byte.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 12,
page 13).
Note: Address pointer will wrap around from max-
imum address to minimum address if consecutive
READ or WRITE cycles are performed.
Figure 11. Slave Address Location
R/W
START
SLAVE ADDRESS
A
1
1
0
1
0
0
0
AI00602
Note: The most significant bit is sent first.
12/26
M41T256Y
Figure 12. READ Mode Sequence
BUS ACTIVITY:
MASTER
BYTE
BYTE
SDA LINE
S
S
DATA n
ADDRESS (0) ADDRESS (1)
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
DATA n+X
P
AI04760
Figure 13. Alternate READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
DATA n
DATA n+1
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00895
Figure 14. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
BYTE
ADDRESS (1)
BYTE
ADDRESS (0)
SDA LINE
S
DATA n
DATA n+X
P
BUS ACTIVITY:
SLAVE
ADDRESS
AI04761
13/26
M41T256Y
Data Retention Mode
With valid V applied, the M41T256Y can be ac-
Note: The Sleep Mode will remove power from the
RAM array only and not affect the data retention of
the TIMEKEEPER Registers (7FF0h through
7FFFh - this includes the Calibration Register).
CC
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the
M41T256Y will automatically deselect, write pro-
tecting itself when V
falls between V
(max)
CC
PFD
The Sleep Mode (SLP) Bit located in register
7FF8h (D6), must be set to a '1' by the user while
and V
(min). This is accomplished by internally
PFD
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until V
the device is powered by V . This will “arm” the
CC
Sleep Mode latch, but not actually disconnect the
RAM array from power until the next power-down
cycle. This protects the user from immediate data
loss in the event he inadvertently sets the SLP Bit.
returns to nominal levels.
CC
When V
falls below the Battery Back-up
CC
Switchover Voltage (V ), power input is switched
SO
from the V
pin to the external battery and the
CC
Once V falls below V (V ), the Sleep Mode
CC
SO
BAT
clock registers and SRAM are maintained from the
attached battery supply.
All outputs become high impedance. On power up,
circuit will be engaged and the RAM array will be
isolated from the battery, resulting in both a lower
battery current, and a loss of RAM data.
when V returns to a nominal value, write protec-
CC
Note: Upon initial battery attach or initial power
application without the battery, the state of the
SLP Bit will be undetermined. Therefore, the SLP
Bit should be initialized to '0' by the user.
tion continues for t
. The RST signal also re-
REC
mains active during this time (see Figure 15, page
15).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Sleep Mode
Additional current reduction can be achieved by
setting the STOP (ST) Bit in register 7FF9h (D7),
turning off the clock oscillator. This combination
will result in the longest possible battery life, but
also loss of time and data. When the device is
again powered-up, the user should first read the
SLP Bit to determine if the device is currently in
Sleep Mode, then reset the bit to '0' in order to dis-
able the Sleep Mode (this will NOT be automatical-
ly taken care of during the power-up).
In order to minimize the battery current draw while
in storage, the M41T256Y provides the user with a
battery “Sleep Mode,” which disconnects the RAM
memory array from the external Lithium battery
normally used to provide non-volatile operation in
the absence of V . This can significantly extend
CC
the lifetime of the battery, when non-volatile oper-
ation is not needed.
Note: See AN1570, “M41T256Y Sleep Mode
Function” for more information on Sleep Mode and
battery lifetimes.
14/26
M41T256Y
Figure 15. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tDR
tREC
RECOGNIZED
RECOGNIZED
INPUTS
RST
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI04757
Table 8. Power Down/Up AC Characteristics
(1)
Symbol
Min
Typ
Max
Unit
Parameter
(2)
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
PFD
PFD
CC
F
(3)
V
V
V
V
Fall Time
10
10
1
µs
µs
µs
ms
t
SS CC
FB
t
(min) to V
(max) V Rise Time
R
PFD CC
to V
SS
(min) V Rise Time
CC
t
PFD
RB
t
Power up Deselect Time
40
200
REC
Expected Data Retention Time (OSC On, Sleep Mode
Off)
(4)
t
YEARS
DR
15
Note: 1. Valid for Ambient Operating Temperature: T = –25 to 70°C; V = 4.5 to 5.5V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after V pass-
PFD CC
PFD
es V
(min).
PFD
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
PFD
SS FB
4. At 25°C and V = 0V, using a BR2330 Li Battery. This drops to 7.2 years when using the M4T32-BR12SH with the oscillator run-
CC
ning.
15/26
M41T256Y
CLOCK OPERATION
Year, Month, and Date are contained in the last
three registers of the TIMEKEEPER Register
updating the registers can be halted without dis-
turbing the clock itself.
®
Map (see Table 9). Bits D0 through D2 of the next
register contain the Day (day of week). Finally,
there are the registers containing the Seconds,
Minutes, and Hours, respectively. The first clock
register is the Control Register (this is described in
the Clock Calibration section).
The nine Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 7FF8h) may be accessed
independently. Provision has been made to as-
sure that a clock update does not occur while any
of the nine clock addresses are being read. If a
clock address is being read, an update of the clock
registers will be halted. This will prevent a transi-
tion of data during the read.
Setting the Clock
Bit D7 of the Control Register (7FF8h) is the Write
Clock Bit. Setting the Write Clock Bit to a '1' will al-
low the user to write the desired Day, Date, and
Time data in 24-hour BCD format. Resetting the
Write Clock Bit to a '0' then transfers the values of
all time registers (7FF8h-7FFFh) to the actual
clock counters and resets the internal divider (or
clock) chain.
Note: The Tenths/Hundredths of Seconds Regis-
ter will automatically be reset to zero when the
WRITE Clock Bit is set.
Other register bits such as FT, TEB, and ST may
be written without setting the WC Bit. In such cas-
es, the clock data will be undisturbed and will re-
tain their previous values.
Reading the Clock
The nine byte clock register (see Table 9) is used
to both set the clock and to read the date and time
from the clock, in a binary coded decimal format.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (7FF9h to 7FFFh). The update will re-
sume either due to a Stop Condition or when the
pointer increments to a RAM address.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The Stop Bit
(ST) is the most significant bit of the Seconds Reg-
ister. Setting it to '1' stops the oscillator. Setting it
to '0' restarts the oscillator in approximately one
second.
This prevents reading data in transition. The
®
TIMEKEEPER cells in the Register Map are only
data registers and not actual clock counters, so
16/26
M41T256Y
®
Table 9. TIMEKEEPER Register Map
Data
Function/Range
BCD Format
Address
D7
D6
D5
D4
10M
TB
D3
D2
D1
D0
7FFFh
7FFEh
7FFDh
7FFCh
10 Years
Year
Year
00-99
01-12
0
0
0
0
0
Month
Month
Date
10 Date
Date: Day of Month
Day of Week
01-31
BL
FT
TEB
0
Tamper/Day
0-1/01-07
10 Hours
7FFBh
0
0
Hours (24 Hour Format)
Hours
00-23
7FFAh
7FF9h
7FF8h
7FF7h
7FF6h
7FF5h
7FF4h
7FF3h
7FF2h
7FF1h
7FF0h
0
10 Minutes
10 Seconds
S
Minutes
Seconds
Minutes
Seconds
Control
00-59
00-59
ST
WC
SLP
Calibration
0.01 Seconds
0.1 Seconds
Seconds
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00-99
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Keys: S = Sign Bit
BL = Battery Low Flag (Read only bit)
TB = Tamper Bit (Read only bit)
TEB = Tamper Enable Bit
0 = Must be set to '0'
FT = Frequency Test Bit
ST = Stop Bit
WC = Write Clock Bit
X = '1' or '0'
SLP = Sleep Mode Bit
Note: 7FF0h through 7FF6h are invalid addresses and when read will return arbitrary data.
17/26
M41T256Y
Power-on Reset
The M41T256Y continuously monitors V . When
pointer to a RAM address and back, the clock can
be read to determine the current time.
CC
V
falls to the power fail detect trip point, the RST
CC
pulls low (open drain) and remains low on power-
up for t after V passes V (max). The RST
pin is an open drain output and an appropriate
pull-up resistor should be chosen to control rise
time.
Note: The Tamper Bit (TB) must always be set to
'0' in order to read the current time.
Calibrating the Clock
REC
CC
PFD
The M41T256Y is driven by a quartz controlled os-
cillator with a nominal frequency of 32,768 Hz. The
devices are tested not exceed +/–35 PPM (parts
Tamper Indication Circuit
o
The M41T256Y provides an independent input
pin, the Tamper Pin (TP) which can be used to
monitor a signal which can result in the setting of
the Tamper Bit (TB) if the Tamper Enable Bit
(TEB) is set to a '1.'
per million) oscillator frequency error at 25 C,
which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than +1/–2
PPM at 25°C.
The Tamper Pin is triggered by being connected to
The oscillation rate of crystals changes with tem-
perature (see Figure 16, page 20). Therefore, the
M41T256Y design employs periodic counter cor-
rection. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure 17, page 20.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register (7FF8h).
These bits can be set to represent any value be-
tween 0 and 31 in binary form. Bit D5 is a Sign Bit;
'1' indicates positive calibration, '0' indicates nega-
tive calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle
may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles. If a binary '1' is loaded into the register,
only the first 2 minutes in the 64 minute cycle will
be modified; if a binary 6 is loaded, the first 12 will
be affected, and so on.
V
/V
through an external switch. This switch
CC BAT
is normally open in the application, allowing the pin
to be “floating” (internally latched to V when TEB
SS
is set). When this switch is closed (connecting the
pin to V /V
), the Tamper Bit will be immedi-
CC BAT
ately set. This allows the user to determine if the
device has been physically moved or tampered
with. The Tamper Bit is a “read only” bit and is re-
set only by taking the Tamper Pin to ground and
resetting the Tamper Enable Bit to '0.'
This function operates both under normal power,
and in battery back-up. If the switch closes during
a power-down condition, the bit will still be set cor-
rectly.
Note: Upon initial battery attach or initial power
application without the battery, the state of TEB
(and TB) will be undetermined. Therefore TEB
must be initialized to a '0.'
Tamper Event Time-Stamp
If a tamper occurs, not only will the Tamper Bit be
set, but the event will also automatically be time-
stamped. This is accomplished by freezing the
normal update of the clock registers (7FF7h
through 7FFFh) immediately following a tamper
event. Thus, when tampering occurs, the user may
first read the time registers to determine exactly
when the tamper event occurred, then re-enable
the clock update to the current time (and reset the
Tamper Bit, TB) by resetting the Tamper Enable
Bit (TEB).
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
The time update will then resume, and after either
a Stop Condition or incrementing the address
18/26
M41T256Y
Two methods are available for ascertaining how
much calibration a given M41T256Y may require.
control the rise time. The FT Bit is cleared on pow-
er-down.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate ref-
erence and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934: TIMEKEEPER
CALIBRATION. This allows the designer to give
the end user the ability to calibrate the clock as the
environment requires, even if the final product is
packaged in a non-user serviceable enclosure.
The designer could provide a simple utility that ac-
cesses the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
FT pin. The pin will toggle at 512Hz, when the Stop
Bit (ST) is '0,' and the Frequency Test Bit (FT) is
'1.'
Battery Low Warning
The M41T256Y automatically performs battery
voltage monitoring upon power-up. The Battery
Low (BL) Bit, Bit D7 of Day Register, will be assert-
ed if the battery voltage is found to be less than ap-
proximately 2.5V. The BL Bit will remain asserted
until completion of battery replacement and sub-
sequent battery low monitoring tests, during the
next power-up sequence.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed. The battery may
be replaced while V is applied to the device.
CC
The M41T256Y only monitors the battery when a
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
nominal V
is applied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
temperature. For example,
a
reading of
512.010124 Hz would indicate a +20 PPM oscilla-
tor frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output fre-
quency.
Preferred Power-on/Battery Attach Defaults
See Table 10, below.
The FT pin is an open drain output which requires
a pull-up resistor to V
for proper operation. A
CC
500 to 10k resistor is recommended in order to
Table 10. Preferred Default Values
(1)
(1)
(1)
(1)
Condition
WC
0
FT
0
TEB
TB
ST
SLP
Battery Attach or Initial Power-up
X
X
X
X
Power-Cycling (with battery)
0
UC
UC
0
UC
UC
Note: 1. X = Undetermined; UC = Unchanged
19/26
M41T256Y
Figure 16. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 17. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
20/26
M41T256Y
PACKAGE MECHANICAL INFORMATION
Figure 18. SOH44 – 44-lead Plastic, Hatless, Small Package Outline
A2
A
C
B
e
CP
D
N
E
H
A1
α
L
1
SOH-C
Note: Drawing is not to scale.
Table 11. SOH44 – 44-lead Plastic, Hatless, Small Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
A
A1
A2
B
0
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
0.81
0.032
H
11.51
0.41
0°
12.70
1.27
8°
0.453
0.016
0°
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
21/26
M41T256Y
Figure 19. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 12. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
0.81
0.032
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
22/26
M41T256Y
Figure 20. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A1
A
A3
eA
D
B
L
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 13. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
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M41T256Y
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M41T
256Y
MT
7
TR
Device Type
M41T
Supply Voltage and Write Protect Voltage
256Y = V = 4.5 to 5.5V; V
= 4.2 to 4.5V
CC
PFD
Package
MT = 44-lead, Hatless SOIC
(1)
MH = SOH44
Temperature Range
7 = –25 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
®
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT ) which is ordered separately under the part number
“M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithium button-cell
battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
®
Table 15. SNAPHAT Battery Table
Part Number
Description
Package
M4T32-BR12SH
Lithium Battery (120mAh) SNAPHAT
SH
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M41T256Y
REVISION HISTORY
Table 16. Document Revision History
Date
Rev. #
1.0
Revision Details
February 2002
26-Apr-02
First Issue
Addition of “Tamper Event Time-Stamp” text
1.1
Add Sleep Mode, 44-pin with SNAPHAT package (Figure 2, 5, 19, 20; Table 1, 2, 14, 15,
12, 13)
31-May-02
1.2
03-Jul-02
12-Jul-02
29-Jul-02
20-Dec-02
04-Jan-03
26-Mar-03
1.3
1.4
1.5
2.0
2.1
2.2
Modify Crystal Electrical Characteristics table footnotes (Table 6)
Added programmable Sleep Mode information to document (Figure 3, 4, 5, 6; Table 9, 10)
Add “Hatless” to package description (Figure 1, 18 and Table 14, 11)
I
Characteristics changed (Table 5); Document promoted to “Datasheet”
CC
Add V value (Table 5)
OL
Update test condition (Table 8)
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M41T256Y
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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