M50FLW080B_技术文档

M50FLW080A

M50FLW080B

8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)

3V Supply Firmware Hub / Low Pin Count Flash Memory

FEATURES SUMMARY

■

FLASH MEMORY

Figure 1. Packages

–

Compatible with either the LPC interface

or the FWH interface (Intel Spec rev1.1)

used in PC BIOS applications

–

5 Signal Communication Interface

supporting Read and Write Operations

5 Additional General Purpose Inputs for

platform design flexibility

Synchronized with 33MHz PCI clock

PLCC32 (K)

■

16 BLOCKS OF 64 KBYTES

–

13 blocks of 64 KBytes each

3 blocks, subdivided into 16 uniform

sectors of 4 KBytes each

Two blocks at the top and one at the

bottom (M50FLW080A)

One block at the top and two at the bottom

(M50FLW080B)

■

ENHANCED SECURITY

–

Hardware Write Protect Pins for Block

Protection

Register-based Read and Write

Protection

Individual Lock Register for Each 4 KByte

Sector

TSOP32 (NB)

8 x 14mm

■

SUPPLY VOLTAGE

–

V_CC= 3.0 to 3.6V for Program, Erase and

Read Operations

–

V_PP= 12V for Fast Program and Erase

TWO INTERFACES

TSOP40 (N)

10 x 20mm

–

Auto Detection of Firmware Hub (FWH) or

Low Pin Count (LPC) Memory Cycles for

Embedded Operation with PC Chipsets

–

Address/Address Multiplexed (A/A Mux)

Interface for programming equipment

compatibility.

■

PROGRAM/ERASE SUSPEND

–

Read other Blocks/Sectors during

Program Suspend

■

PROGRAMMING TIME: 10µs typical

PROGRAM/ERASE CONTROLLER

–

Program other Blocks/Sectors during

Erase Suspend

Embedded Program and Erase algorithms

Status Register Bits

ELECTRONIC SIGNATURE

–

Manufacturer Code: 20h

Device Code (M50FLW080A): 80h

Device Code (M50FLW080B): 81h

June 2005

1/53

M50FLW080A, M50FLW080B

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram (FWH/LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Addresses (M50FLW080A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Addresses (M50FLW080B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 10

Input/Output Communications (FWH0/LAD0-FWH3/LAD3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input Communication Frame (FWH4/LFRAME).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

_CCSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V_PPOptional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

Table 5. Memory Identification Input Configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . . 12

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2/53

M50FLW080A, M50FLW080B

Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. LPC Bus Read Field Definitions (1-Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. LPC Bus Read Waveforms (1-Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. LPC Bus Write Field Definitions (1 Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10.LPC Bus Write Waveforms (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Quadruple Byte Program Command (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Double/Quadruple Byte Program Command (FWH Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 13. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program/Erase Controller Status (Bit SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Suspend Status (Bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

V

_PPStatus (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Suspend Status (Bit SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block/Sector Protection Status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3/53

M50FLW080A, M50FLW080B

FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . . 24

Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15. Configuration Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . . 25

Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 21. FWH/LPC Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.FWH/LPC Interface AC Measurement I/O Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.A/A Mux Interface AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 23. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 24. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14.FWH/LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 25. FWH/LPC Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 15.FWH/LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26. FWH/LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 16.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 27. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 28. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 18.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 29. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 36

Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 37

Figure 20.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 38

Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 38

Figure 21.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 39

Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 39

4/53

M50FLW080A, M50FLW080B

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 34. M50FLW080A Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 41

Table 35. M50FLW080B Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . . 46

Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 47

Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 48

Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 49

Figure 27.Sector/Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 51

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5/53

M50FLW080A, M50FLW080B

SUMMARY DESCRIPTION

The M50FLW080 is a 8 Mbit (1M x8) non-volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single low voltage (3.0 to 3.6V) supply. For

fast programming and fast erasing on production

lines, an optional 12V power supply can be used

to reduce the erasing and programming time.

The memory is divided into 16 Uniform Blocks of

64 KBytes each, three of which are divided into 16

uniform sectors of 4 KBytes each (see APPENDIX

A. for details). All blocks and sectors can be

erased independently. So, it is possible to pre-

serve valid data while old data is erased. Blocks

can be protected individually to prevent accidental

program or erase commands from modifying their

contents.

Program and erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a program or erase operation can be detected and

any error conditions identified. The command set

to control the memory is consistent with the JE-

DEC standards.

Two different bus interfaces are supported by the

memory:

■

The primary interface, the FWH/LPC

Interface, uses Intel’s proprietary Firmware

Hub (FWH) and Low Pin Count (LPC)

protocol. This has been designed to remove

the need for the ISA bus in current PC

Chipsets. The M50FLW080 acts as the PC

BIOS on the Low Pin Count bus for these PC

Chipsets.

■

The secondary interface, the Address/

Address Multiplexed (or A/A Mux) Interface, is

designed to be compatible with current Flash

Programmers, for production line

programming prior to fitting the device in a PC

Motherboard.

The memory is supplied with all the bits erased

(set to ’1’).

6/53

M50FLW080A, M50FLW080B

Figure 2. Logic Diagram (FWH/LPC Interface)

Table 1. Signal Names (FWH/LPC Interface)

FWH0/LAD0-

Input/Output Communications

FWH3/LAD3

V

CC PP

FWH4/

Input Communication Frame

LFRAME

4

5

4

Identification Inputs

ID0-ID3

(ID0 and ID1 are Reserved for

Future Use (RFU) in LPC mode)

FWH0/LAD0

FWH3/LAD3

GPI0-

GPI4

GPI0-GPI4

IC

General Purpose Inputs

Interface Configuration

Interface Reset

CPU Reset

WP

M50FLW080A

M50FLW080B

FWH4/LFRAME

TBL

RP

CLK

IC

INIT

CLK

TBL

Clock

RP

Top Block Lock

Write Protect

INIT

WP

Reserved for Future Use. Leave

disconnected

RFU

V

SS

AI09229B

V

Supply Voltage

CC

Optional Supply Voltage for Fast

Program and Erase Operations

V

PP

SS

Figure 3. Logic Diagram (A/A Mux Interface)

Ground

NC

Not Connected Internally

V

CC PP

Table 2. Signal Names (A/A Mux Interface)

IC

Interface Configuration

Address Inputs

11

8

A0-A10

DQ0-DQ7

A0-A10

DQ0-DQ7

Data Inputs/Outputs

Output Enable

G

RC

IC

W

Write Enable

M50FLW080A

M50FLW080B

RC

RP

Row/Column Address Select

Interface Reset

G

W

V

Supply Voltage

CC

Optional Supply Voltage for Fast

Program and Erase Operations

RP

V

PP

SS

Ground

V

NC

Not Connected Internally

SS

AI09230B

7/53

M50FLW080A, M50FLW080B

Figure 4. PLCC Connections

A/A Mux

1 32

A7

A6

A5

A4

A3

A2

A1

A0

GPI1

IC (V )

IL

NC

IC (V

)

IH

GPI0

WP

NC

TBL

V

SS

CC

SS

CC

M50FLW080A

M50FLW080B

ID3

9

25

ID2

INIT

G

ID1/RFU

ID0/RFU

FWH4/LFRAME

NC

W

NC

DQ7

RFU

DQ0 FWH0/LAD0

17

A/A Mux

AI09231C

Note: Pins 27 and 28 are not internally connected.

Figure 5. TSOP32 Connections

NC

1

32

INIT

G

FWH4/LFRAME

NC

W

NC

V

RFU

DQ7

DQ6

DQ5

DQ4

SS

IC

IC (V

)

IH

A10

RC

GPI4

CLK

V

8

9

25

24

M50FLW080A

M50FLW080B

FWH3/LAD3

DQ3

CC

V

PP

RP

PP

SS

RP

GPI3

GPI2

GPI1

GPI0

WP

FWH2/LAD2

FWH1/LAD1

FWH0/LAD0

ID0/RFU

ID1/RFU

ID2

DQ2

DQ1

DQ0

A0

A9

A8

A7

A6

A5

A4

A1

A2

TBL

16

17

ID3

A3

AI09701B

8/53

M50FLW080A, M50FLW080B

Figure 6. TSOP40 Connections

NC

IC (V

NC

1

40

V

SS

CC

)

IC (V )

IL

IH

CC

NC

A10

NC

RC

NC

FWH4/LFRAME

W

NC

INIT

NC

G

NC

RFU

DQ7

DQ6

DQ5

DQ4

GPI4

NC

CLK

V

10

11

31

30

V

M50FLW080A

M50FLW080B

CC

V

PP

RP

PP

RP

NC

SS

NC

A9

A8

A7

A6

A5

A4

FWH3/LAD3

FWH2/LAD2

FWH1/LAD1

FWH0/LAD0

ID0/RFU

ID1/RFU

ID2

DQ3

DQ2

DQ1

DQ0

A0

NC

GPI3

GPI2

GPI1

GPI0

WP

A1

A2

TBL

20

21

ID3

A3

AI09232C

Table 3. Addresses (M50FLW080A)

BlockSize

(KByte)

Table 4. Addresses (M50FLW080B)

BlockSize

(KByte)

Address Range Sector Size (KByte)

64

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h-6FFFFh

50000h-5FFFFh

40000h-4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

16 x 4 KBytes

64

F0000h-FFFFFh

E0000h-EFFFFh

D0000h-DFFFFh

C0000h-CFFFFh

B0000h-BFFFFh

A0000h-AFFFFh

90000h-9FFFFh

80000h-8FFFFh

70000h-7FFFFh

60000h- 6FFFFh

50000h- 5FFFFh

40000h- 4FFFFh

30000h-3FFFFh

20000h-2FFFFh

10000h-1FFFFh

00000h-0FFFFh

16 x 4 KBytes

64

13 x 64 KBytes

64

13 x 64 KBytes

64

16 x 4 KBytes

64

16 x 4 KBytes

64

Note: Also see APPENDIX A., Table 34. and Table 35. for a full listing of the Block Addresses.

9/53

M50FLW080A, M50FLW080B

SIGNAL DESCRIPTIONS

There are two distinct bus interfaces available on

this device. The active interface is selected before

power-up, or during Reset, using the Interface

Configuration Pin, IC.

The signals for each interface are discussed in the

Firmware Hub/Low Pin Count (FWH/LPC) Signal

Descriptions section and the Address/Address

Multiplexed (A/A Mux) Signal Descriptions sec-

tion, respectively, while the supply signals are dis-

cussed in the Supply Signal Descriptions section.

Firmware Hub/Low Pin Count (FWH/LPC)

Signal Descriptions

Please see Figure 2. and Table 1..

Input/Output Communications (FWH0/LAD0-

FWH3/LAD3). All Input and Output Communica-

tions with the memory take place on these pins.

Addresses and Data for Bus Read and Bus Write

operations are encoded on these pins.

General Purpose Inputs (GPI0-GPI4). The

General Purpose Inputs can be used as digital in-

puts for the CPU to read, with their contents being

available in the General Purpose Inputs Register.

The pins must have stable data throughout the en-

tire cycle that reads the General Purpose Input

Register. These pins should be driven Low, V_IL,or

High, V_IH, and must not be left floating.

Interface Configuration (IC). The Interface Con-

figuration input selects whether the FWH/LPC in-

terface or the Address/Address Multiplexed (A/A

Mux) Interface is used. The state of the Interface

Configuration, IC, should not be changed during

operation of the memory device, except for select-

ing the desired interface in the period before pow-

er-up or during a Reset.

To select the FWH/LPC Interface, the Interface

Configuration pin should be left to float or driven

Low, V_IL. To select the Address/Address Multi-

plexed (A/A Mux) Interface, the pin should be driv-

en High, V_IH. An internal pull-down resistor is

included with a value of R_IL; there will be a leakage

current of I_LI2through each pin when pulled to V_IH.

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the device. When Interface

Reset (RP) is driven Low, V_IL, the memory is in

Reset mode (the outputs go to high impedance,

and the current consumption is minimized). When

RP is driven High, V_IH, the device is in normal op-

eration. After exiting Reset mode, the memory en-

ters Read mode.

Input

Communication

Frame

(FWH4/

LFRAME). The Input Communication Frame

(FWH4/LFRAME) signal indicates the start of a

bus operation. When Input Communication Frame

is Low, V_IL, on the rising edge of the Clock, a new

bus operation is initiated. If Input Communication

Frame is Low, V_IL, during a bus operation then the

operation is aborted. When Input Communication

Frame is High, V_IH, the current bus operation is ei-

ther proceeding or the bus is idle.

Identification Inputs (ID0-ID3). Up to 16 memo-

ries can be addressed on a bus, in the Firmware

Hub (FWH) mode. The Identification Inputs allow

each device to be given a unique 4-bit address. A

‘0’ is signified on a pin by driving it Low, V_IL, or

leaving it floating (since there is an internal pull-

down resistor, with a value of R_IL). A ‘1’ is signified

on a pin by driving it High, V_IH(and there will be a

leakage current of I_LI2through the pin).

CPU Reset (INIT). The CPU Reset, INIT, signal

is used to Reset the device when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, FWH0/LAD0-FWH3/LAD3.

The Clock conforms to the PCI specification.

By convention, the boot memory must have ad-

dress ‘0000’, and all additional memories are giv-

en addresses, allocated sequentially, from ‘0001’.

Top Block Lock (TBL). The Top Block Lock in-

put is used to prevent the Top Block (Block 15)

from being changed. When Top Block Lock, TBL,

is driven Low, V_IL, program and erase operations

in the Top Block have no effect, regardless of the

state of the Lock Register. When Top Block Lock,

TBL, is driven High, V_IH, the protection of the Block

is determined by the Lock Registers. The state of

Top Block Lock, TBL, does not affect the protec-

tion of the Main Blocks (Blocks 0 to 14). For de-

tails, see APPENDIX A..

Top Block Lock, TBL, must be set prior to a pro-

gram or erase operation being initiated, and must

not be changed until the operation has completed,

otherwise unpredictable results may occur. Simi-

larly, unpredictable behavior is possible if WP is

In the Low Pin Count (LPC) mode, the identifica-

tion Inputs (ID2-ID3) can address up to 4 memo-

ries on a bus. In the LPC mode, the ID0 and ID1

signals are Reserved for Future Use (RFU). The

value on address A20-A21 is compared to the

hardware strapping on the ID2-ID3 lines to select

the memory that is being addressed. For an ad-

dress bit to be ‘1’, the corresponding ID pin can be

left floating or driven Low, V_IL(again, with the in-

ternal pull-down resistor, with a value of R_IL). For

an address bit to be ‘0’, the corresponding ID pin

must be driven High, V_IH(and there will be a leak-

age current of I_LI2through the pin, as specified in

Table 24.). For details, see Table 5..

10/53

M50FLW080A, M50FLW080B

changed during Program or Erase Suspend, and

care should be taken to avoid this.

Write Enable (W). The Write Enable signal, W,

controls the Bus Write operation of the Command

Interface.

Row/Column Address Select (RC). The Row/

Column Address Select input selects whether the

Address Inputs are to be latched into the Row Ad-

dress bits (A0-A10) or the Column Address bits

(A11-A19). The Row Address bits are latched on

the falling edge of RC whereas the Column Ad-

dress bits are latched on its rising edge.

Write Protect (WP). The Write Protect input is

used to prevent the Main Blocks (Blocks 0 to 14)

from being changed. When Write Protect, WP, is

driven Low, V_IL, Program and Erase operations in

the Main Blocks have no effect, regardless of the

state of the Lock Register. When Write Protect,

WP, is driven High, V_IH, the protection of the Block

or Sector is determined by the Lock Registers. The

state of Write Protect, WP, does not affect the pro-

tection of the Top Block (Block 15). For details,

see APPENDIX A..

Write Protect, WP, must be set prior to a Program

or Erase operation is initiated, and must not be

changed until the operation has completed other-

wise unpredictable results may occur. Similarly,

unpredictable behavior is possible if WP is

changed during Program or Erase Suspend, and

care should be taken to avoid this.

Supply Signal Descriptions

The Supply Signals are the same for both interfac-

es.

V

_CCSupply Voltage. The V_CCSupply Voltage

supplies the power for all operations (read, pro-

gram, erase, etc.).

The Command Interface is disabled when the V_CC

Supply Voltage is less than the Lockout Voltage,

V_LKO. This is to prevent Bus Write operations from

accidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time, the operation aborts, and the memory

contents that were being altered will be invalid. Af-

ter V_CCbecomes valid, the Command Interface is

reset to Read mode.

Reserved for Future Use (RFU). Reserved for

Future Use (RFU). These pins do not presently

have assigned functions. They must be left discon-

nected, except for ID0 and ID1 (when in LPC

mode) which can be left connected. The electrical

characteristics for these signals are as described

in the “Identification Inputs (ID0-ID3).” section.

A 0.1µF capacitor should be connected between

the V_CCSupply Voltage pins and the V_SSGround

pin to decouple the current surges from the power

supply. Both V_CCSupply Voltage pins must be

connected to the power supply. The PCB track

widths must be sufficient to carry the currents re-

quired during program and erase operations.

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

Please see Figure 3. and Table 2..

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A19). They are

latched during any bus operation by the Row/Col-

umn Address Select input, RC.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs hold the data that is to be written to

or read from the memory. They output the data

stored at the selected address during a Bus Read

operation. During Bus Write operations they carry

the commands that are sent to the Command In-

terface of the internal state machine. The Data In-

puts/Outputs, DQ0-DQ7, are latched during a Bus

Write operation.

V

_PPOptional Supply Voltage. The V_PPOptional

Supply Voltage pin is used to select the Fast Pro-

gram (see the Quadruple Byte Program command

description in A/A Mux interface and the Double/

Quadruple Byte Program command description in

FWH mode) and Fast Erase options of the memo-

ry.

When V_PP= V_CC, program and erase operations

take place as normal. When V_PP= V_PPH, Fast Pro-

gram and Erase operations are used. Any other

voltage input to V_PPwill result in undefined behav-

ior, and should not be used.

V_PPshould not be set to V_PPHfor more than

80 hours during the life of the memory.

Output Enable (G). The Output Enable signal, G,

controls the output buffers during a Bus Read op-

eration.

V_SSGround. V_SSis the reference for all the volt-

age measurements.

11/53

M50FLW080A, M50FLW080B

Table 5. Memory Identification Input Configuration (LPC mode)

Memory Number

ID3

ID2

A21

1

A20

1

V

or float

V

or float

1 (Boot memory)

IL

V

IH

2

3

4

1

0

V

IH

or float

0

1

V

IH

V

IH

0

BUS OPERATIONS

The two interfaces, A/A Mux and FWH/LPC, sup-

port similar operations, but with different bus sig-

nals and timings. The Firmware Hub/Low Pin

Count (FWH/LPC) Interface offers full functional-

ity, while the Address/Address Multiplexed (A/A

Mux) Interface is orientated for erase and program

operations.

See the sections below, The Firmware Hub/Low

Pin Count (FWH/LPC) Bus Operations and Ad-

dress/Address Multiplexed (A/A Mux) Bus Opera-

tions, for details of the bus operations on each

interface.

sequent clock cycles the Host will send to the

memory:

■

ID Select, Address and other control bits on

FWH0-FWH3 in FWH mode.

■

Type+Dir Address and other control bits on

LAD0-LAD3 in LPC mode.

The device responds by outputting Sync data until

the wait states have elapsed, followed by Data0-

Data3 and Data4-Data7.

See Table 6. and Table 8., and Figure 7. and Fig-

ure 9., for a description of the Field definitions for

each clock cycle of the transfer. See Table 26.,

and Figure 15., for details on the timings of the sig-

nals.

Firmware Hub/Low Pin Count (FWH/LPC) Bus

Operations

The M50FLW080 automatically identifies the type

of FWH/LPC protocol from the first received nibble

(START nibble) and decodes the data that it re-

ceives afterwards, according to the chosen FWH

or LPC mode. The Firmware Hub/Low Pin Count

(FWH/LPC) Interface consists of four data signals

(FWH0/LAD0-FWH3/LAD3), one control line

(FWH4/LFRAME) and a clock (CLK).

Protection against accidental or malicious data

corruption is achieved using two additional signals

(TBL and WP). And two reset signals (RP and

INIT) are available to put the memory into a known

state.

Bus Write. Bus Write operations are used to write

to the Command Interface or Firmware Hub/Low

Pin Count Registers. A valid Bus Write operation

starts on the rising edge of the Clock signal when

Input Communication Frame, FWH4/LFRAME, is

Low, V_IL, and the correct Start cycle is present on

FWH0/LAD0-FWH3/LAD3. On subsequent Clock

cycles the Host will send to the memory:

■

ID Select, Address, other control bits, Data0-

Data3 and Data4-Data7 on FWH0-FWH3 in

FWH mode.

■

Cycle Type + Dir, Address, other control bits,

Data0-Data3 and Data4-Data7 on LAD0-

LAD3.

The data, control and clock signals are designed

to be compatible with PCI electrical specifications.

The interface operates with clock speeds of up to

33MHz.

The device responds by outputting Sync data until

the wait states have elapsed.

See Table 7. and Table 9., and Figure 8. and Fig-

ure 10., for a description of the Field definitions for

each clock cycle of the transfer. See Table 26.,

and Figure 15., for details on the timings of the sig-

nals.

Bus Abort. The Bus Abort operation can be used

to abort the current bus operation immediately. A

Bus Abort occurs when FWH4/LFRAME is driven

Low, V_IL, during the bus operation. The device

puts the Input/Output Communication pins,

FWH0/LAD0-FWH3/LAD3, to high impedance.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Standby, Reset and Block Protection.

Bus Read. Bus Read operations are used to read

from the memory cells, specific registers in the

Command Interface or Firmware Hub/Low Pin

Count Registers. A valid Bus Read operation

starts on the rising edge of the Clock signal when

the Input Communication Frame, FWH4/

LFRAME, is Low, V_IL, and the correct Start cycle

is present on FWH0/LAD0-FWH3/LAD3. On sub-

12/53

M50FLW080A, M50FLW080B

Note that, during a Bus Write operation, the Com-

mand Interface starts executing the command as

soon as the data is fully received. A Bus Abort dur-

ing the final TAR cycles is not guaranteed to abort

the command. The bus, however, will be released

immediately.

Standby. When FWH4/LFRAME is High, V_IH, the

device is put into Standby mode, where FWH0/

LAD0-FWH3/LAD3 are put into a high-impedance

state and the Supply Current is reduced to the

available; these include all the Commands but ex-

clude the Security features and other registers.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface is selected, all the blocks are unprotect-

ed. It is not possible to protect any blocks through

this interface.

Bus Read. Bus Read operations are used to read

the contents of the Memory Array, the Electronic

Signature or the Status Register. A valid Bus Read

operation begins by latching the Row Address and

Column Address signals into the memory using

the Address Inputs, A0-A10, and the Row/Column

Address Select RC. Write Enable (W) and Inter-

face Reset (RP) must be High, V_IH, and Output

Enable, G, Low, V_IL. The Data Inputs/Outputs will

output the value, according to the timing con-

straints specified in Figure 17., and Table 28..

Bus Write. Bus Write operations are used to write

to the Command Interface. A valid Bus Write oper-

ation begins by latching the Row Address and Col-

umn Address signals into the memory using the

Address Inputs, A0-A10, and the Row/Column Ad-

dress Select RC. The data should be set up on the

Data Inputs/Outputs; Output Enable, G, and Inter-

face Reset, RP, must be High, V_IH; and Write En-

able, W, must be Low, V_IL. The Data Inputs/

Outputs are latched on the rising edge of Write En-

able, W. See Figure 18., and Table 29., for details

of the timing requirements.

Standby level, I_CC1

.

Reset. During the Reset mode, all internal circuits

are switched off, the device is deselected, and the

outputs are put to high-impedance. The device is

in the Reset mode when Interface Reset, RP, or

CPU Reset, INIT, is driven Low, V_IL. RP or INIT

must be held Low, V_IL, for t_PLPH. The memory re-

verts to the Read mode upon return from the Re-

set mode, and the Lock Registers return to their

default states regardless of their states before Re-

set. If RP or INIT goes Low, V_IL, during a Program

or Erase operation, the operation is aborted and

the affected memory cells no longer contain valid

data. The device can take up to t_PLRHto abort a

Program or Erase operation.

Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at V_IH.

The Address/Address Multiplexed (A/A Mux) Inter-

face has a more traditional-style interface. The sig-

nals consist of a multiplexed address signals (A0-

A10), data signals, (DQ0-DQ7) and three control

signals (RC, G, W). An additional signal, RP, can

be used to reset the memory.

The Address/Address Multiplexed (A/A Mux) Inter-

face is included for use by Flash Programming

equipment for faster factory programming. Only a

subset of the features available to the Firmware

Hub (FWH)/Low Pin Count (LPC) Interface are

Reset. During the Reset mode, all internal circuits

are switched off, the device is deselected, and the

outputs are put at high-impedance. The device is

in the Reset mode when RP is Low, V_IL. RP must

be held Low, V_ILfor t_PLPH. If RP goes Low, V_IL,

during a Program or Erase operation, the opera-

tion is aborted, and the affected memory cells no

longer contain valid data. The memory can take up

to t_PLRHto abort a Program or Erase operation.

13/53

M50FLW080A, M50FLW080B

Table 6. FWH Bus Read Field Definitions

Clock

Cycle

Number Count

Clock

Cycle

FWH0- Memory

Field

Description

FWH3

I/O

On the rising edge of CLK with FWH4 Low, the contents of FWH0-

FWH3 indicate the start of a FWH Read cycle.

1

2

1

START

1101b

I

Indicates which FWH Flash Memory is selected. The value on

FWH0-FWH3 is compared to the IDSEL strapping on the FWH

Flash Memory pins to select which FWH Flash Memory is being

addressed.

IDSEL

ADDR

MSIZE

XXXX

I

A 28-bit address is transferred, with the most significant nibble

first. For the multi-byte read operation, the least significant bits

(MSIZE of them) are treated as Don't Care, and the read operation

is started with each of these bits reset to 0. Address lines A20-21

and A23-27 are treated as Don’t Care during a normal memory

array access, with A22=1, but are taken into account for a register

access, with A22=0. (See Table 15.)

3-9

10

7

1

This one clock cycle is driven by the host to determine the number

of Bytes that will be transferred. M50FLW080 supports: single

Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer

(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).

XXXX

1111b

The host drives FWH0-FWH3 to 1111b to indicate a turnaround

cycle.

11

12

1

TAR

I

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3 during this

cycle.

O

The FWH Flash Memory drives FWH0-FWH3 to 0101b (short

wait-sync) for two clock cycles, indicating that the data is not yet

available. Two wait-states are always included.

13-14

15

2

1

WSYNC 0101b

RSYNC 0000b

O

The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating

that data will be available during the next clock cycle.

Data transfer is two CLK cycles, starting with the least significant

nibble. If multi-Byte read operation is enabled, repeat cycle-16 and

MSIZE

16-17

M=2n

DATA

XXXX

1111b

cycle-17 n times, where n = 2

.

The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate

a turnaround cycle.

1

TAR

O

1111b

(float)

The FWH Flash Memory floats its outputs, the host takes control

of FWH0-FWH3.

N/A

Figure 7. FWH Bus Read Waveforms

CLK

FWH4

FWH0-FWH3

START

1

IDSEL

1

ADDR

7

MSIZE

1

TAR

2

SYNC

3

DATA

M

TAR

2

Number of

clock cycles

AI08433B

14/53

M50FLW080A, M50FLW080B

Table 7. FWH Bus Write Field Definitions

Clock

Cycle

Number

Clock

Cycle

Count

FWH0- Memory

Field

Description

FWH3

I/O

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Write Cycle.

1

2

1

START

1110b

I

Indicates which FWH Flash Memory is selected. The value on

FWH0-FWH3 is compared to the IDSEL strapping on the FWH

Flash Memory pins to select which FWH Flash Memory is being

addressed.

1

IDSEL

XXXX

I

A 28-bit address is transferred, with the most significant nibble

first. Address lines A20-21 and A23-27 are treated as Don’t

Care during a normal memory array access, with A22=1, but are

taken into account for a register access, with A22=0. (See Table

15.)

3-9

10

7

1

ADDR

MSIZE

XXXX

I

0000(Single Byte Transfer) 0001 (Double Byte Transfer) 0010b

(Quadruple Byte Transfer).

Data transfer is two cycles, starting with the least significant

nibble. (The first pair of nibbles is that at the address with A1-

A0 set to 00, the second pair with A1-A0 set to 01, the third

pair with A1-A0 set to 10, and the fourth pair with A1-A0 set

to 11. In Double Byte Program the first pair of nibbles is that at

the address with A0 set to 0, the second pair with A0 set to 1)

11-18

M=2/4/8

DATA

XXXX

1111b

I

The host drives FWH0-FWH3 to 1111b to indicate a turnaround

cycle.

1

TAR

I

O

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3 during

this cycle.

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command.

SYNC

TAR

0000b

1111b

O

The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

O

1111b

(float)

The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

TAR

N/A

Figure 8. FWH Bus Write Waveforms

CLK

FWH4

FWH0-FWH3

START

1

IDSEL

1

ADDR

7

MSIZE

1

DATA

M

TAR

2

SYNC

1

TAR

2

Number of

clock cycles

AI08434B

15/53

M50FLW080A, M50FLW080B

Table 8. LPC Bus Read Field Definitions (1-Byte)

Clock

Clock Cycle

Number

LAD0- Memory

Cycle

Count

Field

Description

LAD3

I/O

On the rising edge of CLK with LFRAME Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a

LPC cycle.

1

2

1

START

0000b

I

Indicates the type of cycle and selects 1-byte reading. Bits

3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b

for read. Bit 0 is Don’t Care.

CYCTYPE

+ DIR

0100b

I

A 32-bit address is transferred, with the most significant

nibble first. A23-A31 must be set to 1. A22=1 for memory

access, and A22=0 for register access. Table 5. shows the

appropriate values for A21-A20.

3-10

8

ADDR

XXXX

1111b

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

11

12

1

TAR

I

1111b

(float)

The LPC Flash Memory takes control of LAD0-LAD3

during this cycle.

O

The LPC Flash Memory drives LAD0-LAD3 to 0101b

(short wait-sync) for two clock cycles, indicating that the

data is not yet available. Two wait-states are always

included.

13-14

15

2

1

WSYNC

RSYNC

0101b

0000b

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating that data will be available during the next clock

cycle.

Data transfer is two CLK cycles, starting with the least

significant nibble.

16-17

18

2

1

DATA

TAR

XXXX

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b to

indicate a turnaround cycle.

1111b

(float)

The LPC Flash Memory floats its outputs, the host takes

control of LAD0-LAD3.

19

TAR

N/A

Figure 9. LPC Bus Read Waveforms (1-Byte)

CLK

LFRAME

CYCTYPE

+ DIR

LAD0-LAD3

START

1

ADDR

8

TAR

2

SYNC

3

DATA

2

TAR

2

Number of

clock cycles

1

AI04429

16/53

M50FLW080A, M50FLW080B

Table 9. LPC Bus Write Field Definitions (1 Byte)

Clock

Cycle

Number Count

Clock

Cycle

LAD0-

LAD3

Memory

I/O

Field

Description

On the rising edge of CLK with LFRAME Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a LPC

cycle.

1

2

1

START

0000b

011Xb

I

CYCTY

PE +

DIR

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 1b for write. Bit 0 is don’t

care (X).

A 32-bit address is transferred, with the most significant

nibble first. A23-A31 must be set to 1. A22=1 for memory

access, and A22=0 for register access. Table 5. shows the

appropriate values for A21-A20.

3-10

8

ADDR

XXXX

I

Data transfer is two cycles, starting with the least significant

nibble.

11-12

13

2

1

DATA

TAR

XXXX

1111b

I

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

1111b

(float)

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle.

14

TAR

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command.

15

SYNC

TAR

0000b

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle.

16

O

1111b

(float)

The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

17

TAR

N/A

Figure 10. LPC Bus Write Waveforms (1 Byte)

CLK

LFRAME

CYCTYPE

+ DIR

LAD0-LAD3

START

1

ADDR

8

DATA

2

TAR

2

SYNC

1

TAR

2

Number of

clock cycles

1

AI04430

Table 10. A/A Mux Bus Operations

V

Operation

Bus Read

G

W

RP

DQ7-DQ0

Data Output

Data Input

Hi-Z

PP

V

IH

Don't Care

V or V

CC

IL

IH

V

IH

Bus Write

Output Disable

Reset

IL

PPH

V

IH

Don't Care

IH

V

IL

or V

V

or V

V

IL

Hi-Z

IH

IL

IH

17/53

M50FLW080A, M50FLW080B

COMMAND INTERFACE

All Bus Write operations to the device are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings, and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time to monitor

the progress or the result of the operation.

any Read Memory Array commands until the oper-

ation has completed.

For a multibyte read, in the FWH mode, the ad-

dress, that was transmitted with the command, will

be automatically aligned, according to the MSIZE

granularity. For example, if MSIZE=7, regardless

of any values that are provided for A6-A0, the first

output will be from the location for which A6-A0 are

all ‘0’s.

The Command Interface reverts to the Read mode

when power is first applied, or when exiting from

Reset. Command sequences must be followed ex-

actly. Any invalid combination of commands will be

ignored. See Table 11. for the available Command

Codes.

Read Status Register Command. The

Read

Status Register command is used to read the Sta-

tus Register. One Bus Write cycle is required to is-

sue the Read Status Register command. Once the

command is issued, subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued. See the section on the Status

Register for details on the definitions of the Status

Register bits.

Table 11. Command Codes

Hexa-

Command

decimal

Read Electronic Signature Command. The

Read Electronic Signature command is used to

read the Manufacturer Code and the Device Code.

One Bus Write cycle is required to issue the Read

Electronic Signature command. Once the com-

mand is issued, the Manufacturer Code and De-

vice Code can be read using conventional Bus

Read operations, and the addresses shown in Ta-

ble 12..

Alternative Program Setup, Double/

10h

Quadruple Byte Program Setup, Chip

Erase Confirm

20h

32h

Block Erase Setup

Sector Erase Setup

Program, Double/Quadruple Byte

Program Setup

40h

Table 12. Electronic Signature Codes

50h

70h

80h

90h

B0h

Clear Status Register

Read Status Register

Chip Erase Setup

1

Code

Data

Address

Manufacturer Code

...00000h

20h

M50FLW080A

M50FLW080B

80h

81h

Device Code

...00001h

Read Electronic Signature

Program/Erase Suspend

Note: 1. A22 should be ‘1’, and the ID lines and upper address bits

should be set according to the rules illustrated in Table 5.,

Table 6. and Table 8..

Program/Erase Resume, Block Erase

Confirm, Sector Erase Confirm

D0h

The device remains in this mode until another

command is issued. That is, subsequent Bus

Read operations continue to read the Manufactur-

er Code, or the Device Code, and not the Memory

Array.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time.

The Program command works by changing appro-

priate bits from ‘1’ to ‘0’. (It cannot change a bit

from ‘0’ back to ‘1’. Attempting to do so will not

modify the value of the bit. Only the Erase com-

mand can set bits back to ‘1’. and does so for all of

the bits in the block.)

Two Bus Write operations are required to issue the

Program command. The second Bus Write cycle

latches the address and data, and starts the Pro-

gram/Erase Controller.

FFh

Read Memory Array

The following commands are the basic commands

used to read from, write to, and configure the de-

vice. The following text descriptions should be

read in conjunction with Table 13..

Read Memory Array Command. The

Read

Memory Array command returns the device to its

Read mode, where it behaves like a ROM or

EPROM. One Bus Write cycle is required to issue

the Read Memory Array command and return the

device to Read mode. Once the command is is-

sued, the device remains in Read mode until an-

other command is issued. From Read mode, Bus

Read operations access the memory array.

If the Program/Erase Controller is executing a Pro-

gram or Erase operation, the device will not accept

18/53

M50FLW080A, M50FLW080B

Once the command is issued, subsequent Bus

Read operations read the value in the Status Reg-

ister. (See the section on the Status Register for

details on the definitions of the Status Register

bits.)

If the address falls in a protected block, the Pro-

gram operation will abort, the data in the memory

array will not be changed, and the Status Register

will indicate the error.

During the Program operation, the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands are ignored.

See Figure 22., for a suggested flowchart on using

the Program command. Typical Program times are

given in Table 18..

the contents of the Status Register. (See the sec-

tion on the Status Register for details on the defi-

nitions of the Status Register bits.)

During the Double/Quadruple Byte Program oper-

ation the memory will only accept the Read Status

register and Program/Erase Suspend commands.

All other commands are ignored.

Note that the Double/Quadruple Byte Program

command cannot change a bit set to ‘0’ back to ‘1’

and attempting to do so will not modify its value.

One of the erase commands must be used to set

all of the bits in the block to ‘1’.

See Figure 23., for a suggested flowchart on using

the Double/Quadruple Byte Program command.

Typical Double/Quadruple Byte Program times

are given in Table 18..

Quadruple Byte Program Command (A/A Mux

Interface). The Quadruple Byte Program Com-

mand is used to program four adjacent Bytes in

the memory array at a time. The four Bytes must

differ only for addresses A0 and A1. Programming

Chip Erase Command. The Chip Erase Com-

mand erases the entire memory array, setting all

of the bits to ‘1’. All previous data in the memory

array are lost. This command, though, is only

available under the A/A Mux interface.

should not be attempted when V_PPis not at V_PPH

.

Two Bus Write operations are required to issue the

command, and to start the Program/Erase Con-

troller. Once the command is issued, subsequent

Bus Read operations read the contents of the Sta-

tus Register. (See the section on the Status Reg-

ister for details on the definitions of the Status

Register bits.)

Erasing should not be attempted when V_PPis not

at V_PPH, otherwise the result is uncertain.

During the Chip Erase operation, the memory will

only accept the Read Status Register command.

All other commands are ignored.

See Figure 26., for a suggested flowchart on using

the Chip Erase command. Typical Chip Erase

times are given in Table 18..

Block Erase Command. The Block Erase com-

mand is used to erase a block, setting all of the bits

to ‘1’. All previous data in the block are lost.

Two Bus Write operations are required to issue the

command. The second Bus Write cycle latches the

block address and starts the Program/Erase Con-

troller. Once the command is issued, subsequent

Bus Read operations read the contents of the Sta-

tus Register. (See the section on the Status Reg-

ister for details on the definitions of the Status

Register bits.)

If the block, or if at least one sector of the block (for

the blocks that are split into sectors), is protected

(FWH/LPC only) then the Block Erase operation

will abort, the data in the block will not be changed,

and the Status Register will indicate the error.

Five Bus Write operations are required to issue the

command. The second, third and fourth Bus Write

cycles latch the respective addresses and data of

the first, second and third Bytes in the Program/

Erase Controller. The fifth Bus Write cycle latches

the address and data of the fourth Byte and starts

the Program/Erase Controller. Once the command

is issued, subsequent Bus Read operations read

the value in the Status Register. (See the section

on the Status Register for details on the definitions

of the Status Register bits.)

During the Quadruple Byte Program operation, the

memory will only accept the Read Status Register

and Program/Erase Suspend commands. All other

commands are ignored.

Note that the Quadruple Byte Program command

cannot change a bit set to ‘0’ back to ‘1’ and at-

tempting to do so will not modify its value. One of

the erase commands must be used to set all of the

bits in the block to ‘1’.

See Figure 24., for a suggested flowchart on using

the Quadruple Byte Program command. Typical

Quadruple Byte Program times are given in Table

18..

Double/Quadruple Byte Program Command

(FWH Mode). The Double/Quadruple Byte Pro-

gram Command can be used to program two/four

adjacent Bytes to the memory array at a time. The

two Bytes must differ only for address A0; the four

Bytes must differ only for addresses A0 and A1.

Two Bus Write operations are required to issue the

command. The second Bus Write cycle latches the

start address and two/four data Bytes and starts

the Program/Erase Controller. Once the command

is issued, subsequent Bus Read operations read

During the Block Erase operation the memory will

only accept the Read Status Register and Pro-

gram/Erase Suspend commands. All other com-

mands are ignored.

19/53

M50FLW080A, M50FLW080B

See Figure 27., for a suggested flowchart on using

the Block Erase command. Typical Block Erase

times are given in Table 18..

Sector Erase Command. The Sector Erase

command is used to erase a Uniform 4-KByte Sec-

tor, setting all of the bits to ‘1’. All previous data in

the sector are lost.

Two Bus Write operations are required to issue the

command. The second Bus Write cycle latches the

Sector address and starts the Program/Erase

Controller. Once the command is issued, subse-

quent Bus Read operations read the contents of

the Status Register. (See the section on the Status

Register for details on the definitions of the Status

Register bits.)

If the Sector is protected (FWH/LPC only), the

Sector Erase operation will abort, the data in the

Sector will not be changed, and the Status Regis-

ter will indicate the error.

Program/Erase Suspend Command. The Pro-

gram/Erase Suspend command is used to pause

the Program/Erase Controller during a program or

Sector/Block Erase operation. One Bus Write cy-

cle is required to issue the command.

Once the command has been issued, it is neces-

sary to poll the Program/Erase Controller Status

bit until the Program/Erase Controller has paused.

No other commands are accepted until the Pro-

gram/Erase Controller has paused. After the Pro-

gram/Erase Controller has paused, the device

continues to output the contents of the Status Reg-

ister until another command is issued.

During the polling period, between issuing the Pro-

gram/Erase Suspend command and the Program/

Erase Controller pausing, it is possible for the op-

eration to complete. Once the Program/Erase

Controller Status bit indicates that the Program/

Erase Controller is no longer active, the Program

Suspend Status bit or the Erase Suspend Status

bit can be used to determine if the operation has

completed or is suspended.

During Program/Erase Suspend, the Read Memo-

ry Array, Read Status Register, Read Electronic

Signature and Program/Erase Resume com-

mands will be accepted by the Command Inter-

face. Additionally, if the suspended operation was

Sector Erase or Block Erase then the program

command will also be accepted. However, it

should be noted that only the Sectors/Blocks not

being erased may be read or programmed correct-

ly.

During the Sector Erase operation the memory will

only accept the Read Status Register and Pro-

gram/Erase Suspend commands. All other com-

mands are ignored.

See Figure 27., for a suggested flowchart on using

the Sector Erase Command. Typical Sector Erase

times are given in Table 18..

Clear Status Register Command. The

Clear

Status Register command is used to reset Status

Register bits SR1, SR3, SR4 and SR5 to ‘0’. One

Bus Write is required to issue the command. Once

the command is issued, the device returns to its

previous mode, subsequent Bus Read operations

continue to output the data from the same area, as

before.

See Figure 25., and Figure 28., for suggested

flowcharts on using the Program/Erase Suspend

command. Typical times and delay durations are

given in Table 18..

Program/Erase Resume Command. The Pro-

gram/Erase Resume command can be used to re-

Once set, these Status Register bits remain set.

They do not automatically return to ‘0’, for exam-

ple, when a new program or erase command is is-

sued. If an error has occurred, it is essential that

any error bits in the Status Register are cleared, by

issuing the Clear Status Register command, be-

fore attempting a new program or erase com-

mand.

start the Program/Erase Controller after

a

Program/Erase Suspend has paused it. One Bus

Write cycle is required to issue the command.

Once the command is issued, subsequent Bus

Read operations read the contents of the Status

Register.

20/53

M50FLW080A, M50FLW080B

Table 13. Commands

Command

(1)

Bus Operations

3rd

1st

2nd

4th

5th

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read Memory

Read

Addr

Read

Data

(Read (Read (Read (Read (Read (Read

Addr2) Data2) Addr3) Data3) Addr4) Data4)

1+

X

FFh

(2,10,11)

Array

Read Status

Status

Reg

(Status

Reg)

(Status

Reg)

(Status

Reg)

1+

X

70h

X

(X)

(3,10)

Register

Read Electronic

90h or

98h

Sig

Addr

Signat

ure

(Sig

Addr)

(Signat

ure)

(Sig

Addr)

(Signat

ure)

(Sig

Addr)

(Signat

ure)

1+

(10)

Signature

Program / Multiple

40h or

10h

Prog

Addr

Prog

Data

Byte program

2

5

X

(4,9,11)

(FWH)

Quadruple Byte

Program

Prog

Data1

Prog

Data2

Prog

Data3

Prog

Data4

30h

A1

A2

A3

A4

(4,12)

(A/A Mux)

(4)

2

X

80h

20h

32h

X

10h

D0h

Chip Erase

(4)

BA

SA

Block Erase

(4)

Sector Erase

Clear Status

1

X

50h

B0h

D0h

(5)

Register

Program/Erase

(6)

suspend

Program/Erase

(7)

resume

1

X

00h

01h

60h

2Fh

C0h

(8)

Invalid reserved

Note: 1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read Electronic

Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles are WRITE.

BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC mode), and

A21 and A20 are set according to the rules shown in Table 5. (for LPC mode)

2. After a Read Memory Array command, read the memory as normal until another command is issued.

3. After a Read Status Register command, read the Status Register as normal until another command is issued.

4. After the erase and program commands read the Status Register until the command completes and another command is issued.

5. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.

6. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during Erase

Suspend) and Program/Erase Resume commands can be issued.

7. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status Register until

the Program/Erase Controller completes and the memory returns to Read Mode.

8. Do not use Invalid or Reserved commands.

9. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t Care. PD is

two or four Bytes depending on Msize code.

10. “1+” indicates that there is one write cycle, followed by any number of read cycles.

11. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read Operation

is all that is needed.

12. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.

21/53

M50FLW080A, M50FLW080B

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The bits in the Status Register convey specific in-

formation about the progress of the operation.

To read the Status Register, the Read Status Reg-

ister command can be issued. The Status Register

is automatically read after Program, Erase and

Program/Erase Resume commands are issued.

The Status Register can be read from any ad-

dress.

The text descriptions, below, should be read in

conjunction with Table 14., where the meanings of

the Status Register bits are summarized.

once the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive).

When the Erase Status bit is ‘0’, the memory has

successfully verified that the Sector/Block has

been erased correctly. When the Erase Status bit

is ‘1’, the Program/Erase Controller has applied

the maximum number of pulses to the Sector/

Block and still failed to verify that the Sector/Block

has been erased correctly.

Once the Erase Status bit is set to ‘1’, it can only

be reset to ‘0’ by a Clear Status Register com-

mand, or by a hardware reset. If it is set to ‘1’, it

should be reset before a new Program or Erase

command is issued, otherwise the new command

will appear to have failed, too.

Program Status (Bit SR4). This bit indicates if a

problem has occurred during the programming of

a byte. The Program Status bit should be read

once the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive).

When the Program Status bit is ‘0’, the memory

has successfully verified that the byte has been

programmed correctly. When the Program Status

bit is ‘1’, the Program/Erase Controller has applied

the maximum number of pulses to the byte and still

failed to verify that the byte has been programmed

correctly.

Program/Erase Controller Status (Bit SR7).

This bit indicates whether the Program/Erase Con-

troller is active or inactive. When the Program/

Erase Controller Status bit is ‘0’, the Program/

Erase Controller is active; when the bit is ‘1’, the

Program/Erase Controller is inactive.

The Program/Erase Controller Status is ‘0’ imme-

diately after a Program/Erase Suspend command

is issued, until the Program/Erase Controller paus-

es. After the Program/Erase Controller pauses,

the bit is ‘1’.

The end of a Program and Erase operation can be

found by polling the Program/Erase Controller

Status bit can be polled. The other bits in the Sta-

tus Register should not be tested until the Pro-

gram/Erase Controller has completed the

operation (and the Program/Erase Controller Sta-

tus bit is ‘1’).

After the Program/Erase Controller has completed

its operation, the Erase Status, Program Status,

V_PPStatus and Block/Sector Protection Status

bits should be tested for errors.

Erase Suspend Status (Bit SR6). This bit indi-

cates that an Erase operation has been suspend-

ed, and that it is waiting to be resumed. The Erase

Suspend Status should only be considered valid

when the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive). After a Pro-

gram/Erase Suspend command is issued, the

memory may still complete the operation rather

than entering the Suspend mode.

When the Erase Suspend Status bit is ‘0’, the Pro-

gram/Erase Controller is active or has completed

its operation. When the bit is ‘1’, a Program/Erase

Suspend command has been issued and the

memory is waiting for a Program/Erase Resume

command.

Once the Program Status bit is set to ‘1’, it can only

be reset to ‘0’ by a Clear Status Register com-

mand, or by a hardware reset. If it is set to ‘1’, it

should be reset before a new Program or Erase

command is issued, otherwise the new command

will appear to have failed, too.

V_PPStatus (Bit SR3). This bit indicates whether

an invalid voltage was detected on the V_PPpin at

the beginning of a Program or Erase operation.

The V_PPpin is only sampled at the beginning of

the operation. Indeterminate results can occur if

V_PPbecomes invalid during a Program or Erase

operation.

Once the V_PPStatus bit set to ‘1’, it can only be re-

set to ‘0’ by a Clear Status Register command, or

by a hardware reset. If it is set to ‘1’, it should be

reset before a new Program or Erase command is

issued, otherwise the new command will appear to

have failed, too.

Program Suspend Status (Bit SR2). This bit in-

dicates that a Program operation has been sus-

pended, and that it is waiting to be resumed. The

Program Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is ‘1’ (Program/Erase Controller inactive).

After a Program/Erase Suspend command is is-

sued, the memory may still complete the operation

instead of entering the Suspend mode.

When a Program/Erase Resume command is is-

sued, the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit SR5). This bit indicates if a

problem has occurred during the erasing of a Sec-

tor or Block. The Erase Status bit should be read

22/53

M50FLW080A, M50FLW080B

When the Program Suspend Status bit is ‘0’, the

Program/Erase Controller is active, or has com-

pleted its operation. When the bit is ‘1’, a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

When a Program/Erase Resume command is is-

sued, the Program Suspend Status bit returns to

‘0’.

Block/Sector Protection Status (Bit SR1). The

Block/Sector Protection Status bit can be used to

identify if the Program or Erase operation has tried

to modify the contents of a protected block or sec-

tor. When the Block/Sector Protection Status bit is

reset to ‘0’, no Program or Erase operations have

been attempted on protected blocks or sectors

since the last Clear Status Register command or

hardware reset. When the Block/Sector Protection

Status bit is ‘1’, a Program or Erase operation has

been attempted on a protected block or sector.

Once it is set to ‘1’, the Block/Sector Protection

Status bit can only be reset to ‘0’ by a Clear Status

Register command or by a hardware reset. If it is

set to ‘1’, it should be reset before a new Program

or Erase command is issued, otherwise the new

command will appear to have failed, too.

Using the A/A Mux Interface, the Block/Sector Pro-

tection Status bit is always ‘0’.

Reserved (Bit SR0). Bit 0 of the Status Register

is reserved. Its value should be masked.

Table 14. Status Register Bits

Operation

SR7

‘0’

SR6

SR5

‘0’

SR4

‘0’

SR3

‘0’

SR2

‘0’

SR1

‘0’

(1)

Program active

X

(1)

Program suspended

‘1

‘0’

‘1’

‘0’

X

(1)

Program completed successfully

‘1’

‘0’

X

(1)

Program failure due to V Error

‘1’

‘0’

‘1’

‘0’

PP

X

Program failure due to Block/Sector Protection

(FWH/LPC Interface only)

(1)

‘1’

‘0’

‘1’

‘0’

‘1’

X

(1)

Program failure due to cell failure

Erase active

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

X

‘0’

‘1’

‘0’

Erase suspended

Erase completed successfully

Erase failure due to V Error

PP

Erase failure due to Block/Sector Protection

(FWH/LPC Interface only)

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Erase failure due to failed cell(s) in block or sector

Note: 1. For Program operations during Erase Suspend, the SR6 bit is ‘1’, otherwise the SR6 bit is ‘0’.

23/53

M50FLW080A, M50FLW080B

FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION

REGISTERS

When the Firmware Hub Interface/Low Pin Count

is selected, several additional registers can be ac-

cessed. These registers control the protection sta-

tus of the Blocks/Sectors, read the General

Purpose Input pins and identify the memory using

the manufacturer code. See Table 15. for the

memory map of the Configuration Registers. The

Configuration registers are accessed directly with-

out using any specific command code. A single

Bus Write or Bus Read Operation, with the appro-

priate address (including A22=0), is all that is

needed.

write protected by the Lock Register, and may be

modified, unless it is write protected by some other

means.

If the Top Block Lock signal, TBL, is Low, V_IL, then

the Top Block (Block 15) is write protected, and

cannot be modified. Similarly, if the Write Protect

signal, WP, is Low, V_IL, then the Main Blocks

(Blocks 0 to 14) are write protected, and cannot be

modified. For details, see APPENDIX A. and Table

16..

After power-up, or reset, the Write Lock Bit is al-

ways set to ‘1’ (write-protected).

Lock Registers

Read Lock. The Read Lock bit determines

whether the contents of the Block/Sector can be

read (in Read mode). When the Read Lock Bit is

set, ‘1’, the Block/Sector is read protected – any

operation that attempts to read the contents of the

Block/Sector will read 00h instead. When the

Read Lock Bit is reset, ‘0’, read operations are al-

lowed in the Block/Sector, and return the value of

the data that had been programmed in the Block/

Sector.

The Lock Registers control the protection status of

the Blocks/Sectors. Each Block/Sector has its own

Lock Register. Three bits within each Lock Regis-

ter control the protection of each Block/Sector: the

Write Lock Bit, the Read Lock Bit and the Lock

Down Bit.

The Lock Registers can be read and written. Care

should be taken, though, when writing. Once the

Lock Down Bit is set, ‘1’, further modifications to

the Lock Register cannot be made until it is

cleared again by a reset or power-up.

After power-up, or reset, the Read Lock Bit is al-

ways reset to ‘0’ (not read-protected).

See Table 16. for details on the bit definitions of

the Lock Registers.

Lock Down. The Lock Down Bit provides a

mechanism for protecting software data from sim-

ple hacking and malicious attack. When the Lock

Down Bit is set, ‘1’, further modification to the

Write Lock, Read Lock and Lock Down Bits cannot

be performed. A reset, or power-up, is required be-

fore changes to these bits can be made. When the

Lock Down Bit is reset, ‘0’, the Write Lock, Read

Lock and Lock Down Bits can be changed.

Write Lock. The Write Lock Bit determines

whether the contents of the Block/Sector can be

modified (using the Program or Erase Command).

When the Write Lock Bit is set, ‘1’, the Block/Sec-

tor is write protected – any operations that attempt

to change the data in the Block/Sector will fail, and

the Status Register will report the error. When the

Write Lock Bit is reset, ‘0’, the Block/Sector is not

Table 15. Configuration Register Map

Memory

Address

Default

Value

Mnemonic

Register Name

Access

Lock Registers (For details, see APPENDIX A.)

Firmware Hub/Low Pin Count (FWH/LPC) General

Purpose Input Register

GPI_REG

FBC0100h

FBC0000h

N/A

20h

R

MANU_REG

Manufacturer Code Register

Note: In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address

bits should be set according to the rules shown in the ADDR field of Table 6. to Table 9..

24/53

M50FLW080A, M50FLW080B

Table 16. Lock Register Bit Definitions

(1)

Bit

Bit Name

Value

Function

7-3

Reserved

‘1’

‘0’

Bus Read operations in this Block or Sector always return 00h.

2

1

Read-Lock

Bus read operations in this Block or Sector return the Memory Array contents.

(Default value).

Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

to ‘0’ following a Reset (using RP or INIT) or after power-up.

‘1’

Lock-Down

Write-Lock

Read-Lock and Write-Lock can be changed by writing new values to them. (Default

value).

‘0’

‘1’

‘0’

Program and Erase operations in this Block or Sector will set an error in the Status

Register. The memory contents will not be changed. (Default value).

0

Program and Erase operations in this Block or Sector are executed and will modify

the Block or Sector contents.

Note: 1. Applies to the registers that are defined in Table 34. and Table 35..

Table 17. General Purpose Inputs Register Definition

(1)

Bit

Bit Name

Value

Function

7-5

Reserved

Input Pin GPI4 is at V

Input Pin GPI3 is at V

Input Pin GPI2 is at V

Input Pin GPI1 is at V

Input Pin GPI0 is at V

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

4

3

2

1

0

GPI4

GPI3

GPI2

GPI1

GPI0

Note: 1. Applies to the General Purpose Inputs Register (GPI-REG).

Firmware Hub/Low Pin Count (FWH/LPC)

General Purpose Input Register

The FWH/LPC General Purpose Input Register

holds the state of the General Purpose Input pins,

GPI0-GPI4. When this register is read, the state of

these pins is returned. This register is read-only.

Writing to it has no effect.

The signals on the FWH/LPC Interface General

Purpose Input pins should remain constant

throughout the whole Bus Read cycle.

Manufacturer Code Register

Reading the Manufacturer Code Register returns

the value 20h, which is the Manufacturer Code for

STMicroelectronics. This register is read-only.

Writing to it has no effect.

25/53

M50FLW080A, M50FLW080B

PROGRAM AND ERASE TIMES

The Program and Erase times are shown in Table

18..

Table 18. Program and Erase Times

(1)

Parameter

Interface

Test Condition

Min

Max Unit

Typ

10

Byte Program

200

µs

(3)

V

= 12V ± 5%

Double Byte Program

FWH

µs

PP

10

A/A Multiplexed

FWH

(4)

(5)

Quadruple Byte Program

200

µs

s

= 12V ± 5%

= V

5

0.1

Block Program

V

0.4

PP

CC

V

= 12V ± 5%

= V

0.4

0.5

0.75

1

4

PP

(2)

s

Sector Erase (4 KBytes)

V

5

PP

CC

= 12V ± 5%

= V

8

PP

Block Erase (64 KBytes)

Chip Erase

V

10

PP

CC

= 12V ± 5%

A/A Multiplexed

10

s

PP

(2)

5

µs

Program/Erase Suspend to Program pause

Program/Erase Suspend to Block Erase/

30

µs

(2)

Sector Erase pause

Note: 1. T = 25°C, V = 3.3V

A

CC

2. Sampled only, not 100% tested.

3. Time to program two Bytes.

4. Time to program four Bytes.

5. Time obtained executing the Quadruple Byte Program command.

26/53

M50FLW080A, M50FLW080B

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 19. Absolute Maximum Ratings

Symbol

T_STG

Parameter

Min.

Max.

Unit

°C

Storage Temperature

–65

150

1

T_LEAD

Lead Temperature during Soldering

°C

See note

2

V

+ 0.6

V_IO

–0.50

–0.6

V

CC

Input or Output range

V_CC

Supply Voltage

4

V

Program Voltage

13

PP

3

V_ESD

–2000

2000

Electrostatic Discharge Voltage (Human Body model)

®

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to V + 2V for

CC

less than 20ns during transitions.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

27/53

M50FLW080A, M50FLW080B

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 20., Table 21.

and Table 22.. Designers should check that the

operating conditions in their circuit match the oper-

ating conditions when relying on the quoted pa-

rameters.

Table 20. Operating Conditions

Symbol

Parameter

Min.

3.0

Max.

3.6

Unit

V

Supply Voltage

Ambient Operating Temperature

CC

T_A

–20

85

°C

Table 21. FWH/LPC Interface AC Measurement Conditions

Parameter

Value

Unit

Load Capacitance (C )

10

pF

ns

V

L

Input Rise and Fall Times

≤ 1.4

0.2 V and 0.6 V

Input Pulse Voltages

CC

0.4 V

Input and Output Timing Ref. Voltages

V

CC

Table 22. A/A Mux Interface AC Measurement Conditions

Parameter

Value

30

Unit

pF

ns

V

Load Capacitance (C )

L

Input Rise and Fall Times

≤ 10

0 to 3

1.5

Input Pulse Voltages

Input and Output Timing Ref. Voltages

V

Figure 11. FWH/LPC Interface AC Measurement I/O Waveforms

0.6 V

CC

0.4 V

CC

0.2 V

CC

Input and Output AC Testing Waveform

I

< I

I

> I

I

< I

O LO

O

LO

O

LO

Output AC Tri-state Testing Waveform

AI03404

28/53

M50FLW080A, M50FLW080B

Figure 12. A/A Mux Interface AC Measurement I/O Waveform

3V

0V

1.5V

AI01417

Figure 13. AC Measurement Load Circuit

V

DD

V

PP

V

DD

16.7kΩ

DEVICE

UNDER

TEST

C

L

16.7kΩ

0.1µF

C

includes JIG capacitance

L

AI08430

Table 23. Impedance

Symbol

Parameter

Test Condition

Min

Max

Unit

(1)

V

= 0V

Input Capacitance

Clock Capacitance

13

pF

C

IN

(1)

V

3

12

20

pF

nH

C

L

CLK

Recommended Pin

Inductance

(2)

Note: 1. Sampled only, not 100% tested.

2. See PCI Specification.

3. T = 25°C, f = 1MHz.

A

29/53

M50FLW080A, M50FLW080B

Table 24. DC Characteristics

Symbol

Parameter

Interface

FWH

Test Condition

Min

Max

Unit

V

0.5 V

V

+ 0.5

CC

V

Input High Voltage

IH

0.7 V

+ 0.3

A/A Mux

FWH/LPC

A/A Mux

FWH/LPC

V

CC

0.3 V

–0.5

-0.5

1.1

V

CC

V

Input Low Voltage

IL

0.8

V + 0.5

CC

V

V (INIT)

IH

INIT Input High Voltage

INIT Input Low Voltage

Input Leakage Current

V

V (INIT)

IL

0.2 V

CC

–0.5

V

(2)

0V ≤ V ≤ V

±10

200

µA

I

LI

IN

CC

IC, IDx Input Leakage

Current

(3)

I

LI2

IC, ID0, ID1, ID2, ID3 = V

CC

IC, IDx Input Pull Low

Resistor

R

20

100

kΩ

IL

0.9 V

FWH/LPC

A/A Mux

FWH/LPC

A/A Mux

I

= –500µA

= –100µA

= 1.5mA

= 1.8mA

V

CC

OH

V

Output High Voltage

OH

V

– 0.4

CC

I

OL

0.1 V

V

CC

V

Output Low Voltage

OL

I

OL

0.45

±10

3.6

V

I

LO

0V ≤ V

≤ V

OUT CC

Output Leakage Current

µA

V

PP1

V

Voltage

3

PP

V

Voltage

PP

V

11.4

1.8

12.6

2.3

V

PPH

(Fast Erase)

Lockout Voltage

(1)

V

LKO

CC

FWH4/LFRAME = 0.9V

CC

V

= V

CC

PP

I

Supply Current (Standby) FWH/LPC

100

µA

CC1

All other inputs 0.9V to 0.1V

CC

V

= 3.6V, f(CLK) = 33MHz

CC

FWH4/LFRAME = 0.1 V , V

=

CC

PP

V

CC

I

Supply Current (Standby) FWH/LPC

Supply Current

10

60

mA

CC2

All other inputs 0.9 V to 0.1 V

CC

V

= 3.6V, f(CLK) = 33MHz

CC

V

= V max, V = V

CC

PP

CC

I

(Any internal operation

active)

FWH/LPC

f(CLK) = 33MHz

= 0mA

CC3

I

OUT

I

G = V , f = 6MHz

IH

Supply Current (Read)

A/A Mux

20

mA

CC4

Supply Current

(Program/Erase)

(1)

Program/Erase Controller Active

I

CC5

V

Supply Current

PP

I

V

> V

400

µA

PP

CC

(Read/Standby)

= V

40

15

mA

PP

CC

V

Supply Current

PP

(1)

PP1

I

(Program/Erase active)

V

= 12V ± 5%

PP

Note: 1. Sampled only, not 100% tested.

2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.

3. ID0 and ID1 are RFU in LPC mode.

30/53

M50FLW080A, M50FLW080B

Figure 14. FWH/LPC Interface Clock Waveform

tCYC

tHIGH

tLOW

0.6 V

CC

0.5 V

CC

0.4 V

,

CC p-to-p

(minimum)

0.4 V

CC

0.3 V

CC

0.2 V

CC

AI03403

Table 25. FWH/LPC Interface Clock Characteristics

Symbol

Parameter

Test Condition

Value

Unit

(1)

t

Min

30

ns

CYC

CLK Cycle Time

t

CLK High Time

CLK Low Time

Min

Max

11

1

ns

HIGH

t

LOW

V/ns

CLK Slew Rate

peak to peak

4

Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed

by design rather than tested. Refer to PCI Specification.

31/53

M50FLW080A, M50FLW080B

Figure 15. FWH/LPC Interface AC Signal Timing Waveforms

CLK

tCHQV

tCHQZ

tDVCH

tCHDX

tCHQX

FWH0-FWH3/

LAD0-LAD3

VALID

tCHFH

tFLCH

FWH4

VALID

OUTPUT DATA

START CYCLE

FLOAT OUTPUT DATA

VALID INPUT DATA

AI09700

Table 26. FWH/LPC Interface AC Signal Timing Characteristics

PCI

Symbol

Parameter

Value

Unit

Symbol

Min

2

ns

t

CLK to Data Out

CLK to Active

CHQV

val

Max

11

(1)

t

Min

Max

Min

2

28

7

ns

t

on

CHQX

(Float to Active Delay)

CLK to Inactive

(Active to Float Delay)

t

CHQZ

off

t

AVCH

(2)

t

su

Input Set-up Time

DVCH

t

CHAX

(2)

t

h

Min

0

ns

Input Hold Time

t

CHDX

t

Input Set-up time on FWH4

Input Hold time on FWH4

Min

10

5

ns

FLCH

t

CHFH

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-

ification.

2. Applies to all inputs except CLK and FWH4.

32/53

M50FLW080A, M50FLW080B

Figure 16. Reset AC Waveforms

RP, INT

tPLPH

tPHWL, tPHGL, tPHFL

W, G, FWH4/LFRAME

Ai09705

Table 27. Reset AC Characteristics

Symbol

Parameter

Test Condition

Value

100

50

Unit

ns

t

RP or INIT Reset Pulse Width

Min

PLPH

(1)

Rising edge only

mV/ns

RP or INIT Slew Rate

RP or INIT High to FWH4/

LFRAME Low

t

FWH/LPC Interface only

Min

30

50

µs

PHFL

t

RP High to Write Enable or Output

Enable Low

PHWL

A/A Mux Interface only

t

PHGL

Note: 1. See Chapter 4 of the PCI Specification.

33/53

M50FLW080A, M50FLW080B

Figure 17. A/A Mux Interface Read AC Waveforms

tAVAV

A0-A10

ROW ADDR VALID COLUMN ADDR VALID

NEXT ADDR VALID

tAVCL

tAVCH

tCLAX

tCHAX

RC

G

tCHQV

tGLQV

tGLQX

tGHQZ

tGHQX

VALID

DQ0-DQ7

W

tPHAV

RP

AI03406

Table 28. A/A Mux Interface Read AC Characteristics

Symbol

Parameter

Read Cycle Time

Test Condition

Value

Unit

t

Min

Max

250

50

ns

AVAV

t

Row Address Valid to RC Low

RC Low to Row Address Transition

Column Address Valid to RC high

RC High to Column Address Transition

RC High to Output Valid

AVCL

t

50

CLAX

t

50

AVCH

t

50

CHAX

(1)

150

t

CHQV

(1)

Output Enable Low to Output Valid

Max

50

ns

t

GLQV

t

RP High to Row Address Valid

Min

Max

Min

1

0

µs

ns

PHAV

t

Output Enable Low to Output Transition

Output Enable High to Output Hi-Z

Output Hold from Output Enable High

GLQX

50

0

GHQZ

GHQX

t

Note: 1. G may be delayed up to t

– t

GLQV

after the rising edge of RC without impact on t

.

CHQV

34/53

M50FLW080A, M50FLW080B

Figure 18. A/A Mux Interface Write AC Waveforms

Write erase or

program setup

Write erase confirm or Automated erase

valid address and data or program delay

Read Status

Register Data

Ready to write

another command

A0-A10

RC

R1

C1

R2

C2

tCLAX

tAVCH

tAVCL

tCHAX

tWHWL

tWLWH

tCHWH

W

G

tVPHWH

tWHGL

tQVVPL

V

PP

tDVWH

tWHDX

DQ0-DQ7

D

VALID SRD

IN1

IN2

AI04185

Table 29. A/A Mux Interface Write AC Characteristics

Symbol

Parameter

Test Condition

Value

100

50

Unit

t

Write Enable Low to Write Enable High

Data Valid to Write Enable High

Write Enable High to Data Transition

Row Address Valid to RC Low

Min

ns

WLWH

t

DVWH

t

5

WHDX

t

50

AVCL

t

RC Low to Row Address Transition

Column Address Valid to RC High

RC High to Column Address Transition

Write Enable High to Write Enable Low

RC High to Write Enable High

50

CLAX

t

50

AVCH

t

50

CHAX

t

100

50

WHWL

t

CHWH

(1)

V

PP

High to Write Enable High

100

t

VPHWH

t

Write Enable High to Output Enable Low

Write Enable High to RB Low

Min

30

0

ns

WHGL

t

WHRL

(1,2)

QVVPL

Output Valid, RB High to V Low

Min

0

ns

t

PP

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

35/53

M50FLW080A, M50FLW080B

PACKAGE MECHANICAL

Figure 19. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline

D

A1

D1

A2

1 N

B1

e

E2

E3

E1 E

F

B

0.51 (.020)

E2

1.14 (.045)

D3

A

R

CP

D2

PLCC-A

Note: Drawing is not to scale.

36/53

M50FLW080A, M50FLW080B

Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

3.56

2.41

–

Typ

Max

0.140

0.095

–

A

A1

A2

B

3.18

0.125

0.060

0.015

0.013

0.026

1.53

0.38

0.33

0.53

0.81

0.10

12.57

11.51

5.66

–

0.021

0.032

0.004

0.495

0.453

0.223

–

B1

CP

D

0.66

12.32

11.35

4.78

–

0.485

0.447

0.188

–

D1

D2

D3

E

7.62

0.300

14.86

13.89

6.05

–

15.11

14.05

6.93

–

0.585

0.547

0.238

–

0.595

0.553

0.273

–

E1

E2

E3

e

10.16

1.27

0.400

0.050

–

F

0.00

–

0.13

–

0.000

–

0.005

–

R

0.89

32

0.035

32

N

37/53

M50FLW080A, M50FLW080B

Figure 20. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Note: Drawing is not to scale.

A1

α

L

Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

5

Typ

Max

0.0472

0.0059

0.0413

5

A

A1

A2

α

0.050

0.950

0

0.0020

0.0374

0

B

0.170

0.100

0.270

0.210

0.100

14.200

12.500

–

0.0067

0.0039

0.0106

0.0083

0.0039

0.5591

0.4921

–

C

CP

D

13.800

12.300

–

0.5433

0.4843

–

D1

e

0.500

32

0.0197

32

E

7.900

0.500

8.100

0.700

0.3110

0.0197

0.3189

0.0276

L

N

38/53

M50FLW080A, M50FLW080B

Figure 21. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Note: Drawing is not to scale.

A1

α

L

Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.100

20.200

18.500

–

Typ

Max

0

A

A1

A2

B

0.050

0.950

0.170

0.100

0

C

0

CP

D

0

19.800

18.300

–

1

–

0

1

D1

e

1

0.500

0

–

E

9.900

0.500

0

10.100

0.700

5

0

L

0

α

5

N

40

39/53

M50FLW080A, M50FLW080B

PART NUMBERING

Table 33. Ordering Information Scheme

Example:

M50FLW080

A

K

5

T

G

Device Type

M50 = Flash Memory for PC BIOS

Architecture

FL = Firmware Hub/Low Pin Count Interface

Operating Voltage

W = V = 3.0 to 3.6V

CC

Device Function

080 = 8 Mbit (x8), Uniform Blocks and Sectors

Array Matrix

A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors

B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors

Package

K = PLCC32

NB = TSOP32: 8 x 14mm

N = TSOP40: 10 x 20mm

Device Grade

5 = Temperature range –20 to 85 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

blank = Standard SnPb plating

G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free

2

3

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

40/53

M50FLW080A, M50FLW080B

APPENDIX A. BLOCK AND SECTOR ADDRESS TABLE

Table 34. M50FLW080A Block, Sector and Lock

Register Addresses

Block

Size

(KByte)

Block Sector

No and Size

Type (KByte)

Address

Range

Sector Register

No

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Address

FBEF002

FBEE002

FBED002

FBEC002

FBEB002

FBEA002

FBE9002

FBE8002

FBE7002

FBE6002

FBE5002

FBE4002

FBE3002

FBE2002

FBE1002

FBE0002

Block

Size

Block Sector

No and Size

Type (KByte)

Address

Range

Sector Register

No

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

Address

FBFF002

FBFE002

FBFD002

FBFC002

FBFB002

FBFA002

FBF9002

FBF8002

FBF7002

FBF6002

FBF5002

FBF4002

FBF3002

FBF2002

FBF1002

FBF0002

EF000h-

EFFFFh

(KByte)

4

FF000h-

FFFFFh

4

EE000h-

EEFFFh

FE000h-

FEFFFh

ED000h-

EDFFFh

FD000h-

FDFFFh

EC000h-

ECFFFh

FC000h-

FCFFFh

EB000h-

EBFFFh

FB000h-

FBFFFh

EA000h-

EAFFFh

FA000h-

FAFFFh

E9000h-

E9FFFh

F9000h-

F9FFFh

E8000h-

E8FFFh

4

14

64

F8000h-

F8FFFh

(Main)

4

E7000h-

E7FFFh

4

15

(Top)

64

F7000h-

F7FFFh

4

E6000h-

E6FFFh

4

F6000h-

F6FFFh

4

E5000h-

E5FFFh

F5000h-

F5FFFh

E4000h-

E4FFFh

F4000h-

F4FFFh

E3000h-

E3FFFh

F3000h-

F3FFFh

E2000h-

E2FFFh

F2000h-

F2FFFh

E1000h-

E1FFFh

F1000h-

F1FFFh

E0000h-

E0FFFh

F0000h-

F0FFFh

41/53

M50FLW080A, M50FLW080B

Block

Size

(KByte)

Block Sector

No and Size

Type (KByte)

Block

Size

(KByte)

Block Sector

No and Size

Type (KByte)

Address

Range

Sector Register

No

Address

Range

Sector Register

Address

FBD0002

FBC0002

FBB0002

FBA0002

FB90002

FB80002

FB70002

FB60002

FB50002

FB40002

FB30002

FB20002

FB10002

No

15

14

13

12

11

10

9

Address

FB0F002

FB0E002

FB0D002

FB0C002

FB0B002

FB0A002

FB09002

FB08002

FB07002

FB06002

FB05002

FB04002

FB03002

FB02002

FB01002

FB00002

D0000h-

13

0F000h-

0FFFFh

64

4

DFFFFh (Main)

C0000h- 12

0E000h-

0EFFFh

CFFFFh (Main)

B0000h- 11

0D000h-

0DFFFh

BFFFFh (Main)

A0000h- 10

0C000h-

0CFFFh

AFFFFh (Main)

90000h-

9

0B000h-

0BFFFh

9FFFFh (Main)

80000h-

8

0A000h-

0AFFFh

8FFFFh (Main)

70000h-

7

09000h-

09FFFh

7FFFFh (Main)

60000h-

6

08000h-

08FFFh

4

8

6FFFFh (Main)

0

64

(Main)

50000h-

5

07000h-

07FFFh

4

7

5FFFFh (Main)

40000h-

4

06000h-

06FFFh

4

6

4FFFFh (Main)

30000h-

3

05000h-

05FFFh

5

3FFFFh (Main)

20000h-

2

04000h-

04FFFh

4

2FFFFh (Main)

10000h-

1

03000h-

03FFFh

3

1FFFFh (Main)

02000h-

02FFFh

2

01000h-

01FFFh

1

00000h-

00FFFh

0

Note: In LPC mode, a most significant nibble, F, must be added to

the memory address. For all registers, A22=0, and the re-

maining address bits should be set according to the rules

shown in the ADDR field of Table 6. to Table 9..

42/53

M50FLW080A, M50FLW080B

Table 35. M50FLW080B Block, Sector and Lock

Register Addresses

Block

Size

(KByte)

Block Sector

Noand Size

Type (KByte)

Address

Range

Sector Register

No

Address

FBE0002

FBD0002

FBC0002

FBB0002

FBA0002

FB90002

FB80002

FB70002

FB60002

FB50002

FB40002

FB30002

FB20002

Block

Size

Block Sector

Noand Size

Type (KByte)

Address

Range

Sector Register

No

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

Address

FBFF002

FBFE002

FBFD002

FBFC002

FBFB002

FBFA002

FBF9002

FBF8002

FBF7002

FBF6002

FBF5002

FBF4002

FBF3002

FBF2002

FBF1002

FBF0002

E0000h-

14

(KByte)

64

EFFFFh (Main)

FF000h-

FFFFFh

4

D0000h- 13

DFFFFh (Main)

C0000h- 12

FE000h-

FEFFFh

CFFFFh (Main)

FD000h-

FDFFFh

B0000h- 11

BFFFFh (Main)

A0000h- 10

FC000h-

FCFFFh

AFFFFh (Main)

FB000h-

FBFFFh

90000h-

9

9FFFFh (Main)

FA000h-

FAFFFh

80000h-

8

8FFFFh (Main)

F9000h-

F9FFFh

70000h-

7

7FFFFh (Main)

F8000h-

F8FFFh

4

60000h-

6

15

(Top)

6FFFFh (Main)

64

F7000h-

F7FFFh

4

50000h-

5

5FFFFh (Main)

F6000h-

F6FFFh

4

40000h-

4

4FFFFh (Main)

F5000h-

F5FFFh

30000h-

3

3FFFFh (Main)

F4000h-

F4FFFh

20000h-

2

2FFFFh (Main)

F3000h-

F3FFFh

F2000h-

F2FFFh

F1000h-

F1FFFh

F0000h-

F0FFFh

43/53

M50FLW080A, M50FLW080B

Block

Size

(KByte)

Block Sector

Noand Size

Type (KByte)

Block

Size

(KByte)

Block Sector

Noand Size

Type (KByte)

Address

Range

Sector Register

Address

Range

Sector Register

No

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Address

FB1F002

FB1E002

FB1D002

FB1C002

FB1B002

FB1A002

FB19002

FB18002

FB17002

FB16002

FB15002

FB14002

FB13002

FB12002

FB11002

FB10002

No

15

14

13

12

11

10

9

Address

FB0F002

FB0E002

FB0D002

FB0C002

FB0B002

FB0A002

FB09002

FB08002

FB07002

FB06002

FB05002

FB04002

FB03002

FB02002

FB01002

FB00002

1F000h-

1FFFFh

0F000h-

0FFFFh

4

1E000h-

1EFFFh

0E000h-

0EFFFh

1D000h-

1DFFFh

0D000h-

0DFFFh

1C000h-

1CFFFh

0C000h-

0CFFFh

1B000h-

1BFFFh

0B000h-

0BFFFh

1A000h-

1AFFFh

0A000h-

0AFFFh

19000h-

19FFFh

09000h-

09FFFh

18000h-

18FFFh

08000h-

08FFFh

4

8

1

0

64

(Main)

17000h-

17FFFh

07000h-

07FFFh

4

7

16000h-

16FFFh

06000h-

06FFFh

4

6

15000h-

15FFFh

05000h-

05FFFh

5

14000h-

14FFFh

04000h-

04FFFh

4

13000h-

13FFFh

03000h-

03FFFh

3

12000h-

12FFFh

02000h-

02FFFh

2

11000h-

11FFFh

01000h-

01FFFh

1

10000h-

10FFFh

00000h-

00FFFh

0

Note: In LPC mode, a most significant nibble, F, must be added to

the memory address. For all registers, A22=0, and the re-

maining address bits should be set according to the rules

shown in the ADDR field of Table 6. to Table 9..

44/53

M50FLW080A, M50FLW080B

APPENDIX B. FLOWCHARTS AND PSEUDO CODES

Figure 22. Program Flowchart and Pseudo Code

Start

Program command:

– Write 40h or 10h

Write 40h or 10h

– Write Address and Data

(memory enters read status state after

the Program command)

Write Address

and Data

do:

NO

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

Read Status

Register

Suspend

YES

– Enter suspend program loop

NO

Suspend

Loop

SR7 = 1

YES

V

Invalid

Error (1, 2)

If SR3 = 1,

– Enter the "V

PP

SR3 = 0

YES

invalid" error handler

PP

Program

Error (1, 2)

If SR4 = 1,

– Enter the "Program error" error handler

SR4 = 0

YES

FWH/LPC

Interface

Only

If SR1 = 1,

– Enter the "Program to protected

block/sector" error handler

Program to Protected

Block/Sector Error (1, 2)

SR1 = 0

YES

End

AI09092

Note: 1. A Status check of SR1 (Protected Block/Sector), SR3 (V invalid) and SR4 (Program Error) can be made after each Program op-

PP

eration by following the correct command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

45/53

M50FLW080A, M50FLW080B

Figure 23. Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only)

Start

Write 40h or 10h

Write Start Address

and 2/4 Data Bytes ⁽³⁾

Double/Quadruple Byte Program command:

– write 40h or 10h

– write Start Address and 2/4 Data Bytes ⁽³⁾

(memory enters read status state after

the Double/Quadruple Byte Program command)

do:

NO

– Read Status Register

Read Status

– If SR7=0 and a Program/Erase Suspend

Register

command has been executed

– SR7 is set to 1

Suspend

YES

– Enter suspend program loop

NO

Suspend

Loop

SR7 = 1

YES

V

Invalid

Error (1, 2)

If SR3 = 1, V invalid error:

PP

SR3 = 0

YES

– error handler

Program

Error (1, 2)

If SR4 = 1, Program error:

– error handler

SR4 = 0

YES

Program to Protected

Block/Sector Error (1, 2)

If SR1 = 1,

SR1 = 0

YES

End

Program to protected block/sector error:

– error handler

AI09093

Note: 1. A Status check of SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation by following the correct

PP

command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. A0 and/or A1 are treated as Don’t Care (A0 for Double Byte Program and A1-A0 for Quadruple Byte Program).

For Double Byte Program: Starting at the Start Address, the first data Byte is programmed at the even address, and the second at

the odd address.

For Quadruple Byte Program: Starting at the Start Address, the first data Byte is programmed at the address that has A1-A0 at 00,

the second at the address that has A1-A0 at 01, the third at the address that has A1-A0 at 10, and the fourth at the address that

has A1-A0 at 11.

46/53

M50FLW080A, M50FLW080B

Figure 24. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

& Data 1 ⁽³⁾

Quadruple Byte Program command:

– write 30h

– write Address 1 & Data 1 ⁽³⁾

– write Address 2 & Data 2 ⁽³⁾

– write Address 3 & Data 3 ⁽³⁾

Write Address 2

& Data 2 ⁽³⁾

– write Address 4 & Data 4 ⁽³⁾

(memory enters read status state after

the Quadruple Byte Program command)

Write Address 3

& Data 3 ⁽³⁾

Write Address 4

& Data 4 ⁽³⁾

do:

NO

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

Read Status

Register

Suspend

YES

– Enter suspend program loop

NO

Suspend

Loop

SR7 = 1

YES

V

Invalid

Error (1, 2)

If SR3 = 1, V invalid error:

PP

SR3 = 0

YES

– error handler

Program

Error (1, 2)

If SR4 = 1, Program error:

– error handler

SR4 = 0

YES

End

AI09099

Note: 1. A Status check of SR3 (V invalid) and SR4 (Program Error) can be made after each Program operation by following the correct

PP

command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.

47/53

M50FLW080A, M50FLW080B

Figure 25. Program Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

– write 70h

Write 70h

do:

– read Status Register

Read Status

Register

NO

SR7 = 1

YES

while SR7 = 0

SR2 = 1

YES

Program Complete

If SR2 = 0 Program completed

Write a read

Command

Read data from

another address

Program/Erase Resume command:

– write D0h to resume the program

– if the Program operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Program Continues

AI08426B

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.

2. Any address within the bank can equally be used.

48/53

M50FLW080A, M50FLW080B

Figure 26. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Chip Erase command:

– write 80h

Write 80h

– write 10h

(memory enters read Status Register after

the Chip Erase command)

Write 10h

do:

– read Status Register

Read Status

Register

NO

while SR7 = 0

SR7 = 1

YES

NO

V

Invalid

If SR3 = 1, V invalid error:

PP

Error (1)

SR3 = 0

YES

– error handler

Command

Sequence Error (1)

If SR4, SR5 = 1, Command sequence error:

– error handler

SR4, SR5 = 0

YES

If SR5 = 1, Erase error:

– error handler

SR5 = 0

Erase Error (1)

YES

End

AI08428B

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

49/53

M50FLW080A, M50FLW080B

Figure 27. Sector/Block Erase Flowchart and Pseudo Code

Start

Block/Sector Erase command:

– Write 20h/32h

Write 20h/32h

– Write Block/Sector Address and D0h

(memory enters read Status Register after

the Block/Sector Erase command)

Write Block/Sector

Address and D0h

do:

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

NO

Read Status

Register

Suspend

YES

– Enter suspend program loop

NO

Suspend

Loop

SR7 = 1

YES

NO

V

Invalid

Error (1)

If SR3 = 1,

– Enter the "V invalid" error handler

PP

SR3 = 0

YES

PP

Command

Sequence Error (1)

If SR4, SR5 = 1,

– Enter the "Command sequence"error handler

SR4, SR5 = 0

YES

If SR5 = 1,

– Enter the "Erase Error" error handler

SR5 = 0

YES

Erase Error (1)

FWH/LPC

Interface

Only

If SR1 = 1,

Erase to Protected

Block/Sector Error (1)

SR1 = 0

– Enter the "Erase to protected Block/Sector"

error handler

YES

End

AI09094

Note: 1. If the Block Erase command is used on a block that is split into 4KByte sectors, each of the 16 sectors of the block should be un-

locked before performing the erase operation.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

50/53

M50FLW080A, M50FLW080B

Figure 28. Erase Suspend and Resume Flowchart and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

Write 70h

– write 70h

do:

Read Status

Register

– read Status Register

NO

SR7 = 1

YES

while SR7 = 0

SR6 = 1

YES

Erase Complete

If SR6 = 0, Erase completed

Read data from

another block/sector

or

Program

Program/Erase Resume command:

– write D0h to resume erase

– if the Erase operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Erase Continues

AI08429B

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M50FLW080A, M50FLW080B

REVISION HISTORY

Table 36. Document Revision History

Date

Version

0.1

Revision Details

02-Feb-2004

21-Apr-2004

24-May-2004

18-Aug-2004

21-Jun-2005

First Issue

0.2

TSOP32 package added

First public release

1.0

2.0

Pins 2 and 5 of the TSOP32 Connections illustration corrected

Datasheet status changed to Full Datasheet.

3.0

52/53

M50FLW080A, M50FLW080B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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www.st.com

53/53


型号：	M50FLW080B
厂家：	ST
描述：	8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory 8兆位（ 13× 64K字节块+ 3 ×16× 4K字节扇区）， 3V供应固件集线器/低引脚数闪存闪存
文件：	总53页 (文件大小：945K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M50FLW080B [STMICROELECTRONICS]

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