M50FW016N5T_技术文档

M50FW016

16 Mbit (2Mb x8, Uniform Block)

3V Supply Firmware Hub Flash Memory

PRELIMINARY DATA

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Package

–

V_CC= 3 V to 3.6 V for Program, Erase and

Read Operations

V_PP= 12 V for Fast Program and Fast

Erase

■

TWO INTERFACES

–

Firmware Hub (FWH) Interface for

embedded operation with PC Chipsets

–

Address/Address Multiplexed (A/A Mux)

Interface for programming equipment

compatibility

■

FIRMWARE HUB (FWH) HARDWARE

INTERFACE MODE

TSOP40 (N)

10 x 20mm

–

5 Signal Communication Interface

supporting Read and Write Operations

Hardware Write Protect Pins for Block

Protection

Register Based Read and Write

Protection

5 Additional General Purpose Inputs for

platform design flexibility

Multi-byte Read Operation (4/16/128-

byte)

Synchronized with 33 MHz PCI clock

■

BYTE PROGRAMMING TIME

–

Single Byte Mode: 10µs (typical)

Quadruple Byte Mode: 2.5µs (typical)

■

32 UNIFORM 64 Kbyte MEMORY BLOCKS

PROGRAM and ERASE SUSPEND

–

Read other Blocks during Program/Erase

Suspend

–

Program other Blocks during Erase

Suspend

■

FOR USE in PC BIOS APPLICATIONS

ELECTRONIC SIGNATURE

–

Manufacturer Code: 20h

Device Code: 2Eh

July 2004

1/45

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M50FW016

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram (FWH Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Input/Output Communications (FWH0-FWH3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

_CCSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V_PPOptional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

FWH Bus Write.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/45

M50FW016

Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 5. FWH Bus Read Waveforms (Single Byte Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 5. FWH Bus Write Field Definitions (Single Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. FWH Bus Write Waveforms (Single Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. FWH Bus Write Field Definitions (Quadruple Byte Program) . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. FWH Bus Write Waveforms (Quadruple Byte Program) . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Quadruple Byte Program Command (A/A Mux Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Quadruple Byte Program Command (FWH Mode).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

V

_PPStatus (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 22

Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3/45

M50FW016

Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Multi-Byte Read/Write Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. General Purpose Input Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 17. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 9. A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 21. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 22. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 23. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 12.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 13.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 14.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 26. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 15.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . . 35

Table 27. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. . 35

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 28. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

APPENDIX A.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 38

Figure 18.Quadruple Byte Program Flowchart and Pseudo Code (FWH Interface Only) . . . . . . . . 39

Figure 19.Program Suspend and Resume Flowchart, and Pseudo Code. . . . . . . . . . . . . . . . . . . . 40

4/45

M50FW016

Figure 20.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 41

Figure 21.Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 22.Erase Suspend and Resume Flowchart, and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 43

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5/45

M50FW016

SUMMARY DESCRIPTION

The M50FW016 is a 16 Mbit (2Mb x8) non-volatile

memory that can be read, erased and

reprogrammed. These operations can be

performed using a single low voltage (3.0 to 3.6V)

supply. For fast programming and fast erasing, an

optional 12V power supply can be used to reduce

the programming and the erasing times.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Blocks can be

protected individually to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are

written to the Command Interface of the memory.

An on-chip Program/Erase Controller simplifies

the process of programming or erasing the

memory by taking care of all of the special

operations that are required to update the memory

contents. The end of a program or erase operation

can be detected and any error conditions

identified. The command set required to control

the memory is consistent with JEDEC standards.

Two different bus interfaces are supported by the

memory. The primary interface, the Firmware Hub

(or FWH) Interface, uses Intel’s proprietary FWH

protocol. This has been designed to remove the

need for the ISA bus in current PC Chipsets; the

M50FW016 acts as the PC BIOS on the Low Pin

Count bus for these PC Chipsets.

The secondary interface, the Address/Address

Multiplexed (or A/A Mux) Interface, is designed to

be compatible with current Flash Programmers for

production line programming prior to fitting to a PC

Motherboard.

The memory is offered in TSOP40 (10 x 20mm)

package and it is supplied with all the bits erased

(set to ’1’).

Figure 2. Logic Diagram (FWH Interface)

Table 1. Signal Names (FWH Interface)

FWH0-FWH3

FWH4

ID0-ID3

FGPI0-FGPI4

IC

Input/Output Communications

Input Communication Frame

Identification Inputs

General Purpose Inputs

Interface Configuration

Interface Reset

V

CC PP

4

5

4

FWH0-

FWH3

ID0-ID3

FGPI0-

FGPI4

RP

WP

INIT

CPU Reset

FWH4

CLK

IC

TBL

M50FW016

CLK

Clock

TBL

Top Block Lock

WP

Write Protect

RP

Reserved for Future Use. Leave

disconnected.

RFU

INIT

V

Supply Voltage

CC

Optional Supply Voltage for Fast

Program and Fast Erase Operations

V

PP

SS

V

SS

AI04462

Ground

NC

Not Connected Internally

Reserved for Future Use

RFU

6/45

M50FW016

Figure 3. Logic Diagram (A/A Mux Interface)

Table 2. Signal Names (A/A Mux Interface)

IC

Interface Configuration

Address Inputs

A0-A10

V

CC PP

DQ0-DQ7

Data Inputs/Outputs

Output Enable

G

11

8

DQ0-DQ7

A0-A10

W

Write Enable

RC

RB

RP

Row/Column Address Select

Ready/Busy Output

Interface Reset

RC

IC

M50FW016

RB

V

Supply Voltage

G

CC

Optional Supply Voltage for Fast

Program and Fast Erase

Operations

W

V

PP

RP

V

Ground

SS

NC

Not Connected Internally

Reserved for Future Use

V

SS

AI04463

RFU

Figure 4. TSOP Connections

NC

1

40

V

SS

IC (V

)

IC (V )

IL

RFU

FWH4

INIT

RFU

IH

NC

A10

NC

RC

NC

W

NC

G

NC

RFU

RB

NC

DQ7

DQ6

DQ5

DQ4

FGPI4

NC

CLK

V

10

11

31

30

V

CC

SS

CC

SS

M50FW016

V

PP

RP

PP

RP

NC

A9

A8

A7

A6

A5

A4

FWH3

FWH2

FWH1

FWH0

ID0

DQ3

DQ2

DQ1

DQ0

A0

NC

FGPI3

FGPI2

FGPI1

FGPI0

WP

ID1

A1

ID2

A2

TBL

20

21

ID3

A3

AI04464b

7/45

M50FW016

SIGNAL DESCRIPTIONS

There are two different bus interfaces available on

this part. The active interface is selected before

power-up or during Reset using the Interface Con-

figuration Pin, IC.

The signals for each interface are discussed in the

Firmware Hub (FWH) Signal Descriptions section

and the Address/Address Multiplexed (A/A Mux)

Signal Descriptions section below. The supply sig-

nals are discussed in the Supply Signal Descrip-

tions section below.

Interface Configuration (IC). The Interface Con-

figuration input selects whether the Firmware Hub

(FWH) or the Address/Address Multiplexed (A/A

Mux) Interface is used. The chosen interface must

be selected before power-up or during a Reset

and, thereafter, cannot be changed. The state of

the Interface Configuration, IC, should not be

changed during operation.

To select the Firmware Hub (FWH) Interface the

Interface Configuration pin should be left to float or

driven Low, V_IL; to select the Address/Address

Multiplexed (A/A Mux) Interface the pin should be

driven High, V_IH. An internal pull-down resistor is

included with a value of R_IL; there will be a leakage

current of I_LI2through each pin when pulled to V_IH;

see Table 21.

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the memory. When Interface

Reset (RP) is set Low, V_IL, the memory is in Reset

mode: the outputs are put to high impedance and

the current consumption is minimized. When RP is

set High, V_IH, the memory is in normal operation.

After exiting Reset mode, the memory enters

Read mode.

CPU Reset (INIT). The CPU Reset, INIT, pin is

used to Reset the memory when the CPU is reset.

It behaves identically to Interface Reset, RP, and

the internal Reset line is the logical OR (electrical

AND) of RP and INIT.

Firmware Hub (FWH) Signal Descriptions

For the Firmware Hub (FWH) Interface see Figure

2., Logic Diagram (FWH Interface), and Table

1., Signal Names (FWH Interface).

Input/Output Communications (FWH0-FWH3). All

Input and Output Communication with the memory

take place on these pins. Addresses and Data for

Bus Read and Bus Write operations are encoded

on these pins.

Input Communication Frame (FWH4). The In-

put Communication Frame (FWH4) signals the

start of a bus operation. When Input Communica-

tion Frame is Low, V_IL, on the rising edge of the

Clock a new bus operation is initiated. If Input

Communication Frame is Low, V_IL, during a bus

operation then the operation is aborted. When In-

put Communication Frame is High, V_IH, the cur-

rent bus operation is proceeding or the bus is idle.

Identification Inputs (ID0-ID3). The

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, FWH0-FWH3. The Clock

conforms to the PCI specification.

Identification Inputs select the address that the

memory responds to. Up to 16 memories can be

addressed on a bus. For an address bit to be ‘0’

the pin can be left floating or driven Low, V_IL; an

internal pull-down resistor is included with a value

of R_IL. For an address bit to be ‘1’ the pin must be

driven High, V_IH; there will be a leakage current of

Top Block Lock (TBL). The Top Block Lock

input is used to prevent the Top Block (Block 31)

from being changed. When Top Block Lock, TBL,

is set Low, V_IL, Program and Block Erase

operations in the Top Block have no effect,

regardless of the state of the Lock Register. When

Top Block Lock, TBL, is set High, V_IH, the

protection of the Block is determined by the Lock

Register. The state of Top Block Lock, TBL, does

not affect the protection of the Main Blocks (Blocks

0 to 30).

Top Block Lock, TBL, must be set prior to a Pro-

gram or Block Erase operation is initiated and

must not be changed until the operation completes

or unpredictable results may occur. Care should

be taken to avoid unpredictable behavior by

changing TBL during Program or Erase Suspend.

I_LI2through each pin when pulled to V_IH; see Table

21.

By convention the boot memory must have

address ‘0000’ and all additional memories take

sequential addresses starting from ‘0001’.

By convention the boot memory must have ID0-

ID3 pins left floating or driven Low, V_ILand a ‘1’

value on A21, A23-A25 and all additional

memories take sequential ID0-ID3 configuration.

General Purpose Inputs (FGPI0-FGPI4). The Gen-

eral Purpose Inputs can be used as digital inputs

for the CPU to read. The General Purpose Input

Register holds the values on these pins. The pins

must have stable data from before the start of the

cycle that reads the General Purpose Input Regis-

ter until after the cycle is complete. These pins

must not be left to float, they should be driven Low,

Write Protect (WP). The Write Protect input is

used to prevent the Main Blocks (Blocks 0 to 30)

from being changed. When Write Protect, WP, is

set Low, V_IL, Program and Block Erase operations

in the Main Blocks have no effect, regardless of

the state of the Lock Register. When Write Protect,

V_IL,or High, V_IH.

8/45

M50FW016

WP, is set High, V_IH, the protection of the Block

determined by the Lock Register. The state of

Write Protect, WP, does not affect the protection of

the Top Block (Block 31).

Write Protect, WP, must be set prior to a Program

or Block Erase operation is initiated and must not

be changed until the operation completes or un-

predictable results may occur. Care should be tak-

en to avoid unpredictable behavior by changing

WP during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do

not have assigned functions in this revision of the

part. They must be left disconnected.

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

memory is busy with a Program or Erase operation

and it will not accept any additional Program or

Erase command except the Program/Erase

Suspend command. When Ready/Busy is High,

V

_OH, the memory is ready for any Read, Program

or Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfac-

es.

V_CCSupply Voltage. The V_CCSupply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the V_CC

Supply Voltage is less than the Lockout Voltage,

V_LKO. This prevents Bus Write operations from

For the Address/Address Multiplexed (A/A Mux)

Interface see Figure 3., Logic Diagram (A/A Mux

Interface), and Table 2., Signal Names (A/A Mux

Interface).

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A20). They are

latched during any bus operation by the Row/Col-

umn Address Select input, RC.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs hold the data that is written to or read

from the memory. They output the data stored at

the selected address during a Bus Read opera-

tion. During Bus Write operations they represent

the commands sent to the Command Interface of

the internal state machine. The Data Inputs/Out-

puts, DQ0-DQ7, are latched during a Bus Write

operation.

accidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the

memory contents being altered will be invalid.

After V_CCbecomes valid the Command Interface

is reset to Read mode.

A 0.1µF capacitor should be connected between

the V_CCSupply Voltage pins and the V_SSGround

pin to decouple the current surges from the power

supply. Both V_CCSupply Voltage pins must be

connected to the power supply. The PCB track

widths must be sufficient to carry the currents

required during program and erase operations.

V_PPOptional Supply Voltage. The V_PPOptional

Supply Voltage pin is used to select the Fast

Program (see the Quadruple Byte Program

Command description) and Fast Erase options of

the memory and to protect the memory. When V_PP

< V_PPLKProgram and Erase operations cannot be

performed and an error is reported in the Status

Register if an attempt to change the memory

contents is made. When V_PP= V_CCProgram and

Erase operations take place as normal. When V_PP

= V_PPHFast Program operations (using the

Quadruple Byte Program command, 30h, from

Table 10.) and Fast Erase operations are used.

Any other voltage input to V_PPwill result in

undefined behavior and should not be used.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Row/Column Address Select (RC). The Row/

Column Address Select input selects whether the

Address Inputs should be latched into the Row

Address bits (A0-A10) or the Column Address bits

(A11-A20). The Row Address bits are latched on

the falling edge of RC whereas the Column

Address bits are latched on the rising edge.

V_PPshould not be set to V_PPHfor more than 80

hours during the life of the memory.

V_SSGround. V_SSis the reference for all the volt-

Ready/Busy Output (RB). The Ready/Busy pin

gives the status of the memory’s Program/Erase

Controller. When Ready/Busy is Low, V_OL, the

age measurements.

9/45

M50FW016

Table 3. Block Addresses

Size

Block

Number

Address Range

(Kbytes)

Block Type

64

1F0000h-1FFFFFh

1E0000h-1EFFFFh

1D0000h-1DFFFFh

1C0000h-1CFFFFh

1B0000h-1BFFFFh

1A0000h-1AFFFFh

190000h-19FFFFh

180000h-18FFFFh

170000h-17FFFFh

160000h-16FFFFh

150000h-15FFFFh

140000h-14FFFFh

130000h-13FFFFh

120000h-12FFFFh

110000h-11FFFFh

100000h-10FFFFh

0F0000h-0FFFFFh

0E0000h-0EFFFFh

0D0000h-0DFFFFh

0C0000h-0CFFFFh

0B0000h-0BFFFFh

0A0000h-0AFFFFh

090000h-09FFFFh

080000h-08FFFFh

070000h-07FFFFh

060000h-06FFFFh

050000h-05FFFFh

040000h-04FFFFh

030000h-03FFFFh

020000h-02FFFFh

010000h-01FFFFh

000000h-00FFFFh

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Top Block

Main Block

8

7

6

5

4

3

2

1

0

10/45

M50FW016

BUS OPERATIONS

The two interfaces have similar bus operations but

the signals and timings are completely different.

The Firmware Hub (FWH) Interface is the usual

interface and all of the functionality of the part is

available through this interface. Only a subset of

functions are available through the Address/

Address Multiplexed (A/A Mux) Interface.

Follow the section Firmware Hub (FWH) Bus

Operations below and the section Address/

Address Multiplexed (A/A Mux) Bus Operations

below for a description of the bus operations on

each interface.

on FWH0-FWH3. The memory outputs Sync data

until the wait-states have elapsed.

Refer to Table 5., FWH Bus Write Field Definitions

(Single Byte), and Figure 6., FWH Bus Write

Waveforms (Single Byte), for a description of the

Field definitions for each clock cycle of the

transfer. See Table 23., FWH Interface AC Signal

Timing Characteristics, and Figure 11., FWH

Interface AC Signal Timing Waveforms, for details

on the timings of the signals.

Bus Abort. The Bus Abort operation can be used

to immediately abort the current bus operation. A

Bus Abort occurs when FWH4 is driven Low, V_IL,

during the bus operation; the memory will tri-state

the Input/Output Communication pins, FWH0-

FWH3.

Note that, during a Bus Write operation, the

Command Interface starts executing the

command as soon as the data is fully received; a

Bus Abort during the final TAR cycles is not

guaranteed to abort the command; the bus,

however, will be released immediately.

Standby. When FWH4 is High, V_IH, the memory

is put into Standby mode where FWH0-FWH3 are

put into a high-impedance state and the Supply

Firmware Hub (FWH) Bus Operations

The Firmware Hub (FWH) Interface consists of

four data signals (FWH0-FWH3), one control line

(FWH4) and a clock (CLK). In addition protection

against accidental or malicious data corruption

can be achieved using two further signals (TBL

and WP). Finally two reset signals (RP and INIT)

are available to put the memory into a known

state.

The data signals, control signal and clock are

designed to be compatible with PCI electrical

specifications. The interface operates with clock

speeds up to 33MHz.

Current is reduced to the Standby level, I_CC1

.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Standby, Reset and Block Protection.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when Interface Reset, RP, or CPU

Reset, INIT, is Low, V_IL. RP or INIT must be held

Low, V_IL, for t_PLPH. The memory resets to Read

mode upon return from Reset mode and the Lock

Registers return to their default states regardless

of their state before Reset, see Table 13. If RP or

INIT goes Low, V_IL, during a Program or Erase

operation, the operation is aborted and the

memory cells affected no longer contain valid

data; the memory can take up to t_PLRHto abort a

Program or Erase operation.

Bus Read. Bus Read operations read from the

memory cells, specific registers in the Command

Interface or Firmware Hub Registers. A valid Bus

Read operation starts when Input Communication

Frame, FWH4, is Low, V_IL, as Clock rises and the

correct Start cycle is on FWH0-FWH3. On the

following clock cycles the Host will send the

Memory ID Select, Address and other control bits

on FWH0-FWH3. The memory responds by

outputting Sync data until the wait-states have

elapsed followed by Data0-Data3 and Data4-

Data7.

Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux)

Interface has a more traditional style interface.

The signals consist of a multiplexed address

signals (A0-A10), data signals, (DQ0-DQ7) and

three control signals (RC, G, W). An additional

signal, RP, can be used to reset the memory.

The Address/Address Multiplexed (A/A Mux)

Interface is included for use by Flash

Programming equipment for faster factory

Refer to Table 4., FWH Bus Read Field Defini-

tions, and Figure 5., FWH Bus Read Waveforms

(Single Byte Read), for a description of the Field

definitions for each clock cycle of the transfer. See

Table 23., FWH Interface AC Signal Timing Char-

acteristics and Figure 11., FWH Interface AC Sig-

nal Timing Waveforms, for details on the timings of

the signals.

FWH Bus Write. Bus Write operations write to

the Command Interface or Firmware Hub

Registers. A valid Bus Write operation starts when

Input Communication Frame, FWH4, is Low, V_IL,

as Clock rises and the correct Start cycle is on

FWH0-FWH3. On the following Clock cycles the

Host will send the Memory ID Select, Address,

other control bits, Data0-Data3 and Data4-Data7

11/45

M50FW016

programming. Only a subset of the features

available to the Firmware Hub (FWH) Interface are

available; these include all the Commands but

exclude the Security features and other registers.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface is selected all the blocks are

unprotected. It is not possible to protect any blocks

through this interface.

Bus Read. Bus Read operations are used to

output the contents of the Memory Array, the

Electronic Signature and the Status Register. A

valid Bus Read operation begins by latching the

Row Address and Column Address signals into

the memory using the Address Inputs, A0-A10,

and the Row/Column Address Select RC. Then

Write Enable (W) and Interface Reset (RP) must

be High, V_IH, and Output Enable, G, Low, V_IL, in

order to perform a Bus Read operation. The Data

Inputs/Outputs will output the value, see Figure

13., A/A Mux Interface Read AC Waveforms, and

Table 25., A/A Mux Interface Read AC

Characteristics, for details of when the output

becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by latching the Row Address and Column

Address signals into the memory using the

Address Inputs, A0-A10, and the Row/Column

Address Select RC. The data should be set up on

the Data Inputs/Outputs; Output Enable, G, and

Interface Reset, RP, must be High, V_IHand Write

Enable, W, must be Low, V_IL. The Data Inputs/

Outputs are latched on the rising edge of Write

Enable, W. See Figure 14., A/A Mux Interface

Write AC Waveforms, and Table 26., A/A Mux

Interface Write AC Characteristics, for details of

the timing requirements.

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at V_IH.

Reset. During Reset mode all internal circuits are

switched off, the memory is deselected and the

outputs are put in high-impedance. The memory is

in Reset mode when RP is Low, V_IL. RP must be

held Low, V_ILfor t_PLPH. If RP is goes Low, V_IL,

during a Program or Erase operation, the

operation is aborted and the memory cells affected

no longer contain valid data; the memory can take

up to t_PLRHto abort a Program or Erase operation.

12/45

M50FW016

Table 4. FWH Bus Read Field Definitions

Clock

Cycle

Number Count

Clock

Cycle

FWH0-

FWH3

Memory

I/O

Field

Description

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Read cycle.

1

2

1

START

1101b

XXXX

I

Indicates which FWH Flash Memory is selected. The value

on FWH0-FWH3 is compared to the IDSEL strapping on the

FWH Flash Memory pins to select which FWH Flash

Memory is being addressed.

IDSEL

ADDR

MSIZE

A 28-bit address phase is transferred starting with the most

significant nibble first. For the multi-byte read operation, the

least significant bits (MSIZE of them) are treated as Don't

Care, and the read operation is started with each of these

bits reset to 0.

3-9

10

7

1

XXXX

I

This one clock cycle is driven by the host to determine how

many bytes will be transferred. M50FW016 will support:

single byte transfer (0000b), 4-byte transfer (0010b), 16-byte

transfer (0100b) and 128-byte transfer (0111b).

0XXXb

1111b

The host drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

11

12

1

TAR

I

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

O

The FWH Flash Memory drives FWH0-FWH3 to 0101b

(short wait-sync) for two clock cycles, indicating that the data

is not yet available. Two wait-states are always included.

13-14

15

2

1

WSYNC

RSYNC

0101b

0000b

O

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating that data will be available during the next clock

cycle.

Data transfer is two CLK cycles, starting with the least

significant nibble. If multi-byte read operation is

enabled, repeat cycle 16-17 n times, where n = 2

16-17

2

DATA

XXXX

1111b

O

MSIZE

– 1

The FWH Flash Memory drives FWH0-FWH3 to 1111b to

indicate a turnaround cycle.

Note 1

Note 2

1

TAR

O

1111b

(float)

The FWH Flash Memory floats its outputs, the host takes

control of FWH0-FWH3.

N/A

MSIZE

Note: 1. Clock Cycle Number = (2

2. Clock Cycle Number = (2

– 1) * 2 + 18

– 1) * 2 + 19

MSIZE

Figure 5. FWH Bus Read Waveforms (Single Byte Read)

CLK

FWH4

FWH0-FWH3

START

1

IDSEL

1

ADDR

7

MSIZE

1

TAR

2

SYNC

3

DATA

2

TAR

2

Number of

clock cycles

AI03437

13/45

M50FW016

Table 5. FWH Bus Write Field Definitions (Single Byte)

Clock

Cycle

Number Count

Clock

Cycle

FWH0-

FWH3

Memory

I/O

Field

Description

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Write Cycle.

1

2

1

START

1110b

XXXX

I

Indicates which FWH Flash Memory is selected. The value

on FWH0-FWH3 is compared to the IDSEL strapping on the

FWH Flash Memory pins to select which FWH Flash

Memory is being addressed.

IDSEL

A 28-bit address phase is transferred starting with the most

significant nibble first.

3-9

10

7

1

2

ADDR

MSIZE

DATA

XXXX

0000b

XXXX

I

Always 0000b (single byte transfer).

Data transfer is two cycles, starting with the least significant

nibble.

11-12

The host drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

13

14

15

16

17

1

TAR

1111b

I

O

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command.

SYNC

TAR

0000b

1111b

O

The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

O

1111b

(float)

The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

TAR

N/A

Figure 6. FWH Bus Write Waveforms (Single Byte)

CLK

FWH4

FWH0-FWH3

START

1

IDSEL

1

ADDR

7

MSIZE

1

DATA

2

TAR

2

SYNC

1

TAR

2

Number of

clock cycles

AI03441

14/45

M50FW016

Table 6. FWH Bus Write Field Definitions (Quadruple Byte Program)

Clock

Cycle

Number Count

Clock

Cycle

FWH0-

FWH3

Memory

I/O

Field

Description

On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Write Cycle.

1

2

1

START

1110b

XXXX

I

Indicates which FWH Flash Memory is selected. The value

on FWH0-FWH3 is compared to the IDSEL strapping on the

FWH Flash Memory pins to select which FWH Flash

Memory is being addressed.

IDSEL

A 28-bit address phase is transferred starting with the most

significant nibble first. The A1-A0 lines are treated as Don't

Care.

3-9

10

7

1

ADDR

MSIZE

XXXX

0010b

I

Always 0010b (quadruple byte transfer).

Data transfer is two cycles, starting with the least significant

nibble. (The first pair of nibbles is that at the address with A1-

A0 set to 00, the second pair with A1-A0 set to 01, the third

pair with A1-A0 set to 10, and the fourth pair with A1-A0 set

to 11.)

11-18

8

DATA

XXXX

I

The host drives FWH0-FWH3 to 1111b to indicate a

turnaround cycle.

19

20

21

22

23

1

TAR

1111b

I

O

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3

during this cycle.

The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command.

SYNC

TAR

0000b

1111b

O

The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

O

1111b

(float)

The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

TAR

N/A

Figure 7. FWH Bus Write Waveforms (Quadruple Byte Program)

CLK

FWH4

FWH0-FWH3

START

1

IDSEL

1

ADDR

7

MSIZE

1

DATA

8

TAR

2

SYNC

1

TAR

2

Number of

clock cycles

AI05784

15/45

M50FW016

Table 7. A/A Mux Bus Operations

V

Operation

Bus Read

G

W

RP

DQ7-DQ0

Data Output

Data Input

Hi-Z

PP

V

IH

Don't Care

V or V

CC

IL

IH

V

IH

Bus Write

Output Disable

Reset

IL

PPH

V

IH

Don't Care

IH

V

IL

or V

V

or V

V

IL

Hi-Z

IH

IL

IH

Table 8. Manufacturer and Device Codes

Operation

Manufacturer Code

Device Code

G

W

RP

A20-A1

A0

DQ7-DQ0

20h

V

IL

V

IH

V

IL

IH

IL

V

IL

V

IH

V

2Eh

IH

16/45

M50FW016

COMMAND INTERFACE

All Bus Write operations to the memory are

If the address falls in a protected block then the

Program operation will abort, the data in the

memory array will not be changed and the Status

Register will output the error.

interpreted

by the

Command

Interface.

Commands consist of one or more sequential Bus

Write operations.

After power-up or a Reset operation the memory

enters Read mode.

The commands are summarized in Table

10., Commands. Refer to Table 10. in conjunction

with the text descriptions below.

During the Program operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands will be ignored. Typical Program

times are given in Table 15.

Note that the Program command cannot change a

bit set at ‘0’ back to ‘1’ and attempting to do so will

not cause any modification on its value. One of the

Erase commands must be used to set all of the

bits in the block to ‘1’.

See Figure 16., Program Flowchart and Pseudo

Code, for a suggested flowchart on using the

Program command.

Read Memory Array Command. The Read Mem-

ory Array command returns the memory to its

Read mode where it behaves like a ROM or

EPROM. One Bus Write cycle is required to issue

the Read Memory Array command and return the

memory to Read mode. Once the command is is-

sued the memory remains in Read mode until an-

other command is issued. From Read mode Bus

Read operations will access the memory array.

While the Program/Erase Controller is executing a

Program or Erase operation the memory will not

accept the Read Memory Array command until the

operation completes.

Read Status Register Command. The Read Sta-

tus Register command is used to read the Status

Register. One Bus Write cycle is required to issue

the Read Status Register command. Once the

command is issued subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued. See the section on the STATUS

REGISTER for details on the definitions of the Sta-

tus Register bits.

Read Electronic Signature Command. The Read

Electronic Signature command is used to read the

Manufacturer Code and the Device Code. One

Bus Write cycle is required to issue the Read

Electronic Signature command. Once the

command is issued subsequent Bus Read

operations read the Manufacturer Code or the

Device Code until another command is issued.

Quadruple Byte Program Command (A/A Mux

Mode). The Quadruple Byte Program Command

can be used to program four adjacent bytes in the

memory array at a time. The four bytes must differ

only for the addresses A0 and A1. Programming

should not be attempted when V_PPis not at V_PPH

.

Five Bus Write operations are required to issue the

command. The second, the third and the fourth

Bus Write cycle latches respectively the address

and data of the first, the second and the third byte

in the internal state machine. The fifth Bus Write

cycle latches the address and data of the fourth

byte in the internal state machine and starts the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the STATUS

REGISTER for details on the definitions of the

Status Register bits.

During the Quadruple Byte Program operation the

memory will only accept the Read Status register

command and the Program/Erase Suspend com-

mand. All other commands will be ignored. Typical

Quadruple Byte Program times are given in Table

15..

Note that the Quadruple Byte Program command

cannot change a bit set to ‘0’ back to ‘1’ and

attempting to do so will not cause any modification

on its value. One of the Erase commands must be

used to set all of the bits in the block to ‘1’.

See Figure 17., for a suggested flowchart on using

the Quadruple Byte Program command.

Quadruple Byte Program Command (FWH

Mode). The Quadruple Byte Program Command

can be used to program four adjacent bytes in the

memory array at a time. The four bytes must differ

only for the addresses A0 and A1. Programming

After the Read Electronic Signature Command is

issued the Manufacturer Code and Device Code

can be read using Bus Read operations using the

addresses in Table 9.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. Two Bus Write

operations are required to issue the command; the

second Bus Write cycle latches the address and

data in the internal state machine and starts the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the STATUS

REGISTER for details on the definitions of the

Status Register bits.

should not be attempted when V_PPis not at V_PPH

.

Two Bus Write operations are required to issue the

command. The second Bus Write cycle latches the

17/45

M50FW016

start address and four data bytes in the internal

state machine and starts the Program/Erase

Controller. Once the command is issued

subsequent Bus Read operations read the Status

Register. See the section on the STATUS

REGISTER for details on the definitions of the

Status Register bits.

During the Quadruple Byte Program operation the

memory will only accept the Read Status register

command and the Program/Erase Suspend com-

mand. All other commands will be ignored. Typical

Quadruple Byte Program times are given in Table

15.

Note that the Quadruple Byte Program command

cannot change a bit set to ‘0’ back to ‘1’ and

attempting to do so will not cause any modification

on its value. One of the Erase commands must be

used to set all of the bits in the block to ‘1’.

See Figure 18., for a suggested flowchart on using

the Quadruple Byte Program command.

Chip Erase Command. The Chip Erase Com-

mand can be only used in A/A Mux mode to erase

the entire chip at a time. Erasing should not be at-

tempted when V_PPis not at V_PPH. The operation

can also be executed if V_PPis below V_PPH, but re-

sult could be uncertain. Two Bus Write operations

are required to issue the command and start the

Program/Erase Controller. Once the command is

issued subsequent Bus Read operations read the

Status Register. See the section on the STATUS

REGISTER for details on the definitions of the Sta-

tus Register bits. During the Chip Erase operation

the memory will only accept the Read Status Reg-

ister command. All other commands will be ig-

nored. Typical Chip Erase times are given in Table

15. The Chip Erase command sets all of the bits in

the memory to ‘1’. See Figure 20., Chip Erase

Flowchart and Pseudo Code (A/A Mux Interface

Only), for a suggested flowchart on using the Chip

Erase command.

Block Erase Command. The Block Erase com-

mand can be used to erase a block. Two Bus Write

operations are required to issue the command; the

second Bus Write cycle latches the block address

in the internal state machine and starts the Pro-

gram/Erase Controller. Once the command is is-

sued subsequent Bus Read operations read the

Status Register. See the section on the STATUS

REGISTER for details on the definitions of the Sta-

tus Register bits.

other commands will be ignored. Typical Block

Erase times are given in Table 15.

The Block Erase command sets all of the bits in

the block to ‘1’. All previous data in the block is

lost.

See Figure 21., Block Erase Flowchart and

Pseudo Code, for a suggested flowchart on using

the Erase command.

Clear Status Register Command. The Clear Sta-

tus Register command can be used to reset bits 1,

3, 4 and 5 in the Status Register to ‘0’. One Bus

Write is required to issue the Clear Status Register

command. Once the command is issued the mem-

ory returns to its previous mode, subsequent Bus

Read operations continue to output the same data.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Program

or Erase command is issued. If an error occurs

then it is essential to clear any error bits in the Sta-

tus Register by issuing the Clear Status Register

command before attempting a new Program or

Erase command.

Program/Erase Suspend Command. The

Pro-

gram/Erase Suspend command can be used to

pause a Program or Block Erase operation. One

Bus Write cycle is required to issue the Program/

Erase Suspend command and pause the Pro-

gram/Erase Controller. Once the command is is-

sued it is necessary to poll the Program/Erase

Controller Status bit to find out when the Program/

Erase Controller has paused; no other commands

will be accepted until the Program/Erase Control-

ler has paused. After the Program/Erase Control-

ler has paused, the memory will continue to output

the Status Register until another command is is-

sued.

During the polling period between issuing the

Program/Erase Suspend command and the

Program/Erase Controller pausing it is possible for

the operation to complete. Once Program/Erase

Controller Status bit indicates that the Program/

Erase Controller is no longer active, the Program

Suspend Status bit or the Erase Suspend Status

bit can be used to determine if the operation has

completed or is suspended. For timing on the

delay between issuing the Program/Erase

Suspend command and the Program/Erase

Controller pausing see Table 15.

During Program/Erase Suspend the Read

Memory Array, Read Status Register, Read

Electronic Signature and Program/Erase Resume

commands will be accepted by the Command

Interface. Additionally, if the suspended operation

was Block Erase then the Program command will

also be accepted; only the blocks not being erased

may be read or programmed correctly.

If the block is protected then the Block Erase

operation will abort, the data in the block will not be

changed and the Status Register will output the

error.

During the Block Erase operation the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

18/45

M50FW016

See Figure 19., Program Suspend and Resume

Flowchart, and Pseudo Code, and Figure

22., Erase Suspend and Resume Flowchart, and

Pseudo Code, for suggested flowcharts on using

the Program/Erase Suspend command.

Resume command. Once the command is issued

subsequent Bus Read operations read the Status

Register.

Table 9. Read Electronic Signature

Program/Erase Resume Command. The

gram/Erase Resume command can be used to re-

start the Program/Erase Controller after

Pro-

Code

Manufacturer Code

Device Code

Address

00000h

00001h

Data

20h

a

Program/Erase Suspend has paused it. One Bus

Write cycle is required to issue the Program/Erase

2Eh

Table 10. Commands

Bus Write Operations

Command

1st

2nd

3rd

4th

5th

Addr Data Addr Data Addr Data Addr Data Addr Data

Read Memory Array

Read Status Register

1

2

X

FFh

70h

90h

98h

40h

10h

Read Electronic Signature

Program

PA

PD

Quadruple Byte Program

(A/A Mux Mode)

A

4

5

2

X

30h

PD

1

2

3

Quadruple Byte Program

(FWH Mode)

A

qbp

PD

qbp

Chip Erase

2

1

X

80h

20h

50h

B0h

D0h

00h

01h

60h

2Fh

C0h

X

10h

D0h

Block Erase

BA

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

Invalid/Reserved

Note: X Don’t Care, PA Program Address, PD Program Data, A

Consecutive Addresses, BA Any address in the Block.

1,2,3,4

Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.

Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.

Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another com-

mand is issued.

Block Erase, Program. After these commands read the Status Register until the command completes and another command is is-

sued.

Quadruple Byte Program (A/A Mux Mode). Addresses A , A , A and A must be consecutive addresses differing only for address

1

2

3

4

bit A0 and A1. After this command, the user should repeatedly read the Status Register until the command has completed, at which

point another command can be issued.

Quadruple Byte Program (FWH Mode). A

is the start address, A1 and A0 are treated as Don’t Care. The first data byte is pro-

qbp

grammed at the address that has A1-A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that has A1-

A0 at 10, and the fourth at the address that has A1-A0 at 11. After this command, the user should repeatedly read the Status Register

until the command has completed, at which point another command can be issued.

Chip Erase. This command is only valid in A/A Mux mode. After this command read the Status Register until the command completes

and another command is issued.

Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.

Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status

Register, Program (during Erase suspend) and Program/Erase resume commands.

Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the

Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.

Invalid/Reserved. Do not use Invalid or Reserved commands.

19/45

M50FW016

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

Different bits in the Status Register convey

different information and errors on the operation.

and still failed to verify that the block(s) has erased

correctly. The Erase Status bit should be read

once the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive).

To read the Status Register the Read Status

Register command can be issued. The Status

Register is automatically read after Program,

Erase and Program/Erase Resume commands

are issued. The Status Register can be read from

any address.

When the Erase Status bit is ‘0’ the memory has

successfully verified that the block(s) has erased

correctly; when the Erase Status bit is ‘1’ the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the block(s) and still failed to

verify that the block(s) has erased correctly.

The Status Register bits are summarized in Table

11., Status Register Bits. Refer to Table 11. in

conjunction with the text descriptions below.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

‘0’, the Program/Erase Controller is active; when

the bit is ‘1’, the Program/Erase Controller is inac-

tive.

The Program/Erase Controller Status is ‘0’ imme-

diately after a Program/Erase Suspend command

is issued until the Program/Erase Controller paus-

es. After the Program/Erase Controller pauses the

bit is ‘1’.

During Program and Erase operation the Pro-

gram/Erase Controller Status bit can be polled to

find the end of the operation. The other bits in the

Status Register should not be tested until the Pro-

gram/Erase Controller completes the operation

and the bit is ‘1’.

Once the Erase Status bit is set to ‘1’ it can only be

reset to ‘0’ by a Clear Status Register command or

a hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong

command sequence has been attempted).

Program Status (Bit 4). The Program Status bit

can be used to identify if the memory has applied

the maximum number of program pulses to the

byte and still failed to verify that the byte has pro-

grammed correctly. The Program Status bit should

be read once the Program/Erase Controller Status

bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has

successfully verified that the byte has pro-

grammed correctly; when the Program Status bit is

‘1’ the Program/Erase Controller has applied the

maximum number of pulses to the byte and still

failed to verify that the byte has programmed cor-

rectly.

Once the Program Status bit is set to ‘1’ it can only

be reset to ‘0’ by a Clear Status Register com-

mand or a hardware reset. If it is set to ‘1’ it should

be reset before a new Program or Erase command

is issued, otherwise the new command will appear

to fail. (When Bit 4 and Bit 5 are set to ‘1’, a wrong

command sequence has been attempted).

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V_PP

Status and Block Protection Status bits should be

tested for errors.

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that a Block Erase oper-

ation has been suspended and is waiting to be

resumed. The Erase Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Erase Suspend Status bit is ‘0’ the Pro-

gram/Erase Controller is active or has completed

its operation; when the bit is ‘1’ a Program/Erase

Suspend command has been issued and the

memory is waiting for a Program/Erase Resume

command.

V_PPStatus (Bit 3). The V_PPStatus bit can be

used to identify an invalid voltage on the V_PPpin

during Program and Erase operations. The V_PP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if V_PPbecomes invalid during a Program or

Erase operation.

When the V_PPStatus bit is ‘0’ the voltage on the

V_PPpin was sampled at a valid voltage; when the

V_PPStatus bit is ‘1’ the V_PPpin has a voltage that

is below the V_PPLockout Voltage, V_PPLK, the

memory is protected; Program and Erase opera-

tion cannot be performed. (The V_PPstatus bit is ‘1’

if a Quadruple Byte Program command is issued

and the V_PPsignal has a voltage less than V_PPH

applied to it.)

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has applied the

maximum number of erase pulses to the block(s)

Once the V_PPStatus bit set to ‘1’ it can only be re-

set to ‘0’ by a Clear Status Register command or a

20/45

M50FW016

hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended and is waiting to be re-

sumed. The Program Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the

Program/Erase Controller is active or has complet-

ed its operation; when the bit is ‘1’ a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if the Pro-

gram or Block Erase operation has tried to modify

the contents of a protected block. When the Block

Protection Status bit is to ‘0’ no Program or Block

Erase operations have been attempted to protect-

ed blocks since the last Clear Status Register

command or hardware reset; when the Block Pro-

tection Status bit is ‘1’ a Program or Block Erase

operation has been attempted on a protected

block.

Once it is set to ‘1’ the Block Protection Status bit

can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If it is set to ‘1’ it

should be reset before a new Program or Block

Erase command is issued, otherwise the new

command will appear to fail.

Using the A/A Mux Interface the Block Protection

Status bit is always ‘0’.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns to

‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value should be masked.

Table 11. Status Register Bits

Operation

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

(1)

Program active

‘0’

‘1

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

X

(1)

Program suspended

Program completed successfully

‘1’

Program failure due to V Error

PP

Program failure due to Block Protection (FWH Interface only)

Program failure due to cell failure

Erase active

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Block Erase suspended

Erase completed successfully

‘1’

‘0’

Erase failure due to V Error

PP

Block Erase failure due to Block Protection (FWH Interface

only)

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

Erase failure due to failed cell(s)

Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.

21/45

M50FW016

FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS

When the Firmware Hub Interface is selected sev-

eral additional registers can be accessed. These

registers control the protection status of the

Blocks, read the General Purpose Input pins and

identify the memory using the Electronic Signature

codes. See Table 12. for the memory map of the

Configuration Registers in the FWH Protocol.

attempts to read the contents of the block will read

00h instead. When the Read Lock Bit is reset, ‘0’,

read operations in the Block return the data pro-

grammed into the block as expected.

After power-up or reset the Read Lock Bit is al-

ways reset to ‘0’ (not read protected).

Lock Down. The Lock Down Bit provides a

mechanism for protecting software data from sim-

ple hacking and malicious attack. When the Lock

Down Bit is set, ‘1’, further modification to the

Write Lock, Read Lock and Lock Down Bits cannot

be performed. A reset or power-up is required be-

fore changes to these bits can be made. When the

Lock Down Bit is reset, ‘0’, the Write Lock, Read

Lock and Lock Down Bits can be changed.

Lock Registers

The Lock Registers control the protection status of

the Blocks. Each Block has its own Lock Register.

Three bits within each Lock Register control the

protection of each block, the Write Lock Bit, the

Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written,

though care should be taken when writing as, once

the Lock Down Bit is set, ‘1’, further modifications

to the Lock Register cannot be made until cleared,

to ‘0’, by a reset or power-up.

Firmware Hub (FWH) General Purpose Input

Register

The Firmware Hub (FWH) General Purpose Input

Register holds the state of the Firmware Hub Inter-

face General Purpose Input pins, FGPI0-FGPI4.

When this register is read, the state of these pins

is returned. This register is read-only and writing to

it has no effect.

The signals on the Firmware Hub Interface Gener-

al Purpose Input pins should remain constant

throughout the whole Bus Read cycle in order to

guarantee that the correct data is read.

See Table 13. for details on the bit definitions of

the Lock Registers.

Write Lock. The Write Lock Bit determines

whether the contents of the Block can be modified

(using the Program or Block Erase Command).

When the Write Lock Bit is set, ‘1’, the block is

write protected; any operations that attempt to

change the data in the block will fail and the Status

Register will report the error. When the Write Lock

Bit is reset, ‘0’, the block is not write protected

through the Lock Register and may be modified

unless write protected through some other means.

When V_PPis less than V_PPLKall blocks are pro-

tected and cannot be modified, regardless of the

state of the Write Lock Bit. If Top Block Lock, TBL,

is Low, V_IL, then the Top Block (Block 31) is write

protected and cannot be modified. Similarly, if

Write Protect, WP, is Low, V_IL, then the Main

Blocks (Blocks 0 to 30) are write protected and

cannot be modified.

Manufacturer Code Register

Reading the Manufacturer Code Register returns

the manufacturer code for the memory. The man-

ufacturer code for STMicroelectronics is 20h. This

register is read-only and writing to it has no effect.

Device Code Register

Reading the Device Code Register returns the de-

vice code for the memory, 2Eh. This register is

read-only and writing to it has no effect.

Multi-Byte Read/Write Configuration Registers

After power-up or reset the Write Lock Bit is al-

ways set to ‘1’ (write protected).

Read Lock. The Read Lock bit determines

whether the contents of the Block can be read

(from Read mode). When the Read Lock Bit is set,

‘1’, the block is read protected; any operation that

The Multi-Byte Read/Write Configuration Regis-

ters contain information as which multi-byte read

and write access sizes will be accepted. The

M50FW016 supports 4/16/128-byte reading and

4-byte writing.

22/45

M50FW016

Table 12. Firmware Hub Register Configuration Map

Default

Value

Memory

Address

Mnemonic

Register Name

Access

T_BLOCK_LK

Top Block Lock Register (Block 31)

FBF0002h

FBE0002h

FBD0002h

FBC0002h

FBB0002h

FBA0002h

FB90002h

FB80002h

FB70002h

FB60002h

FB50002h

FB40002h

FB30002h

FB20002h

FB10002h

FB00002h

FAF0002h

FAE0002h

FAD0002h

FAC0002h

FAB0002h

FAA0002h

FA90002h

FA80002h

FA70002h

FA60002h

FA50002h

FA40002h

FA30002h

FA20002h

FA10002h

FA00002h

FBC0100h

FBC0000h

FBC0001h

FBC0005h

FBC0006h

FBC0007h

FBC0008h

01h

N/A

20h

2Eh

4Ah

00h

02h

00h

R/W

R

T_MINUS01_LK Top Block [-1] Lock Register (Block 30)

T_MINUS02_LK Top Block [-2] Lock Register (Block 29)

T_MINUS03_LK Top Block [-3] Lock Register (Block 28)

T_MINUS04_LK Top Block [-4] Lock Register (Block 27)

T_MINUS05_LK Top Block [-5] Lock Register (Block 26)

T_MINUS06_LK Top Block [-6] Lock Register (Block 25)

T_MINUS07_LK Top Block [-7] Lock Register (Block 24)

T_MINUS08_LK Top Block [-8] Lock Register (Block 23)

T_MINUS09_LK Top Block [-9] Lock Register (Block 22)

T_MINUS10_LK Top Block [-10] Lock Register (Block 21)

T_MINUS11_LK Top Block [-11] Lock Register (Block 20)

T_MINUS12_LK Top Block [-12] Lock Register (Block 19)

T_MINUS13_LK Top Block [-13] Lock Register (Block 18)

T_MINUS14_LK Top Block [-14] Lock Register (Block 17)

T_MINUS15_LK Top Block [-15] Lock Register (Block 16)

T_MINUS16_LK Top Block [-16] Lock Register (Block 15)

T_MINUS17_LK Top Block [-17] Lock Register (Block 14)

T_MINUS18_LK Top Block [-18] Lock Register (Block 13)

T_MINUS19_LK Top Block [-19] Lock Register (Block 12)

T_MINUS20_LK Top Block [-20] Lock Register (Block 11)

T_MINUS21_LK Top Block [-21] Lock Register (Block 10)

T_MINUS22_LK Top Block [-22] Lock Register (Block 9)

T_MINUS23_LK Top Block [-23] Lock Register (Block 8)

T_MINUS24_LK Top Block [-24] Lock Register (Block 7)

T_MINUS25_LK Top Block [-25] Lock Register (Block 6)

T_MINUS26_LK Top Block [-26] Lock Register (Block 5)

T_MINUS27_LK Top Block [-27] Lock Register (Block 4)

T_MINUS28_LK Top Block [-28] Lock Register (Block 3)

T_MINUS29_LK Top Block [-29] Lock Register (Block 2)

T_MINUS30_LK Top Block [-30] Lock Register (Block 1)

T_MINUS31_LK Top Block [-31] Lock Register (Block 0)

FGPI_REG

MANUF_REG

DEV_REG

Firmware Hub (FWH) General Purpose Input Register

Manufacturer Code Register

R

Device Code Register

R

MBR_REG_LB

Multi-Byte Read Configuration Register (Low Byte)

R

MBR_REG_HB Multi-Byte Read Configuration Register (High Byte)

MBW_REG_LB Multi-Byte Write Configuration Register (Low Byte)

MBW_REG_HB Multi-Byte Write Configuration Register (High Byte)

R

23/45

M50FW016

Table 13. Lock Register Bit Definitions

Bit

Bit Name

Value

Function

7-3

Reserved

‘1’

‘0’

Bus Read operations in this Block always return 00h.

2

1

Read-Lock

Bus read operations in this Block return the Memory Array contents. (Default

value).

Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

to ‘0’ following a Reset (using RP or INIT) or after power-up.

‘1’

Lock-Down

Write-Lock

Read-Lock and Write-Lock can be changed by writing new values to them. (Default

value).

‘0’

‘1’

‘0’

Program and Block Erase operations in this Block will set an error in the Status

Register. The memory contents will not be changed. (Default value).

0

Program and Block Erase operations in this Block are executed and will modify the

Block contents.

Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-31] Lock

Register (T_MINUS31_LK).

Table 14. General Purpose Input Register Definition

Bit

Bit Name

Value

Function

7-5

Reserved

Input Pin FGPI4 is at V

Input Pin FGPI3 is at V

Input Pin FGPI2 is at V

Input Pin FGPI1 is at V

Input Pin FGPI0 is at V

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

‘1’

‘0’

IH

IL

IH

IL

IH

IL

IH

IL

IH

IL

4

3

2

1

0

FGPI4

FGPI3

FGPI2

FGPI1

FGPI0

Note: 1. Applies to the General Purpose Input Register (FGPI_REG).

24/45

M50FW016

PROGRAM AND ERASE TIMES

The Program and Erase times are shown in Table

15.

Table 15. Program and Erase Times

(1)

Parameter

Interface

Test Condition

Min

Max

200

Unit

µs

s

Typ

10

Byte Program

(4)

V

= 12V ± 5%

= V

Quadruple Byte Program

Chip Erase

PP

10

A/A Mux

18

(2)

5

s

0.1

Block Program

V

PP

0.4

s

CC

V

= 12V ± 5%

= V

0.75

1

8

s

PP

Block Erase

V

10

5

s

PP

CC

(3)

µs

Program/Erase Suspend to Program pause

(3)

30

µs

Program/Erase Suspend to Block Erase pause

Note: 1. T = 25°C, V = 3.3V

A

CC

2. This time is obtained executing the Quadruple Byte Program Command.

3. Sampled only, not 100% tested.

4. Time to program four bytes.

25/45

M50FW016

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 16. Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

T

Storage Temperature

–65

150

°C

STG

T

Lead Temperature during Soldering

Input or Output Voltage

See note 1

LEAD

(2)

V

CC

+ 0.6

–0.6

V

IO

V

Supply Voltage

–0.6

4

V

CC

V

Program Voltage

13

PP

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

2. Minimum Voltage may undershoot to –2V, for less than 20 ns, during transitions. Maximum Voltage may overshoot to V +2V, for

CC

less than 20 ns, during transitions.

26/45

M50FW016

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 17., Table 18.

and Table 19. Designers should check that the op-

erating conditions in their circuit match the operat-

ing conditions when relying on the quoted

parameters.

Table 17. Operating Conditions

Symbol

Parameter

Ambient Operating Temperature (Device Grade 1)

Ambient Operating Temperature (Device Grade 5)

Supply Voltage

Min

0

Max

70

Unit

°C

V

T

A

–20

3

85

V

CC

3.6

Table 18. FWH Interface AC Measurement Conditions

Parameter

Value

Unit

Load Capacitance (C )

10

pF

ns

V

L

Input Rise and Fall Times

≤ 1.4

0.2 V and 0.6 V

Input Pulse Voltages

CC

0.4 V

Input and Output Timing Ref. Voltages

V

CC

Table 19. A/A Mux Interface AC Measurement Conditions

Parameter

Value

30

Unit

pF

ns

V

Load Capacitance (C )

L

Input Rise and Fall Times

≤ 10

0 to 3

1.5

Input Pulse Voltages

Input and Output Timing Ref. Voltages

V

Figure 8. FWH Interface AC Testing Input Output Waveforms

0.6 V

CC

0.4 V

CC

0.2 V

CC

Input and Output AC Testing Waveform

I

< I

I

> I

I

< I

O LO

O

LO

O

LO

Output AC Tri-state Testing Waveform

AI03404

27/45

M50FW016

Figure 9. A/A Mux Interface AC Testing Input Output Waveform

3V

0V

1.5V

AI01417

Table 20. Impedance

Symbol

Parameter

Test Condition

Min

Max

Unit

(1)

V

= 0V

Input Capacitance

13

pF

C

IN

(1)

V

Clock Capacitance

3

12

20

pF

nH

C

L

CLK

Recommended Pin

Inductance

(2)

Note: 1. Sampled only, not 100% tested.

2. See PCI Specification.

28/45

M50FW016

Table 21. DC Characteristics

Symbol

Parameter

Interface

FWH

Test Condition

Min

Max

Unit

V

0.5 V

V

+ 0.5

CC

V

IH

Input High Voltage

0.7 V

+ 0.3

A/A Mux

FWH

V

CC

0.3 V

–0.5

-0.5

1.35

–0.5

V

CC

V

IL

Input Low Voltage

A/A Mux

FWH

0.8

+ 0.5

V

V (INIT)

IH

V

CC

INIT Input High Voltage

INIT Input Low Voltage

Input Leakage Current

V

V (INIT)

IL

0.2 V

CC

FWH

V

(2)

0V ≤ V ≤ V

CC

±10

200

µA

I

LI

IN

IC, IDx Input Leakage

Current

I

IC, ID0, ID1, ID2, ID3 = V

CC

LI2

IC, IDx Input Pull Low

Resistor

R

20

100

kΩ

IL

0.9 V

FWH

A/A Mux

FWH

I

= –500µA

= –100µA

= 1.5mA

= 1.8mA

V

CC

OH

V

Output High Voltage

OH

V

– 0.4

CC

OH

I

OL

0.1 V

V

CC

V

I

Output Low Voltage

OL

I

OL

A/A Mux

0.45

±10

3.6

V

0V ≤ V

≤ V

CC

Output Leakage Current

µA

V

LO

OUT

V

PP

Voltage

3

PP1

V

PP

Voltage (Fast

11.4

12.6

V

PPH

(1)

Program/Fast Erase)

V

Lockout Voltage

1.5

1.8

V

PP

CC

PPLK

(1)

V

2.3

V

LKO

FWH4 = 0.9 V , V = V

CC

PP

I

All other inputs 0.9 V to 0.1 V

CC

Supply Current (Standby)

FWH

100

µA

mA

CC1

CC

V

CC

= 3.6V, f(CLK) = 33MHz

FWH4 = 0.1 V , V = V

CC

PP

I

All other inputs 0.9 V to 0.1 V

CC

10

60

CC2

CC

V

CC

= 3.6V, f(CLK) = 33MHz

V

= V max, V = V

Supply Current

(Any internal operation

active)

CC

PP

CC

I

f(CLK) = 33MHz

= 0mA

CC3

I

OUT

I

G = V , f = 6MHz

IH

Supply Current (Read)

A/A Mux

20

mA

CC4

Supply Current

(Program/Erase)

(1)

Program/Erase Controller Active

I

CC5

V

Supply Current

PP

I

V

> V

400

µA

PP

CC

(Read/Standby)

= V

5

µA

PP

V

PP

Supply Current

(1)

PP1

I

(Program/Erase active)

V

= 12V ± 5%

15

mA

PP

Note: 1. Sampled only, not 100% tested.

2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.

29/45

M50FW016

Figure 10. FWH Interface Clock Waveform

tCYC

tHIGH

tLOW

0.6 V

CC

0.5 V

CC

0.4 V

,

CC p-to-p

(minimum)

0.4 V

CC

0.3 V

CC

0.2 V

CC

AI03403

Table 22. FWH Interface Clock Characteristics

Symbol

Parameter

Test Condition

Value

Unit

(1)

t

Min

30

ns

CYC

CLK Cycle Time

t

CLK High Time

CLK Low Time

Min

Max

11

1

ns

HIGH

t

LOW

V/ns

CLK Slew Rate

peak to peak

4

Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed

by design rather than tested. Refer to PCI Specification.

30/45

M50FW016

Figure 11. FWH Interface AC Signal Timing Waveforms

CLK

tCHQV

tCHQZ

tCHQX

tDVCH

tCHDX

VALID

FWH0-FWH3

VALID OUTPUT DATA

FLOAT OUTPUT DATA

VALID INPUT DATA

AI03405

Table 23. FWH Interface AC Signal Timing Characteristics

PCI

Symbol

Parameter

Test Condition

Value

Unit

Symbol

Min

2

ns

t

CLK to Data Out

CHQV

VAL

Max

11

CLK to Active

(Float to Active Delay)

(1)

t

Min

Max

Min

2

28

7

ns

t

ON

CHQX

CLK to Inactive

(Active to Float Delay)

t

CHQZ

OFF

t

AVCH

(2)

t

SU

Input Set-up Time

DVCH

t

CHAX

(2)

t

H

Min

0

ns

Input Hold Time

CHDX

Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec-

ification.

2. Applies to all inputs except CLK.

31/45

M50FW016

Figure 12. Reset AC Waveforms

RP, INIT

tPHWL, tPHGL, tPHFL

tPLPH

W, G, FWH4

RB

tPLRH

AI03420

Table 24. Reset AC Characteristics

Symbol

Parameter

Test Condition

Value

Unit

ns

t

RP or INIT Reset Pulse Width

Min

Max

100

30

PLPH

Program/Erase Inactive

Program/Erase Active

ns

t

RP or INIT Low to Reset

PLRH

µs

(1)

Rising edge only

Min

50

30

mV/ns

RP or INIT Slew Rate

t

RP or INIT High to FWH4 Low

FWH Interface only

µs

PHFL

t

RP High to Write Enable or Output

Enable Low

PHWL

A/A Mux Interface only

Min

50

µs

PHGL

Note: 1. See Chapter 4 of the PCI Specification.

32/45

M50FW016

Figure 13. A/A Mux Interface Read AC Waveforms

tAVAV

A0-A10

ROW ADDR VALID COLUMN ADDR VALID

NEXT ADDR VALID

tAVCL

tAVCH

tCLAX

tCHAX

RC

G

tCHQV

tGLQV

tGLQX

tGHQZ

tGHQX

VALID

DQ0-DQ7

W

tPHAV

RP

AI03406

Table 25. A/A Mux Interface Read AC Characteristics

Symbol

Parameter

Read Cycle Time

Test Condition

Value

Unit

ns

t

Min

250

50

AVAV

t

Row Address Valid to RC Low

ns

AVCL

t

RC Low to Row Address Transition

Column Address Valid to RC high

RC High to Column Address Transition

ns

CLAX

t

ns

AVCH

t

ns

CHAX

(1)

RC High to Output Valid

Max

150

ns

t

CHQV

(1)

Output Enable Low to Output Valid

RP High to Row Address Valid

Max

Min

Max

Min

50

1

ns

µs

ns

t

GLQV

t

PHAV

t

Output Enable Low to Output Transition

Output Enable High to Output Hi-Z

Output Hold from Output Enable High

0

GLQX

50

0

GHQZ

GHQX

t

Note: 1. G may be delayed up to t

– t

GLQV

after the rising edge of RC without impact on t

.

CHQV

33/45

M50FW016

Figure 14. A/A Mux Interface Write AC Waveforms

Write erase or

program setup

Write erase confirm or Automated erase

valid address and data or program delay

Read Status

Register Data

Ready to write

another command

A0-A10

RC

R1

C1

R2

C2

tCLAX

tAVCH

tAVCL

tCHAX

tWHWL

tWLWH

tCHWH

W

G

tVPHWH

tWHGL

tWHRL

RB

tQVVPL

V

PP

tDVWH

tWHDX

DQ0-DQ7

D

VALID SRD

IN1

IN2

AI04194

Table 26. A/A Mux Interface Write AC Characteristics

Symbol

Parameter

Test Condition

Value

100

50

Unit

t

Write Enable Low to Write Enable High

Data Valid to Write Enable High

Write Enable High to Data Transition

Row Address Valid to RC Low

Min

ns

WLWH

t

Min

DVWH

t

5

WHDX

t

50

AVCL

t

RC Low to Row Address Transition

Column Address Valid to RC High

RC High to Column Address Transition

Write Enable High to Write Enable Low

RC High to Write Enable High

50

CLAX

t

50

AVCH

t

50

CHAX

t

100

50

WHWL

t

CHWH

(1)

V

High to Write Enable High

Min

100

30

0

ns

t

PP

VPHWH

t

Write Enable High to Output Enable Low

Write Enable High to RB Low

WHGL

t

WHRL

(1,2)

QVVPL

Output Valid, RB High to V Low

0

t

PP

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

34/45

M50FW016

PACKAGE MECHANICAL

Figure 15. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

Note: Drawing is not to scale.

A1

α

L

Table 27. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.100

20.200

18.500

–

Typ

Max

0.0472

0.0059

0.0413

0.0106

0.0083

0.0039

0.7953

0.7283

–

A

A1

A2

B

0.050

0.950

0.170

0.100

0.0020

0.0374

0.0067

0.0039

C

CP

D

19.800

18.300

–

0.7795

0.7205

–

D1

e

0.500

0.0197

E

9.900

0.500

0°

10.100

0.700

5°

0.3898

0.0197

0°

0.3976

0.0276

5°

L

α

N

40

35/45

M50FW016

PART NUMBERING

Table 28. Ordering Information Scheme

Example:

M50FW016

N

1

T

G

Device Type

M50

Architecture

F = Firmware Hub Interface

Operating Voltage

W = 3.0 to 3.6V

Device Function

016 = 16 Mbit (2Mb x8), Uniform Block

Package

N = TSOP40: 10 x 20 mm

Device Grade

5 = Temperature range –20 to 85 °C.

Device tested with standard test flow

1 = Temperature range 0 to 70 °C.

Device tested with standard test flow

Option

blank = Standard Packing

T = Tape & Reel Packing

Plating Technology

blank = Standard SnPb plating

G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

36/45

M50FW016

APPENDIX A. FLOWCHARTS AND PSEUDO CODES

Figure 16. Program Flowchart and Pseudo Code

Start

Program command:

– write 40h or 10h

Write 40h or 10h

– write Address & Data

(memory enters read status state after

the Program command)

Write Address

& Data

do:

NO

–read Status Register if Program/Erase

Suspend command given execute

suspend program loop

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

V

Invalid

Error (1, 2)

If b3 = 1, V

invalid error:

– error handler

PP

b3 = 0

YES

Program

Error (1, 2)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

FWH

Interface

Only

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI03407

Note: 1. A Status check of b1 (Protected Block), b3 (V invalid) and b4 (Program Error) can be made after each Program operation by

PP

following the correct command sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

37/45

M50FW016

Figure 17. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Write 30h

Write Address 1

& Data 1 ⁽³⁾

Quadruple Byte Program command:

– write 30h

– write Address 1 & Data 1 ⁽³⁾

– write Address 2 & Data 2 ⁽³⁾

– write Address 3 & Data 3 ⁽³⁾

Write Address 2

& Data 2 ⁽³⁾

– write Address 4 & Data 4 ⁽³⁾

(memory enters read status state after

the Quadruple Byte Program command)

Write Address 3

& Data 3 ⁽³⁾

Write Address 4

& Data 4 ⁽³⁾

do:

NO

– read Status Register if Program/Erase

Suspend command given execute

suspend program loop

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

V

Invalid

Error (1, 2)

If b3 = 1, V

invalid error:

– error handler

PP

b3 = 0

YES

Program

Error (1, 2)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

End

AI03982

Note: 1. A Status check of b3 (V invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

PP

mand sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1.

38/45

M50FW016

Figure 18. Quadruple Byte Program Flowchart and Pseudo Code (FWH Interface Only)

Start

Write 30h

Write Start Address

and 4 Data Bytes ⁽³⁾

Quadruple Byte Program command:

– write 30h

– write Start Address and 4 Data Bytes ⁽³⁾

(memory enters read status state after

the Quadruple Byte Program command)

do:

NO

– read Status Register if Program/Erase

Suspend command given execute

suspend program loop

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

invalid error:

– error handler

PP

b3 = 0

YES

Error (1, 2)

Program

If b4 = 1, Program error:

– error handler

b4 = 0

Error (1, 2)

YES

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI05736B

Note: 1. A Status check of b3 (V invalid) and b4 (Program Error) can be made after each Program operation by following the correct com-

PP

mand sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. A1 and A0 are treated as Don’t Care. Starting at the Start Address, the first data byte is programmed at the address that has A1-

A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that has A1-A0 at 10, and the fourth at the address

that has A1-A0 at 11.

39/45

M50FW016

Figure 19. Program Suspend and Resume Flowchart, and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

– write 70h

Write 70h

do:

– read Status Register

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

b2 = 1

YES

Program Complete

If b2 = 0 Program completed

Write a read

Command

Read data from

another address

Program/Erase Resume command:

– write D0h to resume the program

– if the Program operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Program Continues

AI03408

40/45

M50FW016

Figure 20. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Start

Chip Erase command:

Write 80h

– write 80h

– write 10h

(memory enters read Status Register after

the Chip Erase command)

Write 10h

do:

– read Status Register

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

invalid error:

– error handler

PP

Error (1)

PP

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

Erase Error (1)

YES

End

AI04195

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

41/45

M50FW016

Figure 21. Block Erase Flowchart and Pseudo Code

Start

Block Erase command:

– write 20h

Write 20h

– write Block Address & D0h

(memory enters read Status Register after

the Block Erase command)

Write Block Address

& D0h

do:

– read Status Register

– if Program/Erase Suspend command

given execute suspend erase loop

NO

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

– error handler

PP

Error (1)

PP

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

Erase Error (1)

FWH

Interface

Only

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error:

– error handler

b1 = 0

YES

End

AI04196

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

42/45

M50FW016

Figure 22. Erase Suspend and Resume Flowchart, and Pseudo Code

Start

Write B0h

Program/Erase Suspend command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read Status Register

NO

b7 = 1

YES

while b7 = 1

b6 = 1

YES

Erase Complete

If b6 = 0, Erase completed

Read data from

another block

or

Program

Program/Erase Resume command:

– write D0h to resume erase

– if the Erase operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Write D0h

Write FFh

Read Data

Erase Continues

AI03410

43/45

M50FW016

REVISION HISTORY

Table 29. Document Revision History

Date

Version

Revision Details

May 2001

-01

First Issue

Added LPC Bus Read and Bus Write cycles

Added FWH 64 and 128 byte Bus Reading

October 2001

-02

21-Feb-2002

01-Mar-2002

30-Jul-2002

-03

-04

-05

Removed LPC Bus Read and Bus Write cycles

RFU pins must be left disconnected

Quadruple Byte Mode changed to 4/16/128 bytes

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 05 equals 5.0)

13-Feb-2003

5.1

Datasheet promoted from Product Preview to Preliminary Data status.

Document imported in new template and reformatted.

Temperature Range ordering information replaced by Device Grade, Standard

packing option added and Plating Technology added to Table 28., Ordering

12-Jul-2004

6.0

Information Scheme. T

parameter added to Table 16., Absolute Maximum

LEAD

Ratings and T

parameter removed. Pin 39 changed from V to RFU in Figure

CC

BIAS

4., TSOP Connections.

44/45

M50FW016

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany -

Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore -

Spain - Sweden - Switzerland - United Kingdom - United States

www.st.com

45/45


型号：	M50FW016N5T
厂家：	ST
描述：	16 Mbit 2Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory 16兆位的2Mb ×8 ，统一座3V供应固件集线器闪存闪存
文件：	总45页 (文件大小：674K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M50FW016N5T [STMICROELECTRONICS]

相关型号：

M50FW016N5TG

M50FW020K1

M50FW020K1T

M50FW020K5T

M50FW040

M50FW040K

M50FW040K1

M50FW040K1G

M50FW040K1T

M50FW040K1TG

M50FW040K5

M50FW040K5G