M54HC390 [STMICROELECTRONICS]
DUAL DECADE COUNTER; 双十进制计数器型号: | M54HC390 |
厂家: | ST |
描述: | DUAL DECADE COUNTER |
文件: | 总13页 (文件大小:268K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M54HC390
M74HC390
DUAL DECADE COUNTER
.
.
.
.
.
.
.
.
HIGH SPEED
fMAX = 84 MHz (TYP.) AT VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH
54/74LS390
ORDER CODES :
M54HC390F1R
M74HC390B1R
M74HC390M1R
M74HC390C1R
PIN CONNECTIONS (top view)
DESCRIPTION
The M54/74HC390 is a high speed CMOS DUAL
DECADE COUNTER fabricated in silicon gate
C2MOS technology. It has the same highspeed per-
formance of LSTTL combined with true CMOS low
power consumption.
This dual decade counter contains two independent
ripple carry counters. Each counter is composed of
a divide-by-two and divide-by-five counter. The
divide-by-two and divide-by-five counters can be
cascaded to form dual decade, dual biquinary, or
various combinations up to a single divide-by-100
counter.
Each 4-bit counter is incremented on the high to low
transition (negative edge) of the clock input, and
each has an independent clear input. When clear is
set low all four bits of each counter are set to low.
This enables count truncation and allows the im-
plementation of divide-by-N counter configurations.
NC =
No Inter-
nal Con-
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
February 1993
1/13
M54/M74HC390
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
OUTPUTS
COUNT
BCD COUNT *
BI-QUINARY **
QD
L
QC
L
QB
L
QA
QA
L
QD
L
QC
L
QB
L
0
1
2
3
4
5
6
7
8
9
L
H
L
L
L
L
L
L
L
H
L
L
L
H
H
L
L
L
H
H
L
L
L
H
L
L
L
H
L
L
H
H
H
H
L
L
H
L
L
L
H
L
H
H
H
H
H
L
L
L
H
H
L
L
L
H
L
L
H
L
L
H
H
L
H
H
L
H
L
L
L
H
H
INPUTS
OUTPUTS
CLOCK A
CLOCK B
CLEAR
QA
QB
QC
QD
X
X
X
H
L
L
L
L
L
L
BINARY COUNT UP
QUINARY COUNT UP
X
Note: * Output QA is connected to input CLOCK B for BCD count.
** Output QD is connected to inputCLOCK A for bi-quinary count.
2/13
M54/M74HC390
BLOCK DIAGRAM
LOGIC DIAGRAM
3/13
M54/M74HC390
TIMING CHART
(1) BCD COUNT SEQUENCE *
(2) BI-QUINARY COUNT SEQUENCE **
*OUTPUT QA IS CONNECTED TO INPUT CLOCK B
4/13
M54/M74HC390
PIN DESCRIPTION
IEC LOGIC SYMBOL
PIN No
SYMBOL
NAME AND FUNCTION
1, 15
1 CLOCK A Clock Input Divide by 2
2 CLOCK B Section (HIGH to LOW
Edge-triggered)
2, 14
1 CLEAR
2 CLEAR
Asynchronous Master
Reset Inputs
3, 5, 6, 7 1QA to 1QD Flip Flop Outputs
4, 12
1 CLOCK B Clock Input Divide by 5
2 CLOCK B Section (HIGH to LOW
Edge-triggered)
13, 11, 10, 9 2QA to 2QD Flip Flop Outputs
8
GND
VCC
Ground (0V)
16
Positive Supply Voltage
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
Unit
Supply Voltage
V
DC Input Voltage
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
V
V
VO
DC Output Voltage
IIK
DC Input Diode Current
DC Output Diode Current
DC Output Source Sink Current Per Output Pin
mA
mA
mA
mA
mW
oC
IOK
± 20
IO
± 25
ICC or IGND DC VCC or Ground Current
± 50
PD
Tstg
TL
Power Dissipation
500 (*)
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
oC
Absolute MaximumRatingsare those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2 to 6
Unit
V
Supply Voltage
Input Voltage
Output Voltage
0 to VCC
0 to VCC
V
VO
V
Top
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
oC
oC
tr, tf
Input Rise and Fall Time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
0 to 1000
0 to 500
0 to 400
ns
5/13
M54/M74HC390
DC SPECIFICATIONS
Test Conditions
VCC
Value
TA = 25 oC
54HC and 74HC
-40 to 85 oC -55 to 125 oC
Symbol
Parameter
Unit
74HC
54HC
(V)
Min. Typ. Max. Min. Max. Min. Max.
VIH
High Level Input
Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
VIL
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
VOH
High Level
Output Voltage
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
1.9
4.4
VI =
VIH
or
IO=-20 µA
V
V
5.9
5.9
VIL
IO=-4.0 mA 4.18 4.31
4.13
5.63
4.10
5.60
IO=-5.2 mA 5.68
5.8
0.0
0.0
0.0
VOL
Low Level Output 2.0
Voltage
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VI =
VIH
or
IO= 20 µA
4.5
6.0
4.5
6.0
0.1
0.1
VIL
IO= 4.0 mA
IO= 5.2 mA
0.17 0.26
0.18 0.26
±0.1
0.33
0.33
±1
0.40
0.40
±1
II
Input Leakage
6.0
VI = VCC or GND
µA
µA
Current
ICC
Quiescent Supply 6.0 VI = VCC or GND
Current
4
40
80
6/13
M54/M74HC390
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Test Conditions
Value
-40 to 85 oC -55 to 125 oC
74HC 54HC
TA = 25 oC
54HC and 74HC
Symbol
Parameter
Unit
VCC
(V)
Min. Typ. Max. Min. Max. Min. Max.
tTLH
tTHL
Output Transition
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
30
8
75
15
95
19
110
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
13
16
19
tPLH
tPHL
Propagation
Delay Time
(CLOCK A - QA)
42
14
12
45
15
13
108
36
31
72
24
20
45
15
13
17
65
79
17
67
79
24
6
120
24
150
30
180
36
20
26
31
tPLH
tPHL
Propagation
Delay Time
(CLOCK A - QB, QD)
120
24
150
30
180
36
20
26
31
tPLH
tPHL
Propagation
Delay Time
(CLOCK A - QC)
QA Connected
to CKB
280
56
350
70
420
84
48
60
71
tPLH
tPHL
Propagation
Delay Time
(CLOCK B - QC)
185
37
230
46
280
56
31
39
48
tPHL
fMAX
fMAX
Propagation
Delay Time
(CLEAR - Qn
125
25
155
31
190
38
21
26
32
Maximum Clock
Frequency
(CLOCK A - QA)
8.4
42
50
8.4
42
50
6.8
34
40
6.8
34
40
5.6
28
33
5.6
28
33
Maximum Clock
Frequency
(CLOCK B - QB)
tW(H)
tW(L)
Minimum Pulse
Wisth
(CLOCK)
75
15
13
75
15
13
25
5
95
19
16
95
19
16
30
6
110
22
19
110
22
19
35
7
5
t(W)H
tREM
CIN
Minimum Pulse
Wisth
(CLEAR)
24
6
5
Propagation
Delay Time
5
5
6
Input Capacitance
5
10
10
10
pF
pF
CPD (*) Power Dissipation
Capacitance
84
(*) CPD isdefined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the followingequation. ICC(opr) = CPD • VCC • fIN + ICC
7/13
M54/M74HC390
TEST CIRCUIT ICC (Opr.)
WHEN THE OUTPUTS DRIVE CAPACITIVE LOAD, TOTAL CURRENT CONSUMPTION IS TO BE A SUM OF THE VALUE CALCULATED
FROMCPD AND∆ICC OBTAINEDFROM THEFOLLOWING FORMULA.
fCK
2
Ca
2
2Cb Cc Cd
.
.
+
.
.
VCC
+
+
∆ICC = fCK VCC
5
5
5
Ca – Cd ARE THE CAPACITANCE AT QA QD OUTPUT.
SWITCHING CHARACTERISTICS TEST WAVEFORM
8/13
M54/M74HC390
Plastic DIP16 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
0.77
TYP.
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
9/13
M54/M74HC390
Ceramic DIP16/1 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
20
MIN.
MAX.
0.787
0.276
A
B
7
D
E
3.3
0.130
0.700
0.38
0.015
e3
F
17.78
2.29
0.4
2.79
0.55
1.52
0.31
1.27
10.3
8.05
5.08
0.090
0.016
0.046
0.009
0.020
0.110
0.022
0.060
0.012
0.050
0.406
0.317
0.200
G
H
L
1.17
0.22
0.51
M
N
P
7.8
0.307
Q
P053D
10/13
M54/M74HC390
SO16 (Narrow) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8° (max.)
P013H
11/13
M54/M74HC390
PLCC20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
9.78
8.89
4.2
TYP.
MAX.
10.03
9.04
MIN.
0.385
0.350
0.165
MAX.
0.395
0.356
0.180
A
B
D
4.57
d1
d2
E
2.54
0.56
0.100
0.022
7.37
8.38
0.290
0.330
0.004
e
1.27
5.08
0.38
0.050
0.200
0.015
e3
F
G
0.101
M
M1
1.27
1.14
0.050
0.045
P027A
12/13
M54/M74HC390
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
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13/13
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