M58BW016BB100ZA6F_技术文档

M58BW016BT, M58BW016BB

M58BW016DT, M58BW016DB

16 Mbit (512Kb x32, Boot Block, Burst)

3V Supply Flash Memories

PE4FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V

= 2.7V to 3.6V for Program, Erase and

DD

Read

– V

= V

= 2.4V to 3.6V for I/O Buffers

DDQIN

DDQ

– V = 12V for fast Program (optional)

PP

■ HIGH PERFORMANCE

– Access Time: 80, 90 and 100ns

PQFP80 (T)

– 56MHz Effective Zero Wait-State Burst Read

– Synchronous Burst Reads

– Asynchronous Page Reads

■ HARDWARE BLOCK PROTECTION

– WP pin Lock Program and Erase

■ SOFTWARE BLOCK PROTECTION

BGA

– Tuning Protection to Lock Program and

Erase with 64 bit User Programmable Pass-

word (M58BW016B version only)

LBGA80 (ZA)

10 x 8 ball array

■ OPTIMIZED for FDI DRIVERS

– Fast Program / Erase suspend latency

time < 6µs

– Common Flash Interface

■ MEMORY BLOCKS

– 8 Parameters Blocks (Top or Bottom)

– 31 Main Blocks

■ LOW POWER CONSUMPTION

– 5µA Typical Deep Power Down

– 60µA Typical Standby

– Automatic Standby after Asynchronous Read

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Top Device Code M58BW016xT: 8836h

– Bottom Device Code M58BW016xB: 8835h

May 2003

1/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. LBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. PQFP Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Tuning Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Top Boot Block Addresses, M58BW016BT, M58BW016DT . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Bottom Boot Block Addresses, M58BW016BB, M58BW016DB . . . . . . . . . . . . . . . . . . . 12

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable (GD).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Burst Clock (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Supply Voltage (V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DD)

Output Supply Voltage (V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DDQ

Input Supply Voltage (V

DDQIN

Program/Erase Supply Voltage (V ).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PP

Ground (V and V

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SSQ

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Asynchronous Read Electronic Signature Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Synchronous Burst Read Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

X-Latency Bits (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Wrap Burst Bit (M3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Tuning Protection Unlock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Tuning Protection Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 9. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 27

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program Status, Tuning Protection Unlock Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

V

PP

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Tuning Protection Status (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 7. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 9. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 34

Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 34

Figure 11. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 12. Asynchronous Write AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Asynchronous Latch Controlled Write AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics . . . . . . . . . . . . . . 38

Figure 14. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . 39

Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 15. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) . . . . . . . . . . . . . . . 40

Figure 16. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 41

Figure 17. Synchronous Burst Read - Burst Address Advance. . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 18. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Bottom View Package Outline . . . . 43

Table 22. LBGA80 10x12mm - 8x10 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . 43

Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline. . . . . . . . . . . . . . . . . . . . 44

Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data. . . . . . . . . . . . . 44

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

APPENDIX A. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 29. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

APPENDIX B. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 21. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 22. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 50

Figure 23. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 52

Figure 25. Unlock Device and Change Tuning Protection Code Flowchart . . . . . . . . . . . . . . . . . 53

4/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart. . . . . . . . . . . . . . . . 54

Figure 27. Unlock Device and Erase a Tuning Protected Block Flowchart . . . . . . . . . . . . . . . . . . 55

Figure 28. Power-up Sequence to Burst the Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 29. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . 57

Figure 30. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . 58

Figure 31. Command Interface and Program Erase Controller Flowchart (c) . . . . . . . . . . . . . . . . 59

Figure 32. Command Interface and Program Erase Controller Flowchart (d) . . . . . . . . . . . . . . . . 60

Figure 33. Command Interface and Program Erase Controller Flowchart (e) . . . . . . . . . . . . . . . . 61

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

SUMMARY DESCRIPTION

The M58BW016B/D is a 16Mbit non-volatile Flash

memory that can be erased electrically at the block

level and programmed in-system on a Double-

ter. The command set required to control the

memory is consistent with JEDEC standards.

Erase can be suspended in order to perform either

Read or Program in any other block and then re-

sumed. Program can be suspended to Read data

in any other block and then resumed. Each block

can be programmed and erased over 100,000 cy-

cles.

Word basis using a 2.7V to 3.6V V supply for the

DD

circuit and a V

supply down to 2.4V for the In-

DDQ

put and Output buffers. Optionally a 12V V sup-

PP

ply can be used to provide fast program and erase

for a limited time and number of program/erase cy-

cles.

All blocks are protected during power-up. The

M58BW016B features four different levels of block

protection to avoid unwanted program/erase oper-

ations. The WP pin offers an hardware protection

on two of the parameter blocks and all of the main

blocks. The Program and Erase commands can

be password protected by the Tuning Protection

command. All Program or Erase operations are

blocked when Reset, RP, is held low. The

M58BW016D offers the same protection features

with the exception of the Tuning Block Protection

which is disabled in the factory.

A Reset/Power-down mode is entered when the

RP input is Low. In this mode the power consump-

tion is lower than in the normal standby mode, the

device is write protected and both the Status and

the Burst Configuration Registers are cleared. A

recovery time is required when the RP input goes

High.

The devices support Asynchronous (Latch Con-

trolled and Page Read) and Synchronous Bus op-

erations. The Synchronous Burst Read Interface

allows a high data transfer rate controlled by the

Burst Clock, K, signal. It is capable of bursting

fixed or unlimited lengths of data. The burst type,

latency and length are configurable and can be

easily adapted to a large variety of system clock

frequencies and microprocessors. All Writes are

Asynchronous. On power-up the memory defaults

to Read mode with an Asynchronous Bus.

The device has a boot block architecture with an

array of 8 parameter block of 64Kb each and 31

main blocks of 512Kb each. The parameter blocks

can be located at the top of the address space,

M58BW016BT, M58BW016DT or at the bottom,

M58BW016BB, M58BW016DB.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a Program or Erase operation can be detected and

any error conditions identified in the Status Regis-

The memory is offered in PQFP80 (14 x 20mm)

and LBGA80 (1.0mm pitch) packages and it is

supplied with all the bits erased (set to ’1’).

6/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 1. Signal Names

Figure 2. Logic Diagram

A0-A18

Address inputs

DQ0-DQ7

Data Input/Output, Command Input

V

Data Input/Output, Burst Configuration

Register

V

DD DDQ DDQIN

PP

DQ8-DQ15

DQ16-DQ31 Data Input/Output

B

Burst Address Advance

Chip Enable

A0-A18

DQ0-DQ31

E

K

L

G

Output Enable

K

Burst Clock

M58BW016BT

M58BW016BB

M58BW016DT

M58BW016DB

E

L

Latch Enable

RP

G

R

Valid Data Ready (open drain output)

Reset/Power-down

Write Enable

RP

W

GD

WP

GD

W

Output Disable

Write Protect

WP

B

V

Supply Voltage

DD

V

Power Supply for Output Buffers

Power Supply for Input Buffers only

DDQ

V

DDQIN

PP

V

SSQ

SS

Optional Supply Voltage for Fast

Program and Fast Erase Operations

AI04155

V

Ground

SS

Input/Output Ground

Not Connected Internally

Don’t Use as Internally Connected

SSQ

NC

DU

7/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 3. LBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A15

A14

V

A6

A3

A2

DD

PP

SS

A16

A17

DQ3

A13

A18

A12

A11

DU

A9

A10

DU

A8

NC

A5

A7

A4

DU

A1

A0

DQ0

DQ4

DQ7

DQ8

DQ12

DQ14

RP

DU

DQ31

DQ28

DQ25

DQ21

DQ19

G

DQ30

DQ26

DQ24

DQ23

DQ18

R

DQ29

V

DQ2

DQ6

DQ10

DQ11

L

DQ1

DQ5

DQ9

WP

B

DQ27

NC

V

DDQ

V

SSQ

G

H

J

V

DQ22

DQ17

E

V

DDQ

DQ13

DQ15

DQ20

DQ16

DU

K

V

K

V

W

GD

DDQIN

SS

DD

AI04151b

8/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 4. PQFP Connections (Top view through package)

DQ16

DQ17

DQ18

DQ19

1

DQ15

DQ14

DQ13

DQ12

64

V

DDQ

SSQ

DDQ

V

SSQ

DQ20

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

M58BW016BT

M58BW016BB

M58BW016DT

12

53

M58BW016DB

V

DDQ

SSQ

DDQ

V

SSQ

DQ28

DQ3

DQ2

DQ1

DQ0

NC

DQ29

DQ30

DQ31

DU

A0

A18

A17

A16

A1

A2

41

24

AI04152b

9/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Block Protection

blocks from program or erase operations. It allows

the user to lock program and erase operations with

a user definable 64 bit code. It is only available on

the M58BW016B version.

The M58BW016B features four different levels of

block protection. The M58BW016D has the same

block protection with the exception of the Tuning

Block Protection, which is disabled in the factory.

The code is written once in the Tuning Protection

Register and cannot be erased. When shipped the

flash memory will have the Tuning Protection

Code bits set to ‘1'. The user can program a ‘0’ in

any of the 64 positions. Once programmed it is not

possible to reset a bit to ‘1’ as the cells cannot be

erased. The Tuning Protection Register can be

programmed at any moment (after providing the

correct code), however once all bits are set to ‘0’

the Tuning Protection Code can no longer be al-

tered.

■ Write Protect Pin, WP, - When WP is low, V ,

IL

all the lockable parameter blocks (two upper

(Top ) or lower (Bottom)) and all the main blocks

are protected. When WP is high (V ) all the

lockable parameter blocks and all the main

blocks are unprotected.

IH

■ Reset/Power-Down Pin, RP, - If the device is

held in reset mode (RP at V ), no program or

IL

erase operations can be performed on any

block.

The Tuning Protection Code locks the program

and erase operations of 2 parameter and 24 main

blocks, blocks 0, 1 and 15-38 for the bottom con-

figuration and the blocks 0-23, 37 and 38 for the

top configuration.

The tuning blocks are "locked" if the tuning protec-

tion code has not been provided, and “unlocked"

once the correct code has been provided. The tun-

ing blocks are locked after reset or power-up. The

tuning protection status can be monitored in the

Status Register. Refer to the Status Register sec-

tion.

Refer to the Command Interface section for the

Tuning Protection Block Unlock and Tuning Pro-

tection Program commands. See Appendix B, Fig-

ure 25, 26 and 27 for suggested flowcharts for

using the Tuning Block Protection commands. For

further information on the Tuning Block Protection

refer to Application Note, AN1361.

■ Tuning Block Protection: M58BW016B

features a 64 bit password protection for

program and erase operations for a fixed

number of blocks After power-up or reset the

device is tuning protected. An Unlock command

is provided to allow program or erase operations

in all the blocks.

After a device reset the first two kinds of block pro-

tection (WP, RP) can be combined to give a flexi-

ble block protection. They do not affect the Tuning

Block Protection. When the two protections are

disabled, WP and RP at V , the blocks locked by

IH

the Tuning Block Protection cannot be modified.

All blocks are protected during power-up.

Tuning Block Protection. The Tuning Block

Protection is a software feature to protect certain

10/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 2. Top Boot Block Addresses,

M58BW016BT, M58BW016DT

(1)

#

Size (Kbit)

Address Range

TP

yes

19

18

17

16

15

14

13

12

11

10

9

512

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

04000h-07FFFh

00000h-03FFFh

(1)

#

Size (Kbit)

64

Address Range

7F800h-7FFFFh

7F000h-7F7FFh

7E800h-7EFFFh

7E000h-7E7FFh

7D800h-7DFFFh

7D000h-7D7FFh

7C800h-7CFFFh

7C000h-7C7FFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

TP

yes

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

64

yes

no

64

no

64

no

64

no

64

no

64

no

512

no

8

no

7

no

6

no

5

no

4

no

3

yes

2

1

0

Note: 1. TP = Tuning Protected Block, only available for the

M58BW016B.

11/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 3. Bottom Boot Block Addresses,

(1)

#

Size (Kbit)

Address Range

TP

yes

M58BW016BB, M58BW016DB

19

18

17

16

15

14

13

12

11

10

9

512

64

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

04000h-07FFFh

03800h-03FFFh

03000h-037FFh

02800h-02FFFh

02000h-027FFh

01800h-01FFFh

01000h-017FFh

00800h-00FFFh

00000h-007FFh

(1)

#

Size (Kbit)

512

Address Range

7C000h-7FFFFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

TP

yes

no

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

yes

no

8

no

7

no

6

64

no

5

64

no

4

64

no

3

64

no

2

64

no

1

64

yes

0

64

Note: 1. TP = Tuning Protected Block, only available for the

M58BW016B.

12/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

ly of Output Enable. The Output Disable pin must

be connected to an external pull-up resistor as

there is no internal pull-up resistor to drive the pin.

Address Inputs (A0-A18). The Address Inputs

are used to select the cells to access in the mem-

ory array during Bus Read operations either to

read or to program data to. During Bus Write oper-

ations they control the commands sent to the

Command Interface of the internal state machine.

Chip Enable must be low when selecting the ad-

dresses.

Write Enable (W). The Write Enable, W, input

controls writing to the Command Interface, Input

Address and Data latches. Both addresses and

data can be latched on the rising edge of Write En-

able (also see Latch Enable, L).

Reset/Power-Down (RP). The

Reset/Power-

Down, RP, is used to apply a hardware reset to the

memory. A hardware reset is achieved by holding

The address inputs are latched on the rising edge

of Latch Enable L or Burst Clock K, whichever oc-

curs first, in a read operation.The address inputs

are latched on the rising edge of Chip Enable,

Write Enable or Latch Enable, whichever occurs

first in a Write operation. The address latch is

Reset/Power-Down Low, V , for at least t

.

IL

PLPH

Writing is inhibited to protect data, the Command

Interface and the Program/Erase Controller are re-

set. The Status Register information is cleared and

power consumption is reduced to deep power-

down level. The device acts as deselected, that is

the data outputs are high impedance.

transparent when Latch Enable is low, V . The ad-

IL

dress is internally latched in an Erase or Program

operation.

After Reset/Power-Down goes High, V , the

memory will be ready for Bus Read operations af-

IH

Data Inputs/Outputs (DQ0-DQ31). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation, or are used

to input the data during a program operation. Dur-

ing Bus Write operations they represent the com-

mands sent to the Command Interface of the

internal state machine. When used to input data or

Write commands they are latched on the rising

edge of Write Enable or Chip Enable, whichever

occurs first.

ter a delay of t

or Bus Write operations after

PHEL

t

.

PHWL

If Reset/Power-Down goes low, V , during a Block

Erase, a Program or a Tuning Protection Program

the operation is aborted, in a time of t

mum, and data is altered and may be corrupted.

IL

maxi-

PLRH

During Power-up power should be applied simulta-

neously to V

and V

with RP held at V .

DDQ(IN) IL

DD

When the supplies are stable RP is taken to V .

Output Enable, G, Chip Enable, E, and Write En-

able, W, should be held at V during power-up.

IH

When Chip Enable and Output Enable are both

IH

low, V , and Output Disable is at V the data bus

IL

IH,

In an application, it is recommended to associate

Reset/Power-Down pin, RP, with the reset signal

of the microprocessor. Otherwise, if a reset opera-

tion occurs while the memory is performing an

erase or program operation, the memory may out-

put the Status Register information instead of be-

ing initialized to the default Asynchronous

Random Read.

outputs data from the memory array, the Electron-

ic Signature, the CFI Information or the contents of

the Status Register. The data bus is high imped-

ance when the device is deselected with Chip En-

able at V , Output Enable at V , Output Disable

IH

at V or Reset/Power-Down at V . The Status

IL

Register content is output on DQ0-DQ7 and DQ8-

DQ31 are at V .

IL

See Table 21 and Figure 18, Reset, Power-Down

and Power-up Characteristics, for more details.

Chip Enable (E). The Chip Enable, E, input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. Chip Enable, E, at

Latch Enable (L). The Bus Interface can be con-

figured to latch the Address Inputs on the rising

edge of Latch Enable, L, for Asynchronous Latch

Enable Controlled Read or Write or Synchronous

Burst Read operations. In Synchronous Burst

Read operations the address is latched on the ac-

tive edge of the Clock when Latch Enable is Low,

V

deselects the memory and reduces the power

IH

consumption to the Standby level.

Output Enable (G). The Output Enable, G, gates

the outputs through the data output buffers during

a read operation, when Output Disable GD is at

V . When Output Enable G is at V , the outputs

IH

V . Once latched, the addresses may change

IL

are high impedance independently of Output Dis-

able.

Output Disable (GD). The Output Disable, GD,

without affecting the address used by the memory.

When Latch Enable is Low, V , the latch is trans-

parent. Latch Enable, L, can remain at V for

Asynchronous Random Read and Write opera-

tions.

Burst Clock (K). The Burst Clock, K, is used to

synchronize the memory with the external bus dur-

IL

deactivates the data output buffers. When Output

Disable, GD, is at V , the outputs are driven by

IH

the Output Enable. When Output Disable, GD, is at

V , the outputs are high impedance independent-

IL

13/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

ing Synchronous Burst Read operations. Bus sig-

nals are latched on the active edge of the Clock.

The Clock can be configured to have an active ris-

ing or falling edge. In Synchronous Burst Read

mode the address is latched on the first active

top configuration) parameter blocks and all main

blocks are locked. When Write Protect WP is at

all the blocks can be programmed or erased, if

V

IH

no other protection is used.

Supply Voltage (V ). The Supply Voltage, V

,

DD

clock edge when Latch Enable is low, V , or on

IL

is the core power supply. All internal circuits draw

the rising edge of Latch Enable, whichever occurs

first.

their current from the V

pin, including the Pro-

DD

gram/Erase Controller.

During Asynchronous bus operations the Clock is

not used.

Output Supply Voltage (V

). The Output Sup-

DDQ

ply Voltage, V

, is the output buffer power supply

DDQ

Burst Address Advance (B). The Burst Address

Advance, B, controls the advancing of the address

by the internal address counter during Synchro-

nous Burst Read operations.

for all operations (Read, Program and Erase) used

for DQ0-DQ31 when used as outputs.

Input Supply Voltage (V

). The Input Sup-

DDQIN

ply Voltage, V

, is the power supply for all input

DDIN

Burst Address Advance, B, is only sampled on the

active clock edge of the Clock when the X-latency

time has expired. If Burst Address Advance is

signal. Input signals are: K, B, L, W, GD, G, E, A0-

A18 and D0-D31, when used as inputs.

Program/Erase Supply Voltage (V ). The Pro-

PP

Low, V , the internal address counter advances. If

IL

gram/Erase Supply Voltage, V , is used for pro-

PP

Burst Address Advance is High, V , the internal

IH

gram and erase operations. The memory normally

address counter does not change; the same data

remains on the Data Inputs/Outputs and Burst Ad-

dress Advance is not sampled until the Y-latency

expires.

executes program and erase operations at V

PP1

voltage levels. In a manufacturing environment,

programming may be speeded up by applying a

higher voltage level, V

, to the V pin.

PPH

PP

The Burst Address Advance, B, may be tied to V .

IL

The voltage level V

may be applied for a total

PPH

Valid Data Ready (R). The Valid Data Ready

output, R, is an open drain output that can be

used, during Synchronous Burst Read operations,

to identify if the memory is ready to output data or

not. The Valid Data Ready output can be config-

ured to be active on the clock edge of the invalid

data read cycle or one cycle before. Valid Data

of 80 hours over a maximum of 1000 cycles.

Stressing the device beyond these limits could

damage the device.

Ground (V and V

). The Ground V is the

SS

SSQ

reference for the internal supply voltage V . The

DD

Ground V

input supplies V

is the reference for the output and

SSQ

and V

. It is essential to

DDQ,

DDQIN

Ready, at V , indicates that new data is or will be

IH

connect V and V

together.

SS

SSQ

available. When Valid Data Ready is Low, V , the

IL

Note: A 0.1µF capacitor should be connected

between the Supply Voltages, V , V and

previous data outputs remain active.

DD

DDQ

In all Asynchronous operations, Valid Data Ready

is high-impedance. It may be tied to other compo-

nents with the same Valid Data Ready signal to

create a unique system Ready signal. The Valid

Data Ready output has an internal pull-up resistor

V

and the Grounds, V and V

to decou-

DDIN

SS

SSQ

ple the current surges from the power supply.

The PCB track widths must be sufficient to car-

ry the currents required during all operations

of the parts, see Table 15, DC Characteristics,

for maximum current supply requirements.

of around 1 MΩ powered from V

, designers

DDQ

should use an external pull-up resistor of the cor-

rect value to meet the external timing require-

Don’t Use (DU). This pin should not be used as it

is internally connected. Its voltage level can be be-

ments for Valid Data Ready going to V .

IH

tween V and V

or leave it unconnected.

SS

DDQ

Write Protect (WP). The Write Protect, WP, pro-

vides protection against program or erase opera-

Not Connected (NC). This pin is not physically

connected to the device.

tions. When Write Protect, WP, is at V the first

IL

two (in the bottom configuration) or last two (in the

14/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

BUS OPERATIONS

Each bus operations that controls the memory is

described in this section, see Tables 4, 5 and 6

Bus Operations, for a summary. The bus operation

is selected through the Burst Configuration Regis-

ter; the bits in this register are described at the end

of this section.

Note that, since the Latch Enable input is transpar-

ent when set Low, V , Asynchronous Bus Read

IL

operations can be performed when the memory is

configured for Asynchronous Latch Enable bus

operations by holding Latch Enable Low, V

throughout the bus operation.

IL

On Power-up or after a Hardware Reset the mem-

ory defaults to Asynchronous Bus Read and Asyn-

chronous Bus Write, no other bus operation can

be performed until the Burst Control Register has

been configured.

Asynchronous Page Read. Asynchronous

Page Read operations are used to read from sev-

eral addresses within the same memory page.

Each memory page is 4 Double-Words and is ad-

dressed by the address inputs A0 and A1.

The Electronic Signature, CFI or Status Register

will be read in asynchronous mode regardless of

the Burst Control Register settings.

Data is read internally and stored in the Page Buff-

er. Valid bus operations are the same as Asyn-

chronous Bus Read operations but with different

timings. The first read operation within the page

has identical timings, subsequent reads within the

same page have much shorter access times. If the

page changes then the normal, longer timings ap-

ply again. Page Read does not support Latched

Controlled Read.

See Figure 11, Asynchronous Page Read AC

Waveforms and Table 18, Asynchronous Page

Read AC Characteristics for details on when the

outputs become valid.

Asynchronous Bus Write. Asynchronous Bus

Write operations write to the Command Interface

in order to send commands to the memory or to

latch addresses and input data to program. Bus

Write operations are asynchronous, the clock, K,

is don’t care during Bus Write operations.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

Asynchronous Bus Operations

For asynchronous bus operations refer to Table 4

together with the following text.

Asynchronous Bus Read. Asynchronous Bus

Read operations read from the memory cells, or

specific registers (Electronic Signature, Status

Register, CFI and Burst Configuration Register) in

the Command Interface. A valid bus operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V , to Chip Enable

IL

and Output Enable and keeping Write Enable and

Output Disable High, V . The Data Inputs/Out-

IH

puts will output the value, see Figure 9, Asynchro-

nous Bus Read AC Waveforms, and Table 16,

Asynchronous Bus Read AC Characteristics, for

details of when the output becomes valid.

Asynchronous Read is the default read mode

which the device enters on power-up or on return

from Reset/Power-Down.

A valid Asynchronous Bus Write operation begins

by setting the desired address on the Address In-

puts, and setting Chip Enable, Write Enable and

Latch Enable Low, V , and Output Enable High,

IL

V , or Output Disable Low, V . The Address In-

IH

IL

puts are latched by the Command Interface on the

rising edge of Chip Enable or Write Enable, which-

ever occurs first. Commands and Input Data are

latched on the rising edge of Chip Enable, E, or

Write Enable, W, whichever occurs first. Output

Enable must remain High, and Output Disable

Low, during the whole Asynchronous Bus Write

operation.

See Figure 12, Asynchronous Write AC Wave-

forms, and Table 19, Asynchronous Write and

Latch Controlled Write AC Characteristics, for de-

tails of the timing requirements.

Asynchronous Latch Controlled Bus Read.

Asynchronous Latch Controlled Bus Read opera-

tions read from the memory cells or specific regis-

ters in the Command Interface. The address is

latched in the memory before the value is output

on the data bus, allowing the address to change

during the cycle without affecting the address that

the memory uses.

A valid bus operation involves setting the desired

address on the Address Inputs, setting Chip En-

able and Latch Enable Low, V and keeping Write

IL

Asynchronous Latch Controlled Bus Write.

Enable High, V ; the address is latched on the ris-

IH

Asynchronous Latch Controlled Bus Write opera-

tions write to the Command Interface in order to

send commands to the memory or to latch ad-

dresses and input data to program. Bus Write op-

erations are asynchronous, the clock, K, is don’t

care during Bus Write operations.

ing edge of Latch Enable. Once latched, the Ad-

dress Inputs can change. Set Output Enable Low,

V , to read the data on the Data Inputs/Outputs;

IL

see Figure 1, Asynchronous Latch Controlled Bus

Read AC Waveforms and Table 17, Asynchro-

nous Latch Controlled Bus Read AC Characteris-

tics for details on when the output becomes valid.

A valid Asynchronous Latch Controlled Bus Write

operation begins by setting the desired address on

15/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

the Address Inputs and pulsing Latch Enable Low,

enters Auto Low Power mode where the internal

V . The Address Inputs are latched by the Com-

Supply Current is reduced to the Auto-Standby

Supply Current. The Data Inputs/Outputs will still

output data if a Bus Read operation is in progress.

Automatic Low Power is only available in Asyn-

chronous Read modes.

IL

mand Interface on the rising edge of Latch Enable,

Write Enable or Chip Enable, whichever occurs

first. Commands and Input Data are latched on the

rising edge of Chip Enable, E, or Write Enable, W,

whichever occurs first. Output Enable must remain

High, and Output Disable Low, during the whole

Asynchronous Bus Write operation.

See Figure 13, Asynchronous Latch Controlled

Write AC Waveforms, and Table 19, Asynchro-

nous Write and Latch Controlled Write AC Charac-

teristics, for details of the timing requirements.

Power-Down. The memory is in Power-down

when Reset/Power-Down, RP, is at V . The pow-

IL

er consumption is reduced to the power-down lev-

el and the outputs are high impedance,

independent of the Chip Enable, E, Output Enable,

G, Output Disable, GD, or Write Enable, W, inputs.

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory allowing programming equipment or ap-

plications to automatically match their interface to

the characteristics of the memory. The Electronic

Signature is output by giving the Read Electronic

Signature command. The manufacturer code is

Output Disable. The data outputs are high im-

pedance when the Output Enable, G, is at V or

IH

Output Disable, GD, is at V .

IL

Standby. When Chip Enable is High, V , and the

IH

Program/Erase Controller is idle, the memory en-

ters Standby mode, the power consumption is re-

duced to the standby level and the Data Inputs/

Outputs pins are placed in the high impedance

state regardless of Output Enable, Write Enable or

Output Disable inputs.

Automatic Low Power. If there is no change in

the state of the bus for a short period of time during

Asynchronous Bus Read operations the memory

output when all the Address inputs are at V . The

IL

device code is output when A1 is at V and all the

IH

other address pins are at V . See Table 5. Issue

IL

a Read Memory Array command to return to Read

mode.

Table 4. Asynchronous Bus Operations

Bus Operation

Step

E

G

GD

W

RP

L

A0-A18

Address

X

DQ0-DQ31

Data Output

High Z

V

IL

V

IH

V

IH

V

IL

Asynchronous Bus Read

IL

IH

V

IH

V

IH

V

Address Latch

Read

IH

IL

Asynchronous Latch

Controlled Bus Read

V

IH

V

IH

Data Output

IL

IH

Asynchronous Page

Read

V

IH

V

IH

X

Address

Data Output

IL

V

IH

V

IL

Asynchronous Bus Write

X

Address

Data Input

High Z

IL

IH

IL

V

IH

V

IH

V

Address Latch

Write

Address

IL

IH

IL

Asynchronous Latch

Controlled Bus Write

V

IH

X

Data Input

High Z

IL

IH

V

IH

V

IH

Output Disable, G

Output Disable, GD

Standby

X

V

IL

V

IH

X

High Z

IL

V

IH

X

High Z

IH

V

IL

Reset/Power-Down

Note: X = Don’t Care

X

High Z

16/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 5. Asynchronous Read Electronic Signature Operation

Code

Device

E

G

GD

W

A18-A0

00000h

00001h

DQ31-DQ0

00000020h

00008836h

V

Manufacturer

All

IL

IH

(1)

V

IH

M58BW016xT

Device

V

00001h

00005h

00008835h

IH

M58BW016xB

Burst Configuration

Register

(2)

V

IL

V

IL

IH

BCR

Note: 1. x= B or D version of the device.

2. BCR= Burst Configuration Register.

Synchronous Bus Operations

For synchronous bus operations refer to Table 6

together with the following text.

When Valid Data Ready is Low on the active clock

edge, no new data is available and the memory

does not increment the internal address counter at

the active clock edge even if Burst Address Ad-

vance, B, is Low.

Synchronous Burst Read. Synchronous Burst

Read operations are used to read from the memo-

ry at specific times synchronized to an external ref-

erence clock. The burst type, length and latency

can be configured. The different configurations for

Synchronous Burst Read operations are de-

scribed in the Burst Configuration Register sec-

tion. Refer to Figures 5 and 6 for examples of

synchronous burst operations.

Valid Data Ready may be configured (by bit M8 of

Burst Configuration Register) to be valid immedi-

ately at the valid clock edge or one data cycle be-

fore the valid clock edge.

Synchronous Burst Read will be suspended if

Burst Address Advance, B, goes High, V .

IH

In continuous burst read, one burst read operation

can access the entire memory sequentially by

If Output Enable is at V and Output Disable is at

IL

V , the last data is still valid.

IH

keeping the Burst Address Advance B at V for

IL

If Output Enable, G, is at V or Output Disable,

IH

the appropriate number of clock cycles. At the end

of the memory address space the burst read re-

starts from the beginning at address 000000h.

A valid Synchronous Burst Read operation begins

when the Burst Clock is active and Chip Enable

GD, is at V , but the Burst Address Advance, B, is

IL

at V the internal Burst Address Counter is incre-

IL

mented at each Burst Clock K valid edge.

The Synchronous Burst Read timing diagrams

and AC Characteristics are described in the AC

and DC Parameters section. See Figures 14, 15,

16 and 17, and Table 20.

and Latch Enable are Low, V . The burst start ad-

IL

dress is latched and loaded into the internal Burst

Address Counter on the valid Burst Clock K edge

(rising or falling depending on the value of M6) or

on the rising edge of Latch Enable, whichever oc-

curs first.

After an initial memory latency time, the memory

outputs data each clock cycle (or two clock cycles

depending on the value of M9). The Burst Address

Advance B input controls the memory burst output.

The second burst output is on the next clock valid

edge after the Burst Address Advance B has been

pulled Low.

Synchronous Burst Read Suspend. During

a

Synchronous Burst Read operation it is possible to

suspend the operation, freeing the data bus for

other higher priority devices.

A valid Synchronous Burst Read operation is sus-

pended when both Output Enable and Burst Ad-

dress Advance are High, V . The Burst Address

IH

Advance going High, V , stops the burst counter

IH

and the Output Enable going High, V , inhibits the

IH

data outputs. The Synchronous Burst Read oper-

ation can be resumed by setting Output Enable

Low.

Valid Data Ready, R, monitors if the memory burst

boundary is exceeded and the Burst Controller of

the microprocessor needs to insert wait states.

17/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 6. Synchronous Burst Read Bus Operations

A0-A18

DQ0-DQ31

(3)

Bus Operation

Step

Address Latch

E

G

GD RP

L

B

K

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

X

T

X

Address Input

Data Output

High Z

IL

IH

V

IH

V

Read

T

X

T

X

IL

V

IH

Read Suspend

Read Resume

Burst Address Advance

Read Abort, E

Read Abort, RP

X

IH

Synchronous Burst

Read

V

IL

V

IH

V

Data Output

High Z

IL

V

IH

X

High Z

IH

V

IL

X

High Z

Note: 1. X = Don't Care, V or V

.

IH

IL

2. M15 = 0, Bit M15 is in the Burst Configuration Register.

3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.

18/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Burst Configuration Register

Burst Type Bit (M7). The Burst Type bit is used

to configure the sequence of addresses read as

The Burst Configuration Register is used to config-

ure the type of bus access that the memory will

perform.

sequential or interleaved. When the Burst Type bit

is ’0’ the memory outputs from interleaved ad-

dresses; when the Burst Type bit is ’1’ the memory

outputs from sequential addresses. See Tables 8,

Burst Type Definition, for the sequence of ad-

dresses output from a given starting address in

each mode.

Valid Clock Edge Bit (M6). The Valid Clock

Edge bit, M6, is used to configure the active edge

of the Clock, K, during Synchronous Burst Read

operations. When the Valid Clock Edge bit is ’0’

the falling edge of the Clock is the active edge;

when the Valid Clock Edge bit is ’1’ the rising edge

of the Clock is active.

Wrap Burst Bit (M3). The burst reads can be

confined inside the 4 or 8 Double-Word boundary

(wrap) or overcome the boundary (no wrap). The

Wrap Burst bit is used to select between wrap and

no wrap. When the Wrap Burst bit is set to ‘0’ the

burst read wraps; when it is set to ‘1’ the burst read

does not wrap.

The Burst Configuration Register is set through

the Command Interface and will retain its informa-

tion until it is re-configured, the device is reset, or

the device goes into Reset/Power-Down mode.

The Burst Configuration Register bits are de-

scribed in Table 7. They specify the selection of

the burst length, burst type, burst X and Y laten-

cies and the Read operation. Refer to Figures 5

and 6 for examples of synchronous burst configu-

rations.

Read Select Bit (M15). The Read Select bit,

M15, is used to switch between asynchronous and

synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

On reset or power-up the Read Select bit is set

to’1’ for asynchronous accesses.

X-Latency Bits (M14-M11). The X-Latency bits

are used during Synchronous Bus Read opera-

tions to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table 7,

Burst Configuration Register. The X-Latency bits

should also be selected in conjunction with Table ,

Burst Performance to ensure valid settings.

Burst Length Bit (M2-M0). The Burst Length bits

set the maximum number of Double-Words that

can be output during a Synchronous Burst Read

operation before the address wraps. Burst lengths

of 4 or 8 are available for both the Sequential and

Interleaved burst types, and a continuous burst is

available for the Sequential type.

Table 7, Burst Configuration Register gives the

valid combinations of the Burst Length bits that the

memory accepts; Table 8, Burst Type Definition,

gives the sequence of addresses output from a

given starting address for each length.

If either a Continuous or a No Wrap Burst Read

has been initiated the device will output data syn-

chronously. Depending on the starting address,

the device activates the Valid Data Ready output

to indicate that a delay is necessary before the

data is output. If the starting address is aligned to

an 8 Double Word boundary, the continuous burst

mode will run without activating the Valid Data

Ready output. If the starting address is not aligned

to an 8 Double Word boundary, Valid Data Ready

is activated to indicate that the device needs an in-

ternal delay to read the successive words in the ar-

ray.

Y-Latency Bit (M9). The Y-Latency bit is used

during Synchronous Bus Read operations to set

the number of clock cycles between consecutive

reads. The Y-Latency value depends on both the

X-Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each

clock cycle; when the Y-Latency is 2 the data

changes every second clock cycle. See Table 7,

Burst Configuration Register and Table , Burst

Performance, for valid combinations of the Y-La-

tency, the X-Latency and the Clock frequency.

Valid Data Ready Bit (M8). The

Valid

Data

Ready bit controls the timing of the Valid Data

Ready output pin, R. When the Valid Data Ready

bit is ’0’ the Valid Data Ready output pin is driven

Low for the active clock edge when invalid data is

output on the bus. When the Valid Data Ready bit

is ’1’ the Valid Data Ready output pin is driven Low

one clock cycle prior to invalid data being output

on the bus.

M10, M5 and M4 are reserved for future use.

19/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 7. Burst Configuration Register

Bit

Description

Value

Description

0

1

Synchronous Burst Read

M15

M14

Read Select

Asynchronous Read (Default at power-on)

Reserved

001

010

011

100

101

110

(1)

4, 4-1-1-1

5, 5-1-1-1, 5-2-2-2

6, 6-1-1-1, 6-2-2-2

7, 7-1-1-1, 7-2-2-2

8, 8-1-1-1, 8-2-2-2

Reserved

(2)

M13-M11

X-Latency

M10

M9

0

1

0

1

0

1

0

1

One Burst Clock cycle

Two Burst Clock cycles

R valid Low during valid Burst Clock edge

R valid Low one data cycle before valid Burst Clock edge

Interleaved

(3)

Y-Latency

M8

M7

Valid Data Ready

Burst Type

Sequential

Falling Burst Clock edge

Rising Burst Clock edge

Reserved

M6

M5-M4

M3

Valid Clock Edge

0

Wrap

Wrapping

1

No wrap

001

010

111

4 Double-Words

M2-M0

Burst Length

8 Double-Words

Continuous

Note: 1. 4 - 2 - 2 - 2 is not allowed.

2. X latencies can be calculated as: (t

is the clock period).

– t

+ t

) + t

QVKH

< (X -1) t (X is an integer number from 4 to 8 and t

SYSTEM MARGIN K. K

AVQV

LLKH

3. Y latencies can be calculated as: t

+ t

< Y t

QVKH K.

KHQV

SYSTEM MARGIN

4. t

is the time margin required for the calculation.

SYSTEM MARGIN

20/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 8. Burst Type Definition

Starting

x4

x8

M 3

Continuous

Address Sequential Interleaved

Sequential

Interleaved

0

1

0

1

2

3

4

5

6

7

8

0

1

2

3

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

–

0-1-2-3

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

–

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-7-8-9-10..

1-2-3-4-5-6-7-8-9-10-11..

2-3-4-5-6-7-8-9-10-11-12..

3-4-5-6-7-8-9-10-11-12-13..

4-5-6-7-8-9-10-11-2-13-14..

5-6-7-8-9-10-11-12-13-14..

6-7-8-9-10-11-12-13-14-15..

7-8-9-10-11-12-13-14-15-16..

8-9-10-11-12-13-14-15-16-17..

0-1-2-3-4-5-6-7-8-9-10..

1-0-3-2

1-0-3-2-5-4-7-6

2-3-0-1

2-3-0-1-6-7-4-5

3-2-1-0

3-2-1-0-7-6-5-4

–

4-5-6-7-0-1-2-3

–

5-4-7-6-1-0-3-2

–

6-7-4-5-2-3-0-1

–

7-6-5-4-3-2-1-0

–

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

1-2-3-4-5-6-7-8-9-10-11..

2-3-4-5-6-7-8-9-10-11-12..

3-4-5-6-7-8-9-10-11-12-13..

4-5-6-7-8-9-10-

11

1

4

5

6

7

8

4-5-6-7

5-6-7-8

–

4-5-6-7-8-9-10-11-12-13-14..

5-6-7-8-9-10-11-12-13-14..

6-7-8-9-10-11-12-13-14-15..

7-8-9-10-11-12-13-14-15-16..

8-9-10-11-12-13-14-15-16-17..

5-6-7-8-9-10-11-

12

6-7-8-9-10-11-

12-13

6-7-8-9

7-8-9-10-11-12-

13-14

7-8-9-10

8-9-10-11

8-9-10-11-12-13-

14-15

21/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 5. Example Burst Configuration X-1-1-1

0

1

2

3

4

5

6

7

8

9

K

ADD

VALID

L

DQ

VALID

4-1-1-1

5-1-1-1

DQ

VALID

DQ

VALID

6-1-1-1

7-1-1-1

8-1-1-1

VALID

AI03841

Figure 6. Example Burst Configuration X-2-2-2

0

1

2

3

4

5

6

7

8

9

K

ADD

VALID

L

DQ

NV

VALID

NV

VALID

NV

VALID

5-2-2-2

DQ

NV

VALID

NV

VALID

NV

VALID

NV

VALID

NV

6-2-2-2

7-2-2-2

8-2-2-2

VALID

NV=NOT VALID

AI04406b

22/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. The Commands are summarized in Table

9, Commands. Refer to Table 9 in conjunction with

the text descriptions below.

able and Output Enable at V and Output Disable

IL

at V .

IH

The content of the Status Register may also be

read at the completion of a Program, Erase or

Suspend operation. During a Block Erase, Pro-

gram, Tuning Protection Program or Tuning Pro-

tection Unlock command, DQ7 indicates the

Program/Erase Controller status. It is valid until

the operation is completed or suspended.

See the section on the Status Register and Table

11 for details on the definitions of the Status Reg-

ister bits

Read Memory Array Command

The Read Memory Array command returns the

memory to Read mode. One Bus Write cycle is re-

quired to issue the Read Memory Array command

and return the memory to Read mode. Subse-

quent read operations will output the addressed

memory array data. Once the command is issued

the memory remains in Read mode until another

command is issued. From Read mode Bus Read

commands will access the memory array.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One Bus Write is required to issue the Clear

Status Register command. Once the command is

issued the memory returns to its previous mode,

subsequent Bus Read operations continue to out-

put the same data.

The bits in the Status Register are sticky and do

not automatically return to ‘0’ when a new Pro-

gram, Erase, Block Protect or Block Unprotect

command is issued. If any error occurs then it is

essential to clear any error bits in the Status Reg-

ister by issuing the Clear Status Register com-

mand before attempting a new Program, Erase or

Resume command.

Read Electronic Signature Command

The Read Electronic Signature command is used

to read the Manufacturer Code, the Device Code

or the Burst Configuration Register. One Bus Write

cycle is required to issue the Read Electronic Sig-

nature command. Once the command is issued

subsequent Bus Read operations, depending on

the address specified, read the Manufacturer

Code, the Device Code or the Burst Configuration

Register until another command is issued; see Ta-

ble 5, Read Electronic Signature.

Read Query Command.

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Area. One Bus Write cycle is required to issue the

Read Query Command. Once the command is is-

sued subsequent Bus Read operations, depend-

ing on the address specified, read from the

Common Flash Interface Memory Area. See Ap-

pendix A, Tables 25, 26, 27, 28 and 29 for details

on the information contained in the Common Flash

Interface (CFI) memory area.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all of the bits in the block to ‘1’. All

previous data in the block is lost. If the block is pro-

tected then the Erase operation will abort, the data

in the block will not be changed and the Status

Register will output the error.

Two Bus Write operations are required to issue the

command; the first write cycle sets up the Block

Erase command, the second write cycle confirms

the Block erase command and latches the block

address in the internal state machine and starts

the Program/Erase Controller. The sequence is

aborted if the Confirm command is not given and

the device will output the Status Register Data with

bits 4 and 5 set to '1'.

Once the command is issued subsequent Bus

Read operations read the Status Register. See the

section on the Status Register for details on the

definitions of the Status Register bits. During the

Erase operation the memory will only accept the

Read Status Register command and the Program/

Erase Suspend command. All other commands

will be ignored.

Read Status Register Command

The Read Status Register command is used to

read the Status Register. One Bus Write cycle is

required to issue the Read Status Register com-

mand. Once the command is issued subsequent

Bus Read operations read the Status Register un-

til another command is issued.

The Status Register information is present on the

output data bus (DQ1-DQ7) when Chip Enable E

and Output Enable G are at V and Output Dis-

IL

able is at V .

IH

An interactive update of the Status Register bits is

possible by toggling Output Enable or Output Dis-

able. It is also possible during a Program or Erase

operation, by disactivating the device with Chip

The command can be executed using either V

DD

Enable at V and then reactivating it with Chip En-

(for a normal erase operation) or V

(for a fast

IH

PP

erase operation). If V is in the V

range when

23/63

PP

PPH

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

the command is issued then a fast erase operation

will be executed, otherwise the operation will use

Program/Erase Controller. Once the command is

issued it is necessary to poll the Program/Erase

Controller Status bit (bit 7) to find out when the

Program/Erase Controller has paused; no other

commands will be accepted until the Program/

Erase Controller has paused. After the Program/

Erase Controller has paused, the memory will con-

tinue to output the Status Register until another

command is issued.

During the polling period between issuing the Pro-

gram/Erase Suspend command and the Program/

Erase Controller pausing it is possible for the op-

eration to complete. Once the Program/Erase

Controller Status bit (bit 7) indicates that the Pro-

gram/Erase Controller is no longer active, the Pro-

gram Suspend Status bit (bit 2) or the Erase

Suspend Status bit (bit 6) can be used to deter-

mine if the operation has completed or is suspend-

ed. For timing on the delay between issuing the

Program/Erase Suspend command and the Pro-

gram/Erase Controller pausing see Table 10.

V

. If V goes below the V Lockout Voltage,

DD

PP PP

, during a fast erase the operation aborts,

PPLK

the Status Register V Status bit is set to ‘1’ and

PP

the command must be re-issued.

Typical Erase times are given in Table 10.

See Appendix B, Figure 23, Block Erase Flowchart

and Pseudo Code, for a suggested flowchart on

using the Block Erase command.

Program Command.

The Program command is used to program the

memory array. Two Bus Write operations are re-

quired to issue the command; the first write cycle

sets up the Program command, the second write

cycle latches the address and data to be pro-

grammed in the internal state machine and starts

the Program/Erase Controller. A program opera-

tion can be aborted by writing FFFFFFFFh to any

address after the program set-up command has

been given.

During Program/Erase Suspend the Read Memo-

ry Array, Read Status Register, Read Electronic

Signature, Read Query and Program/Erase Re-

sume commands will be accepted by the Com-

mand Interface. Additionally, if the suspended

operation was Erase then the Program and the

Program Suspend commands will also be accept-

ed. When a program operation is completed inside

a Block Erase Suspend the Read Memory Array

command must be issued to reset the device in

Read mode, then the Erase Resume command

can be issued to complete the whole sequence.

Only the blocks not being erased may be read or

programmed correctly.

Once the command is issued subsequent Bus

Read operations read the Status Register. See the

section on the Status Register for details on the

definitions of the Status Register bits. During the

Program operation the memory will only accept

the Read Status Register command and the Pro-

gram/Erase Suspend command. All other com-

mands will be ignored.

If Reset/Power-down, RP, falls to V during pro-

IL

gramming the operation will be aborted.

The command can be executed using either V

DD

(for a normal program operation) or V (for a fast

PP

program operation). If V

is in the V

range

PP

PPH

See Appendix B, Figure 22, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

24, Erase Suspend & Resume Flowchart and

Pseudo Code, for suggested flowcharts on using

the Program/Erase Suspend command.

when the command is issued then a fast program

operation will be executed, otherwise the opera-

tion will use V . If V goes below the V Lock-

DD

PP

out Voltage, V

, during a fast program the

PPLK

operation aborts and the Status Register V Sta-

PP

tus bit is set to ‘1’. As data integrity cannot be guar-

anteed when the program operation is aborted, the

memory block must be erased and repro-

grammed.

See Appendix B, Figure 21, Program Flowchart

and Pseudo Code, for a suggested flowchart on

using the Program command.

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the Pro-

gram/Erase Resume command.

See Appendix B, Figure 22, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

24, Erase Suspend & Resume Flowchart and

Pseudo Code, for suggested flowcharts on using

the Program/Erase Resume command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. The com-

mand will only be accepted during a Program or

Erase operation. It can be issued at any time dur-

ing a program or erase operation. The command

is ignored if the device is already in suspend

mode.

Set Burst Configuration Register Command.

The Set Burst Configuration Register command is

used to write a new value to the Burst Configura-

tion Control Register which defines the burst

length, type, X and Y latencies, Synchronous/

One Bus Write cycle is required to issue the Pro-

gram/Erase Suspend command and pause the

24/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Asynchronous Read mode and the valid Clock

edge configuration.

Device locked means that the 64 bit password is

wrong. If the unlock operation is attempted using a

wrong code on an already unlocked device, the

device becomes locked. Status register bit 4 is set

to '1' if there has been a verify failure.

Two Bus Write cycles are required to issue the Set

Burst Configuration Register command. The first

cycle writes the setup command and the address

corresponding to the Set Burst Configuration Reg-

ister content. The second cycle writes the Burst

Configuration Register data and the confirm com-

mand. Once the command is issued the memory

returns to Read mode as if a Read Memory Array

command had been issued.

Unlocking aborts if V drops out of the allowed

PP

range or RP goes to V .

IL

Once the device is successfully unlocked, a Read

Memory Array command must be issued to return

the memory to read mode before issuing any other

commands. The user can then program or erase

The value for the Burst Configuration Register is

always presented on A0-A15. M0 is on A0, M1 on

A1, etc.; the other address bits are ignored.

all blocks, depending on WP status and V level.

PP

At this point, it is also possible to configure a new

protection code. To write a new protection code

into the device tuning register, the user must per-

form the Tuning Protection Program sequence.

The device can be re-locked with a reset or power-

down.

Tuning Protection Unlock Command

The Tuning Protection Unlock command unlocks

the tuning protected blocks by writing the 64bit

Tuning Protection Code (M58BW016B only). After

a reset or power-up the blocks are locked and so

a Tuning Protection Unlock command must be is-

sued to allow program or erase operations on tun-

ing protected block or to program a new Tuning

Protection Code. Read operations output the Sta-

tus Register content after the unlock operation has

started.

See Appendix B, Figure 25, 26 and 27 for suggest-

ed flowcharts for using the Tuning Protection Un-

lock command.

Tuning Protection Program Command.

The Tuning Protection Program command is used

to program a new Tuning Protection Code which

can be configured by the designer of the applica-

tion (M58BW016B only). The device should be un-

locked by the Tuning Protection Unlock command

before issuing the Tuning Protection Program

command.

The Tuning Protection Code is composed of 64

bits, but the data bus is 32 bits wide so four (2 x 2)

write cycles are required to unlock the device.

■ The first write cycle issues the Tuning

Read operations output the Status Register con-

tent after the program operation has started.

The Tuning Protection Code is composed of 64

bits, but the data bus is 32 bits wide so four (2 x 2)

write cycles are required to program the code.

Protection Unlock Setup command (0x78).

■ The second write cycle inputs the first 32 bits of

the tuning protection code on the data bus, at

address 0x00000.

Bit 7 of the Status Register should now be

checked to verify that the device has successfully

stored the first part of the code in the internal reg-

ister. If b7 = ‘1’, the device is ready to accept the

second part of the code. This does not mean that

the first 32 bits match the tuning protection code,

simply that it was correctly stored for the compar-

ing. If b7 = ‘0’, the user must wait for this bit setting

(refer to write cycle AC timings).

■ The first write cycle issues the Tuning

Protection Program Setup command (0x48).

■ The second write cycle inputs the first 32 bits of

the new tuning protection code on the data bus,

at address 0x00000.

Bit 7 of the Status Register should now be

checked to verify that the device has successfully

stored the first part of the code in the internal reg-

ister. If b7 = ‘1’, the device is ready to accept the

second part of the code. If b7 = ‘0’, the user must

wait for this bit setting (refer to write cycle AC tim-

ings).

■ The third write cycle re-issues the Tuning

Protection Unlock Setup command (0x78).

■ The fourth write cycle inputs the second 32 bits

of the code at address 0x00001.

■ The third write cycle re-issues the Tuning

Bit 7 of the Status Register should again be

checked to verify that the device has successfully

stored the second part of the code. When the de-

vice is ready (b7 = ‘1’), the tuning protection status

can be monitored on Status Register bit0. If b0 =

‘0’ the device is locked; b0 = ‘1’ the device is un-

locked. If the device is still locked a Read Memory

Array command must be issued before re-issuing

the Tuning Protection Unlock command.

Protection Program Setup command (0x48).

■ The fourth write cycle inputs the second 32 bits

of the new code at address 0x00001.

Bit 7 of the Status Register should again be

checked to verify that the device has successfully

stored the second part of the code. When the de-

vice is ready (b7 = ‘1’). After completion Status

25/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Register bit 4 is set to '1' if there has been a pro-

gram failure.

any other commands. Once the code has been

changed a device reset or power-down will make

the protection active with the new code.

Programming aborts if V

drops out of the al-

PP

lowed range or RP goes to V .

A Read Memory Array command must be issued

to return the memory to read mode before issuing

See Appendix B, Figure 25, 26 and 27 for suggest-

ed flowcharts for using the Tuning Protection Pro-

gram command.

IL

Table 9. Commands

Bus Operations

Command

1st Cycle

2nd Cycle

Addr. Data Op. Addr. Data Op. Addr. Data

FFh Read RA RD

3rd Cycle

4th Cycle

Op. Addr. Data Op.

Read Memory Array

≥ 2 Write

X

Read Electronic Signature

(Manufacturer Code)

90h Read 00000h 20h

90h Read 00001h IDh

Read Electronic Signature

(Device Code)

≥ 2 Write

X

Read Electronic Signature

(Burst Configuration

Register)

90h Read 00005h BCRh

Read Status Register

Read Query

2

Write

X

70h Read

X

SRDh

QDh

≥ 2 Write

98h Read QAh

Clear Status Register

Block Erase

1

2

Write

50h

20h Write BAh

D0h

PD

40h

Program

2

Write

X

Write

PA

10h

B0h

D0h

Program/Erase Suspend

Program/Erase Resume

1

Write

X

Set Burst Configuration

Register

2

Write

X

60h Write BCRh 03h

(2)

Tuning Protection

Program

4

Write

X

48h Write TPAh TPCh Write

78h Write TPAh TPCh Write

X

48h Write TPAh TPCh

78h Write TPAh TPCh

(2)

Tuning Protection Unlock

Note: 1. X Don’t Care; RA Read Address, RD Read Data, ID Device Code, SRD Status Register Data, PA Program Address; PD Program

Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Burst Configuration Register value, TPA = Tuning

Protection Address, TPC = Tuning Protection Code.

2. Cycles 1 and 2 input the first 32 bits of the code, cycles 3 and 4 the second 32 bits of the code.

26/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 10. Program, Erase Times and Program Erase Endurance Cycles

M58BW016B/D

Parameters

Unit

Min

Typ

Max

V

PP

= V

V

= 12V

V

PP

= V

V

PP

= 12V

DD

PP

DD

Parameter Block (64Kb) Program

Main Block (512Kb) Program

Parameter Block Erase

0.030

0.23

0.8

0.016

0.060

0.46

1.8

0.032

s

0.13

0.64

0.9

0.26

1.5

s

Main Block Erase

1.5

3

1.8

s

Program Suspend Latency Time

Erase Suspend Latency Time

Program/Erase Cycles (per Block)

3

10

30

µs

10

µs

100,000

cycles

Note: T = –40 to 125°C, V = 2.7V to 3.6V, V

= 2.4V to V

DD

A

DD

DDQ

27/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

STATUS REGISTER

The Status Register provides information on the

current or previous Program, Erase, Block Protect

or Tuning Protection operation. The various bits in

the Status Register convey information and errors

on the operation. They are output on DQ7-DQ0.

To read the Status Register the Read Status Reg-

ister command can be issued. The Status Register

is automatically read after Program, Erase, Block

Protect, Program/Erase Resume commands. The

Status Register can be read from any address.

and the memory is waiting for a Program/Erase

Resume command.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit 5)

The Erase Status bit can be used to identify if the

memory has failed to verify that the block has

erased correctly. The Erase Status bit should be

read once the Program/Erase Controller Status bit

is High (Program/Erase Controller inactive).

When the Erase Status bit is set to ‘0’, the memory

has successfully verified that the block has erased

correctly. When the Erase Status bit is set to ‘1’,

the Program/Erase Controller has applied the

maximum number of pulses to the block and still

failed to verify that the block has erased correctly.

Once set to ‘1’, the Erase Status bit can only be re-

set to ‘0’ by a Clear Status Register command or a

hardware reset. If set to ‘1’ it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status, Tuning Protection Unlock

Status (Bit 4)

The Program Status and Tuning Protection Unlock

Status bit is used to identify a Program failure or a

Tuning Protection Code verify failure. Bit4 should

be read once the Program/Erase Controller Status

bit is High (Program/Erase Controller inactive).

When bit4 is set to ‘0’ the memory has successful-

ly verified that the device has programmed cor-

rectly or that the correct Tuning Protection Code

has been written. When bit4 is set to ‘1’ the device

has failed to verify that the data has been pro-

grammed correctly or that the correct Tuning Pro-

tection code has been written.

Once set to 1’, the Program Status bit can only be

reset to ‘0’ by a Clear Status Register command or

a hardware reset. If set to ‘1’ it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

The contents of the Status Register can be updat-

ed during an erase or program operation by tog-

gling the Output Enable or Output Disable pins or

by dis-activating (Chip Enable, V ) and then reac-

IH

tivating (Chip Enable and Output Enable, V , and

IL

Output Disable, V .) the device.

IH

The Status Register bits are summarized in Table

11, Status Register Bits. Refer to Table 11 in con-

junction with the following text descriptions.

Program/Erase Controller Status (Bit 7)

The Program/Erase Controller Status bit indicates

whether the Program/Erase Controller is active or

inactive. When the Program/Erase Controller Sta-

tus bit is set to ‘0’, the Program/Erase Controller is

active; when bit7 is set to ‘1’, the Program/Erase

Controller is inactive.

The Program/Erase Controller Status is set to ‘0’

immediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is set to ‘1’.

During Program and Erase operations the Pro-

gram/Erase Controller Status bit can be polled to

find the end of the operation. The other bits in the

Status Register should not be tested until the Pro-

gram/Erase Controller completes the operation

and the bit is set to ‘1’.

After the Program/Erase Controller completes its

operation the Erase Status (bit5), Program Status

and Tuning Protection Unlock status (bit4) bits

should be tested for errors.

V

Status (Bit 3)

PP

Erase Suspend Status (Bit 6)

The V Status bit can be used to identify an in-

PP

The Erase Suspend Status bit indicates that an

Erase operation has been suspended and is wait-

ing to be resumed. The Erase Suspend Status

should only be considered valid when the Pro-

gram/Erase Controller Status bit is set to ‘1’ (Pro-

gram/Erase Controller inactive); after a Program/

Erase Suspend command is issued the memory

may still complete the operation rather than enter-

ing the Suspend mode.

When the Erase Suspend Status bit is set to ‘0’,

the Program/Erase Controller is active or has com-

pleted its operation; when the bit is set to ‘1’, a Pro-

gram/Erase Suspend command has been issued

valid voltage on the V pin during fast program

PP

and erase operations. The V pin is only sampled

PP

at the beginning of a program or erase operation.

Indeterminate results can occur if V becomes in-

PP

valid during a fast Program or Erase operation.

When the V Status bit is set to ‘0’, the voltage on

PP

the V pin was sampled at a valid voltage; when

PP

the V Status bit is set to ‘1’, the V pin has a

PP

voltage that is below the V Lockout Voltage, V

PP

P-

.

PLK

Once set to ‘1’, the V Status bit can only be reset

PP

to ‘0’ by a Clear Status Register command or a

hardware reset. If set to ‘1’ it should be reset be-

28/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

When the Block Protection Status bit is set to ‘0’,

no Program or Erase operations have been at-

tempted to protected blocks since the last Clear

Status Register command or hardware reset;

when the Block Protection Status bit is set to ‘1’, a

Program or Erase operation has been attempted

on a protected block.

Once set to ‘1’, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set to ‘1’ it should be

reset before a new Program or Erase command is

issued, otherwise the new command will appear to

fail.

Program Suspend Status (Bit 2)

The Program Suspend Status bit indicates that a

Program operation has been suspended and is

waiting to be resumed. The Program Suspend

Status should only be considered valid when the

Program/Erase Controller Status bit is set to ‘1’

(Program/Erase Controller inactive); after a Pro-

gram/Erase Suspend command is issued the

memory may still complete the operation rather

than entering the Suspend mode.

When the Program Suspend Status bit is set to ‘0’,

the Program/Erase Controller is active or has com-

pleted its operation; when the bit is set to ‘1’, a Pro-

gram/Erase Suspend command has been issued

and the memory is waiting for a Program/Erase

Resume command.

Tuning Protection Status (Bit 0)

The Tuning Protection Status bit indicates if the

device is locked (Tuning Protection is enabled) or

unlocked (Tuning Protection is disabled).

When the Tuning Protection Status bit is set to ‘0’

the device is locked, when it is set to ‘1’ the device

is unlocked. After a reset or power-up the device is

locked and so bit0 is set to ‘0’.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns to

‘0’.

Block Protection Status (Bit 1)

The Tuning Protection Status bit is set to ‘1’ for the

M58BW016D version.

The Block Protection Status bit can be used to

identify if a Program or Erase operation has tried

to modify the contents of a protected block.

Table 11. Status Register Bits

Bit

Name

Logic Level

Definition

7

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

Ready

Program/Erase Controller Status

Busy

6

5

4

3

Suspended

Erase Suspend Status

Erase Status

In Progress or Completed

Erase Error

Erase Success

Program Error

Program Status,

Tuning Protection Unlock Status

Program Success

V

Invalid, Abort

OK

PP

V

PP

Status

PP

2

1

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on Protected Block,

Abort

’1’

Erase/Program in a Protected

Block

’0’

’1’

’0’

No Operations to Protected Sectors

(1)

0

Tuning Protection Disabled

Tuning Protection Status

Tuning Protection Enabled

Note: 1. For the M58BW016D version the Tuning Protection Status bit is always set to ‘1’.

29/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

MAXIMUM RATING

Stressing the device above the ratings listed in Ta-

ble 12, Absolute Maximum Ratings, may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 12. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

–40

–55

Max

125

155

T

Temperature Under Bias

°C

BIAS

T

Storage Temperature

Input or Output Voltage

STG

V

+0.6

DDQ

V

–0.6

V

IO

+0.6

DDQIN

V

, V

V

Supply Voltage

–0.6

4.2

V

DD DDQ, DDQIN

(1)

V

Program Voltage

PP

13.5

Note: Cumulative time at a high voltage level of 13.5V should not exceed 80 hours on V pin.

PP

30/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 13,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 13. Operating and AC Measurement Conditions

Parameter

Value

Units

Min

2.7

Max

Supply Voltage (V

)

3.6

V

DD

Input/Output Supply Voltage (V

)

V

DD

2.4

DDQ

Grade 6

Grade 3

–40

90

°C

pF

ns

V

Ambient Temperature (T )

A

125

Load Capacitance (C )

60

L

Clock Rise and Fall Times

Input Rise and Fall Times

Input Pulses Voltages

4

0 to V

DDQ

V

/2

DDQ

Input and Output Timing Ref. Voltages

V

Figure 7. AC Measurement Input Output

Waveform

Figure 8. AC Measurement Load Circuit

1.3V

V

DDQ

V

1N914

DDQIN

V

/2

DDQ

V

DDQIN

0V

3.3kΩ

AI04153

DEVICE

UNDER

TEST

OUT

Note: V = V

.

DDQ

DD

C

L

C

includes JIG capacitance

L

AI04154

Table 14. Device Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Typ

6

Max

8

Unit

pF

C

IN

V

= 0V

IN

C

OUT

V

OUT

8

12

pF

Note: 1. T = 25°C, f = 1 MHz

A

2. Sampled only, not 100% tested.

31/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Table 15. DC Characteristics

Symbol

Parameter

Input Leakage Current

Test Condition

Min

Max

±1

Unit

µA

I

0V≤V ≤V

DDQ

LI

IN

I

0V≤V

≤V

Output Leakage Current

Supply Current (Random Read)

±5

µA

LO

OUT DDQ

I

E = V , G = V , f

= 6MHz

20

mA

DD

IL

IH add

E = V , G = V , f

=

IL

IH clock

I

Supply Current (Burst Read)

Supply Current (Standby)

30

60

30

mA

µA

mA

DDB

56MHz

E = RP = V ± 0.2V

DD

I

DD1

E = V ± 0.2V,

SS

Supply Current (Auto Low-Power)

Supply Current (Reset/Power-down)

RP = V ± 0.2V

DD

I

RP = V ± 0.2V

DD2

SS

Supply Current (Program or Erase,

Set Lock Bit, Erase Lock Bit)

Program, Block Erase in

progress

DD3

Supply Current

(Erase/Program Suspend)

I

E = V

40

µA

DD4

IH

I

V

≥ V

≤V

Program Current (Read or Standby)

Program Current (Power-down)

± 30

± 5

200

20

µA

mA

µA

mA

V

PP

PP1

I

V

PP

PP1

PP2

PP1

I

RP = V

IL

Program Current (Program)

Program in Progress

V

= V

PP

PP1

PPH

PP1

PPH

I

PP3

PP4

V

PP

V

200

20

PP

Program Current (Erase)

Erase in Progress

I

PP

V

0.2V

DDQIN

Input Low Voltage

–0.5

IL

0.8V

V +0.3

DDQ

Input High Voltage (for DQ lines)

V

IH

DDQIN

Input High Voltage (for Input only

lines)

V

0.8V

3.6

V

I

= 100µA

OL

Output Low Voltage

0.1

V

OL

V

I

= –100µA

V

–0.1

Output High Voltage CMOS

OH

DDQ

Program Voltage

(Program or Erase operations)

V

2.7

11.4

3.6

12.6

2.2

V

PP1

Program Voltage

(Program or Erase operations)

PPH

V

DD

Supply Voltage (Erase and

V

LKO

Program lockout)

V

PP

Supply Voltage (Erase and

V

PPLK

11.4

Program lockout)

32/63

M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB

Figure 9. Asynchronous Bus Read AC Waveforms

tAVAV

A0-A18

VALID

tAVQV

tEHLX

tLLEL

L

tELQX

tAXQX

tELQV

E

tGLQX

tEHQX

tGLQX

tGLQV

tEHQX

tEHQZ

G

GD

tGHQX

tGHQZ

DQ0-DQ31

OUTPUT


型号：	M58BW016BB100ZA6F
厂家：	ST
描述：	暂无描述闪存存储内存集成电路
文件：	总63页 (文件大小：843K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58BW016BB100ZA6F [STMICROELECTRONICS]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E