M58BW16FT5ZA3T_技术文档

M58BW16F

M58BW32F

16 or 32 Mbit (x32, Boot Block, Burst)

3.3V supply Flash memories

Preliminary Data

Features

■ Supply voltage

– V = 2.7V to 3.6V (45ns) or

DD

V

= 2.5V to 3.3V (55ns)

DD

– V

= V

= 2.4V to 3.6V for I/O

DDQIN

DDQ

Buffers

■ High performance

– Access times: 45 and 55ns

– Synchronous Burst Reads

PQFP80 (T)

– 75MHz Effective Zero Wait-State Burst

Read

– Asynchronous Page Reads

BGA

■ M58BW32F memory organization:

– Eight 64 Kbit small parameter blocks

– Four 128 Kbit large parameter blocks

– Sixty-two 512 Kbit main blocks

LBGA80 (ZA)

10 x 8 ball array

■ M58BW16F memory organization:

– Eight 64 Kbit parameter blocks

– Thirty-one 512 Kbit main blocks

■ Hardware block protection

■ Low power consumption

– WP pin to protect any block combination

from Program and Erase operations

– 100µA typical Standby current

■ Electronic signature

– PEN signal for Program/Erase Enable

– Manufacturer Code: 0020h

■ Irreversible Modify protection (OTP like) on 128

– Top Device Codes:

M58BW32FT: 8838h

M58BW16FT: 883Ah

Kbits:

– Block 1 (bottom device) or Block 72 (top

device) in the M58BW32F

– Bottom Device Codes:

M58BW32FB: 8837h

M58BW16FB: 8839h

– Blocks 2 & 3 (bottom device) or Blocks 36 &

35 (top device) in the M58BW16F

■ Security

■ Automotive Device Grade 3:

– Temperature: ^–40 to 125°C

– Automotive grade certified

– 64-bit Unique Device Identifier (UID)

■ Fast programming

– Write to Buffer and Program capability

■ Optimized for FDI drivers

– Common Flash Interface (CFI)

– Fast Program/Erase Suspend feature in

each block

November 2006

Rev 2

1/81

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

1

Contents

M58BW16F, M58BW32F

Contents

1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1

Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2

Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Address Inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Inputs/Outputs (DQ0-DQ31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Output Disable (GD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Reset/Power-Down (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Enable (PEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.10 Burst Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.11 Burst Address Advance (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.12 Valid Data Ready (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.13 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.14 Supply Voltage (V_{DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23}

2.15 Output Supply Voltage (V_DDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.16 Input Supply Voltage (V_DDQIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.17 Ground (V_SSand V_SSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.18 Don’t Use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.19 Not Connected (NC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3

Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1

Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

3.1.6

Asynchronous Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . 24

Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Asynchronous Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . 25

Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/81

M58BW16F, M58BW32F

Contents

3.1.7

3.1.8

Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2

3.3

Synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.2.1

3.2.2

Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

3.3.7

Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Standby Disable Bit (M14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

X-Latency Bits (M13-M11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Y-Latency Bit (M9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Valid Data Ready Bit (M8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Wrap Burst Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Burst Length Bit (M2-M0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4

Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Erase All Main Blocks command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.10 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.11 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.12 Set Burst Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . 37

4.13 Set Block Protection Configuration Register command . . . . . . . . . . . . . . 37

4.14 Clear Block Protection Configuration Register command . . . . . . . . . . . . 37

5

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1

5.2

5.3

5.4

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Program/ Write to Buffer and Program Status (Bit 4) . . . . . . . . . . . . . . . . 41

3/81

Contents

M58BW16F, M58BW32F

5.4.1

PEN Status (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.5

5.6

5.7

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6

7

8

9

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Appendix A Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4/81

M58BW16F, M58BW32F

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

M58BW32F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

M58BW32F Bottom Boot Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

M58BW16F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

M58BW16F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Synchronous Burst Read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Burst Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Program, Erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Asynchronous Bus Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Asynchronous Page Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Asynchronous Write and Latch controlled Write AC characteristics. . . . . . . . . . . . . . . . . . 53

Synchronous Burst Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Reset, Power-Down and Power-up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

LBGA80 10 × 12mm - 8 × 10 active ball array, 1mm pitch, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PQFP80 - 80 lead Plastic Quad Flat Pack, package mechanical data. . . . . . . . . . . . . . . . 63

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

CFI - Query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

CFI - Device voltage and timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

M58BW16F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

M58BW16F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

M58BW32F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

M58BW32F Extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

5/81

List of figures

M58BW16F, M58BW32F

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

LBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PQFP connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Example burst configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AC measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Asynchronous Bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Asynchronous Latch controlled bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 47

Asynchronous Chip Enable controlled bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . 48

Figure 10. Asynchronous Address controlled bus Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 11. Asynchronous Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 12. Asynchronous Write AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 13. Asynchronous Latch controlled Write AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from ’n’ clock rising edge). 54

Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from ’n’ clock rising edge) . 55

Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid

from ’n’ clock rising edge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 17. Synchronous Burst Read (data valid from ’n’ clock rising edge). . . . . . . . . . . . . . . . . . . . . 57

Figure 18. Synchronous Burst Read - valid data ready output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 19. Synchronous Burst Read - burst address advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 20. Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 21. Reset, Power-Down and Power-up AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 22. LBGA80 10 × 12mm - 8 × 10 ball array, 1mm pitch, bottom view package outline . . . . . . 61

Figure 23. PQFP80 - 80 lead Plastic Quad Flat Pack, package outline . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 24. Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 25. Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 26. Block Erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 27. Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 28. Power-up sequence followed by Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 29. Command Interface and Program Erase Controller flowchart (a). . . . . . . . . . . . . . . . . . . . 70

Figure 30. Command Interface and Program Erase Controller flowchart (b). . . . . . . . . . . . . . . . . . . . 71

Figure 31. Command Interface and Program Erase Controller flowchart (c). . . . . . . . . . . . . . . . . . . . 72

Figure 32. Command Interface and Program Erase Controller flowchart (d). . . . . . . . . . . . . . . . . . . . 73

Figure 33. Command Interface and Program Erase Controller flowchart (e). . . . . . . . . . . . . . . . . . . . 74

6/81

M58BW16F, M58BW32F

Description

1

Description

The M58BW16F and M58BW32F are 16 and 32 Mbit non-volatile Flash memories,

respectively. They can be erased electrically at block level and programmed in-system on a

Double-Word basis using a 2.7V to 3.6V or 2.5V to 3.3V V supply for the circuit and a

DD

2.4V to 3.6V V

supply voltage for the Input and Output buffers.

DDQ

In the rest of the document the M58BW16F and M58BW32F will be referred to as

M58BWxxF unless otherwise specified.

The devices support Asynchronous (Latch Controlled and Page Read) and Synchronous

Bus operations. The Synchronous Burst Read Interface allows a high data transfer rate

controlled by the Burst Clock signal, K. It is capable of bursting fixed or unlimited lengths of

data. The burst type, latency and length are configurable and can be easily adapted to a

large variety of system clock frequencies and microprocessors. All Write operations are

Asynchronous. On power-up the memory defaults to Read mode with an Asynchronous

Bus.

The device features an asymmetrical block architecture:

■

The M58BW32F has an array of 62 main blocks of 512 Kbits each, plus 4 large

parameter blocks of 128Kbits each and 8 small parameter blocks of 64 Kbits each. The

large and small parameter blocks are located either at the top (M58BW32FT) or at the

bottom (M58BW32FB) of the address space. The first large parameter block is referred

to as Boot Block and can be used either to store a boot code or parameters. The

memory array organization is detailed in Table 2: M58BW32F top boot block addresses

and Table 3: M58BW32F Bottom Boot Block Addresses.

■

The M58BW16F has an array of 8 parameter blocks of 64Kb each and 31 main blocks

of 512Kb each. In the M58BW16FT the parameter blocks are located at the top of the

address space whereas in the M58BW16FB, they are located at the bottom. The

memory array organization is detailed in Table 4: M58BW16F top boot block addresses

and Table 5: M58BW16F bottom boot block addresses.

Program and Erase commands are written to the Command Interface of the memory. An on-

chip Program/Erase Controller simplifies the process of programming or erasing the

memory by taking care of all of the special operations that are required to update the

memory contents. The end of a Program or Erase operation can be detected and any error

conditions identified in the Status Register. The command set required to control the

memory is consistent with JEDEC standards.

Erase can be suspended in order to perform either Read or Program in any other block, and

then resumed. Program can be suspended to Read data in any other block, and then

resumed. Each block can be programmed and erased over 100,000 cycles.

7/81

Description

M58BW16F, M58BW32F

All blocks are protected during power-up. The M58BWxxF features five different levels of

hardware and software block protection to avoid unwanted program/erase operations:

■

Write/Protect Enable input, WP, hardware protects a combination of blocks from

program and erase operations. The blocks to be protected are configured individually

by issuing a Set Block Protection Configuration Register or a Clear Block Protection

Configuration Register command.

■

All Program or Erase operations are blocked when Reset, RP, is held Low.

A Program/Erase Enable input, PEN, is used to protect all blocks, preventing Program

and Erase operations from affecting their data.

■

A permanent user-enabled protection against Modify operations is available:

–

on one specific 128-Kbit parameter block in the M58BW32F – Block 1 for bottom

devices or Block 72 for top devices

–

on two specific 64-Kbit parameter blocks in the M58BW16F – Blocks 2 & 3 for

bottom devices or Blocks 36 & 35 for top devices.

A Reset/Power-down mode is entered when the RP input is Low. In this mode the power

consumption is reduced to the standby level, the device is write protected and both the

Status and Burst Configuration Registers are cleared. A recovery time is required when the

RP input goes High.

A manufacturer code and a device code are available. They can be read from the memory

allowing programming equipment or applications to automatically match their interface to

the characteristics of the memory.

Finally, the M58BWxxF features a 64-bit Unique Device Identifier (UID) which is

programmed by ST on the production line. It is unique for each die and can be used to

implement cryptographic algorithms to improve security. Information is available in the CFI

area (see Table 30: M58BW16F extended query information).

The memory is offered in PQFP80 (14 x 20mm) and LBGA80 (1.0mm pitch) packages and it

is supplied with all the bits erased (set to ’1’).

8/81

M58BW16F, M58BW32F

Figure 1.

Description

Logic diagram

V

DDQ DDQIN

DD

DQ0-DQ31

(1)

A0-Amax

E

K

PEN

L

M58BW32F

M58BW16F

RP

G

R

GD

W

WP

B

V

SSQ

SS

AI13224b

9/81

Description

M58BW16F, M58BW32F

Table 1.

A0-Amax⁽¹⁾

Signal names

Address inputs

DQ0-DQ7

Data Input/Output, Command Input

Data Input/Output, Burst Configuration Register

Data Input/Output

DQ8-DQ15

DQ16-DQ31

B

Burst Address Advance input

Chip Enable input

E

G

Output Enable input

K

Burst Clock input

L

Latch Enable input

R

Valid Data Ready output

Reset /Power-Down input

Write Enable input

RP

W

GD

WP

V_DD

V_DDQ

V_DDQIN

PEN

V_SS

V_SSQ

NC

DU

Output Disable input

Write Protect input

Supply Voltage

Power Supply for Output Buffers

Power Supply for Input Buffers only

Program/Erase Enable

Ground

Input/Output Ground

Not Connected Internally

Don’t Use as Internally Connected

1. Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F.

10/81

M58BW16F, M58BW32F

Figure 2.

Description

LBGA connections (top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A15

A14

V

PEN

V

A6

A3

A2

DD

SS

A16

A17

DQ3

A13

A18

A12

A11

A9

A10

NC

A8

NC

A5

A7

A4

NC

A1

A0

A19/

NC⁽¹⁾

DQ0

DQ4

DQ7

DQ8

DQ12

DQ14

RP

NC

DQ31

DQ28

DQ25

DQ21

DQ19

G

DQ30

DQ26

DQ24

DQ23

DQ18

R

DQ29

V

DQ2

DQ6

DQ10

DQ11

L

DQ1

DQ5

DQ9

WP

B

DQ27

NC

V

DDQ

V

SSQ

DDQ

SSQ

G

H

J

V

DQ22

DQ17

E

V

DDQ

DQ13

DQ15

DQ20

DQ16

NC

K

V

K

V

W

GD

DDQIN

SS

DD

AI12854b

1. Ball D3 is NC in the M58BW16F and A19 in the M58BW32F.

11/81

Description

M58BW16F, M58BW32F

Figure 3.

PQFP connections (top view through package)

DQ16

1

DQ15

DQ14

DQ13

DQ12

64

DQ17

DQ18

DQ19

V

DDQ

SSQ

DDQ

V

SSQ

DQ20

DQ11

DQ10

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

M58BW16F

M58BW32F

12

53

V

DDQ

SSQ

DDQ

V

SSQ

DQ28

DQ3

DQ2

DQ1

DQ0

A19/NC

A18

DQ29

DQ30

DQ31

DU

(1)

A0

A1

A17

A2

A16

41

24

AI13225b

12/81

M58BW16F, M58BW32F

Description

1.1

Block Protection

The M58BWxxF features four different levels of block protection.

■

Write Protect Pin, WP, - When WP is Low, V , the protection status that has been

IL

configured in the Block Protection Configuration Register is activated. The Block

Protection Configuration Register is volatile. Any combination of blocks is possible. Any

attempt to program or erase a protected block will return an error in the Status Register

(see Table 13: Status Register Bits).

■

Reset/Power-Down Pin, RP, - If the device is held in reset mode (RP at V ), no

program or erase operation can be performed on any block.

IL

Program/Erase Enable, PEN - The Program/Erase Enable input, PEN, protects all

,

blocks by preventing Program and Erase operations from modifying the data.

Prior to issuing a Program or Erase command, the Program/Erase Enable must be set

to High (V ). If it is Low (V ), the Program or Erase operation is not accepted and an

IH

IL

error is generated in the Status Register.

■

Permanent protection against Modify operations - specific OTP-like blocks can be

permanently protected against Modify operations (program/ erase):

–

in the M58BW32F, a unique 128-Kbit parameter block – Block 1 (01000h-01FFFh)

for bottom devices or Block 72 (FE000h-FEFFFh) for Top devices

–

in the M58BW16F, two 64-Kbit parameter blocks – Blocks 2 & 3 (01000h-01FFFh)

for bottom devices or Blocks 36 & 35 (7E000h-7EFFFh) for top devices

This protection is user-enabled. Details of how this protection is activated are provided

in a dedicated application note.

After a device reset the first two kinds of block protection (WP, RP) can be combined to give

a flexible block protection. All blocks are protected at power-up.

13/81

Description

M58BW16F, M58BW32F

Table 2.

#

M58BW32F top boot block addresses

Size (Kbit)

Address Range⁽¹⁾

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

128

64

FF000h-FFFFFh

FE000h-FEFFFh⁽²⁾

FD000h-FDFFFh

FC000h-FCFFFh

FB800h-FBFFFh

FB000h-FB7FFh

FA800h-FAFFFh

FA000h-FA7FFh

F9800h-F9FFFh

F9000h-F97FFh

F8800h-F8FFFh

F8000h-F87FFh

F4000h-F7FFFh

F0000h-F3FFFh

EC000h-EFFFFh

E8000h-EBFFFh

E4000h-E7FFFh

E0000h-E3FFFh

DC000h-DFFFFh

D8000h-DBFFFh

D4000h-D7FFFh

D0000h-D3FFFh

CC000h-CFFFFh

C8000h-CBFFFh

C4000h-C7FFFh

C0000h-C3FFFh

BC000h-BFFFFh

B8000h-BBFFFh

B4000h-B7FFFh

B0000h-B3FFFh

AC000h-AFFFFh

A8000h-ABFFFh

A4000h-A7FFFh

A0000h-A3FFFh

9C000h-9FFFFh

98000h-9BFFFh

94000h-97FFFh

90000h-93FFFh

64

512

14/81

M58BW16F, M58BW32F

Description

Table 2.

#

M58BW32F top boot block addresses (continued)

Size (Kbit)

Address Range⁽¹⁾

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

512

8C000h-8FFFFh

88000h-8BFFFh

84000h-87FFFh

80000h-83FFFh

7C000h-7FFFFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

04000h-07FFFh

00000h-03FFFh

8

7

6

5

4

3

2

1

0

1. Addresses are indicated in 32-bit addressing.

2. OTP Block.

15/81

Description

M58BW16F, M58BW32F

Table 3.

#

M58BW32F Bottom Boot Block Addresses

Size (Kbit)

Address Range⁽¹⁾

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

512

FC000h-FFFFFh

F8000h-FBFFFh

F4000h-F7FFFh

F0000h-F3FFFh

EC000h-EFFFFh

E8000h-EBFFFh

E4000h-E7FFFh

E0000h-E3FFFh

DC000h-DFFFFh

D8000h-DBFFFh

D4000h-D7FFFh

D0000h-D3FFFh

CC000h-CFFFFh

C8000h-CBFFFh

C4000h-C7FFFh

C0000h-C3FFFh

BC000h-BFFFFh

B8000h-BBFFFh

B4000h-B7FFFh

B0000h-B3FFFh

AC000h-AFFFFh

A8000h-ABFFFh

A4000h-A7FFFh

A0000h-A3FFFh

9C000h-9FFFFh

98000h-9BFFFh

94000h-97FFFh

90000h-93FFFh

8C000h-8FFFFh

88000h-8BFFFh

84000h-87FFFh

80000h-83FFFh

7C000h-7FFFFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

16/81

M58BW16F, M58BW32F

Description

Table 3.

#

M58BW32F Bottom Boot Block Addresses (continued)

Size (Kbit)

Address Range⁽¹⁾

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

512

64

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

07800h-07FFFh

07000h-077FFh

06800h-06FFFh

06000h-067FFh

05800h-05FFFh

05000h-057FFh

04800h-04FFFh

04000h-047FFh

03000h-03FFFh

02000h-02FFFh

01000h-01FFFh⁽²⁾

00000h-00FFFh

64

8

64

7

64

6

64

5

64

4

64

3

128

2

1

0

1. Addresses are indicated in 32-bit Word addressing.

2. OTP Block.

17/81

Description

M58BW16F, M58BW32F

Table 4.

#

M58BW16F top boot block addresses

Size (Kbit)

Address Range

38

37

36⁽¹⁾

35⁽¹⁾

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

64

7F800h-7FFFFh

7F000h-7F7FFh

7E800h-7EFFFh

7E000h-7E7FFh

7D800h-7DFFFh

7D000h-7D7FFh

7C800h-7CFFFh

7C000h-7C7FFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

04000h-07FFFh

00000h-03FFFh

64

512

8

7

6

5

4

3

2

1

0

1. OTP block.

18/81

M58BW16F, M58BW32F

Description

Table 5.

#

M58BW16F bottom boot block addresses

Size (Kbit)

Address Range

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

512

64

7C000h-7FFFFh

78000h-7BFFFh

74000h-77FFFh

70000h-73FFFh

6C000h-6FFFFh

68000h-6BFFFh

64000h-67FFFh

60000h-63FFFh

5C000h-5FFFFh

58000h-5BFFFh

54000h-57FFFh

50000h-53FFFh

4C000h-4FFFFh

48000h-4BFFFh

44000h-47FFFh

40000h-43FFFh

3C000h-3FFFFh

38000h-3BFFFh

34000h-37FFFh

30000h-33FFFh

2C000h-2FFFFh

28000h-2BFFFh

24000h-27FFFh

20000h-23FFFh

1C000h-1FFFFh

18000h-1BFFFh

14000h-17FFFh

10000h-13FFFh

0C000h-0FFFFh

08000h-0BFFFh

04000h-07FFFh

03800h-03FFFh

03000h-037FFh

02800h-02FFFh

02000h-027FFh

01800h-01FFFh

01000h-017FFh

00800h-00FFFh

00000h-007FFh

8

7

6

64

5

64

4

64

3⁽¹⁾

2⁽¹⁾

1

64

0

64

1. OTP block.

19/81

Signal descriptions

M58BW16F, M58BW32F

2

Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

Address Inputs (A0-Amax)

Amax is equal to A18 in the M58BW16F, and to A19 in the M58BW32F.

The Address Inputs are used to select the cells to access in the memory array during Bus

operations. During Bus Write operations they control the commands sent to the Command

Interface of the Program/Erase Controller. Chip Enable must be Low when selecting the

addresses.

The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K,

whichever occurs first, in a read operation.The address inputs are latched on the rising edge

of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation.

The address latch is transparent when Latch Enable is Low, V . The address is internally

IL

latched in an Erase or Program operation.

2.2

Data Inputs/Outputs (DQ0-DQ31)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operation, or are used to input the data during a program operation. During Bus Write

operations they represent the commands sent to the Command Interface of the

Program/Erase Controller. When used to input data or Write commands they are latched on

the rising edge of Write Enable or Chip Enable, whichever occurs first.

When Chip Enable and Output Enable are both Low, V , and Output Disable is at V the

IL

IH,

data bus outputs data from the memory array, the Electronic Signature, the Block Protection

Configuration Register, the CFI Information or the contents of Burst Configuration Register

or Status Register. The data bus is high impedance when the device is deselected with Chip

Enable at V , Output Enable at V , Output Disable at V or Reset/Power-Down at V . The

IH

IL

Status Register content is output on DQ0-DQ7 and DQ8-DQ31 are at V .

IL

2.3

2.4

Chip Enable (E)

The Chip Enable, E, input activates the memory control logic, input buffers, decoders and

sense amplifiers. Chip Enable, E, at V deselects the memory and reduces the power

consumption to the Standby level.

IH

Output Enable (G)

The Output Enable, G, gates the outputs through the data output buffers during a read

operation, when Output Disable GD is at V . When Output Enable G is at V , the outputs

IH

are high impedance independently of Output Disable.

20/81

M58BW16F, M58BW32F

Signal descriptions

2.5

Output Disable (GD)

The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at

V , the outputs are driven by the Output Enable. When Output Disable, GD, is at V , the

IH

IL

outputs are high impedance independently of Output Enable. The Output Disable pin must

be connected to an external pull-up resistor as there is no internal pull-up resistor to drive

the pin.

2.6

2.7

Write Enable (W)

The Write Enable, W, input controls writing to the Command Interface, Input Address and

Data latches. Both addresses and data can be latched on the rising edge of Write Enable

(also see Latch Enable, L).

Reset/Power-Down (RP)

The Reset/Power-Down, RP, is used to apply a hardware reset to the memory. A hardware

reset is achieved by holding Reset/Power-Down Low, V , for at least t

. Writing is

IL

PLPH

inhibited to protect data, the Command Interface and the Program/Erase Controller are

reset. The Status Register information is cleared and power consumption is reduced to the

standby level (I

impedance.

). The device acts as deselected, that is the data outputs are high

DD1

After Reset/Power-Down goes High, V , the memory will be ready for Bus Read operations

IH

after a delay of t

or Bus Write operations after t

.

PHEL

PHWL

If Reset/Power-Down goes Low, V , during a Block Erase or a Program operation, the

IL

operation is aborted, in a time of t

maximum, and data is altered and may be corrupted.

PLRH

During Power-up power should be applied simultaneously to V and V

with RP held

DDQ(IN)

DD

at V . When the supplies are stable RP is taken to V . Output Enable, G, Chip Enable, E,

IL

IH

and Write Enable, W, should be held at V during power-up.

IH

In an application, it is recommended to associate the Reset/Power-Down pin, RP, with the

reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory

is performing an erase or program operation, the memory may output the Status Register

information instead of being initialized to the default Asynchronous Random Read mode.

See Table 22 and Figure 21: Reset, Power-Down and Power-up AC waveform, for more

details.

2.8

Program/Erase Enable (PEN)

The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase

operations from modifying the data.

Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to

High (V ). If it is Low (V ), the Program or Erase operation is not accepted and an error is

IH

IL

generated in the Status Register.

21/81

Signal descriptions

M58BW16F, M58BW32F

2.9

Latch Enable (L)

The Bus Interface can be configured to latch the Address Inputs on the rising edge of Latch

Enable, L, for Asynchronous Latch Enable Controlled Read or Write or Synchronous Burst

Read operations. In Synchronous Burst Read operations the address is latched on the

active edge of the Clock when Latch Enable is Low, V . Once latched, the addresses may

IL

change without affecting the address used by the memory. When Latch Enable is Low, V ,

IL

the latch is transparent. Latch Enable, L, can remain at V for Asynchronous Random Read

IL

and Write operations.

2.10

2.11

Burst Clock (K)

The Burst Clock, K, is used to synchronize the memory with the external bus during

Synchronous Burst Read operations. Bus signals are latched on the active edge of the

Clock. In Synchronous Burst Read mode the address is latched on the first rising clock edge

when Latch Enable is Low, V , or on the rising edge of Latch Enable, whichever occurs first.

IL

During Asynchronous bus operations the Clock is not used.

Burst Address Advance (B)

The Burst Address Advance, B, controls the advancing of the address by the internal

address counter during Synchronous Burst Read operations.

Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the

X-latency time has expired. If Burst Address Advance is Low, V , the internal address

IL

counter advances. If Burst Address Advance is High, V , the internal address counter does

IH

not change; the same data remains on the Data Inputs/Outputs and Burst Address Advance

is not sampled until the Y-latency expires.

The Burst Address Advance, B, may be tied to V .

IL

2.12

2.13

Valid Data Ready (R)

The Valid Data Ready output, R, can be used during Synchronous Burst Read operations to

identify if the memory is ready to output data or not. The Valid Data Ready output can be

configured to be active on the clock edge of the invalid data read cycle or one cycle before.

Valid Data Ready, at V , indicates that new data is or will be available. When Valid Data

IH

Ready is Low, V , the previous data outputs remain active.

IL

Write Protect (WP)

The Write Protect, WP, provides protection against program or erase operations. When

Write Protect, WP, is at V , the protection status that has been configured in the Block

IL

Protection Configuration Register is activated. Program and erase operations to protected

blocks are disabled. When Write Protect WP is at V all the blocks can be programmed or

IH

erased, if no other protection is used.

22/81

M58BW16F, M58BW32F

Signal descriptions

2.14

2.15

2.16

Supply Voltage (V_DD)

The Supply Voltage, V , is the core power supply. All internal circuits draw their current

DD

from the V pin, including the Program/Erase Controller.

DD

Output Supply Voltage (V_DDQ

)

The Output Supply Voltage, V

, is the output buffer power supply for all operations (Read,

DDQ

Program and Erase) used for DQ0-DQ31 when used as outputs.

Input Supply Voltage (V_DDQIN

)

The Input Supply Voltage, V

, is the power supply for all input signal. Input signals are: K, B,

DDIN

L, W, GD, G, E, A0-Amax and DQ0-DQ31, when used as inputs.

2.17

Ground (V_SSand V_SSQ)

The Ground V is the reference for the internal supply voltage V . The Ground V is

SSQ

SS

DD

the reference for the output and input supplies V

and V

. It is essential to connect

DDQ,

DDQIN

V

and V

together.

SS

SSQ

Note:

A 0.1µF capacitor should be connected between the Supply Voltages, V , V

and V

DD DDQ DDIN

and the Grounds, V and V

to decouple the current surges from the power supply. The

SS

SSQ

PCB track widths must be sufficient to carry the currents required during all operations of

the parts, see Table 17: DC characteristics, for maximum current supply requirements.

2.18

2.19

Don’t Use (DU)

This pin should not be used as it is internally connected. Its voltage level can be between

V

and V

or leave it unconnected.

SS

DDQ

Not Connected (NC)

This pin is not physically connected to the device.

23/81

Bus operations

M58BW16F, M58BW32F

3

Bus operations

Each bus operations that controls the memory is described in this section, see Tables 6 and

7 Bus Operations, for a summary. The bus operation is selected through the Burst

Configuration Register; the bits in this register are described at the end of this section.

On Power-up or after a Hardware Reset the memory defaults to Asynchronous Bus Read

and Asynchronous Bus Write. No synchronous operation can be performed until the Burst

Control Register has been configured.

The Electronic Signature, Block Protection Configuration, CFI or Status Register will be read

in asynchronous mode regardless of the Burst Control Register settings.

Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the

memory and do not affect bus operations.

3.1

Asynchronous Bus Operations

For asynchronous bus operations refer to Table 6 together with the following text. The read

access will start at whichever of the three following events occurs last: valid address

transition, Chip Enable, E, going Low, V or Latch Enable, L, going Low, V .

IL

3.1.1

Asynchronous Bus Read

Asynchronous Bus Read operations read from the memory cells, or specific registers

(Electronic Signature, Block Protection Configuration Register, Status Register, CFI and

Burst Configuration Register) in the Command Interface. A valid bus operation involves

setting the desired address on the Address Inputs, applying a Low signal, V , to Chip

IL

Enable and Output Enable and keeping Write Enable and Output Disable High, V . The

IH

Data Inputs/Outputs will output the value, see Figure 7: Asynchronous Bus Read AC

waveforms, and Table 18: Asynchronous Bus Read AC characteristics, for details of when

the output becomes valid.

Asynchronous Read is the default read mode which the device enters on power-up or on

return from Reset/Power-Down.

3.1.2

Asynchronous Latch Controlled Bus Read

Asynchronous Latch Controlled Bus Read operations read from the memory cells or specific

registers in the Command Interface. The address is latched in the memory before the value

is output on the data bus, allowing the address to change during the cycle without affecting

the address that the memory uses.

A valid bus operation involves setting the desired address on the Address Inputs, setting

Chip Enable and Latch Enable Low, V and keeping Write Enable High, V ; the address is

IL

IH

latched on the rising edge of Latch Enable. Once latched, the Address Inputs can change.

Set Output Enable Low, V , to read the data on the Data Inputs/Outputs; see Figure

IL

Figure 8: Asynchronous Latch controlled bus Read AC waveforms and Table 18:

Asynchronous Bus Read AC characteristics, for details on when the output becomes valid.

Note that, since the Latch Enable input is transparent when set Low, V , Asynchronous Bus

IL

Read operations can be performed when the memory is configured for Asynchronous Latch

Enable bus operations by holding Latch Enable Low, V throughout the bus operation.

IL

24/81

M58BW16F, M58BW32F

Bus operations

3.1.3

Asynchronous Page Read

Asynchronous Page Read operations are used to read from several addresses within the

same memory page. Each memory page is 4 Double-Words and is addressed by the

address inputs A0 and A1.

Data is read internally and stored in the Page Buffer. Valid bus operations are the same as

Asynchronous Bus Read operations but with different timings. The first read operation within

the page has identical timings, subsequent reads within the same page have much shorter

access times. If the page changes then the normal, longer timings apply again. Page Read

does not support Latched Controlled Read.

See Figure 11: Asynchronous Page Read AC waveforms, and Table 19: Asynchronous

Page Read AC characteristics, for details on when the outputs become valid.

3.1.4

Asynchronous Bus Write

Asynchronous Bus Write operations write to the Command Interface in order to send

commands to the memory or to latch addresses and input data to program. Bus Write

operations are asynchronous, the clock, K, is don’t care during Bus Write operations.

A valid Asynchronous Bus Write operation begins by setting the desired address on the

Address Inputs, and setting Chip Enable, Write Enable and Latch Enable Low, V , and

IL

Output Enable High, V , or Output Disable Low, V . The Address Inputs are latched by the

IH

IL

Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs

first. Commands and Input Data are latched on the rising edge of Chip Enable, E, or Write

Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable

Low, during the whole Asynchronous Bus Write operation.

See Figure 12: Asynchronous Write AC waveform, and Table 20: Asynchronous Write and

Latch controlled Write AC characteristics, for details of the timing requirements.

3.1.5

Asynchronous Latch Controlled Bus Write

Asynchronous Latch Controlled Bus Write operations write to the Command Interface in

order to send commands to the memory or to latch addresses and input data to program.

Bus Write operations are asynchronous, the clock, K, is don’t care during Bus Write

operations.

A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired

address on the Address Inputs and pulsing Latch Enable Low, V . The Address Inputs are

IL

latched by the Command Interface on the rising edge of Latch Enable, Write Enable or Chip

Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of

Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain

High, and Output Disable Low, during the whole Asynchronous Bus Write operation.

See Figure 13: Asynchronous Latch controlled Write AC waveform, and Table 20:

Asynchronous Write and Latch controlled Write AC characteristics, for details of the timing

requirements.

3.1.6

Output Disable

The data outputs are high impedance when the Output Enable, G, is at V or Output

IH

Disable, GD, is at V .

IL

25/81

Bus operations

M58BW16F, M58BW32F

3.1.7

Standby

When Chip Enable is High, V , and the Program/Erase Controller is idle, the memory

IH

enters Standby mode, the power consumption is reduced to the standby level (I

) and the

DD1

Data Inputs/Outputs pins are placed in the high impedance state regardless of Output

Enable, Write Enable or Output Disable inputs.

The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst

Configuration Register to ‘1’ (see Table 17: DC characteristics).

3.1.8

Reset/Power-Down

The memory is in Reset/ Power-Down mode when Reset/Power-Down, RP, is at V . The

IL

power consumption is reduced to the standby level (I

) and the outputs are high

DD1

impedance, independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or

Write Enable, W, inputs. In this mode the device is write protected and both the Status and

the Burst Configuration Registers are cleared. A recovery time is required when the RP

input goes High.

(1)

Table 6.

Asynchronous bus operations

Bus Operation

Step

E

G

GD

W

RP

L

A0-Amax

DQ0-DQ31

Asynchronous Bus Read⁽²⁾

V_IL

V_IH

V_IL

V_IH

V_IL

X

V_IH

X

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

X

V_IH

V_IL

V_IH

X

Address

Data Output

High Z

Address Latch V_IL

Address

Asynchronous Latch

Controlled Bus Read

Read

V_IL

X

Data Output

Data Input

High Z

Asynchronous Page Read

Asynchronous Bus Write

Address

V_IL

V_IH

X

Address

Address Latch V_IL

X

Address

Asynchronous Latch

Controlled Bus Write

Write

V_IL

V_IH

X

Data Input

High Z

Output Enable, G

Output Disable, GD

Standby

V_IH

V_IL

X

High Z

X

High Z

Reset/Power-Down

1. X = Don’t Care.

X

High Z

2. Data, Manufacturer Code, Device Code, Burst Configuration Register, Standby Status and Block Protection Configuration

Register are read using the Asynchronous Bus Read command.

26/81

M58BW16F, M58BW32F

Bus operations

3.2

Synchronous bus operations

For synchronous bus operations refer to Table 7 together with the following text. The read

access will start at whichever of the three following events occurs last: valid address

transition, Chip Enable, E, going Low, V or Latch Enable, L, going Low, V .

IL

3.2.1

Synchronous Burst Read

Synchronous Burst Read operations are used to read from the memory at specific times

synchronized to an external reference clock. The valid edge of the Clock signal is the rising

edge. Once the Flash memory is configured in Burst mode, it is mandatory to have an active

clock signal since the switching of the output buffer databus is synchronized to the rising

edge of the clock. In the absence of clock, no data is output.

The burst type, length and latency can be configured. The different configurations for

Synchronous Burst Read operations are described in the Burst Configuration Register

section. Refer to Figure 4 for examples of synchronous burst operations.

A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip

Enable and Latch Enable are Low, V . The burst start address is latched and loaded into

IL

the internal Burst Address Counter on the valid Burst Clock K edge or on the rising edge of

Latch Enable, whichever occurs first.

After an initial memory latency time, the memory outputs data each clock cycle. The Burst

Address Advance B input controls the memory burst output. The second burst output is on

the next clock valid edge after the Burst Address Advance B has been pulled Low.

Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst

Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low

on the rising clock edge, no new data is available and the memory does not increment the

internal address counter at the active clock edge even if Burst Address Advance, B, is Low.

Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid

immediately at the rising clock edge.

Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, V .

IH

If Output Enable is at V and Output Disable is at V , the last data is still valid.

IL

IH

If Output Enable, G, is at V or Output Disable, GD, is at V , but the Burst Address

IH

IL

Advance, B, is at V the internal Burst Address Counter is incremented at each Burst Clock

IL

K rising edge.

The Synchronous Burst Read timing diagrams and AC Characteristics are described in the

AC and DC Parameters section. See Figures 14, 17, 18 and 19, and Table 21.

27/81

Bus operations

M58BW16F, M58BW32F

3.2.2

Synchronous Burst Read Suspend

During a Synchronous Burst Read operation it is possible to suspend the operation, freeing

the data bus for other higher priority devices.

A valid Synchronous Burst Read operation is suspended when both Output Enable and

Burst Address Advance are High, V . The Burst Address Advance going High, V , stops

IH

the burst counter and the Output Enable going High, V , inhibits the data outputs. The

IH

Synchronous Burst Read operation can be resumed by setting Output Enable Low.

Table 7.

Synchronous Burst Read bus operations

A0-Amax

Bus Operation

Step

E

G

GD RP

K

L

B

DQ0-DQ31

Address Latch

Read

V_ILV_IH

V_IL

V_ILV_IH

V_IL

V_ILV_IHV_IHR⁽³⁾V_IHV_IL

X

V_IHR⁽³⁾V_IL

X

Address Input

Data Output

High Z

V_ILV_IHV_IHR⁽³⁾V_IHV_IL

Read Suspend

Read Resume

X

V_IHV_IHV_IH

X

Synchronous

Burst Read⁽²⁾

Data Output

Burst Address

Advance

V_ILV_IH

X

V_IHR⁽³⁾V_IHV_IL

High Z

Read Abort, E

V_IH

X

V_IH

V_IL

X

High Z

Read Abort, RP

1. X = Don't Care, V_ILor V_IH

.

2. M15 = 0, Bit M15 is in the Burst Configuration Register.

3. R = Rising Edge.

3.3

Burst Configuration Register

The Burst Configuration Register is used to configure the type of bus access that the

memory will perform.

The Burst Configuration Register is set through the Command Interface and will retain its

information until it is re-configured, the device is reset, or the device goes into Reset/Power-

Down mode. The Burst Configuration Register bits are described in Table 8. They specify

the selection of the burst length, burst type, burst X and Y latencies and the Read operation.

Refer to Figure 4 for examples of synchronous burst configurations.

3.3.1

Read Select Bit (M15)

The Read Select bit, M15, is used to switch between asynchronous and synchronous Bus

Read operations. When the Read Select bit is set to ’1’, Bus Read operations are

asynchronous; when the Read Select but is set to ’0’, Bus Read operations are

synchronous.

On reset or power-up the Read Select bit is set to’1’ for asynchronous accesses.

3.3.2

Standby Disable Bit (M14)

The Standby Disable Bit, M14, is used to disable the Standby mode. When the Standby bit

is ‘1’, the device will not enter Standby mode when Chip Enable goes High, V .

IH

28/81

M58BW16F, M58BW32F

Bus operations

3.3.3

X-Latency Bits (M13-M11)

The X-Latency bits are used during Synchronous Bus Read operations to set the number of

clock cycles between the address being latched and the first data becoming available. For

correct operation the X-Latency bits can only assume the values in Table 8: Burst

Configuration Register.

3.3.4

Y-Latency Bit (M9)

The Y-Latency bit is used during Synchronous Bus Read operations to set the number of

clock cycles between consecutive reads. The Y-Latency value depends on both the X-

Latency value and the setting in M9.

When the Y-Latency is 1 the data changes each clock cycle.

3.3.5

3.3.6

3.3.7

Valid Data Ready Bit (M8)

The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When

the Valid Data Ready bit is ’0’ the Valid Data Ready output pin is driven Low for the rising

clock edge when invalid data is output on the bus.

Wrap Burst Bit (M3)

Burst read can be confined inside the 4 double-word boundary (wrap) or overcome the

boundary (no wrap). When the wrap burst bit is set to '1' the burst read does not wrap. The

wrap mode is not available (M3 is always ‘1’).

Burst Length Bit (M2-M0)

The Burst Length bits set the maximum number of Double-Words that can be output during

a Synchronous Burst Read operation. Burst lengths of 4 or 8 are available.

Table 8: Burst Configuration Register gives the valid combinations of the Burst Length bits

that the memory accepts.

If a Burst Read operation (no wrap) has been initiated the device will output data

synchronously. Depending on the starting address, the device activates the Valid Data

Ready output to indicate that a delay is necessary before the data is output. If the starting

address is aligned to a 4 double word boundary, the 8-double-word burst mode will run

without activating the Valid Data Ready output. If the starting address is not aligned to a 4

Double Word boundary, Valid Data Ready is activated to indicate that the device needs an

internal delay to read the successive words in the array.

M10, M7 to M4 are reserved for future use.

29/81

Bus operations

M58BW16F, M58BW32F

Table 8.

Burst Configuration Register

Description Value

Bit

Description

Synchronous Burst Read

0

1

0

1

M15

Read Select

Asynchronous Read (Default at power-up)

Standby Mode Enabled (Default at power-up)

M14

Standby Disable

X-Latency

Standby Mode Disabled

001

010

011

100

3

4

5

6

M13-M11

M10

M9

Reserved

Y-Latency

0

1

Reserved

One Burst Clock cycle (M9 is always at ‘1’)

R valid Low during valid Burst Clock edge. (M8 is

always at ‘0’)

0

1

M8

Valid Data Ready

Reserved

M7-M4

M3

Reserved

Wrapping

0

Reserved

1

No Wrap (M3 is always at ‘1’)

4 Double-Words

001

010

M2-M0

Burst Length

8 Double-Words

30/81

M58BW16F, M58BW32F

Bus operations

Table 9.

Burst type definition

Start Address

×4 Sequential

×8 Sequential

0

1

2

3

4

5

6

7

8

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

4-5-6-7

5-6-7-8

6-7-8-9

7-8-9-10

8-9-10-11

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

4-5-6-7-8-9-10-11

5-6-7-8-9-10-11-12

6-7-8-9-10-11-12-13

7-8-9-10-11-12-13-14

8-9-10-11-12-13-14-15

Figure 4.

Example burst configuration X-1-1-1

0

1

2

3

4

5

6

7

8

9

K

ADD

VALID

L

DQ

VALID

3-1-1-1

DQ

VALID

4-1-1-1

5-1-1-1

VALID

DQ

VALID

6-1-1-1

7-1-1-1

8-1-1-1

AI03841b

31/81

Command interface

M58BW16F, M58BW32F

4

Command interface

All Bus Write operations to the memory are interpreted by the Command Interface.

Commands consist of one or more sequential Bus Write operations. The Commands are

summarized in Table 10: Commands. Refer to Table 10 in conjunction with the text

descriptions below.

4.1

4.2

Read Memory Array command

The Read Memory Array command returns the memory to Read mode. One Bus Write cycle

is required to issue the Read Memory Array command and return the memory to Read

mode. Subsequent read operations will output the addressed memory array data. Once the

command is issued the memory remains in Read mode until another command is issued.

From Read mode Bus Read commands will access the memory array.

Read Electronic Signature command

The Read Electronic Signature command is used to read the Manufacturer Code, the Device

Code, the Block Protection Configuration Register and the Burst Configuration Register.

One Bus Write cycle is required to issue the Read Electronic Signature command. Once the

command is issued, subsequent Bus Read operations, depending on the address specified,

read the Manufacturer Code, the Device Code, the Block Protection Configuration or the

Burst Configuration Register until another command is issued; see Table 11: Read

Electronic Signature.

4.3

Read Query command

The Read Query Command is used to read data from the Common Flash Interface (CFI)

Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once

the command is issued subsequent Bus Read operations, depending on the address

specified, read from the Common Flash Interface Memory Area.

32/81

M58BW16F, M58BW32F

Command interface

4.4

Read Status Register command

The Read Status Register command is used to read the Status Register. One Bus Write

cycle is required to issue the Read Status Register command. Once the command is issued

subsequent Bus Read operations read the Status Register until another command is issued.

The Status Register information is present on the output data bus (DQ0-DQ7) when Chip

Enable E and Output Enable G are at V and Output Disable is at V .

IL

IH

An interactive update of the Status Register bits is possible by toggling Output Enable or

Output Disable. It is also possible during a Program or Erase operation, by de-activating the

device with Chip Enable at V and then reactivating it with Chip Enable and Output Enable

IH

at V and Output Disable at V .

IL

IH

The content of the Status Register may also be read at the completion of a Program, Erase

or Suspend operation. During a Block Erase or Program command, DQ7 indicates the

Program/Erase Controller status. It is valid until the operation is completed or suspended.

See the section on the Status Register and Table 13 for details on the definitions of the

Status Register bits.

4.5

Clear Status Register command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status

Register to ‘0’. One Bus Write is required to issue the Clear Status Register command.

Once the command is issued the memory returns to its previous mode, subsequent Bus

Read operations continue to output the same data.

The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new

Program, Erase, Block Protect or Block Unprotect command is issued. If any error occurs

then it is essential to clear any error bits in the Status Register by issuing the Clear Status

Register command before attempting a new Program, Erase or Resume command.

4.6

Block Erase command

The Block Erase command can be used to erase a block. It sets all of the bits in the block to

‘1’. All previous data in the block is lost. If the block is protected then the Erase operation will

abort, the data in the block will not be changed and the Status Register will output the error.

Two Bus Write operations are required to issue the command; the first write cycle sets up

the Block Erase command, the second write cycle confirms the Block erase command and

latches the block address in the Program/Erase Controller and starts the Program/Erase

Controller. The sequence is aborted if the Confirm command is not given and the device will

output the Status Register Data with bits 4 and 5 set to '1'.

Once the command is issued subsequent Bus Read operations read the Status Register.

See the section on the Status Register for details on the definitions of the Status Register

bits. During the Erase operation the memory will only accept the Read Status Register

command and the Program/Erase Suspend command. All other commands will be ignored.

If PEN is at V , the operation can be performed. If PEN goes below V the operation

IH

IH,

aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re-

issued.

Typical Erase times are given in Table 12. See Appendix A, Figure 26: Block Erase flowchart

and pseudo code, for a suggested flowchart on using the Block Erase command.

33/81

Command interface

M58BW16F, M58BW32F

4.7

Erase All Main Blocks command

The Erase All Main Blocks command is used to erase all 63 Main Blocks, without affecting

the Parameter Blocks.

Issuing the Erase All Main Blocks command sets every bit in each Main Block to '1'. All data

previously stored in the Main Blocks are lost.

Two Bus Write cycles are required to issue the Erase All Main Blocks command. The first

cycle sets up the command, the second cycle confirms the command and starts the

Program/Erase Controller. If the Confirm Command is not given the sequence is aborted,

and Status Register bits 4 and 5 are set to '1'.

If the address given in the second cycle is located in a protected block, the Erase All Main

Blocks operation aborts. The data remains unchanged in all blocks and the Status Register

outputs the error.

Once the Erase All Main Blocks command has been issued, subsequent Bus Read

operations output the Status Register. See the Status Register section for details.

During an Erase All Main Blocks operation, only the Read Status Register command is

accepted by the memory; any other command are ignored. Erase All Main Blocks, once

started, cannot be suspended.

If PEN is at V , the operation will be performed. If PEN is lower than V the operation

IH

aborts and the Status Register PEN bit (bit 3) is set to '1'.

4.8

Program command

The Program command is used to program the memory array. Two Bus Write operations are

required to issue the command; the first write cycle sets up the Program command, the

second write cycle latches the address and data to be programmed and starts the

Program/Erase Controller. A program operation can be aborted by writing FFFFFFFFh to

any address after the program set-up command has been given.

The Program command is also used to program the OTP block. Refer to Table 10:

Commands, for details of the address.

Once the command is issued subsequent Bus Read operations read the Status Register.

See the section on the Status Register for details on the definitions of the Status Register

bits. During the Program operation the memory will only accept the Read Status Register

command and the Program/Erase Suspend command. All other commands will be ignored.

If Reset/Power-down, RP, falls to V during programming the operation will be aborted.

IL

If PEN is at V , the operation can be performed. If PEN goes below V the operation

IH

IH,

aborts, the PEN Status bit in the Status Register is set to ‘1’ and the command must be re-

issued.

See Appendix A, Figure 24: Program flowchart and pseudo code, for a suggested flowchart

on using the Program command.

34/81

M58BW16F, M58BW32F

Command interface

4.9

Write to Buffer and Program command

The Write to Buffer and Program Command makes use of the device’s double Word (32 bit)

Write Buffer to speed up programming.

Up to eight Double Words can be loaded into the Write Buffer and programmed into the

memory.

Four successive steps are required to issue the command.

1. One Bus Write operation is required to set up the Write to Buffer and Program

Command. Any Bus Read operations will start to output the Status Register after the

1st cycle.

2. Use one Bus Write operation to write the selected memory Block Address (any address

in the block where the values will be programmed can be used) along with the value N

on the Data Inputs/Outputs, where N+1 is the number of Words to be programmed. The

maximum value of N+1 is 8 Words.

3. Use N+1 Bus Write operations to load the address and data for each Word into the

Write Buffer. The address must be between Start Address and Start Address plus N,

where Start Address is the first word address.

4. Finally, use one Bus Write operation to issue the final cycle to confirm the command

and start the Program operation.

If any address is outside the block boundaries or if the correct sequence is not followed,

Status Register bits 4 and 5 are set to ‘1’ and the operation will abort without affecting the

data in the memory array. A protected block must be unprotected using the Blocks Unprotect

command.

During a Write to Buffer and Program operation the memory will only accept the Read

Status Register and the Program/Erase Suspend commands. All other commands are

ignored. If PEN is at V , the operation will be performed. If PEN is lower than V the

IH

operation aborts and the Status Register PEN bit (bit 3) is set to '1'.

The Status Register should be cleared before re-issuing the command.

35/81

Command interface

M58BW16F, M58BW32F

4.10

Program/Erase Suspend command

The Program/Erase Suspend command is used to pause a Program or Erase operation. The

command will only be accepted during a Program or Erase operation. It can be issued at

any time during a program or erase operation. The command is ignored if the device is

already in suspend mode.

One Bus Write cycle is required to issue the Program/Erase Suspend command and pause

the Program/Erase Controller. Once the command is issued it is necessary to poll the

Program/Erase Controller Status bit (bit 7) to find out when the Program/Erase Controller

has paused; no other commands will be accepted until the Program/Erase Controller has

paused. After the Program/Erase Controller has paused, the memory will continue to output

the Status Register until another command is issued.

During the polling period between issuing the Program/Erase Suspend command and the

Program/Erase Controller pausing it is possible for the operation to complete. Once the

Program/Erase Controller Status bit (bit 7) indicates that the Program/Erase Controller is no

longer active, the Program Suspend Status bit (bit 2) or the Erase Suspend Status bit (bit 6)

can be used to determine if the operation has completed or is suspended. For timing on the

delay between issuing the Program/Erase Suspend command and the Program/Erase

Controller pausing see Note 12.

During Program/Erase Suspend the Read Memory Array, Read Status Register, Read

Electronic Signature, Read Query and Program/Erase Resume commands will be accepted

by the Command Interface. Additionally, if the suspended operation was Erase then the

Program, the Write to Buffer and Program, the Set/Clear Block Protection Configuration

Register and the Program Suspend commands will also be accepted. When a program

operation is completed inside a Block Erase Suspend the Read Memory Array command

must be issued to reset the device in Read mode, then the Erase Resume command can be

issued to complete the whole sequence. Only the blocks not being erased may be read or

programmed correctly.

Erase operations can be suspended in a systematic and periodical way, however, in order to

ensure the effectiveness of erase operations and avoid infinite erase times, it is imperative to

wait a minimum time between successive Erase Resume and Erase Suspend commands.

This time, called the Minimum effective erase time, is given in Table 12 on page 39.

See Appendix A, Figure 25: Program Suspend & Resume flowchart and pseudo code, and

Figure 27: Erase Suspend & Resume flowchart and pseudo code, for suggested flowcharts

on using the Program/Erase Suspend command.

4.11

Program/Erase Resume command

The Program/Erase Resume command can be used to restart the Program/Erase Controller

after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to

issue the Program/Erase Resume command.

See Appendix A, Figure 25: Program Suspend & Resume flowchart and pseudo code, and

Figure 27: Erase Suspend & Resume flowchart and pseudo code, for suggested flowcharts

on using the Program/Erase Suspend command.

36/81

M58BW16F, M58BW32F

Command interface

4.12

Set Burst Configuration Register command

The Set Burst Configuration Register command is used to write a new value to the Burst

Configuration Register which defines the burst length, type, X and Y latencies,

Synchronous/Asynchronous Read mode.

Two Bus Write cycles are required to issue the Set Burst Configuration Register command.

The first cycle writes the setup command. The second cycle writes the address where the

new Burst Configuration Register content is to be written, and confirms the command. If the

command is not confirmed, the sequence is aborted and the device outputs the Status

Register with bits 4 and 5 set to ‘1’. Once the command is issued the memory returns to

Read mode as if a Read Memory Array command had been issued.

The value for the Burst Configuration Register is always presented on A0-A15. M0 is on A0,

M1 on A1, etc.; the other address bits are ignored.

4.13

Set Block Protection Configuration Register command

The Set Block Protection Configuration Register command is used to configure the Block

Protection Configuration Register to ‘Protected’, for a specific block. Protected blocks are

fully protected from program or erase when WP pin is Low, V . The status of a protected

IL

block can be changed to ‘Unprotected’ by using the Clear Block Protection Configuration

Register command. At power-up, all block are configured as ‘Protected’.

Two bus operations are required to issue a Set Block Protection Configuration Register

command:

■

The first cycle writes the setup command

The second write cycle specifies the address of the block to protect and confirms the

command. If the command is not confirmed, the sequence is aborted and the device

outputs the Status Register with bits 4 and 5 set to ‘1’.

To protect multiple blocks, the Set Block Protection Configuration Register command must

be repeated for each block.

Any attempt to re-protect a block already protected does not change its status.

4.14

Clear Block Protection Configuration Register command

The Clear Block Protection Configuration Register command is used to configure the Block

Protection Configuration Register to ‘Unprotected’, for a specific block thus allowing

program/erase operations to this block, regardless of the WP pin status.

Two bus operations are required to issue a Clear Block Protection Configuration Register

command:

■

The first cycle writes the setup command

The second write cycle specifies the address of the block to unprotect and confirms the

command. If the command is not confirmed, the sequence is aborted and the device

outputs the Status Register with bits 4 and 5 set to ‘1’.

To unprotect multiple blocks, the Clear Block Protection Configuration Register command

must be repeated for each block.

Any attempt to unprotect a block already unprotected does not affect its status.

37/81

Command interface

M58BW16F, M58BW32F

(1)

Table 10. Commands

Bus operations

2nd Cycle 3rd Cycle

Op. Addr. Data Op. Addr. Data Op. Addr. Data Op. Addr. Data

Command

1st Cycle

4th Cycle

Read Memory Array

≥ 2 Write

X

FFh Read RA

90h Read IDA

70h

RD

Read Electronic Signature⁽²⁾≥ 2 Write

IDD

Read Status Register

Read Query

1

Write

≥ 2 Write

98h Read RA

50h

RD

Clear Status Register

Block Erase

1

2

Write

Write 55h 20h Write BA

Write 55h 80h Write AAh

40h

D0h

Erase All Main Blocks

any block

Program

2

Write AAh

Write

PA

PD

10h

OTP Block

Write AAh 40h Write

PA

PD

N

Write to Buffer and Program N+4 Write AAh E8h Write BA

Write PA PD Write

X

D0h

Program/Erase Suspend

Program/Erase Resume

1

Write

X

B0h

D0h

Set Burst Configuration

Register

Š3 Write

X

60h Write BCRh 03h Read RA RD

Set Block Protection

Configuration Register

2

Write

60h Write BA

01h

D0h

Clear Block Protection

Configuration Register

1. X Don’t Care; RA Read Address, RD Read Data, ID Device Code, IDA Identifier Address, IDD Identifier Data, SRD Status

Register Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block,

BCR Burst Configuration Register value, N+1 number of Words to program, BA Block address.

2. The Manufacturer Code, the Device Code, the Burst Configuration Register, and the Block Protection Configuration

Register of each block are read using the Read Electronic Signature command.

38/81

M58BW16F, M58BW32F

Command interface

DQ31-DQ0

Table 11. Read Electronic Signature

Code

Device

Amax-A0

Manufacturer

Device

All

00000h

00001h

00000020h

0000883Ah

00008839h

00008838h

00008837h

M58BW16FT

M58BW16FB

M58BW32FT

M58BW32FB

Burst Configuration

Register

00005h

BCR⁽¹⁾

00000000h (Unprotected)

00000001h (Protected)

Block Protection

Configuration Register

All

SBA+02h⁽²⁾

1. BCR = Burst Configuration Register.

2. SBA is the start address of each block.

(1)

Table 12. Program, Erase times and endurance cycles

M58BWxxF

Typ

Parameters

Unit

Max

Min

Full Chip Program

15

1

20

35

s

µs

s

Double Word Program

512 Kbit Block Erase

2

256 Kbit Block Erase

0.8

0.6

1.6

s

64 Kbit Block Erase

1.2

s

Program Suspend Latency Time

Erase Suspend Latency Time

Minimum effective erase time⁽²⁾

Program/Erase Cycles (per Block)

10

µs

cycles

30

100,000

1. T_A= –40 to 125°C, V_DD= 2.7V to 3.6V, V_DDQ= 2.6V to V_DD

2. The minimum effective erase time is defined as the minimum time required between the last Erase

Resume command and the next Erase Suspend command for the internal Flash memory Program/Erase

Controller to be able to execute its algorithm.

39/81

Status Register

M58BW16F, M58BW32F

5

Status Register

The Status Register provides information on the current or previous Program, Erase or

Block Protect operation. The various bits in the Status Register convey information and

errors on the operation. They are output on DQ7-DQ0.

To read the Status Register the Read Status Register command can be issued. The Status

Register is automatically read after Program, Erase, Block Protect, Program/Erase Resume

commands. The Status Register can be read from any address.

The contents of the Status Register can be updated during an erase or program operation

by toggling the Output Enable or Output Disable pins or by de-activating (Chip Enable, V )

IH

and then reactivating (Chip Enable and Output Enable, V , and Output Disable, V .) the

IL

IH

device.

The Status Register bits are summarized in Table 13: Status Register Bits. Refer to Table 13

in conjunction with the following text descriptions.

5.1

Program/Erase Controller Status (Bit 7)

The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is

active or inactive. When the Program/Erase Controller Status bit is set to ‘0’, the

Program/Erase Controller is active; when bit7 is set to ‘1’, the Program/Erase Controller is

inactive.

The Program/Erase Controller Status is set to ‘0’ immediately after a Program/Erase

Suspend command is issued until the Program/Erase Controller pauses. After the

Program/Erase Controller pauses the bit is set to ‘1’.

During Program and Erase operations the Program/Erase Controller Status bit can be polled

to find the end of the operation. The other bits in the Status Register should not be tested

until the Program/Erase Controller completes the operation and the bit is set to ‘1’.

After the Program/Erase Controller completes its operation the Erase Status (bit5), Program

Status (bit4) bits should be tested for errors.

5.2

Erase Suspend Status (Bit 6)

The Erase Suspend Status bit indicates that an Erase operation has been suspended and is

waiting to be resumed. The Erase Suspend Status should only be considered valid when the

Program/Erase Controller Status bit is set to ‘1’ (Program/Erase Controller inactive); after a

Program/Erase Suspend command is issued the memory may still complete the operation

rather than entering the Suspend mode.

When the Erase Suspend Status bit is set to ‘0’, the Program/Erase Controller is active or

has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command

has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the Erase Suspend Status bit returns

to ‘0’.

40/81

M58BW16F, M58BW32F

Status Register

5.3

Erase Status (Bit 5)

The Erase Status bit can be used to identify if the memory has failed to verify that the block

has erased correctly. The Erase Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Controller inactive).

When the Erase Status bit is set to ‘0’, the memory has successfully verified that the block

has erased correctly. When the Erase Status bit is set to ‘1’, the Program/Erase Controller

has applied the maximum number of pulses to the block and still failed to verify that the

block has erased correctly.

Once set to ‘1’, the Erase Status bit can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase

command is issued, otherwise the new command will appear to fail.

5.4

Program/ Write to Buffer and Program Status (Bit 4)

The Program/Write to Buffer and Program Status bit is used to identify a Program failure or

a Write to Buffer and Program failure. Bit4 should be read once the Program/Erase

Controller Status bit is High (Program/Erase Controller inactive).

When bit 4 is set to ‘0’ the memory has successfully verified that the device has

programmed correctly. When bit 4 is set to ‘1’ the device has failed to verify that the data has

been programmed correctly.

Once set to 1’, the Program Status bit can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase

command is issued, otherwise the new command will appear to fail.

5.4.1

PEN Status (Bit 3)

The PEN Status bit can be used to identify if a program or erase operation has been

attempted when PEN is Low, V .

IL

When Bit 3 is set to ‘0’ no program or erase operations have been attempted with PEN Low,

V , since the last Clear Status Register command, or hardware reset.

IL

When Bit 3 is set to ‘1’ a program or erase operation has been attempted with PEN Low, V .

IL

Once set to ‘1’, Bit 3 can only be reset by an Clear Status Register command or a hardware

reset. If set to ‘1’ it should be reset before a new program or erase command is issued,

otherwise the new command will appear to fail.

41/81

Status Register

M58BW16F, M58BW32F

5.5

Program Suspend Status (Bit 2)

The Program Suspend Status bit indicates that a Program operation has been suspended

and is waiting to be resumed. The Program Suspend Status should only be considered valid

when the Program/Erase Controller Status bit is set to ‘1’ (Program/Erase Controller

inactive); after a Program/Erase Suspend command is issued the memory may still

complete the operation rather than entering the Suspend mode.

When the Program Suspend Status bit is set to ‘0’, the Program/Erase Controller is active or

has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command

has been issued and the memory is waiting for a Program/Erase Resume command.

When a Program/Erase Resume command is issued the Program Suspend Status bit

returns to ‘0’.

5.6

Block Protection Status (Bit 1)

The Block Protection Status bit can be used to identify if a Program or Erase operation has

tried to modify the contents of a protected block.

When the Block Protection Status bit is set to ‘0’, no Program or Erase operations have been

attempted to protected blocks since the last Clear Status Register command or hardware

reset; when the Block Protection Status bit is set to ‘1’, a Program or Erase operation has

been attempted on a protected block.

Once set to ‘1’, the Block Protection Status bit can only be reset Low by a Clear Status

Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program

or Erase command is issued, otherwise the new command will appear to fail.

5.7

Bit 0

Reserved bit (set to ‘1’).

42/81

M58BW16F, M58BW32F

Status Register

Table 13. Status Register Bits

Bit

Name

Logic Level

Definition

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

‘0’

‘1’

’1’

’0’

Ready

7

Program/Erase Controller Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In Progress or Completed

Erase Error

Erase Success

Program Error

Program Status,

Program Success

no program or erase attempted

program or erase attempted

Suspended

PEN Status bit

Program Suspend Status

In Progress or Completed

program/erase on protected block,

abort

’1’

Erase/Program in a Protected

Block

1

0

’0’

’1’

No operations to protected blocks

Reserved

43/81

Maximum rating

M58BW16F, M58BW32F

6

Maximum rating

Stressing the device above the ratings listed in Table 14: Absolute maximum ratings, may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 14. Absolute maximum ratings

Value

Symbol

Parameter

Unit

Min

Max

T_BIAS

T_STG

Temperature Under Bias

Storage Temperature

–40

–55

125

155

°C

V_DDQ+0.6

V_IO

Input or Output Voltage

–0.6

V

V_DDQIN+0.6

V

_DD, V_DDQ,V_DDQINSupply Voltage

4.2

44/81

M58BW16F, M58BW32F

DC and AC parameters

7

DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 15: Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the measurement conditions when relying on the

quoted parameters.

Table 15. Operating and AC measurement conditions

M58BW16F, M58BW32F

Parameter

45ns

55ns

Units

Min

Max

Min

Max

Supply Voltage (V_DD

)

2.7

2.4

–40

3.6

125

2.5

2.4

–40

3.3

3.6

125

V

Input/Output Supply Voltage (V_DDQ

Ambient Temperature (T_A)

Load Capacitance (C_L)

)

Grade 3

°C

pF

ns

V

30

Clock Rise and Fall Times

Input Rise and Fall Times

Input Pulses Voltages

3

0 to V_DDQ

_DDQ/2

0 to V_DDQ

V_DDQ/2

Input and Output Timing Ref. Voltages

V

Figure 5.

AC measurement input/output waveform

V

DDQ

V

DDQIN

V

/2

DDQ

V

DDQIN

0V

AI04153

1. V_DD= V_DDQ

.

Figure 6.

AC measurement load circuit

DEVICE

UNDER

TEST

OUT

C

L

C

includes JIG capacitance

L

AI04154b

45/81

DC and AC parameters

M58BW16F, M58BW32F

(1)(2)

Table 16. Device capacitance

Symbol

Parameter

Test Condition

Typ

Max

Unit

C_IN

Input Capacitance

Output Capacitance

V_IN= 0V

6

8

pF

C_OUT

V_OUT= 0V

12

1. T_A= 25°C, f = 1 MHz

2. Sampled only, not 100% tested.

Table 17. DC characteristics

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

I_LI

Input Leakage Current

Output Leakage Current

0V≤V_IN≤V_DDQ

0V≤V_OUT≤V_DDQ

E = V_IL, G = V_IH,

±1

±5

µA

I_LO

Supply Current (Random

Read)

(1)

I_DD

25

20

50

mA

f_add= 6MHz

(2)

I_DDP-UP

Supply Current (Power-up)

Supply Current (Burst

Read)

E = V_IL, G = V_IH,

f_clock= 75MHz

(1)

I_DDB

I_DD1

I_DD2

I_DD3

I_DD4

E = RP = V_DD

0.2V

±

(1)

Supply Current (Standby)

150

30

µA

mA

µA

Supply Current (Program Program, Erasein

or Erase)

progress

Supply Current

E = V_IH

150

10

(Erase/Program Suspend)

Supply Current (Standby

Disable)

5

mA

V

V_IL

V_IH

Input Low Voltage

–0.5

0.2V_DDQIN

V_DDQ+0.3

Input High Voltage (for DQ

lines)

0.8V_DDQIN

V

Input High Voltage (for

Input only lines)

V_IH

V_OL

V_OH

3.6

0.1

V

Output Low Voltage

I_OL= 100µA

Output High Voltage

CMOS

I_OH= –100µA

V_DDQ–0.1

V_DDSupply Voltage (Erase

and Program lockout)

V_LKO

2.2

V

1. The Standby mode can be disabled by setting the Standby Disable bit (M14) of the Burst Configuration

Register to ‘1’.

2. I_DDP-UPis defined only during the power-up phase, from the moment current is applied with RP Low to the

moment when the supply voltage has become stable and RP is brought to High.

46/81

M58BW16F, M58BW32F

Figure 7.

DC and AC parameters

Asynchronous Bus Read AC waveforms

tAVAV

VALID

A0-A19

tAVQV

tEHLX

L

tELQX

tELQV

tAXQX

E

tGLQX

tGLQV

tEHQX

tEHQZ

G

GD

tGHQX

tGHQZ

DQ0-DQ31

OUTPUT

See also Page Read

AI08921b

Figure 8.

Asynchronous Latch controlled bus Read AC waveforms

A0-A19

VALID

tLHAX

L

tLHLL

tLLLH

tEHLX

E

tEHQX

tEHQZ

tGLQX

tGLQV

G

tLLQV

tLLQX

tGHQX

GHQZ

DQ0-DQ31

OUTPUT

See also Page Read

AI08922b

47/81

DC and AC parameters

M58BW16F, M58BW32F

Figure 9.

Asynchronous Chip Enable controlled bus Read AC waveforms

A0-A19

VALID

tLHAX

L

tEHLX

E

tEHQX

tEHQZ

tGLQX

tGLQV

G

tELQX

tELQV

tGHQX

GHQZ

DQ0-DQ31

OUTPUT

See also Page Read

AI13434

Figure 10. Asynchronous Address controlled bus Read AC waveforms

A0-A19

VALID

tLHAX

L

tEHLX

E

tEHQX

tEHQZ

tGLQX

tGLQV

G

tGHQX

GHQZ

tAVQV

DQ0-DQ31

OUTPUT

See also Page Read

AI13435

48/81

M58BW16F, M58BW32F

DC and AC parameters

Table 18. Asynchronous Bus Read AC characteristics

M58BWxxF

Unit

Symbol

Parameter

Test Condition

45

55

t_AVAV

Address Valid to Address Valid

E = V_IL, G = V_ILMin

E = V_IL, G = V_ILMax

45

55

ns

t_AVQVAddress Valid to Output Valid

45

0

55

0

ns

t_AXQXAddress Transition to Output Transition L = V_IL, G = V_ILMin

Chip Enable High to Latch Enable

t_EHLX

Min

0

ns

Transition

t_EHQXChip Enable High to Output Transition

G = V_IL

Min

0

ns

t_EHQZChip Enable High to Output Hi-Z

Max

20

(1)

t_ELQV

Chip Enable Low to Output Valid

G = V_IL

Max

45

55

ns

t_GHQXOutput Enable High to Output Transition

t_GHQZOutput Enable High to Output Hi-Z

t_GLQVOutput Enable Low to Output Valid

t_GLQXOutput Enable Low to Output Transition

t_LHAXLatch Enable High to Address Transition

E = V_IL

Min

Max

Min

0

15

0

15

0

ns

5

t_LHLL

t_LLLH

Latch Enable High to Latch Enable Low

Latch Enable Low to Latch Enable High

10

E = V_IL

Latch Enable Low to Output Valid

Chip Enable Low to Output Valid

t_LLQV

t_LLQX

E = V_IL, G = V_ILMax

45

55

ns

Latch Enable Low to Output Transition

E = V_IL, G = V_ILMin

L = V_IL, G = V_ILMin

0

ns

t_ELQXChip Enable Low to Output Transition

1. Output Enable G may be delayed up to t_ELQV- t_GLQVafter the falling edge of Chip Enable E without

increasing t_ELQV

.

49/81

DC and AC parameters

M58BW16F, M58BW32F

Figure 11. Asynchronous Page Read AC waveforms

A0-A1

A0 and/or A1

tAVQV1

tAXQX

OUTPUT + 1

OUTPUT

DQ0-DQ31

AI03646

(1)

Table 19. Asynchronous Page Read AC characteristics

M58BWxxF

Symbol Parameter Test Condition

Unit

45

55

t_AVQV1Address Valid to Output Valid

t_AXQXAddress Transition to Output Transition

E = V_IL, G = V_IL

Max

Min

25

0

25

0

ns

1. For other timings see Table 18: Asynchronous Bus Read AC characteristics.

50/81

M58BW16F, M58BW32F

DC and AC parameters

Figure 12. Asynchronous Write AC waveform

51/81

DC and AC parameters

M58BW16F, M58BW32F

Figure 13. Asynchronous Latch controlled Write AC waveform

52/81

M58BW16F, M58BW32F

DC and AC parameters

Table 20. Asynchronous Write and Latch controlled Write AC characteristics

M58BWxxF

Symbol

Parameter

Test Condition

Unit

45

55

t_AVAV

t_AVLH

t_AVLL

t_AVWH

t_DVWH

t_ELLL

Address Valid toAddress Valid

Min

45

8

55

8

Address Valid to Latch Enable High

Address Valid to Latch Enable Low

Address Valid to Write Enable High

Data Input Valid to Write Enable High

Chip Enable Low to Latch Enable Low

Chip Enable Low to Write Enable Low

Latch Enable High to Address Transition

Latch Enable Low to Latch Enable High

latch Enable Low to Write Enable High

Min

ns

0

E = V_IL

25

0

25

0

t_ELWL

t_LHAX

t_LLLH

t_LLWH

0

5

10

25

0

10

25

0

E = V_IL

t_QVVPLOutput Valid to PEN Low

t_VPHWHPEN High to Write Enable High

0

t_WHAX

t_WHDX

t_WHEH

t_WHGL

t_WHQV

t_WHWL

t_WLWH

t_QVPL

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

Write Enable High to Output Valid

E = V_IL

0

150

165

20

25

0

150

165

20

25

0

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Output Valid to Reset/Power-down Low

E = V_IL

53/81

DC and AC parameters

M58BW16F, M58BW32F

Figure 14. Synchronous Burst Read, Latch Enable controlled (data valid from ’n’

clock rising edge)

54/81

M58BW16F, M58BW32F

DC and AC parameters

Figure 15. Synchronous Burst Read, Chip Enable controlled (data valid from ’n’

clock rising edge)

55/81

DC and AC parameters

M58BW16F, M58BW32F

Figure 16. Synchronous Burst Read, Valid Address transition controlled (data valid

from ’n’ clock rising edge)

56/81

M58BW16F, M58BW32F

DC and AC parameters

Figure 17. Synchronous Burst Read (data valid from ’n’ clock rising edge)

n

n+1

n+2

n+3

n+4

n+5

K

tKHQV

DQ0-DQ31

Q0

Q1

Q2

Q3

Q4

Q5

tKHQX

SETUP

Burst Read

Q0 to Q3

Note: n depends on Burst X-Latency

AI04408c

1. For set up signals and timings see Synchronous Burst Read.

Figure 18. Synchronous Burst Read - valid data ready output

K

(1)

Output

R

V

tRLKH

(2)

AI03649b

1. Valid Data Ready = Valid Low during valid clock edge

2. V= Valid output.

3. The internal timing of R follows DQ.

57/81

DC and AC parameters

M58BW16F, M58BW32F

Figure 19. Synchronous Burst Read - burst address advance

K

VALID

A0-A19

L

DQ0-DQ31

G

Q0

Q1

Q2

tGLQV

tBLKH

tBHKH

B

AI03650

Figure 20. Clock input AC waveform

tKHKL

K

tKLKH

ai13286

58/81

M58BW16F, M58BW32F

DC and AC parameters

(1) (2)

Table 21. Synchronous Burst Read AC characteristics

M58BWxxF

Unit

Symbol

Parameter

Test Condition

45

55

X-Latency = 3

X-Latency = 4

Max

40

56

75

33

40

56

MHz

f

Clock frequency

X-Latency = 5 or 6

E = V_IL, L = V_IL

X-Latency = 3

Min

9

6

ns

t_AVKHAddress Valid to Valid Clock Edge,

E = V_IL, L = V_IL

X-Latency = 4, 5 or 6

t_KHKL

t_KLKH

Clock High Time

Clock Low Time

Min

6

ns

Burst Address Advance High to Valid

Clock Edge

t_BHKH

t_BLKH

E = V_IL, G = V_IL, L = V_IH

Min

8

9

6

8

6

ns

Burst Address Advance Low to Valid

Clock Edge

L = V_IL

X-Latency = 3

t_ELKH

Chip Enable Low to Valid Clock Edge

L = V_IL

X-Latency = 4, 5 or 6

t_GLQVOutput Enable Low to Output Valid

t_KHAXValid Clock Edge to Address Transition

E = V_IL, L = V_IH

E = V_IL

Max

Min

15

5

15

5

ns

t_KHEL

t_KHLL

Valid Clock Edge to Chip Enable Low

Valid Clock Edge to Latch Enable Low

L = V_IL

0

E = V_IL

0

t_KHLHValid Clock Edge to Latch Enable High

t_KHQXValid Clock Edge to Output Transition

E = V_IL

0

E = V_IL, G = V_IL, L = V_IH

2

E = V_IL

X-Latency = 3

Min

9

6

ns

t_LLKH

Latch Enable Low to Valid Clock Edge,

E = V_IL

X-Latency = 4, 5 or 6

Valid Data Ready Low to Valid Clock

Edge

t_RLKH

E = V_IL, G = V_IL, L = V_IH

Min

6

8

6

8

ns

t_KHQVValid Clock Edge to Output Valid

Max

1. Data output should be read on the valid clock edge.

2. For other timings see Table 18: Asynchronous Bus Read AC characteristics.

59/81

DC and AC parameters

M58BW16F, M58BW32F

Figure 21. Reset, Power-Down and Power-up AC waveform

W, E, G

tPHWL

tPHEL

tPHGL

tPLRH

R

tPHWL

tPHEL

tPHGL

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI03849b

Table 22. Reset, Power-Down and Power-up AC characteristics

Symbol

Parameter

Min

Max

Unit

t_PHEL

Reset/Power-down High to Chip Enable Low

Reset/Power-down High to Output Valid

50

ns

µs

(1)

t_PHQV

130

t_PHWL

t_PHGL

t_PLPH

Reset/Power-down High to Write Enable Low

Reset/Power-down High to Output Enable Low

Reset/Power-down Low to Reset/Power-down High

Reset/Power-down Low to Valid Data Ready High

Supply Voltages High to Reset/Power-down High

50

100

2

t_PLRH

t_VDHPH

30

50

1. This time is t_PHEL+ t_AVQVor t_PHEL+ t_ELQV

.

60/81

M58BW16F, M58BW32F

Package mechanical

8

Package mechanical

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 22. LBGA80 10 × 12mm - 8 × 10 ball array, 1mm pitch, bottom view package

outline

D

D1

FD

FE

SD

SE

E

E1 BALL "A1"

ddd

e

b

A

A2

A1

BGA-Z05

1. Drawing is not to scale.

61/81

Package mechanical

M58BW16F, M58BW32F

Table 23. LBGA80 10 × 12mm - 8 × 10 active ball array, 1mm pitch, package

mechanical data

millimeters

inches

Min

Symbol

Typ

Min

Max

Typ

Max

A

A1

A2

b

1.700

0.0669

0.350

0.0138

1.100

0.500

10.000

7.000

0.0433

0.0197

0.3937

0.2756

D

–

D1

ddd

E

–

0.120

0.0047

12.000

9.000

1.000

1.500

0.500

–

0.4724

0.3543

0.0394

0.0591

0.0197

–

E1

e

FD

FE

SD

SE

62/81

M58BW16F, M58BW32F

Package mechanical

Figure 23. PQFP80 - 80 lead Plastic Quad Flat Pack, package outline

Ne

A2

N

1

e

b

Nd

D2 D1

D

E2

E1

E

A

c

CP

L1

A1

α

L

QFP-B

1. Drawing is not to scale.

Table 24. PQFP80 - 80 lead Plastic Quad Flat Pack, package mechanical data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

3.400

0.1339

0.250

2.550

0.300

0.0098

0.1004

0.0118

2.800

3.050

0.450

0.100

0.230

23.450

20.100

–

0.1102

0.1201

0.0177

0.0039

0.0091

0.9232

0.7913

–

CP

c

0.130

22.950

19.900

–

0.0051

0.9035

0.7835

–

D

23.200

20.000

18.400

0.800

0.9134

0.7874

0.7244

0.0315

0.6772

0.5512

0.4724

0.0315

0.0630

D1

D2

e

–

E

17.200

14.000

12.000

0.800

16.950

13.900

–

17.450

14.100

–

0.6673

0.5472

–

0.6870

0.5551

–

E1

E2

L

0.650

–

0.950

–

0.0256

–

0.0374

–

L1

α

1.600

0°

7°

0°

7°

N

80

Nd

Ne

24

16

63/81

Part numbering

M58BW16F, M58BW32F

9

Part numbering

Table 25. Ordering information scheme

Example:

M58BW32F

T

4

T

3

T

Device Type

M58

Architecture

B = Burst Mode

Operating Voltage

W = [2.7 V to 3.6 V] V_DDrange for 45 ns speed class

[2.5 V to 3.3 V] V_DDrange for 55 ns speed class

[2.4 V to V_DD] V_DDQrange for 45 ns and 55 ns speed classes

Device Function

32F = 32 Mbit (x32), Boot Block, Burst, 0.11µm technology

16F = 16 Mbit (x32), Boot Block, Burst, 0.11µm technology

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

4 = 45 ns

5 = 55 ns

Package

T = PQFP80

ZA = LBGA80: 1.0mm pitch

Device Grade

3 = Automotive grade certified⁽¹⁾, –40 to 125 °C

Option

Blank = Standard packing

T = Tape & Reel Packing

F = ECOPACK® Package, Tape & Reel 24mm Packing

1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening

according to AEC Q001 & Q002 or equivalent.

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc) or for further information on any aspect

of this device, please contact the ST Sales Office nearest to you.

64/81

M58BW16F, M58BW32F

Flowcharts

Appendix A Flowcharts

Figure 24. Program flowchart and pseudo code

Start

Program Command:

– write 40h, Address AAh

– write Address & Data

Write 40h

(memory enters read status

state after the Program command)

Write Address

& Data

Read Status

Register

do:

– read status register

(E or G must be toggled)

NO

b7 = 1

while b7 = 1

YES

NO

PEN Invalid

Error (1)

If b3 = 1, PEN invalid error:

– error handler

b3 = 0

YES

Program

Error (1)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

Program to Protect

Block Error

If b1 = 1, Program to Protected Block Error:

– error handler

b1 = 0

YES

End

AI03850e

1. If an error is found, the Status Register must be cleared before further P/E operations.

65/81

Flowcharts

M58BW16F, M58BW32F

Figure 25. Program Suspend & Resume flowchart and pseudo code

Start

Write B0h

Program/Erase Suspend Command:

– write B0h

– write 70h

Write 70h

do:

Read Status

Register

– read status register

NO

b7 = 1

YES

while b7 = 1

If b2 = 0, Program completed

b2 = 1

YES

Program Complete

Read Memory Array Command:

– write FFh

Write FFh

– one or more data reads

from other blocks

Read data from

another block

Program Erase Resume Command:

– write D0h

to resume programming

– if the program operation completed

then this is not necessary. The device

returns to Read Array as normal

(as if the Program/Erase Suspend

command was not issued).

Write D0h

Write FFh

Read Data

Program Continues

AI00612b

66/81

M58BW16F, M58BW32F

Flowcharts

Figure 26. Block Erase flowchart and pseudo code

Start

Erase Command:

Write 20h

– write 20h, Address 55h

– write Block Address

(A11-A19) & D0h

(memory enters read status

state after the Erase command)

Write Block Address

& D0h

NO

do:

Read Status

– read status register

(E or G must be toggled)

if Erase command given execute

suspend erase loop

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

YES

NO

PEN Invalid

Error (1)

If b3 = 1, PEN invalid error:

– error handler

b3 = 0

YES

Command

Sequence Error

If b4, b5 = 1, Command Sequence error:

– error handler

b4 and b5

= 1

NO

Erase

Error (1)

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

Erase to Protected

Block Error

If b1 = 1, Erase to Protected Block Error:

– error handler

b1 = 0

YES

End

AI08623d

1. If an error is found, the Status Register must be cleared before further P/E operations.

67/81

Flowcharts

M58BW16F, M58BW32F

Figure 27. Erase Suspend & Resume flowchart and pseudo code

Erase cycle in progress

Write B0h

Program/Erase Suspend Command

Write 70h

Read Status

Register

Do:

– Read status register while b7 = 1

(b7 = Program/Erase status bit)

NO

b7 = 1

YES

If b6 = 0, Erase is completed

(b6 = Erase Suspend status bit)

b6 = 1

YES

Erase Complete

The device returns to Read mode as normal

(as if the Program/Erase Suspend was not issued).

Write FFh

Read Data

Read Memory Array command:

– Write FFh

– One or more data reads

from other blocks

Read data from

another block

or Program

Write D0h

Program/Erase Resume command:

– Write D0h to resume the Erase

operation

Erase Continues

AI00615c

68/81

M58BW16F, M58BW32F

Flowcharts

Figure 28. Power-up sequence followed by Synchronous Burst Read

Power-up

or Reset

BCR bit 15 = '1'

Asynchronous Read

Set Burst Configuration Register Command:

– write 60h

Write 60h command

– write 03h

and BCR on A15-A0

Write 03h with A15-A0

BCR inputs

BCR bit 15 = '0'

BCR bit 14-bit 0 = '1'

Synchronous Read

AI03834

69/81

Flowcharts

M58BW16F, M58BW32F

Figure 29. Command Interface and Program Erase Controller flowchart (a)

WAIT FOR

COMMAND

WRITE

READ

ARRAY

NO

90h

YES

READ ELEC.

SIGNATURE

NO

98h

YES

D

READ CFI

NO

70h

YES

READ

STATUS

NO

20h

YES

ERASE

SET-UP

NO

40h

YES

ERASE

COMMAND

ERROR

NO

PROGRAM

SET-UP

D0h

50h

E

YES

A

CLEAR

C

STATUS

D

READ

STATUS

B

AI03835

70/81

M58BW16F, M58BW32F

Flowcharts

Figure 30. Command Interface and Program Erase Controller flowchart (b)

E

NO

48h

YES

TP

NO

78h

YES

PROGRAM

SET_UP

F

TP

UNLOCK

SET_UP

NO

60h

YES

NO

FFh

YES

G

SET BCR

SET_UP

NO

03h

YES

D

AI03836

71/81

Flowcharts

M58BW16F, M58BW32F

Figure 31. Command Interface and Program Erase Controller flowchart (c)

A

B

ERASE

YES

READY

NO

READ

STATUS

B0h

YES

ERASE

SUSPEND

YES

READY

NO

ERASE

SUSPENDED

READ

STATUS

YES

READ

STATUS

70h

NO

YES

PROGRAM

SET_UP

40h

NO

C

NO

READ

STATUS

READ

ARRAY

D0h

AI03837

72/81

M58BW16F, M58BW32F

Flowcharts

Figure 32. Command Interface and Program Erase Controller flowchart (d)

C

B

PROGRAM

YES

READY

NO

READ

STATUS

B0h

YES

PROGRAM

SUSPEND

YES

READY

NO

PROGRAM

SUSPENDED

READ

STATUS

YES

READ

STATUS

70h

NO

YES

READ

STATUS

READ

ARRAY

D0h

AI03838

73/81

Flowcharts

M58BW16F, M58BW32F

Figure 33. Command Interface and Program Erase Controller flowchart (e)

F

B

TP

PROGRAM

YES

NO

READ

STATUS

READY

G

B

TP

UNLOCK

YES

NO

READ

STATUS

READY

AI03839

74/81

M58BW16F, M58BW32F

Common Flash Interface (CFI)

Appendix B Common Flash Interface (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be

read from the Flash memory device. It allows a system software to query the device to

determine various electrical and timing parameters, density information and functions

supported by the memory. The system can interface easily with the device, enabling the

software to upgrade itself when necessary.

When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the

data structure is read from the memory. Table 26, Table 27, Table 28, Table 31 and Table 30

show the addresses used to retrieve the data.

Table 26. Query structure overview

Offset

Sub-section Name

Description

Manufacturer Code ST

M58BW16FT (top)

00h 0020h

883A

8839

8838

M58BW16FB (bottom)

M58BW32FT (top)

01h

Device Code

8837

M58BW32FB (bottm)

10h CFI Query Identification String

1Bh System Interface Information

27h Device Geometry Definition

Command set ID and algorithm data offset

Device timing and voltage information

Flash memory layout

Primary Algorithm-specific Extended Query

Table

Additional information specific to the

Primary Algorithm (optional)

P(h)⁽¹⁾

Alternate Algorithm-specific Extended Query Additional information specific to the

A(h)⁽²⁾

Table

Alternate Algorithm (optional)

1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.

2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.

75/81

Common Flash Interface (CFI)

M58BW16F, M58BW32F

(1) (2)

Table 27. CFI - Query address and data output

Address A0-Amax

Data

Instruction

10h

11h

12h

13h

14h

51h

52h

59h

"Q"

"R"

"Y"

51h;"Q"

Query ASCII String 52h;"R"

59h; "Y"

03h

00h

Primary Vendor:

Command Set and Control Interface ID Code

35h (M58BW16F)

39h (M58BW32F)

15h

Primary algorithm extended Query Address Table:

P(h)

16h

17h

18h

19h

1Ah

00h

Alternate Vendor:

Command Set and Control Interface ID Code

Alternate Algorithm Extended Query address Table

1. The x8 or Byte Address and the x16 or Word Address mode are not available.

2. Query Data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'.

Table 28. CFI - Device voltage and timing specification

Address

Data

Description

Value

A0-Amax

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h⁽¹⁾

36h⁽¹⁾

V_DDmin

V_DDmax

Reserved

2.7 V

3.6 V

xxxx xxxxh

04h

2ⁿµs typical for Word, DWord prog

xxxx xxxxh

0Ah

Reserved

2ⁿms, typical time-out for Erase Block

1 s

xxxx xxxxh

Reserved

1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.

76/81

M58BW16F, M58BW32F

Common Flash Interface (CFI)

Table 29. M58BW16F device geometry definition

Address A0-Amax

Data

Description

Value

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

15h

03h

00h

02h

1Eh

00h

01h

07h

00h

20h

00h

2ⁿnumber of bytes memory size

Device Interface Sync./Async.

Organization Sync./Async.

2 MBytes

x32

Async.

Maximum number of Byte in multi-Byte program = 2ⁿ32 Bytes

Bit7-0 = number of Erase Block Regions in device

2

Number (n-1) of erase blocks of identical size; n=31 31 blocks

Erase Block region information x 256 bytes per Erase

Block (64 Kbytes)

512 Kbits

Number (n-1) of erase blocks of identical size; n=8

8 blocks

64 Kbits

Erase Block region information x 256 bytes per Erase

Block (8 Kbytes)

Table 30. M58BW16F extended query information

Address

Address offset

Data (Hex)

Description

Amax-A0

(P)h

35h

36h

37h

38h

39h

50

52

49

P

R

Y

(P+1)h

(P+2)h

(P+3)h

(P+4)h

Query ASCII string - Extended Table

31h

Major revision number

Minor revision number

Optional Feature: (1=yes, 0=no)

bit0, Chip Erase Supported (0= no)

bit1, Suspend Erase Supported (1=yes)

bit2, Suspend Program Supported (1=yes)

bit3, Lock/Unlock Supported (0=no)

bit4, Queue Erase Supported (0=no)

bit5, Instant individual block locking (0=no)

bit6, Protection bits supported (0=no)

bit7, Page read supported (1=yes)

bit8, Synchronous read supported (1=yes)

Bit 9 reserved

(P+5)h

3Ah

86h

(P+6)h

(P+7)h

(P+8)h

3Bh

3Ch

3Dh

01h

00h

Synchronous read supported

77/81

Common Flash Interface (CFI)

M58BW16F, M58BW32F

Table 30. M58BW16F extended query information (continued)

Address

Amax-A0

Address offset

Data (Hex)

Description

Function allowed after Suspend:

(P+9)h

3Eh

01h

Program allowed after Erase Suspend (1=yes)

Bit 7-1 reserved for future use

(P+A)h-(P+40)h 3Fh-7Fh

Reserved

(P+41)h

(P+42)h

(P+43)h

(P+44)h

80h

81h

82h

83h

xxxx xxxxh Unique Device ID - 1 (16 bits)

xxxx xxxxh Unique Device ID - 2 (16 bits)

xxxx xxxxh Unique Device ID - 3 (16 bits)

xxxx xxxxh Unique Device ID - 4 (16 bits)

Table 31. M58BW32F device geometry definition

Address A0-Amax

Data

Description

Value

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

16h

03h

00h

05h

00h

03h

3Dh

00h

01h

07h

00h

20h

00h

03h

00h

40h

00h

2ⁿnumber of bytes memory size

Device Interface Sync./Async.

Organization Sync./Async.

4 MBytes

x32

Async.

Page size in bytes, 2ⁿ

32 Bytes

Bit7-0 = number of Erase Block Regions in device

3

Number (n-1) of Erase Block Regions of identical

size; n = 62

62

Erase Block region information x 256 bytes per Erase

Block (64 Kbytes)

512 Kbits

Number (n-1) of Erase blocks of identical size; n = 8 8 blocks

Erase Block region information x 256 bytes per Erase

Block (8 Kbytes)

64 Kbits

Number (n-1) of Erase Block of identical size; n = 4

4 blocks

Erase Block Region Information x 256 bytes per

Erase block (16 Kbytes)

128 Kbits

78/81

M58BW16F, M58BW32F

Common Flash Interface (CFI)

Description

Table 32. M58BW32F Extended query information

Address

Amax-A0

Address offset

Data (Hex)

(P)h

39h

3Ah

3Bh

3Ch

3Dh

50

52

49

P

R

Y

(P+1)h

(P+2)h

(P+3)h

(P+4)h

Query ASCII string - Extended Table

31h

Major revision number

Minor revision number

Optional Feature: (1=yes, 0=no)

bit0, Chip Erase Supported (0= no)

bit1, Suspend Erase Supported (1=yes)

bit2, Suspend Program Supported (1=yes)

bit3, Lock/Unlock Supported (0=no)

bit4, Queue Erase Supported (0=no)

bit5, Instant individual block locking (0=no)

bit6, Protection bits supported (0=no)

bit7, Page read supported (1=yes)

bit8, Synchronous read supported (1=yes)

Bit 9 reserved

(P+5)h

3Eh

86h

(P+6)h

(P+7)h

(P+8)h

3Fh

40h

41h

01h

00h

Synchronous read supported

Function allowed after Suspend:

(P+9)h

42h

01h

Program allowed after Erase Suspend (1=yes)

Bit 7-1 reserved for future use

(P+A)h-(P+40)h 43h-7Fh

Reserved

(P+41)h

(P+42)h

(P+43)h

(P+44)h

80h

81h

82h

83h

xxxx xxxxh Unique Device ID - 1 (16 bits)

xxxx xxxxh Unique Device ID - 2 (16 bits)

xxxx xxxxh Unique Device ID - 3 (16 bits)

xxxx xxxxh Unique Device ID - 4 (16 bits)

79/81

Revision history

M58BW16F, M58BW32F

Revision history

Table 33. Document revision history

Date

Revision

Changes

09-Jun-2006

1

Initial release.

_PENsignal renamed as PEN and Program/Erase Enable (PEN)

V

modified.

Continuous burst and wrap options are not available, X-Latencies 7

and 8 removed (see Table 8: Burst Configuration Register and

Table 9: Burst type definition). Notes removed below Table 8.

t_WHQVtiming modified in Table 20: Asynchronous Write and Latch

controlled Write AC characteristics.

I_DDmax modified and I_DD4added to Table 17: DC characteristics.

t_AXQXmodified in Table 19: Asynchronous Page Read AC

characteristics.

23-Nov-2006

2

Read access specified in Asynchronous Bus Read and

Synchronous Burst Read.

t_AVKHand t_ALKHadded and t_KHQVfor 55 ns modified in Table 21:

Synchronous Burst Read AC characteristics. Figure 9, Figure 10,

Figure 18 and Figure 19 added. Double Word Program max

modified and Minimum effective erase time added to Table 12:

Program, Erase times and endurance cycles.

All Asynchronous Bus Read AC characteristics brought together in

Table 18: Asynchronous Bus Read AC characteristics. t_LLEL

removed from Table 18 and Figure 7. Appendix B: Common Flash

Interface (CFI) modified.

80/81

M58BW16F, M58BW32F

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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

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型号：	M58BW16FT5ZA3T
厂家：	ST
描述：	16 or 32 Mbit (x32, Boot Block, Burst) 3.3V supply Flash memories 16或32兆位（ X32 ，引导块，爆发） 3.3V电源闪存闪存存储内存集成电路
文件：	总81页 (文件大小：661K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58BW16FT5ZA3T [STMICROELECTRONICS]

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