M58CR032C100ZB6T_技术文档

M58CR032C

M58CR032D

32 Mbit (2Mb x 16, Dual Bank, Burst )

1.8V Supply Flash Memory

PRELIMINARY DATA

FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V

= 1.65V to 2V for Program, Erase and

DD

Read

– V

= 1.65V to 3.3V for I/O Buffers

DDQ

– V = 12V for fast Program (optional)

PP

■ SYNCHRONOUS / ASYNCHRONOUS READ

– Burst mode Read: 54MHz

FBGA

– Page mode Read (4 Words Page)

– Random Access: 85, 100, 120 ns

■ PROGRAMMING TIME

– 10µs by Word typical

TFBGA56 (ZB)

6.5 x 10 mm

– Double/Quadruple Word programming option

■ MEMORY BLOCKS

– Dual Bank Memory Array: 8/24 Mbit

– Parameter Blocks (Top or Bottom location)

■ DUAL OPERATIONS

– Read in one Bank while Program or Erase in

other

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– No delay between Read and Write operations

■ BLOCK LOCKING

– Top Device Code, M58CR032C: 88C8h

– Bottom Device Code, M58CR032D: 88C9h

– All blocks locked at Power up

– Any combination of blocks can be locked

– WP for Block Lock-Down

■ SECURITY

– 64 bit user programmable OTP cells

– 64 bit unique device identifier

– One parameter block permanently lockable

■ COMMON FLASH INTERFACE (CFI)

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

September 2002

1/63

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M58CR032C, M58CR032D

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

V

Supply Voltage (1.65V to 2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DD

Supply Voltage (1.65V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DDQ

Program Supply Voltage (12V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PP

SS

and V

Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SSQ

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Asynchronous Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reset/Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Synchronous Single Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Synchronous Single Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

X-Latency Bits (M13-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-Down Bit (M10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Wait Bit (M8).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/63

M58CR032C, M58CR032D

Wrap Burst Bit (M3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Burst length Bits (M2-M0).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Burst Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. X-Latency Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Wait Configuration Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 7. Dual Bank Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 9. Read Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 10. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 11. Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 12. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 26

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3/63

M58CR032C, M58CR032D

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

V

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PP

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 15. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 16. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 17. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 19. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 20. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11. Asynchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 12. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 21. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 13. Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 22. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 14. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 23. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 15. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 24. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 16. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 25. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline. . 45

Table 26. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . 45

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 47

APPENDIX A. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 30. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 31. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 32. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 33. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4/63

M58CR032C, M58CR032D

Table 34. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 35. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

APPENDIX B. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 18. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 20. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 21. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 56

Figure 22. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 24. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 25. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 60

APPENDIX C. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 36. Command Interface States - Lock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 37. Command Interface States - Modify Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5/63

M58CR032C, M58CR032D

SUMMARY DESCRIPTION

The M58CR032 is a 32 Mbit (2Mbit x16) non-vola-

tile Flash memory that may be erased electrically

at block level and programmed in-system on a

Status Register. The command set required to

control the memory is consistent with JEDEC stan-

dards.

Word-by-Word basis using a 1.65V to 2.0V V

DD

The device supports synchronous burst read and

asynchronous read from all blocks of the memory

array; at power-up the device is configured for

page mode read. In synchronous burst mode, data

is output on each clock cycle at frequencies of up

to 54MHz.

The M58CR032 features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

supply for the circuitry and a 1.65V to 3.3V V

DDQ

supply for the Input/Output pins. An optional 12V

V

power supply is provided to speed up custom-

PP

er programming. The V pin can also be used as

PP

a control pin to provide absolute protection against

program or erase.

The device features an asymmetrical block archi-

tecture. M58CR032 has an array of 71 blocks and

is divided into two banks, Banks A and B, provid-

ing Dual Bank operations. While programming or

erasing in Bank A, read operations are possible in

Bank B or vice versa. Only one bank at a time is

allowed to be in program or erase mode. It is pos-

sible to perform burst reads that cross bank

boundaries. The bank architecture is summarized

in Table 2, and the memory maps are shown in

Figure 4. The Parameter Blocks are located at the

top of the memory address space for the

M58CR032C and at the bottom for the

M58CR032D.

Each block can be erased separately. Erase can

be suspended, in order to perform either read or

program in any other block, and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

When V ≤ V

all blocks are protected against

PP

PPLK

program or erase. All blocks are locked at Power

Up.

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system’s design. The Protection Register is di-

vided into two 64 bit segments. The first segment

contains a unique device number written by ST,

while the second one is one-time-programmable

by the user. The user programmable segment can

be permanently protected. The Security Block, pa-

rameter block 0, can be permanently protected by

the user. Figure 5, shows the Security Block and

Protection Register Memory Map.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified in the

The memory is offered in a TFBGA56, 0.75 mm

ball pitch package and is supplied with all the bits

erased (set to ’1’).

6/63

M58CR032C, M58CR032D

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A20

Address Inputs

Data Input/Outputs or Address

Inputs, Command Inputs

DQ0-DQ15

V

DD DDQ PP

E

Chip Enable

21

16

G

Output Enable

Write Enable

A0-A20

DQ0-DQ15

WAIT

W

E

RP

WP

K

Reset/Power-down

Write Protect

M58CR032C

M58CR032D

G

Burst Clock

RP

WP

L

Latch Enable

WAIT

Wait Data in Burst Mode

Supply Voltage

V

DD

K

Supply Voltage for Input/Output

Buffers

V

DDQ

V

Optional Supply Voltage for

Fast Program & Erase

SS

PP

AI90067

V

Ground

SS

Ground Input/Output Supply

Not Connected Internally

SSQ

NC

7/63

M58CR032C, M58CR032D

Figure 3. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A11

A12

A13

A15

A8

A9

V

A18

A17

A19

WP

A6

A5

A4

A3

A2

A1

A0

G

SS

DD

K

PP

A20

NC

RP

W

A10

L

A7

A14

WAIT

DQ6

DQ13

DQ5

A16

DQ4

DQ12

DQ2

DQ10

DQ3

NC

E

V

DQ15

DQ14

DQ1

DQ9

DDQ

V

DQ11

DQ0

DQ8

SS

G

DQ7

V

SSQ

DD

DDQ

AI90001

Table 2. Bank Architecture

Bank Size

8 Mbit

Parameter Blocks

Main Blocks

Bank A

Bank B

8 blocks of 4 KWord

-

15 blocks of 32 KWord

48 blocks of 32 KWord

24 Mbit

8/63

M58CR032C, M58CR032D

Figure 4. Memory Map

Top Boot Block

Bottom Boot Block

Address lines A20-A0

000000h

007FFFh

000000h

000FFFh

512 Kbit or

32 KWord

64 Kbit or

4 KWord

Total of 48

Main Blocks

Total of 8

Parameter

Blocks

Bank B

178000h

007000h

512 Kbit or

32 KWord

64 Kbit or

4 KWord

17FFFFh

180000h

007FFFh

008000h

Bank A

512 Kbit or

32 KWord

512 Kbit or

32 KWord

187FFFh

1F0000h

00FFFFh

078000h

Total of 15

Main Blocks

Total of 15

Main Blocks

512 Kbit or

32 KWord

512 Kbit or

32 KWord

1F7FFFh

1F8000h

07FFFFh

080000h

Bank A

64 Kbit or

4 KWord

512 Kbit or

32 KWord

1F8FFFh

087FFFh

Total of 8

Parameter

Blocks

Total of 48

Main Blocks

Bank B

1FF000h

1FFFFFh

1F8000h

1FFFFFh

64 Kbit or

4 KWord

512 Kbit or

32 KWord

AI90069

Figure 5. Security Block and Protection Register Memory Map

PROTECTION REGISTER

88h

SECURITY BLOCK

Parameter Block # 0

User Programmable OTP

85h

84h

Unique device number

81h

80h

Protection Register Lock

2

1

0

AI90004

9/63

M58CR032C, M58CR032D

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Reset/Power-Down (RP). The

Reset/Power-

Down input provides hardware reset of the memo-

ry, and/or Power-Down functions, depending on

the Burst Configuration Register status. A Reset or

Power-Down of the memory is achieved by pulling

RP to V for at least t

. When the reset pulse

IL

PLPH

is given, the memory will recover from Power-

Down (when enabled) in a minimum of t

,

PHEL

t

or t

(see Table 25 and Figure 16) after

PHLL

PHWL

The address inputs for the memory array are

latched on the rising edge of Latch Enable L. The

the rising edge of RP. After a Reset or Power-Up

the device is configured for asynchronous page

read (M15=1) and the power save function is dis-

abled (M10=0). All blocks are locked after a Reset

or Power-Down. Either Chip Enable or Write En-

address latch is transparent when L is at V . In

IL

synchronous operations the address is also

latched on the first rising/falling edge of K (de-

pending on clock configuration) when L is low.

During a Write operation the address is latched on

the rising edge of L or W, whichever occurs first.

able must be tied to V during Power-Up to allow

IH

maximum security and the possibility to write a

command on the first rising edge of Write Enable.

Data Inputs/Outputs (DQ0-DQ15). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the internal state

machine.

Latch Enable (L). Latch Enable latches the ad-

dress bits A0-A20 on its rising edge. The ad-

dress latch is transparent when L is at V and

IL

it is inhibited when L is at V

.

IH

Clock (K). The clock input synchronizes the

memory to the microcontroller during burst mode

read operation; the address is latched on a K edge

(rising or falling, according to the configuration set-

Both input data and commands are latched on the

rising edge of Write Enable, W. When Chip En-

able, E, and Output Enable, G, are at V the data

IL

tings) when L is at V . K is don't care during asyn-

IL

bus outputs data from the Memory Array, the Elec-

tronic Signature, Manufacturer or Device codes,

the Block Protection Status, the Burst Configura-

tion Register, the Protection Register or the Status

Register. The data bus is high impedance when

chronous page mode read and in write operations.

Wait (WAIT). Wait is an output signal used during

burst mode read, indicating whether the data on

the output bus are valid or a wait state must be in-

serted. This output is high impedance when Chip

the chip is deselected, Output Enable, G, is at V ,

IH

Enable or Output Enable are at V or Reset/Pow-

IH

or Reset/Power-Down, RP, is at V .

IL

er-Down is at V . It can be configured to be active

IL

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable,

during the wait cycle or one clock cycle in ad-

vance.

V

Supply Voltage (1.65V to 2V). V

pro-

DD

E, is at V , the memory is deselected and the

IH

vides the power supply to the internal core of the

memory device. It is the main power supply for all

operations (Read, Program and Erase). It ranges

from 1.65V to 2.0V.

power consumption is reduced to the standby lev-

el. Chip Enable can also be used to control writing

to the Command Interface and to the memory ar-

ray, while Write Enable, W, remains at V .

IL

V

Supply Voltage (1.65V to 3.3V). V

DDQ

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

provides the power supply to the I/O pins and en-

ables all Outputs to be powered independently

from V . V

separate supply. It can be powered either from

1.65V to 2.0V or from 1.65V to 3.3V.

V

eration. When Output Enable, G, is at V the out-

IH

can be tied to V or it can use a

DD

DDQ

puts are high impedance.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. Data are latched on the rising edge of

Write Enable.

Write Protect (WP). Write Protect is an input that

gives an additional hardware protection for each

Program Supply Voltage (12V).

is a power supply pin. The Supply Voltage

PP

DD

and the Program Supply Voltage V can be

PP

applied in any order. The pin can also be used as

a control input.

block. When Write Protect is at V , the Lock-Down

IL

is enabled and the protection status of the block

The two functions are selected by the voltage

cannot be changed. When Write Protect is at V ,

range applied to the pin. If V is kept in a low volt-

IH

PP

the Lock-Down is disabled and the block can be

locked or unlocked. (refer to Table 10, Read Pro-

tection Register).

age range (0V to 2V) V is seen as a control in-

PP

put. In this case a voltage lower than V

gives

PPLK

an absolute protection against program or erase,

10/63

M58CR032C, M58CR032D

while V > V

ble 19, DC Characteristics for the relevant values).

enables these functions (see Ta-

PP1

gram and erase operations the current may in-

crease up to 10mA.

PP

V

is only sampled at the beginning of a program

PP

V

and V

Grounds. V and V

grounds

SSQ

SS

SSQ

SS

or erase; a change in its value after the operation

has started does not have any effect on Program

or Erase, however for Double or Quadruple Word

Program the results are uncertain.

If V is in the range 11.4V to 12.6V it acts as a

power supply pin. In this condition V

stable until the Program/Erase algorithm is com-

pleted (see Table 16 and 17). In read mode the

current sunk is less then 0.5mA, while during pro-

are the reference for the core supply and the input/

output voltage measurements respectively.

Note: Each device in a system should have

V

, V

and V decoupled with a 0.1µF ca-

DD DDQ PP

PP

pacitor close to the pin. See Figure 10, AC Mea-

surement Load Circuit. The PCB trace widths

must be

PP

should be sufficient to carry the required V

program and erase currents.

PP

11/63

M58CR032C, M58CR032D

BUS OPERATIONS

There are two types of bus operations that control

the device: Asynchronous (Read, Page Read,

Write, Output Disable, Standby, Automatic Stand-

by and Reset/Power-Down) and Synchronous

(Synchronous Read and Synchronous Burst

Read).

The Dual Bank architecture of the M58CR032 al-

lows read/write operations in Bank A, while read

operations are being executed in Bank B or vice

versa. Write operations are only allowed in one

bank at a time (see Table 7).

See Table 3, Bus Operations, for a summary. Typ-

ically glitches of less than 5ns on Chip Enable or

Write Enable are ignored by the memory and do

not affect bus operations.

Asynchronous Read. Asynchronous Read oper-

ations read from the Memory Array, or specific

registers (Electronic Signature, Status Register,

CFI, Block Protection Status, Read Configuration

Register status and Protection Register) in the

Command Interface.

Asynchronous Write. Bus Write operations are

used to write to the Command Interface of the

memory or latch Input Data to be programmed. A

valid Bus Write operation begins by setting the de-

sired address on the Address Inputs and setting

Chip Enable, E, and Write Enable, W, to V and

IL

Output Enable to V . Addresses are latched on

IH

the rising edge of L, W or E whichever occur first.

Commands and Input Data are latched on the ris-

ing edge of W or E whichever occurs first. Output

Enable must remain High, V , during the whole

IH

Bus Write operation. See Figures 14 and 15, Write

AC Waveforms, and Tables 23 and 24, Write AC

Characteristics, for details of the timing require-

ments.

Write operations are asynchronous and the clock

is ignored during write.

Output Disable. The data outputs are high im-

pedance when the Output Enable, G, and Write

Enable, W, are High, V .

IH

Standby. When Chip Enable is High, V , and the

IH

Program/Erase Controller is idle, the memory en-

ters Standby mode and the Data Inputs/Outputs

pins are placed in the high impedance state, inde-

pendent of Output Enable, G, or Write Enable, W.

For the Standby current level see Table 19, DC

Characteristics.

A valid Asynchronous Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V , to Chip Enable

IL

and Output Enable and keeping Write Enable

High, V . The address is latched on the rising

IH

edge of the Latch, L, input. The Data Inputs/Out-

puts will output the value, see Figure 11, Asyn-

chronous Read AC Waveforms, and Table 21,

Asynchronous Read AC Characteristics, for de-

tails of when the output becomes valid.

According to the device configuration the following

Read operations: Electronic Signature, Status

Register, CFI, Block Protection Status, Burst Con-

figuration Register Status and Protection Register

must be accessed as asynchronous read or as

single synchronous read.

Asynchronous Page Read. Asynchronous

Page Read operations can be used to read the

content of the memory array, where data is inter-

nally read and stored in a page buffer. The page

has a size of 4 words and is addressed by A0 and

A1 address inputs.

Valid bus operations are the same as Asynchro-

nous Bus Read operations but with different tim-

ings. The first read operation within the page has

identical timings, subsequent reads within the

same page have much shorter access times. If the

page changes then the normal, longer timings ap-

ply again. See Figure 12, Asynchronous Page

Read AC Waveforms and Table 21, Asynchro-

nous Read AC Characteristics for details on when

the outputs become valid.

Reset/Power-Down. The memory is in Power-

Down when the Burst Configuration Register is set

for Power-Down and RP is at V . The power con-

IL

sumption is reduced to the Power-Down level, and

Outputs are in high impedance, independent of

Chip Enable E, Output Enable G or Write Enable

W. The memory is in reset mode when the Burst

Configuration Register is set for Reset and RP is

at V . The power consumption is the same of the

IL

standby and the outputs are in high impedance.

After a Reset/Power-Down the device defaults to

Asynchronous Page Read, the Status Register is

cleared and the Burst configuration register de-

faults to Asynchronous Page read.

Automatic Standby. If CMOS levels (V

±

DD

0.2V) are used to drive the bus and the bus is in-

active for 150ns or more in Read mode, the mem-

ory enters Automatic Standby where the internal

Supply Current is reduced to the Standby Supply

Current, I

. The Data Inputs/Outputs will still

DD2

output data if a Bus Read operation is in progress.

The automatic standby feature is not available

when the device is configured for synchronous

burst mode.

Synchronous Single Read. Synchronous sin-

gle Reads can be used to read the Electronic Sig-

nature, Status Register, CFI, Block Protection

Status, Burst Configuration Register Status or

Asynchronous Page Read is the default state of

the device when exiting power-down or after pow-

er-up.

12/63

M58CR032C, M58CR032D

Protection Register, see Figure 6, for an example

of a single synchronous read operation.

Definition). Wrap and no-wrap modes are also

supported.

Synchronous Burst Read. The device also sup-

ports a synchronous burst read. In this mode a

burst sequence is started at the first clock edge

(rising or falling according to configuration set-

tings) after the falling edge of Latch Enable. After

a configurable delay of 2 to 5 clock cycles a new

data is output at each clock cycle. The burst se-

quence may be configured to be sequential or in-

terleaved and for a length of 4 or 8 words or for

continuous burst mode (see Table 5, Burst Type

A WAIT signal may be asserted to indicate to the

system that an output delay will occur. This delay

will depend on the starting address of the burst se-

quence; the worst case delay will occur when the

sequence is crossing a 64 word boundary and the

starting address was at the end of a four word

boundary. See the Burst Configuration Register

command for more details on all the possible set-

tings for the synchronous burst read (see Table 4).

It is possible to perform burst read across bank

boundaries (all banks in read array mode).

Table 3. Bus Operations

Operation

E

G

W

L

K

RP

WP

DQ15-DQ0

(3)

V

Asynchronous Read

X

Data Output

IL

IH

V

IH

IL

(3)

V

IH

Asynchronous Page Read

X

Data Output

IL

V

IH

V

IH

Asynchronous Write

Output Disable

X

Data Input

Hi-Z

IL

IH

IL

V

IH

V

IH

X

IH

V

IH

Standby

X

Hi-Z

IH

V

Reset / Power-Down

Synchronous Read

X

Hi-Z

IL

(2)

V

IL

V

IH

Data Output

IL

IH

T

(2)

V

IL

V

IH

Synchronous Burst Read

Note: 1. X = Don’t care.

X

Data Output

T

2. T = transition, falling edge for L, rising or falling edge for K depending on M6 in the Burst Configuration Register. The burst sequence

is started on the first active clock edge after the falling edge of Latch Enable.

3. L can be tied to V if the valid address has been previously latched

IH

13/63

M58CR032C, M58CR032D

Figure 6. Synchronous Single Read Operation

K

L

A20-A0

VALID ADDRESS

X latency = 2

DQ15-DQ0

VALID DATA NOT VALID

NOT VALID

X latency = 3

VALID DATA NOT VALID

X latency = 4

VALID DATA NOT VALID

AI90103

14/63

M58CR032C, M58CR032D

Burst Configuration Register

nificantly longer when power-down is enabled

(see Table 25).

The Burst Configuration Register is used to config-

ure the type of bus access that the memory will

perform.

Wait Bit (M8). In burst mode the Wait bit controls

the timing of the Wait output pin, WAIT. When the

Wait bit is ’0’ the Wait output pin is asserted during

the wait state. When the Wait bit is ’1’ (default) the

Wait output pin is asserted one clock cycle before

the wait state.

The Burst Configuration Register is set through

the Command Interface. After a Reset or Power-

Up the device is configured for asynchronous

page read (M15 = 1) and the power save function

is disabled (M10 = 0). The Burst Configuration

Register bits are described in Table 4. They spec-

ify the selection of the burst length, burst type,

burst X latency and the Read operation. Refer to

Figures 7 and 8 for examples of synchronous burst

configurations.

Read Select Bit (M15). The Read Select bit,

M15, is used to switch between asynchronous and

synchronous Bus Read operations. When the

Read Select bit is set to ’1’, Bus Read operations

are asynchronous; when the Read Select but is

set to ’0’, Bus Read operations are synchronous.

Synchronous Burst Read is supported in both pa-

rameter and main blocks and can be performed

across banks.

WAIT is asserted during a continuous burst and

also during a 4 or 8 burst length if no-wrap config-

uration is selected. WAIT is not asserted during

asynchronous reads, single synchronous reads or

during latency in synchronous reads.

Burst Type Bit (M7). The Burst Type bit is used

to configure the sequence of addresses read as

sequential or interleaved. When the Burst Type bit

is ’0’ the memory outputs from interleaved ad-

dresses; when the Burst Type bit is ’1’ (default) the

memory outputs from sequential addresses. See

Tables 5, Burst Type Definition, for the sequence

of addresses output from a given starting address

in each mode.

Valid Clock Edge Bit (M6). The Valid Clock

Edge bit, M6, is used to configure the active edge

of the Clock, K, during Synchronous Burst Read

operations. When the Valid Clock Edge bit is ’0’

the falling edge of the Clock is the active edge;

when the Valid Clock Edge bit is ’1’ the rising edge

of the Clock is active.

Wrap Burst Bit (M3). The burst reads can be

confined inside the 4 or 8 Double-Word boundary

(wrap) or overcome the boundary (no wrap). The

Wrap Burst bit is used to select between wrap and

no wrap. When the Wrap Burst bit is set to ‘0’ the

burst read wraps; when it is set to ‘1’ the burst read

does not wrap.

On reset or power-up the Read Select bit is set

to’1’ for asynchronous access.

X-Latency Bits (M13-M11). The X-Latency bits

are used during Synchronous Bus Read opera-

tions to set the number of clock cycles between

the address being latched and the first data be-

coming available. For correct operation the X-La-

tency bits can only assume the values in Table 4,

Burst Configuration Register.

The correspondence between X-Latency settings

and the maximum sustainable frequency must be

calculated taking into account some system pa-

rameters.

Burst length Bits (M2-M0). The Burst Length

bits set the number of Words to be output during a

Synchronous Burst Read operation; 4 words, 8

words or continuous burst, where all the words are

read sequentially.

Two conditions must be satisfied:

– (n + 1) t ≥ t

- t

+ t

QVK_CPU

K

ACC AVK_CPU

– t > t

+ t

QVK_CPU

K

KQV

where "n" is the chosen X-Latency configuration

code, t is the clock period, t is Clock to

K

AVK_CPU

In continuous burst mode the burst sequence can

cross bank boundaries.

In continuous burst mode or in 4, 8 words no-wrap,

depending on the starting address, the device ac-

tivates the WAIT output to indicate that a delay is

necessary before the data is output.

If the starting address is aligned to a 4 word

boundary no wait states are needed and the WAIT

output is not activated.

If the starting address is shifted by 1,2 or 3 posi-

tions from the four word boundary, WAIT will be

asserted for 1, 2 or 3 clock cycles when the burst

sequence crosses the first 64 word boundary, to

indicate that the device needs an internal delay to

read the successive words in the array. WAIT will

Address Valid, L Low or E Low, whichever occurs

last, and t is the data setup time required

QVK_CPU

by the system CPU.

Power-Down Bit (M10). The Power-Down bit is

used to enable or disable the power-down func-

tion. When the Power-Down bit is set to ‘0’ (de-

fault) the power-down function is disabled. When

the Power-Down bit is set to ‘1’ power-down is en-

abled and the device goes into the power-down

state where the I

supply current is reduced to a

.

DD

typical figure of I

DD2

if this function is disabled the Reset/Power-Down,

RP, pin causes only a reset of the device and the

supply current is the standby value. The recovery

time after a Reset/Power-Down, RP, pulse is sig-

15/63

M58CR032C, M58CR032D

be asserted only once during a continuous burst

access. See also Table 5, Burst Type Definition.

M14, M9, M5 and M4 are reserved for future use.

Table 4. Burst Configuration Register

Bit

Description

Value

Description

0

1

Synchronous Burst Read

M15

M14

Read Select

Asynchronous Page Read (Default at power-on)

Reserved

010

011

100

101

111

2 clock latency

3 clock latency

4 clock latency

5 clock latency

Reserved

(2)

M13-M11

X-Latency

Other configurations reserved

0

1

Power-Down disabled

(3)

M10

M9

Power-Down

Power-Down enabled

Reserved

0

1

0

1

0

1

WAIT is active during wait state

M8

Wait

WAIT is active one data cycle before wait state (default)

Interleaved

M7

Burst Type

Sequential (default)

Falling Burst Clock edge

Rising Burst Clock edge

Reserved

M6

M5-M4

M3

Valid Clock Edge

0

Wrap

Wrapping

1

No wrap

001

010

111

4 words

M2-M0

Burst Length

8 words

Continuous (M7 must be set to ‘1’)

16/63

M58CR032C, M58CR032D

Table 5. Burst Type Definition

Start

Address

4 Words

8 Words

Sequential

Continuous Burst

Sequential

Interleaved

0-1-2-3

Interleaved

0

1

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

3-4-5-6-7-8-9...

1-0-3-2

2

2-3-0-1

3

3-2-1-0

...

7

7-4-5-6

7-6-5-4

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

7-8-9-10-11-12-13...

...

60

61

62

60-61-62-63-64-65-66...

61-62-63-WAIT-64-65-66...

62-63-WAIT-WAIT-64-65-66...

63-WAIT-WAIT-WAIT-64-65-

66...

63

Sequential

0-1-2-3

Interleaved

Sequential

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9...

3-4-5-6-7-8-9-10

Interleaved

0

1

0-1-2-3-4-5-6...

1-2-3-4-5-6-7...

2-3-4-5-6-7-8...

3-4-5-6-7-8-9...

1-2-3-4

2

2-3-4-5

3

3-4-5-6

...

7

7-8-9-10

7-8-9-10-11-12-13-14

7-8-9-10-11-12-13...

...

60-61-62-63-64-65-66-

67

60

61

62

63

60-61-62-63

60-61-62-63-64-65-66...

61-62-63-WAIT-64-65-66...

62-63-WAIT-WAIT-64-65-66...

61-62-63-WAIT-64-65-

66-67-68

61-62-63-WAIT-64

62-63-WAIT-

WAIT-64-65

62-63-WAIT-WAIT-64-

65-66-67-68-69

63-WAIT-WAIT-

WAIT-64-65-66

63-WAIT-WAIT-WAIT-

64-65-66-67-68-69-70

63-WAIT-WAIT-WAIT-64-65-

66...

17/63

M58CR032C, M58CR032D

Figure 7. X-Latency Configuration Sequence

K

L

A20-A0

VALID ADDRESS

X latency = 2

DQ15-DQ0

VALID DATA VALID DATA VALID DATA VALID DATA

VALID DATA VALID DATA VALID DATA

VALID DATA VALID DATA

X latency = 3

X latency = 4

AI90105

Figure 8. Wait Configuration Sequence

K

L

E

G

A20-A0

VALID ADDRESS

DQ15-DQ0

VALID DATA VALID DATA NOT VALID VALID DATA

WAIT

M8 = '0'

WAIT

M8 = '1'

AI90106

18/63

M58CR032C, M58CR032D

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time during, to

monitor the progress of the operation, or the Pro-

gram/Erase states. See Appendix C, Tables 36

and 37, Command Interface States - Lock and

Modify Tables, for a summary of the Command In-

terface.

The Read Electronic Signature command consists

of one write cycle to an address within the bottom

bank. A subsequent read operation in the address

of the bottom bank will output the Manufacturer

Code, the Device Code, the protection Status of

Blocks of the bottom bank, the Die Revision Code,

the Protection Register, or the Read Configuration

Register (see Table 11).

If the first write cycle of Read Electronic Signature

command is issued to an address within the top

bank, a subsequent read operation in an address

of the top bank will output the protection Status of

blocks of the top bank. The status of the other

bank is not affected by the command (see Table

7). This mode supports asynchronous or single

synchronous reads only.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever V

is lower than V

. Com-

DD

LKO

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 6, Commands,

in conjunction with the text descriptions below.

See Tables 8, 9, 10 and 11 for the valid addresses.

Read CFI Query Command

The Read CFI Query Command is used to read

data from the Common Flash Interface (CFI)

Memory Area, located in the bottom bank. One

Bus Write cycle, addressed to the bottom bank, is

required to issue the Read Query Command.

Once the command is issued subsequent Bus

Read operations in the bottom bank read from the

Common Flash Interface Memory Area. The sta-

tus of the top bank is not affected by the command

(see Table 7). After issuing a Read CFI Query

command, a Read command should be issued to

return the bank to read mode.

Read Command.

The Read command returns the addressed bank

to Read mode. One Bus Write cycle is required to

issue the Read command and return the ad-

dressed Bank to Read mode. Subsequent read

operations will read the addressed location and

output the data. A Read command can be issued

in one bank while programming or erasing in the

other bank. However if a Read command is issued

to a bank currently executing a program or erase

operation the command will be ignored.

See Appendix B, Common Flash Interface, Tables

29, 30, 31, 32, 33, 34 and 35 for details on the in-

formation contained in the Common Flash Inter-

face memory area.

When a device Reset occurs, the memory defaults

to Read mode.

Read Status Register Command

A bank’s Status Register indicates when a pro-

gram or erase operation is complete and the suc-

cess or failure of operation itself. Issue a Read

Status Register command to read the Status Reg-

ister content of the addressed bank. The status of

the other bank is not affected by the command.

The Read Status Register command can be is-

sued at any time, even during program or erase

operations.

The following Read operations output the content

of the Status Register of the addressed bank. The

Status Register is latched on the falling edge of E

or G signals, and can be read until E or G returns

Clear Status Register Command

The Clear Status Register command can be used

to reset (set to ‘0’) bits 1, 3, 4 and 5 in the Status

Register of the addressed bank’. One bus write cy-

cle is required to issue the Clear Status Register

command. After the Clear Status Register com-

mand the bank returns to read mode.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

Block Erase Command

to V . Either E or G must be toggled to update the

IH

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error. It is not

necessary to pre-program the block as the Pro-

latched data. See Table 15 for the description of

the Status Register Bits. This mode supports

asynchronous or single synchronous reads only.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes and the Block

Locking Status, or the Protection Register.

19/63

M58CR032C, M58CR032D

gram/Erase Controller does it automatically before

erasing.

bank will remain in Read Status Register until a

Read command is issued.

Two Bus Write cycles are required to issue the

command.

■ The first bus cycle sets up the Erase command.

During Erase operations the bank being erased

will only accept the Read Status Register com-

mand and the Program/Erase Suspend command,

all other commands will be ignored. Typical Erase

times are given in Table 12, Program, Erase

Times and Program/Erase Endurance Cycles.

■ The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts. Erase aborts if Reset turns

Program Command

The memory array can be programmed word-by-

word. Only one bank can be programmed at any

one time. The other bank must be in Read mode

or Erase Suspend. Two bus write cycles are re-

quired to issue the Program Command.

to V . As data integrity cannot be guaranteed

IL

when the Erase operation is aborted, the block

must be erased again.

■ The first bus cycle sets up the Program

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register until a

Read command is issued.

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

During Erase operations the bank containing the

block being erased will only accept the Read Sta-

tus Register command and the Program/Erase

Suspend command, all other commands will be ig-

nored. Typical Erase times are given in Table 12,

Program, Erase Times and Program/Erase Endur-

ance Cycles.

See Appendix B, Figure 22, Block Erase Flowchart

and Pseudo Code, for a suggested flowchart for

using the Block Erase command.

After programming has started, Read operations

in the bank being programmed output the Status

Register content.

During Program operations the bank being pro-

grammed will only accept the Read Status Regis-

ter command and the Program/Erase Suspend

command. Typical Program times are given in Ta-

ble 12, Program, Erase Times and Program/Erase

Endurance Cycles.

Programming aborts if Reset goes to V . As data

IL

Bank Erase Command

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

See Appendix B, Figure 18, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

The Bank Erase command can be used to erase a

bank. It sets all the bits within the selected bank to

’1’. All previous data in the bank is lost. The Bank

Erase command will ignore any protected blocks

within the bank. If the bank is protected then the

Erase operation will abort, the data in the bank will

not be changed and the Status Register will output

the error.

Double Word Program Command

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel. The two words must differ only for the

address A0. Only one bank can be programmed at

any one time. The other bank must be in Read

mode or Erase Suspend.

Two Bus Write cycles are required to issue the

command.

■ The first bus cycle sets up the Bank Erase

command.

■ The second latches the bank address in the

internal state machine and starts the Program/

Erase Controller.

Programming should not be attempted when V

PP

is not at V

. The command can be executed if

PPH

V

is below V

but the result is not guaranteed.

PP

PPH

If the second bus cycle is not Write Bank Erase

Confirm (D0h), Status Register bits b4 and b5 are

set and the command aborts. Erase aborts if Re-

Three bus write cycles are necessary to issue the

Double Word Program command.

set turns to V . As data integrity cannot be guar-

anteed when the Erase operation is aborted, the

bank must be erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

IL

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

20/63

M58CR032C, M58CR032D

Read operations in the bank being programmed

output the Status Register content after the pro-

gramming has started.

During Double Word Program operations the bank

being programmed will only accept the Read Sta-

tus Register command and the Program/Erase

Suspend command. Typical Program times are

given in Table 12, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

given in Table 12, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix B, Figure 20, Quadruple Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Quadruple Word Program

command.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler. The command must be addressed to the bank

containing the program or erase operation.

Programming aborts if Reset goes to V . As data

IL

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read, Read Status Register, Read Electronic Sig-

nature and Read CFI Query commands. Addition-

ally, if the suspend operation was Erase then the

Program, Block Lock, Block Lock-Down or Protec-

tion Program commands will also be accepted.

The block being erased may be protected by issu-

ing the Block Lock, Block Lock-Down or Protection

Program commands. Only the blocks not being

erased may be read or programmed correctly.

When the Program/Erase Resume command is is-

sued the operation will complete.

See Appendix B, Figure 19, Double Word Program

Flowchart and Pseudo Code, for the flowchart for

using the Double Word Program command.

Quadruple Word Program Command

This feature is offered to improve the programming

throughput, writing a page of four adjacent words

in parallel. The four words must differ only for the

addresses A0 and A1. The first write cycle must be

addressed to the bank to be programmed.

Only one bank can be programmed at any one

time. The other bank must be in Read mode or

Erase Suspend.

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

Programming should not be attempted when V

PP

is not at V

. The command can be executed if

PPH

Chip Enable to V . Program/Erase is aborted if

IH

V

is below V

but the result is not guaranteed.

PP

PPH

Reset turns to V .

IL

Five bus write cycles are necessary to issue the

Quadruple Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

See Appendix B, Figure 21, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

23, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

the Data of the first word to be written.

Program/Erase Resume Command

■ The third bus cycle latches the Address and the

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend command has paused

it. One Bus Write cycle is required to issue the

command. The command must be addressed to

the bank containing the program or erase opera-

tion. Once the command is issued subsequent

Bus Read operations read the Status Register.

If a Program command is issued during a Block

Erase Suspend, then the erase cannot be re-

sumed until the programming operation has com-

pleted. It is possible to accumulate suspend

operations. For example: suspend an erase oper-

ation, start a programming operation, suspend the

programming operation then read the array. See

Appendix B, Figure 21, Program Suspend & Re-

sume Flowchart and Pseudo Code, and Figure 23,

Erase Suspend & Resume Flowchart and Pseudo

Code for flowcharts for using the Program/Erase

Resume command.

Data of the second word to be written.

■ The fourth bus cycle latches the Address and

the Data of the third word to be written.

■ The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

Read operations to the bank being programmed

output the Status Register content after the pro-

gramming has started.

Programming aborts if Reset goes to V . As data

IL

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed.

During Quadruple Word Program operations the

bank being programmed will only accept the Read

Status Register command and the Program/Erase

Suspend command. Typical Program times are

21/63

M58CR032C, M58CR032D

Protection Register Program Command

Block Unlock Command

The Protection Register Program command is

used to Program the 64 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

The Blocks Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Blocks Unlock command.

■ The first bus cycle sets up the Block Unlock

command.

Two write cycles are required to issue the Protec-

tion Register Program command.

■ The second Bus Write cycle latches the block

address.

■ The first bus cycle sets up the Protection

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 13 shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation and Ap-

pendix B, Figure 24, Locking Operations Flow-

chart and Pseudo Code, for a flowchart for using

the Unlock command.

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The segment can be protected by programming bit

1 of the Protection Lock Register. Bit 1 of the Pro-

tection Lock Register protects bit 2 of the Protec-

tion Lock Register. Programming bit 2 of the

Protection Lock Register will result in a permanent

protection of the Security Block (see Figure 5, Se-

curity Block and Protection Register Memory

Map). Attempting to program a previously protect-

ed Protection Register will result in a Status Reg-

ister error. The protection of the Protection

Register and/or the Security Block is not revers-

ible.

The Protection Register Program cannot be sus-

pended. See Appendix B, Figure 25, Protection

Register Program Flowchart and Pseudo Code,

for a flowchart for using the Protection Register

Program command.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,

or have its protection status changed when WP is

low, V . When WP is high, V the Lock-Down

IL

IH,

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table. 14 shows the Lock Status af-

ter issuing a Block Lock-Down command. Refer to

the section, Block Locking, for a detailed explana-

tion and Appendix B, Figure 24, Locking Opera-

tions Flowchart and Pseudo Code, for a flowchart

for using the Lock-Down command.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

■ The first bus cycle sets up the Block Lock

Set Burst Configuration Register Command.

command.

The Set Burst Configuration Register command is

used to write a new value to the Burst Configura-

tion Control Register which defines the burst

length, type, X latency, Synchronous/Asynchro-

nous Read mode and the valid Clock edge config-

uration.

Two Bus Write cycles are required to issue the Set

Burst Configuration Register command. The first

cycle writes the setup command and the address

corresponding to the Set Burst Configuration Reg-

ister content. The second cycle writes the Burst

Configuration Register data and the confirm com-

mand. Once the command is issued the memory

returns to Read mode as if a Read Memory Array

command had been issued.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 14 shows the Lock Status after issuing a

Block Lock command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, Block Locking, for

a detailed explanation. See Appendix B, Figure

24, Locking Operations Flowchart and Pseudo

Code, for a flowchart for using the Lock command.

22/63

M58CR032C, M58CR032D

The value for the Burst Configuration Register is

always presented on A0-A15. M0 is on A0, M1 on

A1, etc.; the other address bits are ignored.

Table 6. Commands

Bus Write Operations

3rd Cycle

Commands

1st Cycle

2nd Cycle

4th Cycle

5th Cycle

Op. Add Data Op. Add Data Op. Add Data Op. Add Data Op. Add Data

1+ Write BKA FFh RA RD

Read Memory

Array

Read

Read Status

Register

1+ Write BKA 70h Read BKA SRD

Read Electronic

Signature

(2)

1+ Write ESA 90h Read

IDh

ESA

Read CFI Query 1+ Write QA

98h Read QA

QD

D0h

Block Erase

Bank Erase

2

Write BA

20h Write

BA

Write BKA 80h Write BKA

40h

Program

2

Write PA

or Write

10h

PA

PD

Double Word

3

5

Write PA1

30h Write PA1

55h Write PA1

PD1 Write PA2 PD2

(3)

Program

Quadruple Word

PD1 Write PA2 PD2 Write PA3 PD3 Write PA4 PD4

(4)

Program

Clear Status

Register

1

Write BKA 50h

Write BKA B0h

Write BKA D0h

Program/Erase

Suspend

Program/Erase

Resume

Block Lock

2

Write BA

60h Write BA

60h Write

01h

D0h

2Fh

Block Unlock

Block Lock-Down

BA

60h Write BA

Protection

Register Program

2

Write PRA C0h Write

Write BCRA 60h Write

PRD

03h

PRA

Set Burst

Configuration

Register

BCRA

Note: 1. X = Don’t Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ESA= Electronic Signature Address, ID=Identifier

(Manufacture and Device Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program

Data, PRA=Protection Register Address, PRD=Protection Register Data, BCRA=Burst Configuration Register Address,

BCRD=Burst Configuration Register Data.

2. The signature addresses are listed in Tables 8, 9 and 10.

3. Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.

4. Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

23/63

M58CR032C, M58CR032D

Table 7. Dual Bank Operations

Status of one

Commands allowed in the other bank

Erase/

Read

Array

Read

CFI

Program

Erase

Lock

Unlock

bank

Program

Erase

Status

Suspend Suspend

Resume

Idle

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Reading

Programming

Erasing

Yes

–

Yes

–

Program

Suspended

Yes

–

Yes

Erase

Suspended

Yes

Note: 1. For detailed description of command see Table 6, 36 and 37.

2. There is a Status Register for each bank; Status Register indicates bank state, not P/E.C. status.

3. Command must be written to an address within the block targeted by that command.

Table 8. Read Electronic Signature

Other

Code

Device

E

G

W

DQ15-DQ0

A1

A0

Addresses

(2)

V

Manufacturer Code

0020h

88C8h

88C9h

IL

IH

IL

ESA

(2)

V

M58CR032C

M58CR032D

IL

IH

ESA

Device Code

(2)

V

IL

IH

ESA

Note: 1. Addresses are latched on the rising edge of L input.

2. ESA means Electronic Signature Address (see Read Electronic Signature)

Table 9. Read Block Protection

Other

Address

Block Status

Locked Block

E

G

W

A0

A1

DQ15-DQ0

(3)

V

IL

V

0001

0000

0003

0002

IL

IH

BA

(3)

V

IL

V

Unlocked Block

IH

BA

(3)

V

IL

V

Locked and Locked-Down Block

Unlocked and Locked-Down

IH

BA

(3)

V

IL

V

IH

BA

Note: 1. Addresses are latched on the rising edge of L input.

2. A locked block can only be unlocked with WP at V

IH.

3. BA means Block Address. First cycle command address should indicate the bank of the block address.

24/63

M58CR032C, M58CR032D

Table 10. Read Protection Register

Word

E

G

W

A20-16 A15-8 A7-0

DQ15-8

DQ7-3

DQ2

DQ1

DQ0

Security

prot.data

OTP

prot.data

(2)

V

IL

V

IL

V

IH

Lock

80h

00h

00000B

0

X

(2)

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

V

IH

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

81h

82h

83h

84h

ID data

X

85h OTP data OTP data OTP data OTP data OTP data

86h OTP data OTP data OTP data OTP data OTP data

87h OTP data OTP data OTP data OTP data OTP data

88h OTP data OTP data OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

Note: 1. Addresses are latched on the rising edge of L input.

2. X = Don’t care.

Table 11. Identifier Codes

Code

Address (h)

Data (h)

0020

88C8

88C9

0001

0000

0003

0002

DRC

BCR

Manufacturer Code

Bank Address + 00

Top (M58CR032C)

Device Code

Bank Address + 01

Bank Address + 02

Bottom (M58CR032D)

Lock

Unlocked

Block Protection

Locked and Locked-Down

Unlocked and Locked-Down

Die Revision Code

Bank Address + 03

Bank Address + 05

Bank Address + 80

Burst Configuration Register

Lock Protection Register

LPR

Bank Address + 81

Bank Address + 88

Protection Register

PR

Note: DRC=Die Revision Code, BCR=Burst Configuration Register, LPR= Lock Protection Register, PR=Protection Register (Unique Device

Number and User Programmable OTP).

25/63

M58CR032C, M58CR032D

Table 12. Program, Erase Times and Program, Erase Endurance Cycles

Typicalafter

100k W/E

Cycles

Parameter

Condition

Min

Typ

Unit

Max

(2)

0.3

1

3

2.5

s

Parameter Block (4 KWord) Erase

Main Block (32 KWord) Erase

Preprogrammed

0.8

1.1

5.5

9

4

s

Not Preprogrammed

Preprogrammed

s

Bank A (8Mbit) Erase

Bank B (24Mbit) Erase

Not Preprogrammed

Preprogrammed

s

16.5

27

s

Not Preprogrammed

s

(3)

40

ms

Parameter Block (4 KWord) Program

(3)

300

10

ms

Main Block (32 KWord) Program

(3)

10

100

µs

Word Program

Program Suspend Latency

Erase Suspend Latency

5

10

20

µs

Main Blocks

100,000

cycles

s

Program/Erase Cycles (per Block)

Parameter Blocks

0.3

0.9

6.5

19.5

510

8

2.5

4

Parameter Block (4 KWord) Erase

Main Block (32 KWord) Erase

Bank A (8Mbit) Erase

s

Bank B (24Mbit) Erase

4Mbit Program

s

Quadruple Word

ms

µs

(3)

100

Word/ Double Word/ Quadruple Word Program

Parameter Block (4 KWord)

Quadruple Word

8

ms

(3)

Program

Word

32

ms

Quadruple Word

Word

64

ms

(3)

Main Block (32 KWord) Program

256

Main Blocks

Parameter Blocks

1000 cycles

2500 cycles

Program/Erase Cycles (per Block)

Note: 1. T = –40 to 85°C; V = 1.65V to 2V; V = 1.65V to 3.3V.

DDQ

A

DD

2. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).

3. Excludes the time needed to execute the command sequence.

26/63

M58CR032C, M58CR032D

BLOCK LOCKING

The M58CR032 features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their protection status can-

not be changed using software commands alone.

A Locked or Unlocked block can be Locked-Down

by issuing the Lock-Down command. Locked-

Down blocks revert to the Locked state when the

device is reset or powered-down.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■ V ≤ V

- the third level offers a complete

PP

PPLK

The Lock-Down function is dependent on the WP

hardware protection against program and erase

on all blocks.

input pin. When WP=0 (V ), the blocks in the

IL

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

For all devices the protection status of each block

can be set to Locked, Unlocked, and Lock-Down.

Table 14, defines all of the possible protection

states (WP, DQ1, DQ0), and Appendix B, Figure

24, shows a flowchart for the locking operations.

WP=1 (V ) the Lock-Down function is disabled

IH

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be re-locked

(1,1,1) and unlocked (1,1,0) as desired while WP

remains high. When WP is low , blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WP was high. Device reset or power-down

resets all blocks , including those in Lock-Down, to

the Locked state.

Reading a Block’s Lock Status

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 9,

will output the protection status of that block. The

lock status is represented by DQ0 and DQ1. DQ0

indicates the Block Lock/Unlock status and is set

by the Lock command and cleared by the Unlock

command. It is also automatically set when enter-

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the lock status will be changed. After complet-

ing any desired lock, read, or program operations,

resume the erase operation with the Erase Re-

sume command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operations cannot be performed during a

program suspend. Refer to Appendix C, Com-

mand Interface State Table, for detailed informa-

tion on which commands are valid during erase

suspend.

The following sections explain the operation of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

27/63

M58CR032C, M58CR032D

Table 13. Block Lock Status

Item

Address

Data

Block Lock Configuration

LOCK

Block is Unlocked

Block is Locked

DQ0=0

DQ0=1

DQ1=1

xx002

Block is Locked-Down

Table 14. Lock Status

Current

(1)

Next Protection Status

(WP, DQ1, DQ0)

(1)

Protection Status

(WP, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

Allowed

After

WP transition

Current State

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

28/63

M58CR032C, M58CR032D

STATUS REGISTER

The M58CR032 has two Status Registers, one for

each bank. The Status Registers provide informa-

tion on the current or previous Program or Erase

operations executed in each bank. The various

bits convey information and errors on the opera-

tion. Issue a Read Status Register command to

read the Status Register content of the addressed

bank, refer to Read Status Register Command

section for more details. To output the contents,

the Status Register is latched on the falling edge

of the Chip Enable or Output Enable signals, and

can be read until Chip Enable or Output Enable re-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

turns to V . Either Chip Enable or Output Enable

IH

must be toggled to update the latched data.

Bus Read operations from any address within the

bank, always read the Status Register during Pro-

gram and Erase operations.

The bits in the Status Register are summarized in

Table 15, Status Register Bits. Refer to Table 15

in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive

in the addressed bank. When the Program/Erase

Controller Status bit is Low (set to ‘0’), the Pro-

gram/Erase Controller is active; when the bit is

High (set to ‘1’), the Program/Erase Controller is

inactive, and the device is ready to process a new

command.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the Byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

V

Status (Bit 3). The V

Status bit can be

PP

used to identify an invalid voltage on the V pin

during Program and Erase operations. The V

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if V becomes invalid during an operation.

PP

After the Program/Erase Controller completes its

When the V Status bit is Low (set to ‘0’), the volt-

PP

operation the Erase Status, Program Status, V

PP

age on the V pin was sampled at a valid voltage;

PP

Status and Block Lock Status bits should be tested

for errors.

when the V Status bit is High (set to ‘1’), the V

PP

pin has a voltage that is below the V

Lockout

PP

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended

in the addressed block. When the Erase Suspend

Status bit is High (set to ‘1’), a Program/Erase

Suspend command has been issued and the

memory is waiting for a Program/Erase Resume

command.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

Voltage, V

, the memory is protected and Pro-

PPLK

gram and Erase operations cannot be performed.

Once set High, the V Status bit can only be reset

PP

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended in the addressed block.

When the Program Suspend Status bit is High (set

to ‘1’), a Program/Erase Suspend command has

29/63

M58CR032C, M58CR032D

been issued and the memory is waiting for a Pro-

gram/Erase Resume command. The Program

Suspend Status should only be considered valid

when the Program/Erase Controller Status bit is

High (Program/Erase Controller inactive). Bit 2 is

set within 5µs of the Program/Erase Suspend

command being issued therefore the memory may

still complete the operation rather than entering

the Suspend mode.

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix B, Flowcharts and

Pseudo Codes, for using the Status Register.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

Table 15. Status Register Bits

Bit

Name

Logic Level

Definition

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

’1’

’0’

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PP

V

PP

Status

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level ’1’ is High, ’0’ is Low.

30/63

M58CR032C, M58CR032D

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 16. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

T

A

–40 to 85

–40 to 125

–55 to 155

Ambient Operating Temperature

T

BIAS

Temperature Under Bias

Storage Temperature

°C

T

°C

STG

(1)

–0.5 to V

+0.5

Input or Output Voltage

Supply Voltage

V

DDQ

–0.5 to 2.7

–0.5 to 13

IO

V

, V

DD DDQ

V

Program Voltage

PP

Note: 1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

31/63

M58CR032C, M58CR032D

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 17, Operating

and AC Measurement Conditions. Designers

should check that the operating conditions in their

circuit match the operating conditions when rely-

ing on the quoted parameters.

Table 17. Operating and AC Measurement Conditions

M58CR032C, M58CR032D

100

85

120

Parameter

Units

Min

1.8

Max

2.0

3.3

85

Min

1.65

– 40

Max

2.0

3.3

85

Min

1.65

– 40

Max

2.0

3.3

85

V

Supply Voltage

V

DD

1.8

DDQ

Ambient Operating Temperature

– 40

°C

pF

ns

V

Load Capacitance (C )

30

L

Input Rise and Fall Times

4

0 to V

DDQ

Input Pulse Voltages

DDQ

V

DDQ

/2

V

DDQ

/2

V /2

DDQ

Input and Output Timing Ref. Voltages

V

Figure 9. AC Measurement I/O Waveform

Figure 10. AC Measurement Load Circuit

V

/ 2

DDQ

V

DDQ

V

/2

DDQ

1N914

0V

AI90007

3.3kΩ

DEVICE

UNDER

TEST

OUT

C

L

C

includes JIG capacitance

L

AI90008

Table 18. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: Sampled only, not 100% tested.

32/63

M58CR032C, M58CR032D

Table 19. DC Characteristics - Currents

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V ≤ V ≤ V

LI

IN

DDQ

I

LO

0V ≤ V

≤ V

OUT DDQ

±1

µA

Supply Current

Asynchronous Read (f=6MHz)

E = V , G = V

3

6

mA

IL

IH

4 Word

8 Word

6

8

6

13

14

10

mA

I

DD1

Supply Current

Synchronous Read (f=40MHz)

Continuous

Supply Current

(Reset)

I

RP = V ± 0.2V

2

10

µA

DD2

DD3

SS

E = V ± 0.2V

Supply Current (Standby)

10

8

50

15

20

15

20

µA

mA

DD

V

= V

PPH

PP

Supply Current (Program)

V

= V

10

8

PP

DD

(1)

I

DD4

V

PP

PPH

Supply Current (Erase)

V

PP

= V

DD

10

Program/Erase in one

Bank, Asynchronous

Read in another Bank

13

26

mA

Supply Current

(Dual Operations)

(1,2)

(1)

I

DD5

Program/Erase in one

Bank, Synchronous

Read in another Bank

16

10

30

50

mA

µA

Supply Current Program/ Erase

Suspended (Standby)

E = V ± 0.2V

I

DD

DD6

V

= V

PPH

2

5

mA

µA

mA

µA

PP

V

Supply Current (Program)

Supply Current (Erase)

PP

V

= V

0.2

2

PP

DD

(1)

I

PP1

5

PP

PPH

V

= V

DD

0.2

100

0.2

5

PP

= V

400

5

PP

PPH

I

V

Supply Current (Read)

PP2

PP

V

≤ V

PP

DD

(1)

Supply Current (Standby)

V

5

I

PP3

Note: 1. Sampled only, not 100% tested.

2. V Dual Operation current is the sum of read and program or erase currents.

DD

33/63

M58CR032C, M58CR032D

Table 20. DC Characteristics - Voltages

Symbol

Parameter

Input Low Voltage

Test Condition

Min

Typ

Max

Unit

V

–0.5

0.4

IL

V

–0.4

V

+ 0.4

Input High Voltage

Output Low Voltage

Output High Voltage

V

IH

DDQ

V

OL

I

= 100µA

0.1

V

OL

V

OH

I

= –100µA

–0.1

V

OH

V

Program Voltage-Logic

Program Voltage Factory

Program, Erase

1

1.8

12

1.95

12.6

0.9

V

PP1

PP

V

PPH

11.4

V

PP

V

Program or Erase Lockout

V Lock Voltage

DD

V

PPLK

V

LKO

1

V

RPH

RP pin Extended High Voltage

3.3

34/63

M58CR032C, M58CR032D

Figure 11. Asynchronous Read AC Waveforms

35/63

M58CR032C, M58CR032D

Figure 12. Asynchronous Page Read AC Waveforms

36/63

M58CR032C, M58CR032D

Table 21. Asynchronous Read AC Characteristics

M58CR032

Symbol

Alt

Parameter

Test Condition

85

100

Max

120

Max

Unit

Min

Max Min

Min

Address Valid to Next

Address Valid

t

E = V , G = V

85

100

120

ns

AVAV

RC

IL

Address valid to Latch

Enable High

t

G = V

IH

10

AVLH

AVAVDH

Address Valid to Output

Valid (Random)

t

E = V , G = V

85

35

0

100

45

120

45

AVQV

ACC

IL

Address Valid to Output

Valid (Page)

t

E = V , G = V

AVQV1

PAGE

IL

Chip Enable High to

Output Transition

t

G = V

0

EHQX

OH

IL

Chip Enable High to

Output Hi-Z

(1)

t

G = V

20

10

85

0

20

t

HZ

IL

EHQZ

Chip Enable Low to

Latch Enable High

t

E = V , G = V

10

ELLH

ELAVDH

IL

IH

Chip Enable Low to

Output Valid

(2)

t

G = V

100

120

t

CE

IL

ELQV

Chip Enable Low to

Output Transition

(1)

t

G = V

0

LZ

IL

ELQX

Output Enable High to

Output Transition

t

E = V

0

GHQX

OH

IL

Output Enable High to

Output Hi-Z

(1)

t

E = V

20

25

0

20

25

20

35

t

DF

IL

GHQZ

Output Enable Low to

Output Valid

(2)

(1)

t

E = V

t

OE

IL

GLQV

Output Enable Low to

Output Transition

t

E = V

0

OLZ

IL

GLQX

Latch Enable High to

Address Transition

t

E = V , G = V

10

85

35

10

LHAX

AVDHAX

IL

IH

Latch Enable Pulse

Width

t

E = V , G = V

LLLH

AVDLAVDH

IL

IH

Latch Enable Low to

Output Valid (Random)

t

E = V

100

45

120

45

LLQV

AVDLQV

IL

Latch Enable Low to

Output Valid (Page)

t

E = V

LLQV1

IL

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

37/63

M58CR032C, M58CR032D

Figure 13. Synchronous Burst Read

38/63

M58CR032C, M58CR032D

Table 22. Synchronous Burst Read AC Characteristics

M58CR032

Symbol

Alt

Parameter

Test Condition

85

100

120

Unit

Min Max Min Max Min Max

Address Valid to Clock

High

t

AVCLKH

7

ns

AVKH

Chip Enable Low to Clock

High

t

CELCLKH

7

ns

ELKH

t

Clock Period

18

10

18

10

25

10

KHKH

CLK

Clock High to Address

Transition

t

E = V , G = V

IH

KHAX

CLKHAX

IL

t

Clock High to Clock Low

Clock Low to Clock High

5

ns

KHKL

CLKHCLKL

t

KLKH

CLKLCLKH

Clock to Data Valid

Clock to WAIT Valid

t

E = V , G = V

14

18

ns

KHQV

CLKHQV

IL

Clock to Output Transition

Clock to WAIT Transition

t

E = V

4

7

4

7

4

7

KHQX

CLKHQX

IL

Latch Enable Low to Clock

High

t

LLKH

AVDLCLKH

Note: For other timings please refer to Table 21, Asynchronous Read AC Characteristics

39/63

M58CR032C, M58CR032D

Figure 14. Write AC Waveforms, Write Enable Controlled

40/63

M58CR032C, M58CR032D

Table 23. Write AC Characteristics, Write Enable Controlled

M58CR032

Symbol

Alt

Parameter

85

100

120

Unit

Min

85

10

40

10

0

Max

Min

100

10

40

10

0

Max

Min

120

10

40

10

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Latch Enable High

Input Valid to Write Enable High

ns

µs

ns

AVAV

t

AVLH

t

DVWH

DS

t

Chip Enable Low to Latch Enable High

Chip Enable Low to Write Enable Low

Latch Enable High to Address Transition

Latch Enable Pulse Width

ELLH

t

ELWL

CS

t

10

50

200

0

10

50

200

0

10

50

200

0

LHAX

t

LLLH

t

V

High to Chip Enable Low

VDHEL

VCS

DD

PP

t

V

High to Write Enable High

VPPHWH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

Write Enable High to Latch Enable Low

WHDX

DH

t

0

WHEH

CH

t

OEH

0

WHGL

t

0

WHLL

t

Write Enable High to V Low

200

30

200

50

200

30

200

50

200

30

200

50

200

WHVPPL

PP

t

WPH

Write Enable High to Write Enable Low

Write Enable High to Write Protect Valid

Write Enable Low to Write Enable High

Write Protect Valid to Write Enable High

WHWL

t

WHWPV

t

WLWH

WP

t

WPVWH

41/63

M58CR032C, M58CR032D

Figure 15. Write AC Waveforms, Chip Enable Controlled

42/63

M58CR032C, M58CR032D

Table 24. Write AC Characteristics, Chip Enable Controlled

M58CR032

100

Symbol

Alt

Parameter

85

120

Unit

Min

85

10

40

0

Max

Min

100

10

40

0

Max

Min

120

10

40

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Latch Enable High

Input Valid to Chip Enable High

ns

µs

ns

AVAV

t

AVLH

t

DVEH

DS

t

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Latch Enable High

Latch Enable High to Address Transition

Latch Enable High to Chip Enable High

Latch Enable Pulse Width

EHDX

DH

t

CPH

30

0

30

0

30

0

EHEL

t

WH

EHWH

t

CP

60

10

50

200

0

60

10

50

200

0

60

10

50

200

0

ELEH

t

ELLH

t

LHAX

t

LHEH

t

LLLH

t

V

High to Chip Enable Low

VDHEL

VCS

DD

PP

t

V

High to Chip Enable High

VPPHEH

t

Chip Enable High to V Low

EHVPPL

PP

t

Chip Enable High to Write Protect Low

Chip Enable Low to Chip Enable Low

Write Protect High to Chip Enable High

EHWPL

t

WS

WLEL

t

200

WPHEH

43/63

M58CR032C, M58CR032D

Figure 16. Reset and Power-up AC Waveforms

W, E, G

tPLWL

tPLEL

tPLGL

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI90013b

Table 25. Reset and Power-up AC Characteristics

Symbol

Parameter

Test Condition

Min

50

Unit

(1,2)

RP Pulse Width

ns

µs

ns

t

PLPH

t

During Program and Erase

10/20

80

PLWL

t

Reset Low to Device Enabled

PLEL

PLGL

Other Conditions

(3)

Supply Valid to Reset High

50

µs

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset.

44/63

M58CR032C, M58CR032D

PACKAGE MECHANICAL

Figure 17. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Bottom View Package Outline

D

D1

FD

SD

FE

E

E1

BALL "A1"

A

e

ddd

e

b

A2

A1

BGA-Z20

Note: Drawing is not to scale.

Table 26. TFBGA56 6.5x10mm - 8x7 ball array, 0.75 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.400

Typ

Max

A

A1

A2

b

1.010

0.0398

0.0098

0.0472

0.0157

0.250

0.790

0.400

6.500

5.250

0.0311

0.0157

0.2559

0.2067

0.350

6.400

–

0.450

0.0138

0.2520

–

0.0177

D

6.600

0.2598

D1

ddd

E

–

0.100

0.0039

10.000

4.500

0.750

0.625

2.750

0.375

9.900

10.100

0.3937

0.1772

0.0295

0.0246

0.1083

0.0148

0.3898

0.3976

E1

e

–

FD

FE

SD

45/63

M58CR032C, M58CR032D

PART NUMBERING

Table 27. Ordering Information Scheme

Example:

M58CR032C

85 ZB

6

T

Device Type

M58

Architecture

C = Dual Bank, Burst Mode

Operating Voltage

R = V = 1.65V to 2.0V, V

= 1.65V to 3.3V

DD

DDQ

Device Function

032C = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot

032D = 32 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot

Speed

85 = 85 ns

100 = 100 ns

120 = 120 ns

Package

ZB = TFBGA56: 0.75 mm pitch

Temperature Range

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc....) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

46/63

M58CR032C, M58CR032D

REVISION HISTORY

Table 28. Document Revision History

Date

Version

-01

Revision Details

April 2001

23-OCT-2001

First Issue

-02

85ns speed class added, document classified as Preliminary Data

Document completely revised. Changes in CFI content, Program and Erase Times

Table and DC Characteristics Table

21-Mar-2002

06-Sep-2002

-03

3.1

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 03 equals 3.0).

Latch Enable, L, logic level modified during Asynchronous Read/Write operations as

shown in Table 3, Bus Operations.

First X-Latency formula modified together with meaning of t

parameter in

AVK_CPU

formula (under Burst Configuration Register Paragraph).

Minimum V

and V

supply voltages reduced to 1.8V for 85ns class speed in

DD

DDQ

Table 17, Operating and AC Measurement Conditions.

‘Number of identical-size erase block’ parameters modified in Table 32, Device

Geometry Definition.

47/63

M58CR032C, M58CR032D

APPENDIX A. COMMON FLASH INTERFACE

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 29, 30,

31, 32, 33, 34 and 35 show the addresses used to

retrieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 35, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by ST. Issue a Read

command to return to Read mode.

When the Read CFI Query Command is issued

the device enters CFI Query mode and the data

Table 29. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Lock Protection Register

Unique device Number and

User Programmable OTP

80h

Security Code Area

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 30, 31, 32, 33, 34 and 35. Query data are always presented on the lowest order data outputs.

Table 30. CFI Query Identification String

Offset

Sub-section Name

Description

Value

00h

0020h

Manufacturer Code

ST

88C8h

88C9h

Top

Bottom

01h

Device Code (M58CR032C/D)

02h

03h

reserved

0051h

Reserved

04h-0Fh

10h

"Q"

"R"

"Y"

11h

0052h

Query Unique ASCII String "QRY"

12h

0059h

13h

0003h

Primary Algorithm Command Set and Control Interface ID code 16

bit ID code defining a specific algorithm

14h

0000h

15h

offset = P = 0039h

0000h

Address for Primary Algorithm extended Query table (see Table 32)

p = 39h

NA

16h

17h

0000h

Alternate Vendor Command Set and Control Interface ID Code

second vendor - specified algorithm supported

18h

0000h

19h

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

NA

1Ah

Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’.

48/63

M58CR032C, M58CR032D

Table 31. CFI Query System Interface Information

Offset

Data

Description

Value

V

DD

V

DD

V

PP

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0017h

1.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0020h

0017h

00C0h

2V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

1.7V

12V

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

0003h

000Ah

0000h

0003h

0004h

0002h

0000h

16µs

8µs

Typical time-out per single Byte/Word program = 2 µs

n

Typical time-out for Quadruple Word Program = 2 µs

n

1s

Typical time-out per individual Block Erase = 2 ms

n

NA

Typical time-out for full Chip Erase = 2 ms

n

128µs

4s

Maximum time-out for Word Program = 2 times typical

n

Maximum time-out for Quadruple Word = 2 times typical

n

Maximum time-out per individual Block Erase = 2 times typical

n

NA

Maximum time-out for Chip Erase = 2 times typical

Table 32. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0016h

4 MByte

Device Size = 2 in number of Bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0003h

0000h

n

8 Byte

2

Maximum number of Bytes in multi-Byte program or page = 2

2Ch

0002h

Number of Erase Block Regions within the device

bit 7 to 0 = x = number of Erase Block Regions

It specifies the number of regions within the device containing one or more

contiguous Erase Blocks of the same size.

49/63

M58CR032C, M58CR032D

Offset Word

Data

Description

Value

63

Mode

2Dh

2Eh

003Eh

0000h

Region 1 Information

Number of identical-size erase block = 003Eh+1

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 Bytes

64 KByte

8

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase block = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 Bytes

8 KByte

NA

35h

38h

0000h

Reserved for future raise block region information

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

8

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 Bytes

8 KByte

63

31h

32h

003Eh

0000h

Region 2 Information

Number of identical-size erase block = 003Eh+1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 Bytes

64 KByte

NA

35h

38h

0000h

Reserved for future raise block region information

Table 33. Primary Algorithm-Specific Extended Query Table

Data

0050h

0052h

0049h

0031h

0030h

00E6h

0003h

0000h

Description

Value

"P"

"R"

"I"

Offset

(P)h = 39h

Primary Algorithm extended Query table unique ASCII string “PRI”

(P+3)h = 3Ch

(P+4)h = 3Dh

(P+5)h = 3Eh

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant Byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

Chip Erase supported

(1 = Yes, 0 = No)

No

Yes

No

(P+7)h

(P+8)h

Erase Suspend supported

Program Suspend supported

Legacy Lock/Unlock supported

Queued Erase supported

Instant individual block locking supported (1 = Yes, 0 = No)

Protection bits supported

Page mode read supported

Synchronous read supported

Simultaneous operation supported

No

Yes

(1 = Yes, 0 = No)

bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31

bit field of optional features follows at the end of the bit-30

field.

50/63

M58CR032C, M58CR032D

Data

Description

Supported Functions after Suspend

Value

Offset

(P+9)h = 42h

0001h

Read Array, Read Status Register and CFI Query

Yes

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

(P+A)h = 43h

(P+B)h

0003h

0000h

Block Protect Status

Defines which bits in the Block Status Register section of the Query are

implemented.

bit 0 Block protect Status Register Lock/Unlock

bit active

(1 = Yes, 0 = No)

Yes

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

(P+C)h = 45h

(P+D)h = 46h

0018h

00C0h

0000h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

1.8V

DD

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

12V

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

(P+E)h = 47h

(P+F)h

Reserved

(P+10)h

(P+11)h

(P+12)h

Table 34. Burst Read Information

Data

Description

Value

Offset

(P+13)h = 4Ch

0003h

Page-mode read capability

8 Byte

n

bits 0-7

’n’ such that 2 HEX value represents the number of read-

page Bytes. See offset 28h for device word width to

determine page-mode data output width.

(P+14)h = 4Dh

(P+15)h = 4Eh

0003h

0001h

Number of synchronous mode read configuration fields that follow.

Synchronous mode read capability configuration 1

3

4

bit 3-7

Reserved

n+1

bit 0-2

’n’ such that 2

HEX value represents the maximum

number of continuous synchronous reads when the device is

configured for its maximum word width. A value of 07h

indicates that the device is capable of continuous linear

bursts that will output data until the internal burst counter

reaches the end of the device’s burstable address space.

This field’s 3-bit value can be written directly to the read

configuration register bit 0-2 if the device is configured for its

maximum word width. See offset 28h for word width to

determine the burst data output width.

(P+16)h = 4Fh

(P+17)h = 50h

(P+18)h = 51h

0002h

0007h

0036h

Synchronous mode read capability configuration 2

Synchronous mode read capability configuration 3

Max operating clock frequency (MHz)

8

Cont.

54 MHz

51/63

M58CR032C, M58CR032D

Data

Description

Value

Offset

(P+19)h = 52h

0001h

Supported handshaking signal (WAIT pin)

bit 0

bit 1

during Synchronous Read

during Asynchronous Read

(1 = Yes, 0 = No)

Yes

No

Table 35. Security Code Area

Offset

Data

LPR

Description

Lock Protection Register

bit 0: ST programmed, value 0

bit 1: OTP protection and bit 2

protection bit

80h

bit 2: Security Block Protection bit

bits 3 - 15 reserved

81h

82h

83h

84h

85h

86h

87h

88h

ID data

64 bits: unique device number

OTP data

64 bits: User Programmable OTP

52/63

M58CR032C, M58CR032D

APPENDIX B. FLOWCHARTS AND PSEUDO CODES

Figure 18. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

writeToFlash (any_address, 0x40) ;

Write 40h or 10h

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

Program

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI090014b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

53/63

M58CR032C, M58CR032D

Figure 19. Double Word Program Flowchart and Pseudo code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI090015b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

54/63

M58CR032C, M58CR032D

Figure 20. Quadruple Word Program Flowchart and Pseudo Code

Start

quadruple_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

Write 55h

Write Address 1

& Data 1 (3)

writeToFlash (any_address, 0x55) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 2

& Data 2 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

Write Address 3

& Data 3 (3)

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

Write Address 4

& Data 4 (3)

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI05283

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

55/63

M58CR032C, M58CR032D

Figure 21. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI90016b

56/63

M58CR032C, M58CR032D

Figure 22. Block Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

Error (1)

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI90017b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

57/63

M58CR032C, M58CR032D

Figure 23. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

Write B0h

Write 70h

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

} while (status_register.b7== 0) ;

b7 = 1

YES

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

Write D0h

Write FFh

Read Data

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

}

Erase Continues

AI90018b

58/63

M58CR032C, M58CR032D

Figure 24. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

writeToFlash (any_address, 0x60) ; /*configuration setup*/

Write 60h

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

Write 90h

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

Write FFh

}

End

AI05281

59/63

M58CR032C, M58CR032D

Figure 25. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

Write C0h

writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI05282

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

60/63

M58CR032C, M58CR032D

APPENDIX C. COMMAND INTERFACE STATE TABLES

Table 36. Command Interface States - Lock table

Current State of the

Current Bank

Command Input to the Current Bank (and Next State of the Current Bank)

Erase

Confirm

P/E

Resume

Unlock

Confirm

(D0h)

Current

State of

Other

Block Lock

Block

Read

Status

Register

(70h)

Clear

Status

Register Signature

(50h)

Read

Electronic

Unlock

Read

Array

(FFH)

Read

CFI Query

(98h)

Block lock

Confirm

(01h)

Lock-

Down

Confirm

(2Fh)

Set BCR

Confirm

(03h)

Lock-Down

setup

Set BCR

setup (60h)

Mode

State

Others

Bank

(90h)

Array

CFI

Block Lock,

Unlock,

SEE

Read

Elect.

Sign.

Any State

Read

MODIFY Read Array Read Array Status ReadArray

TABLE

Read CFI Lock-Down, Read Array Read Array Read Array

Electronic

Signature

Register

Set BCR

Setup

Status

Setup

Error

Block Lock Block lock

Unlock

Lock-Down Lock-Down

Error, Set Error, Set

BCR Error BCR Error

Block Lock Block Lock Block Lock Block Lock Block Lock

Block Lock

Unlock

Lock-Down

Block

Block Lock Block Lock

Unlock Unlock

Lock-Down Lock-Down

Block Block

Unlock

Lock-Down Lock-Down Lock-Down Lock-Down Lock-Down

Error, Set Error, Set Error, Set Error, Set Error, Set

BCR Error BCR Error BCR Error BCR Error BCR Error

Set BCR

Lock

Unlock

Lock-Down

BCR

Any State

Block LocK

Unlock

Lock

Unlock

Lock-Down

Block

SEE

Read

Elect.

Sign.

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Register

Setup, Set

BCR Setup

Set BCR

Block LocK

SEE

Read

Elect.

Sign.

Unlock

Protection

Register

Any State

Done

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Register

Setup, Set

BCR Setup

Block LocK

Unlock

Program-

Double/

Quadruple

Program

SEE

Read

Elect.

Sign.

Done

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Register

Setup, Set

BCR Setup

Setup

Idle

Read

Array, CFI,

Elect.

Sign.,

Status

SEE

MODIFY

TABLE

PS Read

Status

Register

PS Read

Elect.

Sign.

Program

Suspend

PS Read Program

PS Read

Array

PS Read

CFI

PS Read

Array

PS Read PS Read PS Read

Array

(Busy)

Array

Erase

Suspend

Erase

Error

Erase

Error

Erase

(Busy)

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Idle

Setup

Error

Erase Error

Block/

Bank

Erase

Block LocK

Unlock

SEE

Read

Elect.

Sign.

Any State

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI Lock-Down Read Array Read Array Read Array

Done

Register

Setup, Set

BCR Setup

Erase

(Busy)

Setup

Busy

Idle

Read

Array, CFI,

Elect.

Sign.,

Status

Block LocK

Unlock

Lock-Down

Setup, Set

BCR Setup

ES Read

Array

SEE

MODIFY

TABLE

ES Read

Status

Register

ES Read

Elect.

Sign.

Erase

Suspend

ES Read

Array

ES Read

Array

ES Read

CFI

ES Read ES Read ES Read

Array

Erase

(Busy)

Program

Suspend

ES Read

Array

Note: PS = Program Suspend, ES = Erase Suspend.

61/63

M58CR032C, M58CR032D

Table 37. Command Interface States - Modify Table

Current State of the Current

Command Input to the Current Bank (and Next State of the Current Bank)

Bank

Current State

of the Other

Bank

Protection

Register

Double/

Quadruple

Program Setup Block Erase Program-Erase

(10h/40h)

Bank Erase

Setup (80h)

Mode

State

Others

Setup (20h) Suspend (B0h) ProgramSetup ProgramSetup

(C0h)

(30h/55h)

Setup

Busy

Read Array

Array, CFI,

Electronic

Signature,

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

SEE LOCK

TABLE

Read

Read Array

Program setup

Erase Suspend

Status Register

Read Array

Program

Suspend

Read Array

Setup

Busy

Read Array

Error,

Lock Unlock

Lock-Down

Block,

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

Lock Unlock

Lock-Down BCR

SEE LOCK

TABLE

Read Array

Protection

Program setup

Erase Suspend

Set BCR

Read Array

Program

Suspend

Read Array

Protection

Read Array

Protection

Idle

Setup

Busy

Setup

Busy

Protection

Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy)

Read Array

Protection

Register

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

SEE LOCK

TABLE

Program Setup

Done

Read Array

Erase Suspend

Read Array

Program

Suspend

Read Array

Any State

Setup

Busy

Program(Busy)

Program(Busy) Program(Busy) Program(Busy)

Program(Busy) Program (Busy) Program (Busy)

PS Read Status

Register

Idle

Setup

Busy

Program

Double/

Quadruple

Word Program

Read Array

Program Setup

Read Array

Block Erase

Setup

Protection

Register Setup

Bank Erase

Setup

Double/

Quadruple

Program Setup

Idle

SEE LOCK

TABLE

Done

Read Array

Erase Suspend

Read Array

Program

Suspend

Read Array

Setup

Idle

Read Array,

CFI, Elect.

Sign., Status

Register

Program

Suspend

SEE LOCK

TABLE

PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array

Erase Suspend

SEE LOCK

TABLE

Setup

Busy

Erase Error

Block/ Bank

Erase

Idle

ES Read Status

Register

Erase (Busy)

Setup

Busy

ES Read Array

Program Setup

ES Read Array

Read Array,

CFI, Elect.

Sign., Status

Register

Double/

Quadruple

Program Setup

SEE LOCK

TABLE

Erase Suspend

ES Read Array ES Read Array ES Read Array

ES Read Array

Idle

Program

Suspend

ES Read Array

Note: PS = Program Suspend, ES = Erase Suspend.

62/63

M58CR032C, M58CR032D

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

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63/63


型号：	M58CR032C100ZB6T
厂家：	ST
描述：	32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory 32兆位（2MB ×16 ，双行，突发） 1.8V供应快闪记忆体闪存存储内存集成电路
文件：	总63页 (文件大小：435K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58CR032C100ZB6T [STMICROELECTRONICS]

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