M58LR016C100ZC6T_技术文档

M58MR016C

M58MR016D

16 Mbit (1Mb x16, Mux I/O, Dual Bank, Burst)

1.8V Supply Flash Memory

PRELIMINARY DATA

■ SUPPLY VOLTAGE

– V = V = 1.7V to 2.0V for Program,

DD

DDQ

Erase and Read

– V = 12V for fast Program (optional)

PP

■ MULTIPLEXED ADDRESS/DATA

■ SYNCHRONOUS / ASYNCHRONOUS READ

– Burst mode Read: 40MHz

FBGA

TFBGA48 (ZC)

10 x 4 ball array

– Page mode Read (4 Words Page)

– Random Access: 100ns

■ PROGRAMMING TIME

– 10µs by Word typical

– Two or four words programming option

■ MEMORY BLOCKS

– Dual Bank Memory Array: 4/12 Mbit

– Parameter Blocks (Top or Bottom location)

■ DUAL OPERATIONS

Figure 1. Logic Diagram

V

DD DDQ PP

– Read within one Bank while Program or

Erase within the other

4

16

A16-A19

– No delay between Read and Write operations

■ PROTECTION/SECURITY

ADQ0-ADQ15

W

E

– All Blocks protected at Power-up

WAIT

BINV

– Any combination of Blocks can be protected

– 64 bit unique device identifier

M58MR016C

M58MR016D

G

RP

WP

L

– 64 bit user programmable OTP cells

– One parameter block permanently lockable

■ COMMON FLASH INTERFACE (CFI)

■ 100,000 PROGRAM/ERASE CYCLES per

K

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

V

SS

– Top Device Code, M58MR016C: 88DEh

– Bottom Device Code, M58MR016D: 88E0h

AI05228

August 2002

1/51

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M58MR016C, M58MR016D

Figure 2. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

DU

A

B

DU

C

D

E

F

WAIT

NC

A16

K

L

V

W

RP

V

A19

A18

A17

E

NC

V

DD

PP

SS

V

NC

BINV

WP

SS

DDQ

ADQ13 ADQ12

V

ADQ7

ADQ6

ADQ3

ADQ2

ADQ9

ADQ8

ADQ1

G

SS

ADQ15 ADQ14

V

ADQ5

ADQ4 ADQ11 ADQ10

V

ADQ0

SS

DDQ

G

H

DU

AI05229

DESCRIPTION

in order to increase the data security. An optional

12V V power supply is provided to speed up the

PP

The M58MR016 is a 16 Mbit non-volatile Flash

memory that may be erased electrically at block

level and programmed in-system on a Word-by-

program phase at costumer production. An inter-

nal command interface (C.I.) decodes the instruc-

tions to access/modify the memory content. The

program/erase controller (P/E.C.) automatically

executes the algorithms taking care of the timings

necessary for program and erase operations. Two

status registers indicate the state of each bank.

Instructions for Read Array, Read Electronic Sig-

nature, Read Status Register, Clear Status Regis-

ter, Write Read Configuration Register, Program,

Block Erase, Bank Erase, Program Suspend, Pro-

gram Resume, Erase Suspend, Erase Resume,

Block Protect, Block Unprotect, Block Locking,

Protection Program, CFI Query, are written to the

memory through a Command Interface (C.I.) using

standard micro-processor write timings.

Word basis using a 1.7V to 2.0V V supply for the

DD

circuitry. For Program and Erase operations the

necessary high voltages are generated internally.

The device supports synchronous burst read and

asynchronous read from all the blocks of the mem-

ory array; at power-up the device is configured for

page mode read. In synchronous burst mode, a

new data is output at each clock cycle for frequen-

cies up to 40MHz.

The array matrix organization allows each block to

be erased and reprogrammed without affecting

other blocks. All blocks are protected against pro-

gramming and erase at Power-up.

Blocks can be unprotected to make changes in the

application and then re-protected.

A parameter block "Security block" can be perma-

nently protected against programming and erasing

The memory is offered in TFBGA48, 0.5 mm ball

pitch packages and it is supplied with all the bits

erased (set to ’1’).

2/51

M58MR016C, M58MR016D

Table 1. Signal Names

Organization

The M58MR016 is organized as 1Mb by 16 bits.

The first sixteen address lines are multiplexed with

the Data Input/Output signals on the multiplexed

address/data bus ADQ0-ADQ15. The remaining

address lines A16-A19 are the MSB addresses.

A16-A19

Address Inputs

Data Input/Outputs or Address

Inputs, Command Inputs

ADQ0-ADQ15

E

Chip Enable

Chip Enable E, Output Enable G and Write Enable

W inputs provide memory control.

The clock K input synchronizes the memory to the

microprocessor during burst read.

G

Output Enable

Write Enable

W

Reset RP is used to reset all the memory circuitry

and to set the chip in power-down mode if a proper

setting of the Read Configuration Register en-

ables this function.

WAIT output indicates to the microprocessor the

status of the memory during the burst mode oper-

ations.

RP

WP

K

Reset/Power-down

Write Protect

Burst Clock

L

Latch Enable

Memory Blocks

WAIT

BINV

Wait Data in Burst Mode

Bus Invert

The device features asymmetrically blocked archi-

tecture. M58MR016 has an array of 71 blocks and

is divided into two banks A and B, providing Dual

Bank operations. While programming or erasing in

Bank A, read operations are possible into Bank B

or vice versa. Only one bank at the time is allowed

to be in program or erase mode. It is possible to

perform burst reads that cross bank boundaries.

V

DD

Supply Voltage

Supply Voltage for Input/Output

Buffers

V

DDQ

Optional Supply Voltage for

Fast Program & Erase

The memory features an erase suspend allowing

reading or programming in another block. Once

suspended the erase can be resumed. Program

can be suspended to read data in another block

and then resumed. The Bank Size and sectoriza-

tion are summarized in Table 3. Parameter Blocks

are located at the top of the memory address

space for the M58MR016C, and at the bottom for

the M58MR016D. The memory maps are shown in

Figure 3.

V

PP

Ground

SS

DU

Don’t Use as Internally Connected

Not Connected Internally

NC

(1)

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

V

(2)

T

A

–40 to 85

–40 to 125

–55 to 155

Ambient Operating Temperature

T

Temperature Under Bias

Storage Temperature

Input or Output Voltage

Supply Voltage

BIAS

T

STG

(3)

–0.5 to V

+0.5

V

DDQ

–0.5 to 2.7

–0.5 to 13

IO

V

, V

DD DDQ

V

Program Voltage

V

PP

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-

ity documents.

2. Depends on range.

3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3/51

M58MR016C, M58MR016D

The architecture includes a 128 bit Protection reg-

ister that is divided into two 64 bit segments. In the

first one is written a unique device number, while

the second one is programmable by the user. The

user programmable segment can be permanently

protected programming the bit 1 of the Protection

Lock Register (see protection register and Securi-

ty Block). The parameter block (# 0) is a security

block. It can be permanently protected by the user

programming the bit 2 of the Protection Lock Reg-

ister.

Block protection against Program or Erase pro-

vides additional data security. All blocks are pro-

tected and unlocked at Power-up. Instructions are

provided to protect or un-protect any block in the

application. A second register locks the protection

status while WP is low (see Block Locking descrip-

tion).

Table 3. Bank Size and Sectorization

Bank Size

Parameter Blocks

Main Blocks

Bank A

Bank B

4 Mbit

8 blocks of 4 KWord

-

7 blocks of 32 KWord

24 blocks of 32 KWord

12 Mbit

Figure 3. Memory Map

Top Boot Block

Bottom Boot Block

Address lines A19-A0

000000h

007FFFh

000000h

000FFFh

512 Kbit or

32 KWord

64 Kbit or

4 KWord

Total of 24

Main Blocks

Total of 8

Parameter

Blocks

Bank B

0B8000h

007000h

512 Kbit or

32 KWord

64 Kbit or

4 KWord

0BFFFFh

0C0000h

007FFFh

008000h

Bank A

512 Kbit or

32 KWord

512 Kbit or

32 KWord

0C7FFFh

0F0000h

00FFFFh

038000h

Total of 7

Main Blocks

Total of 7

Main Blocks

512 Kbit or

32 KWord

512 Kbit or

32 KWord

0F7FFFh

0F8000h

03FFFFh

040000h

Bank A

64 Kbit or

4 KWord

512 Kbit or

32 KWord

0F8FFFh

047FFFh

Total of 8

Parameter

Blocks

Total of 24

Main Blocks

Bank B

0FF000h

0FFFFFh

0F8000h

0FFFFFh

64 Kbit or

4 KWord

512 Kbit or

32 KWord

AI05230

4/51

M58MR016C, M58MR016D

SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs or Data Input/Output (ADQ0-

ADQ15). When Chip Enable E is at V and Out-

at least t

. When the reset pulse is given, the

PLPH

memory will recover from Power-down (when en-

abled) in a minimum of t , t or t (see

PHEL PHLL

PHWL

Table 31 and Figure 15) after the rising edge of

RP. Exit from Reset/Power-down changes the

contents of the Read Configuration Register bits

14 and 15, setting the memory in asynchronous

page mode read and power save function dis-

abled. All blocks are protected and unlocked after

a Reset/Power-down.

Latch Enable (L). L latches the address bits

ADQ0-ADQ15 and A16-A19 on its rising edge.

The address latch is transparent when L is at V

and it is inhibited when L is at V .

Clock (K). The clock input synchronizes the

memory to the micro controller during burst mode

read operation; the address is latched on a K edge

(rising or falling, according to the configuration set-

tings) when L is at V . K is don’t care during asyn-

chronous page mode read and in write operations.

Wait (WAIT). WAIT is an output signal used dur-

ing burst mode read, indicating whether the data

on the output bus are valid or a wait state must be

inserted. This output is high impedance when E or

IL

put Enable G is at V the multiplexed address/

IH

data bus is used to input addresses for the memo-

ry array, data to be programmed in the memory ar-

ray or commands to be written to the C.I. The

address inputs for the memory array are latched

on the rising edge of Latch Enable L. The address

latch is transparent when L is at V . In synchro-

IL

nous operations the address is also latched on the

first rising/falling edge of K (depending on clock

configuration) when L is low. Both input data and

commands are latched on the rising edge of Write

Enable W. When Chip Enable E and Output En-

IL

IH

able G are at V the address/data bus outputs

IL

data from the Memory Array, the Electronic Signa-

ture Manufacturer or Device codes, the Block Pro-

tection status the Read Configuration Register

status, the protection register or the Status Regis-

ter. The address/data bus is high impedance when

IL

the chip is deselected, Output Enable G is at V ,

IH

or RP is at V .

IL

Address Inputs (A16-A19). The five MSB ad-

dresses of the memory array are latched on the

rising edge of Latch Enable L. In synchronous op-

eration these inputs are also latched on the first

rising/falling edge of K (depending on clock config-

uration) when L is low.

G are high or RP is at V , and can be configured

to be active during the wait cycle or one clock cy-

cle in advance.

IL

Bus Invert (BINV). BINV is an input/output signal

used to reduce the amount of power needed to

switch the external address/data bus. The power

saving is achieved by inverting the data output on

ADQ0-ADQ15 every time this gives an advantage

in terms of number of toggling bits. In burst mode

read, each new data output from the memory is

compared with the previous data. If the number of

transitions required on the data bus is in excess of

8, the data is inverted and the BINV signal will be

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. E at V deselects

IH

the memory and reduces the power consumption

to the standby level. E can also be used to control

writing to the command register and to the memo-

ry array, while W remains at V .

IL

driven by the memory at V

to inform the receiv-

OH

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

ing system that data must be inverted before any

further processing. By doing so, the actual transi-

tions on the data bus will be less than 8.

eration. When G is at V the outputs are High im-

IH

pedance.

In a similar way, when a command is given, BINV

Write Enable (W). This input controls writing to

the Command Register and Data latches. Data are

latched on the rising edge of W.

may be driven by the system at V to inform the

IH

memory that the data input must be inverted.

Like the other input/output pins, BINV is high im-

pedance when the chip is deselected, output en-

Write Protect (WP). This input gives an addition-

al hardware protection level against program or

able G is at V or RP is at V ; when used as an

IH

IL

erase when pulled at V , as described in the Block

IL

input, BINV must follow the same set-up and hold

timings of the data inputs.

Lock instruction description.

Reset/Power-down Input (RP). The RP input

provides hardware reset of the memory, and/or

Power-down functions, depending on the Read

Configuration Register status. Reset/Power-down

V

and V

Supply Voltage (1.7V to 2.0V).

DDQ

DD

V

is the main power supply for all operations

DD

(Read, Program and Erase). V

voltage for Input and Output.

is the supply

DDQ

of the memory is achieved by pulling RP to V for

IL

5/51

M58MR016C, M58MR016D

V

Program Supply Voltage (12V). V is both

operation has been started does not have any ef-

fect and program or erase are carried on regularly.

PP

a control input and a power supply pin. The two

functions are selected by the voltage range ap-

If V is used in the 11.4V to 12.6V range (V

)

PP

PPH

plied to the pin; if V is kept in a low voltage range

then the pin acts as a power supply (see Table

26). This supply voltage must remain stable as

long as program or erase are running. In read

mode the current sunk is less then 0.5mA, while

during program and erase operations the current

may increase up to 10mA.

PP

(0 to 2V) V is seen as a control input, and the

PP

current absorption is limited to 5µA (0.2µA typical).

In this case with V = V we obtain an absolute

PP

IL

protection against program or erase; with V

=

PP

V

these functions are enabled (see Table 26).

value is only sampled during program or

PP1

PP

V

Ground. V is the reference for all the volt-

SS

erase write cycles; a change in its value after the

age measurements.

6/51

M58MR016C, M58MR016D

DEVICE OPERATIONS

nature, the Status Register, the CFI, the Block

Protection Status, the Read Configuration Regis-

ter status and the Protection Register.

Read operation of the Memory Array may be per-

formed in asynchronous page mode or synchro-

nous burst mode. In asynchronous page mode

data is internally read and stored in a page buffer.

The page has a size of 4 words and is addressed

by ADQ0 and ADQ1 address inputs.

According to the device configuration the following

Read operations: Electronic Signature - Status

Register - CFI - Block Protection Status - Read

Configuration Register Status - Protection Regis-

ter must be accessed as asynchronous read or as

single synchronous read (see Figure 4).

The following operations can be performed using

the appropriate bus cycles: Address Latch, Read

Array (Random, and Page Modes), Write com-

mand, Output Disable, Standby, reset/Power-

down and Block Locking. See Table 4.

Address Latch. In asynchronous operation, the

address is latched on the rising edge of L input. In

burst mode the address is latched either on the ris-

ing edge of L or on the first rising/falling edge of K

(depending on configuration settings) when L is

low.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

(1)

Table 4. User Bus Operations

Operation

E

G

W

L

RP

WP

ADQ15-ADQ0

V

IL

V

IL

V

IH

V

IH

V

IH

V

IH

Address Latch

Address Input

(rising edge)

V

Write

Data Input

Hi-Z

IL

IH

IL

IH

V

IH

V

IH

V

IH

Output Disable

Standby

IL

IH

V

IH

X

Hi-Z

IH

V

Reset / Power-down

X

Hi-Z

IL

V

IH

V

Block Locking

X

IL

Note: 1. X = Don’t care.

(1)

Table 5. Read Electronic Signature (AS and Read CFI instructions)

Other

(3)

Code

Device

E

G

W

ADQ15-0

ADQ1

ADQ0

(2)

Address

(2)

V

Manufacturer Code

0020h

88DEh

88E0h

IL

IH

IL

EA

(2)

V

M58MR016C

M58MR016D

IL

IH

EA

Device Code

(2)

V

IL

IH

EA

Note: 1. Addresses are latched on the rising edge of L input.

2. EA means Electronic Signature Address (see Read Electronic Signature)

3. Value during address latch.

(1)

Table 6. Read Block Protection (AS and Read CFI instructions)

Other

Address

(3)

Block Status

E

G

W

ADQ15-0

ADQ1

ADQ0

(4)

V

Protected and unlocked

Unprotected and unlocked

Protected and locked

0001

0000

0003

0002

IL

IH

IL

BA

(4)

V

IH

V

IL

BA

(4)

V

IH

V

IL

BA

(2)

(4)

V

IH

V

IL

Unprotected and locked

BA

Note: 1. Addresses are latched on the rising edge of L input.

2. A locked block can be unprotected only with WP at V

3. Value during address latch.

IH.

4. BA means Block Address. First cycle command address should indicate the bank of the block address.

7/51

M58MR016C, M58MR016D

(1)

Table 7. Read Protection Register (RSIG and RCFI Instruction)

Word

E

G

W

A19-17 ADQ15-8 ADQ7-0 ADQ15-8 ADQ7-3

ADQ2

ADQ1

ADQ0

Security

prot.data prot.data

OTP

(2)

V

Lock

80h

81h

82h

83h

84h

85h

86h

87h

88h

00h

00000B

ID data

0

IL

IH

X

Unique

ID 0

V

ID data

ID data ID data

Unique

ID 1

ID data

Unique

ID 2

ID data

Unique

ID 3

ID data

OTP

data

OTP

data

OTP

data

OTP

data

OTP 0

OTP 1

OTP 2

OTP 3

OTP data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

OTP

data

Note: 1. Addresses are latched on the rising edge of L input.

2. X = Don’t care.

(1, 2, 3)

Table 8. Dual Bank Operations

Commands allowed in the other bank

Erase/

Status of one

bank

Read

Array

Read

Status

Read

Program

Erase

Protect

Program

Erase

ID/CFI

Suspend Suspend Unprotect

Resume

Idle

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Yes

–

Reading

Programming

Erasing

Yes

–

Yes

–

Program

Suspended

Yes

–

Yes

Erase

Suspended

Yes

Note: 1. For detailed description of command see Table 33 and 34.

2. There is a status register for each bank; status register indicates bank state, not P/E.C. status.

3. Command must be written to an address within the block targeted by that command.

8/51

M58MR016C, M58MR016D

Figure 4. Single Synchronous Read Sequence (RSIG, RCFI, RSR instructions)

K

L

A19-A16

ADQ15-ADQ0

VALID ADDRESS

CONF. CODE 2

VALID ADDRESS

CONFIGURATION CODE 3

VALID DATA NOT VALID

NOT VALID

VALID ADDRESS

VALID DATA NOT VALID

CONFIGURATION CODE 4

VALID ADDRESS

VALID DATA NOT VALID

AI05231

Both Chip Enable E and Output Enable G must be

5ns typical on E, W and G signals do not start a

write cycle. Write operations are asynchronous

and clock is ignored during write.

Dual Bank Operations. The Dual Bank allows to

run different operations simultaneously in the two

banks. It is possible to read array data from one

bank while the other is programming, erasing or

reading any data (CFI, status register or electronic

signature).

Read and write cycles can be initiated for simulta-

neous operations in different banks without any

delay. Only one bank at a time is allowed to be in

program or erase mode, while the other must be in

one of the read modes (see Table 8).

at V in order to read the output of the memory.

IL

Read array is the default state of the device when

exiting power down or after power up.

Burst Read. The device also supports a burst

read. In this mode a burst sequence is started at

the first clock edge (rising or falling according to

configuration settings) after the falling edge of L.

After a configurable delay of 2 to 5 clock cycles a

new data is output at each clock cycle. The burst

sequence may be configured for linear or inter-

leaved order and for a length of 4, 8 words or for

continuous burst mode. Wrap and no-wrap modes

are also supported.

A WAIT signal may be asserted to indicate to the

system that an output delay will occur. This delay

will depend on the starting address of the burst se-

quence; the worst case delay will occur when the

sequence is crossing a 64 word boundary and the

starting address was at the end of a four word

boundary. See the Write Read Configuration Reg-

ister (CR) Instruction for more details on all the

possible settings for the synchronous burst read

(see Table 14). It is possible to perform burst read

across bank boundary (all banks in read array

mode).

Commands must be written to an address within

the block targeted by that command.

Output Disable. The data outputs are high im-

pedance when the Output Enable G is at V with

IH

Write Enable W at V .

IH

Standby. The memory is in standby when Chip

Enable E is at V and the P/E.C. is idle. The pow-

IH

er consumption is reduced to the standby level

and the outputs are high impedance, independent

of the Output Enable G or Write Enable W inputs.

Automatic Standby. When in Read mode, after

150ns of bus inactivity and when CMOS levels are

driving the addresses, the chip automatically en-

ters a pseudo-standby mode where consumption

is reduced to the CMOS standby value, while out-

puts still drive the bus. The automatic standby fea-

ture is not available when the device is configured

for synchronous burst mode.

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch Input

Data to be programmed. A write operation is initi-

ated when Chip Enable E and Write Enable W are

at V with Output Enable G at V . Addresses are

IL

IH

latched on the rising edge of L. Commands and In-

put Data are latched on the rising edge of W or E

whichever occurs first. Noise pulses of less than

9/51

M58MR016C, M58MR016D

Table 9. Identifier Codes

Code

Address (h)

Bank Address + 00

Bank Address + 01

Data (h)

0020

Manufacturer Code

Top

88DE

88E0

0001

Device Code

Bottom

Protected and Unlocked

Unprotected and Unlocked

Protected and Locked

0000

Block Protection

Bank Address + 02

0003

Unprotected and Locked

0002

(1)

Die Revision Code

Bank Address + 03

Bank Address + 05

Bank Address + 80

DRC

(1)

Read Configuration Register

Lock Protection Register

CR

(1)

LPR

Bank Address + 81

Bank Address + 88

(1)

Protection Register

PR

Note: 1. DRC means Die Revision Code.

CR means Read Configuration Register.

LPR means Lock Protection Register.

PR means Unique Device Number and User Programmable OTP.

Reset/Power-down. The memory is in Power-

down when the Read Configuration Register is set

Block Locking. Any combination of blocks can

be temporarily protected against Program or

Erase by setting the lock register and pulling WP

for Power-down and RP is at V . The power con-

IL

sumption is reduced to the Power-down level, and

Outputs are in high impedance, independent of the

Chip Enable E, Output Enable G or Write Enable

W inputs. The memory is in reset when the Read

Configuration Register is set for Reset and RP is

at VIL. The power consumption is the same of the

standby and the outputs are in high impedance.

After a Reset/Power down the device defaults to

read array mode, the status register is set to 80h

and the read configuration register defaults to

asynchronous read.

to V . The following summarizes the locking oper-

IL

ation. All blocks are protected on power-up. They

can then be unprotected or protected with the Un-

protect and Protect commands. The Lock com-

mand protects a block and prevents it from being

unlocked when WP = 0. When WP = 1, Lock is

overridden. Lock is cleared only when the device

is reset or powered-down (see Protect instruction).

10/51

M58MR016C, M58MR016D

INSTRUCTIONS AND COMMANDS

Table 10. Commands

Eighteen instructions are available (see Tables 10

and 11) to perform Read Memory Array, Read Sta-

tus Register, Read Electronic Signature, CFI Que-

ry, Block Erase, Bank Erase, Program, Tetra Word

Program, Double Word Program, Clear Status

Register, Program/Erase Suspend, Program/

Erase Resume, Block Protect, Block Unprotect,

Block Lock, Protection Register Program, Read

Configuration Register and Lock Protection Pro-

gram.

Hex Code

00h

Command

Invalid Reset

01h

Protect Confirm

Write Read Configuration Register

Confirm

03h

10h

20h

2Fh

30h

40h

50h

55h

Alternative Program Set-up

Block Erase Set-up

Status Register output may be read at any time,

during programming or erase, to monitor the

progress of the operation.

Lock Confirm

Double Word Program Set-up

Program Set-up

An internal Command Interface (C.I.) decodes the

instructions while an internal Program/Erase Con-

troller (P/E.C.) handles all timing and verifies the

correct execution of the Program and Erase in-

structions. P/E.C. provides a Status Register

whose bits indicate operation and exit status of the

internal algorithms. The Command Interface is re-

set to Read Array when power is first applied,

Clear Status Register

Tetra Word Program Set-up

Protect Set-up and Write Read

Configuration Register

60h

70h

80h

90h

98h

B0h

Read Status Register

Bank Erase Set-up

Read Electronic Signature

CFI Query

when exiting from Reset or whenever V is lower

DD

than V

. Command sequence must be followed

LKO

exactly. Any invalid combination of commands will

reset the device to Read Array.

Read (RD)

The Read instruction consists of one write cycle

(refer to Device Operations section) and places

the addressed bank in Read Array mode. When a

device reset occurs, the memory is in Read Array

as default. A read array command will be ignored

while a bank is programming or erasing. However

in the other bank a read array command will be ac-

cepted.

Program/Erase Suspend

Protection Program and Lock Protection

Program

C0h

Program/Erase Resume, Erase Confirm

or Unprotect Confirm

D0h

FFh

Read Array

Read Status Register (RSR)

A bank’s Status Register indicates when a pro-

gram or erase operation is complete and the suc-

cess or failure of operation itself. Issue a Read

Status Register Instruction (70h) to read the Sta-

tus Register content of the addressed bank. The

status of the other bank is not affected by the com-

mand. The Read Status Register instruction may

be issued at any time, also when a Program/Erase

operation is ongoing. The following Read opera-

tions output the content of the Status Register of

the addressed bank. The Status Register is

latched on the falling edge of E or G signals, and

within the bank A. A subsequent read in the ad-

dress of bank A will output the Manufacturer Code,

the Device Code, the protection Status of Blocks

of bank A, the Die Revision Code, the Protection

Register, or the Read Configuration Register (see

Table 9).

If the first write cycle of Read Electronic Signature

instruction is issued to an address within the bank

B, a subsequent read in an address of bank B will

output the protection Status of Blocks of bank B.

The status of the other bank is not affected by the

command (see Table 8).

See Tables 5, 6, 7 and 8 for the valid address. The

Electronic Signature can be read from the memory

allowing programming equipment or applications

to automatically match their interface to the char-

acteristics of M58MR016C and M58MR016D.

can be read until E or G returns to V . Either E or

IH

G must be toggled to update the latched data.

Read Electronic Signature (RSIG)

The Read Electronic Signature instruction con-

sists of one write cycle (refer to Device Operations

section) giving the command 90h to an address

11/51

M58MR016C, M58MR016D

Table 11. Instructions

(1,2)

(3)

(1,2)

(3)

Instruction Cyc. Operation

Operation

Address

Data

Address

Data

Read Memory

Array

Read

Address

(1)

RD

1+

Write

BKA

FFh

70h

Data

Read

Read Status

Register

Status

Register

(1)

RSR

BKA

EA

BKA

Read

RSIG Electronic

Signature

(1)

1+

Write

90h

EA

ED

Read

(1)

RCFI Read CFI

1+

1

Write

CFIA

BKA

98h

50h

CFIA

CFID

Read

Clear Status

(5)

CLRS

Register

EE

BE

PG

Block Erase

Bank Erase

Program

2

Write

BA

BKA

WA

20h

80h

Write

BA

BKA

WA

D0h

WD

40h or 10h

Double Word

Program

DPG

3

Write

WA1

30h

55h

Write

WA1

WA2

WA1

WD1

WD2

WD1

Tetra Word

Program

TPG

5

Write

WA1

Write

WA2

WA3

WA4

WD2

WD3

WD4

Program

PES Erase

Suspend

1

Write

BKA

B0h

D0h

Program

PER Erase

Resume

BP

BU

BL

Block Protect

2

Write

BA

60h

Write

BA

01h

D0h

2Fh

Block

Unprotect

Block Lock

Protection

PRP Register

Program

2

Write

PA

C0h

60h

Write

PA

PD

LPD

03h

Lock Protec-

LPRP tion Register

Program

LPA

RCA

LPA

RCA

Write Read

CR

Configuration

Register

Note: 1. First cycle command address should be the same as the operation’s target address. The first cycle of the RD, RSR, RSIG or RCFI

instruction is followed by read operations in the bank array or special register. Any number of read cycles can occur after one com-

mand cycle.

2. BKA = Address within the bank, BA = Block Address, EA = Electronic Signature Address, CFIA = Common Flash Interface Address;

WA = Word Address, PA = Protection Register Address, LPA = Lock Protection Register Address, RCA = Read Configuration Reg-

ister Address, PD = Protection Data, CFID = Common Flash Interface Data, ED = Electronic Signature Data, WD = Word Data, LPD

= Lock protection Register Data

3. WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0.

4. Read cycle after CLSR instruction will output the memory array.

12/51

M58MR016C, M58MR016D

CFI Query (RCFI)

the erase by the P/E.C., the bank with the block in

erase accepts only the RSR (Read Status Regis-

ter) and PES (Program/Erase Suspend) instruc-

tions. See figure 19 for Erase Flowchart and

Pseudo Code.

The CFI Query Mode is associated to bank A. The

address of the first write cycle must be within the

bank A. The status of the other bank is not affected

by the command (see Table 8). Writing 98h the de-

vice enters the Common Flash Interface Query

mode. Next read operations in the bank A will read

the CFI data. Write a read instruction to return to

Read mode (refer to the Common Flash Interface

section).

Bank Erase (BE)

Bank erase sets all the bits within the selected

bank to ’1’. It is not necessary to pre-program the

block as the P/E.C. will do it automatically before

erasing.

Clear Status Register (CLSR)

This instruction uses two writes cycles. The first

command written is the Bank Erase set-up com-

mand 80h. The second command is the Erase

Confirm command D0h. An address within the

bank to be erased should be given to the memory

during the two cycles command. See the Block

Erase command section for status register bit de-

tails.

The Clear Status Register uses a single write op-

eration, which resets bits b1, b3, b4 e b5 of the sta-

tus register. The Clear Status Register is executed

writing the command 50h independently of the ap-

plied V voltage. After executing this command

PP

the device returns to read array mode. The Clear

Status Register command clears only the status

register of the addressed bank.

Program (PG)

Block Erase (EE)

The Program instruction programs the array on a

word-by-word basis. The first command must be

given to the target block and only one partition can

be programmed at a time; the other partition must

be in one of the read modes or in the erase sus-

pended mode (see Table 8).

This instruction uses two write cycles. The first

command written is the Program Set-up command

40h (or 10h). A second write operation latches the

Address and the Data to be written and starts the

P/E.C.

Block erasure sets all the bits within the selected

block to ’1’. One block at a time can be erased. It

is not necessary to pre-program the block as the

P/E.C. will do it automatically before erasing. This

instruction use two writes cycles. The first com-

mand written is the Block Erase Set up command

20h. The second command is the Erase Confirm

command D0h. An address within the block to be

erased should be given to the memory during the

two cycles command. If the second command giv-

en is not an erase confirm, the status register bits

b4 and b5 are set and the instruction aborts.

After writing the command, the device outputs sta-

tus register data when any address within the bank

is read. At the end of the operation the bank will re-

main in read status register until a read array com-

mand is written.

Read operations in the targeted bank output the

Status Register content after the programming

has started.

The Status Register bit b7 returns '0' while the pro-

gramming is in progress and '1' when it has com-

pleted. After completion the Status register bit b4

returns '1' if there has been a Program Failure (see

Table 12). Status register bit b1 returns '1' if the

user is attempting to program a protected block.

Status Register bit b7 is ’0’ while the erasure is in

progress and ’1’ when it has completed. After com-

pletion the Status Register bit b5 returns ’1’ if there

has been an Erase Failure. Status register bit b1

returns ’1’ if the user is attempting to erase a pro-

tected block. Status Register bit b3 returns a ’1’ if

Status Register bit b3 returns a '1' if V is below

PP

V

. Any attempt to write a ’1’ to an already pro-

PPLK

grammed bit will result in a program fail (status

register bit b4 set) if V = V and will be ig-

PP

PPH

V

is below V

. Erase aborts if RP turns to

PP

PPLK

nored if V = V

.

PP

PP1

V . As data integrity cannot be guaranteed when

IL

Programming aborts if RP goes to V . As data in-

IL

the erase operation is aborted, the erase must be

repeated (see Table 12). A Clear Status Register

instruction must be issued to reset b1, b3, b4 and

b5 of the Status Register. During the execution of

tegrity cannot be guaranteed when the program

operation is aborted, the block containing the

memory location must be erased and repro-

grammed. A Clear Status Register instruction

13/51

M58MR016C, M58MR016D

Table 12. Status Register Bits

Logic

Level

Mnemonic

P/ECS

Bit

Name

Definition

Ready

Note

7

P/ECS

Status

1

0

Indicates the P/E.C. status, check during

Program or Erase, and on completion before

checking bits b4 or b5 for Program or Erase

Success.

Busy

ESS

6

Erase

Suspend

Status

1

Suspended

On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’ until

an Erase Resume instruction is given.

In Progress or

Completed

0

ES

PS

5

4

Erase

Status

1

0

1

Erase Error

ES bit is set to ’1’ if P/E.C. has applied the

maximum number of erase pulses to the block

without achieving an erase verify.

Erase Success

Program Error

Program

Status

PS bit set to ’1’ if the P/E.C. has failed to

program a word.

Program

Success

0

1

VPPS

3

V

PP

Status

V

Invalid,

VPPS bit is set if the V voltage is below

PP

Abort

V

when a Program or Erase instruction is

PPLK

executed. V is sampled only at the beginning

of the erase/program operation.

PP

V

OK

0

1

PP

PSS

BPS

2

1

Program

Suspend

Status

Suspended

On a program Suspend instruction P/ECS and

PSS bits are set to ’1’. PSS remains ’1’ until a

Program Resume Instruction is given.

In Progress or

Completed

0

1

0

Block

Program/Erase

on protected

Block, Abort

Protection

Status

BPS bit is set to ’1’ if a Program or Erase

operation has been attempted on a protected

block.

No operation to

protected blocks

0

Reserved

Note: Logic level ’1’ is V and ’0’ is V .

IH

IL

must be issued to reset b5, b4, b3 and b1 of the

Status Register.

These instruction uses three write cycles. The first

command written is the Double Word Program

Set-Up command 30h. A second write operation

latches the Address and the Data of the first word

to be written, the third write operation latches the

Address and the Data of the second word to be

written and starts the P/E.C. (see Table 11).

During the execution of the program by the P/E.C.,

the bank in programming accepts only the RSR

(Read Status Register) and PES (Program/Erase

Suspend) instructions. See Figure 16 for Program

Flowchart and Pseudo Code.

Read operations in the targeted bank output the

Status Register content after the programming

has started. The Status Register bit b7 returns ’0’

while the programming is in progress and ’1’ when

it has completed. After completion the Status reg-

ister bit b4 returns ’1’ if there has been a Program

Failure. Status register bit b1 returns ’1’ if the user

is attempting to program a protected block. Status

Double Word Program (DPG)

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel. The first command must be given to the

target block and only one partition can be pro-

grammed at a time; the other partition must be in

one of the read modes or in the erase suspended

mode (see Table 8).

Register bit b3 returns a ’1’ if V is below V

.

PP

PPLK

The two words must differ only for the address A0.

Programming should not be attempted when V

Any attempt to write a ’1’ to an already pro-

grammed bit will result in a program fail (status

register bit b4 set). (See Table 12).

PP

is not at V

. The operation can also be executed

PPH

if V is below V

but result could be uncertain.

PP

PPH

14/51

M58MR016C, M58MR016D

Figure 5. Security Block Memory Map

88h

User Programmable OTP

85h

84h

Parameter Block # 0

Unique device number

81h

80h

Protection Register Lock

2

1

0

AI05232

(1)

Table 13. Protection States

(3)

(2)

Next State After Event

Program/Erase

Allowed

Current State

(WP, DQ1, DQ0)

Protect

101

Unprotect

100

Lock

111

WP transition

100

101

110

111

000

001

Yes

No

000

001

011

100

101

100

111

011

Yes

No

111

110

111

110

Yes

No

001

000

001

000

(4)

011

No

011

111 or 110

Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status.

2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect in and by

DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = V

IH

and A0 = V .

IL

3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed

its logic value.

4. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

15/51

M58MR016C, M58MR016D

Programming aborts if RP goes to V . As data in-

lows read in another block within the targeted bank

or program in the other block.

IL

tegrity cannot be guaranteed when the program

operation is aborted, the memory location must be

erased and reprogrammed. A Clear Status Regis-

ter instruction must be issued to reset b5, b4, b3

and b1 of the Status Register. During the execu-

tion of the program by the P/E.C., the bank in pro-

gramming accepts only the RSR (Read Status

Register) instruction. See Figure 17 for Double

Word Program Flowchart and Pseudo code.

This instruction uses one write cycle B0h and the

address should be within the bank with the block

in erase (see Table 11). The device continues to

output status register data after the erase suspend

is issued. The status register bit b7 and bit b6 are

set to ’1’ then the erase operation has been sus-

pended. Bit b6 is set to '0' in case the erase is com-

pleted or in progress (see Table 12).

Tetra Word Program (TPG)

The valid commands while erase is suspended

are: Program/Erase Resume, Program, Read

Memory Array, Read Status Register, Read Elec-

tronic Signature, CFI Query, Block Protect, Block

Unprotect and Block Lock. The user can protect

the Block being erased issuing the Block Protect

or Block Lock commands.

This feature is offered to improve the programming

throughput, writing a page of four adjacent words

in parallel. The first command must be given to the

target block and only one partition can be pro-

grammed at a time; the other partition must be in

one of the read modes or in the erase suspended

mode (see Table 8).

During a block erase suspend, the device goes

The four words must differ only for the addresses

A0 and A1. Programming should not be attempted

into standby mode by taking E to V , which reduc-

es active current draw. Erase is aborted if RP turns

IH

when V is not at V

. The operation can also

to V .

PP

PPH

IL

be executed if V is below V

but result could

PP

PPH

If an Erase Suspend instruction was previously ex-

ecuted, the erase operation may be resumed by

issuing the command D0h using an address within

the suspended bank. The status register bit b6 and

bit b7 are cleared when erase resumes and read

operations output the status register after the

erase is resumed. Block erase cannot resume until

program operations initiated during block erase

suspend have completed. It is also possible to

nest suspends as follows: suspend erase in the

first partition, start programming in the second or

in the same partition, suspend programming and

then read from the second or the same partition.

The suggested flowchart for erase suspend/re-

sume features of the memory is shown from Fig-

ure 20.

be uncertain. These instruction uses five write cy-

cles. The first command written is the Tetra Word

Program Set-Up command 55h. A second write

operation latches the Address and the Data of the

first word to be written, the third write operation

latches the Address and the Data of the second

word to be written, the fourth write operation latch-

es the Address and the Data of the third word to be

written, the fifth write operation latches the Ad-

dress and the Data of the fourth word to be written

and starts the P/E.C. (see Table 11).

Read operations in the targeted bank output the

Status Register content after the programming

has started. The Status Register bit b7 returns ’0’

while the programming is in progress and ’1’ when

it has completed. After completion the Status reg-

ister bit b4 returns ’1’ if there has been a Program

Failure. Status register bit b1 returns ’1’ if the user

is attempting to program a protected block. Status

Program Suspend/Resume (PES/PER)

Program suspend is accepted only during the Pro-

gram instruction execution. When a Program Sus-

pend command is written to the C.I., the P/E.C.

freezes the Program operation.

Program Resume (PER) continues the Program

operation. Program Suspend (PES) consists of

writing the command B0h and the address should

be within the bank with the word in programming

(see Table 11).

The Status Register bit b2 is set to '1' (within 5µs)

when the program has been suspended. Bit b2 is

set to '0' in case the program is completed or in

progress (see Table 12).

The valid commands while program is suspended

are: Program/Erase Resume, Read Array, Read

Status Register, Read Electronic Signature, CFI

Query. During program suspend mode, the device

Register bit b3 returns a ’1’ if V is below V

.

PP

PPLK

Any attempt to write a ’1’ to an already pro-

grammed bit will result in a program fail (status

register bit b4 set). (See Table 12).

Programming aborts if RP goes to V . As data in-

IL

tegrity cannot be guaranteed when the program

operation is aborted, the memory location must be

erased and reprogrammed. A Clear Status Regis-

ter instruction must be issued to reset b5, b4, b3

and b1 of the Status Register. During the execu-

tion of the program by the P/E.C., the bank in pro-

gramming accepts only the RSR (Read Status

Register) instruction. See Figure 17 for Tetra Word

Program Flowchart and Pseudo code.

Erase Suspend/Resume (PES/PER)

The Erase Suspend freezes, after a certain laten-

cy period (within 25us), the erase operation and al-

goes in standby mode by taking E to V . This re-

IH

16/51

M58MR016C, M58MR016D

duces active current consumption. Program is

– when WP is at V , the Lock status is overridden

IH

aborted if RP turns to V .

and all blocks can be protected or unprotected;

IL

If a Program Suspend instruction was previously

executed, the Program operation may be resumed

by issuing the command D0h using an address

within the suspended bank (see Table 11). The

status register bit b2 and bit b7 are cleared when

program resumes and read operations output the

status register after the erase is resumed (see Ta-

ble 12). The suggested flowchart for program sus-

pend/resume features of the memory is shown

from Figure 18.

– when WP is at V , Lock status is enabled; the

IL

locked blocks are protected, regardless of their

previous protect state, and protection status

cannot be changed. Blocks that are not locked

can still change their protection status;

– the lock status is cleared for all blocks at power

up.

The protection and lock status can be monitored

for each block using the Read Electronic Signature

(RSIG) instruction. Protected blocks will output a

'1' on DQ0 and locked blocks will output a '1' in

DQ1 (see Table 13).

Block Protect (BP)

The BP instruction use two write cycles. The first

command written is the protection set-up 60h. The

second command is block Protect command 01h,

written to an address within the block to be protect-

ed (see Table 11). If the second command is not

recognized by the C.I the bit 4 and bit 5 of the sta-

tus register will be set to indicate a wrong se-

quence of commands (see Table 12). To read the

status register write the RSR command.

PROTECTION REGISTER PROGRAM (PRP)

and LOCK PROTECTION REGISTER

PROGRAM (LPRP)

The M58MR016C/M58MR016D features a 128-bit

protection register and a security Block in order to

increase the protection of a system design. The

Protection Register is divided in two 64-bit seg-

ments. The first segment (81h to 84h) is a unique

device number, while the second one (85h to 88h)

can be programmed by the user. When shipped

the user programmable segment is read at '1'. It

can be only programmed at '0'.

Block Unprotect (BU)

The instruction use two write cycles. The first com-

mand written is the protection set-up 60h. The sec-

ond command is block Unprotect command D0h,

written to an address within the block to be protect-

ed (see Table 11). If the second command is not

recognized by the C.I the bit 4 and bit 5 of the sta-

tus register will be set to indicate a wrong se-

quence of commands (see Table 12). To read the

status register write the RSR command.

The user programmable segment can be protect-

ed writing the bit 1 of the Protection Lock register

(80h). The bit 1 protects also the bit 2 of the Pro-

tection Lock Register.

The M58MR016C/M58MR016D feature a security

Block. The security Block is located at 0FF000-

0FFFFF (M58MR016C) or at 000000-000FFF

(M58MR016D) of the device. This block can be

permanently protected by the user programming

the bit 2 of the Protection Lock Register (see Fig-

ure 5).

The protection Register and the Protection Lock

Register can be read using the RSIG and RCFI in-

structions. A subsequent read in the address start-

ing from 80h to 88h, the user will retrieve

respectively the Protection Lock register, the

unique device number segment and the OTP user

programmable register segment (see Table 23).

Block Lock (BL)

The instruction use two write cycles. The first com-

mand written is the protection set-up 60h. The sec-

ond command is block Lock command 2Fh,

written to an address within the block to be protect-

ed (see Table 11). If the second command is not

recognized by the C.I the bit 4 and bit 5 of the sta-

tus register will be set to indicate a wrong se-

quence of commands. To read the status register

write the RSR command (see Table 12).

BLOCK PROTECTION

The M58MR016C/M58MR016D provide a flexible

protection of all the memory providing the protec-

tion, un-protection and locking of any blocks. All

blocks are protected at power-up. Each block of

the array has two levels of protection against pro-

gramming or erasing operation. The first level is

set by the Block Protect instruction; a protected

block cannot be programmed or erased until a

Block Unprotect instruction is given for that block.

A second level of protection is set by the Block

Lock instruction, and requires the use of the WP

pin, according to the following scheme:

WRITE READ CONFIGURATION REGISTER

(CR).

This instruction uses two Coded Cycles, the first

write cycle is the write Read Configuration Regis-

ter set-up 60h, the second write cycle is write

Read Configuration Register confirm 03h both to

Read Configuration Register address (see Table

11).

This instruction writes the contents of address bits

ADQ15-ADQ0 to bits CR15-CR0 of the Read Con-

17/51

M58MR016C, M58MR016D

figuration Register (A19-A16 are don’t care). At

Power-up the Read Configuration Register is set

to asynchronous Read mode, Power-down dis-

abled and bus invert (power save function) dis-

abled. A description of the effects of each

configuration bit is given in Table 14.

Read mode (CR15). The device supports an

asynchronous page mode and a synchronous

burst mode. In asynchronous page mode, the de-

fault at power-up, data is internally read and stored

in a buffer of 4 words selected by ADQ0 and ADQ1

address inputs. In synchronous burst mode, the

device latches the starting address and then out-

puts a sequence of data that depends on the Read

Configuration Register settings (see Figures 10,

11 and 12).

uration bit determines if WAIT will be asserted one

clock cycle before the wait state or during the wait

state (see Figure 7). WAIT is asserted during a

continuous burst and also during a 4 or 8 burst

length if no-wrap configuration is selected.

Burst order configuration (CR7) and Burst

Wrap configuration (CR3). See Table 16 for

burst order and length.

Clock configuration (CR6). In burst mode deter-

mines if address is latched and data is output on

the rising or falling edge of the clock.

Burst length (CR2-CR0). In burst mode deter-

mines the number of words output by the memory.

It is possible to have 4 words, 8 words or a contin-

uous burst mode, in which all the words are read

sequentially. In continuous burst mode the burst

sequence can cross the end of each of the two

banks (all banks in read array mode). In continu-

ous burst mode or in 4, 8 words no-wrap it may

happen that the memory will stop the data output

flow for a few clock cycles; this event is signaled by

WAIT going low until the output flow is resumed.

The initial address determines if the output delay

will occur as well as its duration. If the starting ad-

dress is aligned to a four words boundary no wait

states will be needed. If the starting address is

shifted by 1,2 or 3 positions from the four word

boundary, WAIT will be asserted for 1, 2 or 3 clock

cycles when the burst sequence is crossing the

first 64 word boundary. WAIT will be asserted only

once during a continuous burst access. See also

Table 16.

Synchronous burst mode is supported in both pa-

rameter and main blocks; it is also possible to per-

form burst mode read across the banks.

Bus Invert configuration (CR14). This register

bit is used to enable the BINV pin functionality.

BINV functionality depends upon configuration

bits CR14 and CR15 (see Table 14 for configura-

tion bits definition) as shown in Table 15. As output

pin BINV is active only when enabled (CR14 = 1)

in Read Array burst mode (CR15 = 0). As input pin

BINV is active only when enabled (CR14 = 1).

BINV is ignored when ADQ0-ADQ15 lines are

used as address inputs (addresses must not be in-

verted).

X-Latency (CR13-CR11). These

configuration

bits define the number of clock cycles elapsing

from L going low to valid data available in burst

mode (see Figure 6). The correspondence be-

tween X-Latency settings and the maximum sus-

tainable frequency must be calculated taking into

account some system parameters.

Two conditions must be satisfied:

– (n + 2) t ≥ t

t

+ t

AVK_CPU

K

ACC + QVK_CPU

– t > t

+ t

QVK_CPU

K

KQV

where "n" is the chosen X-Latency configuration

code, t is the clock period, t is the ad-

K

AVK_CPU

dress setup time guaranteed by the system CPU,

and t is the data setup time required by

QVK_CPU

the system CPU.

Power-down configuration (CR10). The RP pin

may be configured to give very low power con-

sumption when driven low (power-down state). In

power-down the I supply current is reduced to a

CC

typical figure of I

; if this function is disabled

CC2

(default at power-up) the RP pin causes only a re-

set of the device and the supply current is the

stand-by value. The recovery time after a RP pulse

is significantly longer when power-down is en-

abled (see Table 31).

Wait configuration (CR8). In burst mode WAIT

indicates whether the data on the output bus are

valid or a wait state must be inserted. The config-

18/51

M58MR016C, M58MR016D

(1)

Table 14. Read Configuration Register (AS and Read CFI instructions)

Configuration Register

Function

Read mode

0 = Synchronous Burst mode read

CR15

1 = Asynchronous Page mode read (default)

Bus Invert configuration (power save)

0 = disabled (default)

CR14

1 = enabled

X-Latency

010 = 2 clock latency

011 = 3 clock latency

100 = 4 clock latency

101 = 5 clock latency

111 = reserved

CR13-CR11

Other configurations reserved

Power-down configuration

0 = power-down disabled (default)

1 = power-down enabled

CR10

CR9

CR8

Reserved

Wait configuration

0 = WAIT is active during wait state

1 = WAIT is active one data cycle before wait state (default)

Burst order configuration

0 = Interleaved

CR7

1 = Linear (default)

Clock configuration

CR6

CR5-CR4

CR3

0 = Address latched and data output on the falling clock edge

1 = Address latched and data output on the rising clock edge (default)

Reserved

Burst Wrap

0 = burst wrap within burst length set by CR2-CR0

1 = Don’t wrap accesses within burst length set by CR2-CR0 (default)

Burst length

001 = 4 word burst length

010 = 8 word burst length

111 = Continuous burst mode (requires CR7 = 1)

CR2-CR0

Note: 1. The RCR can be read via the RSIG command (90h). Bank A Address + 05h contains the RCR data. See Table 9.

2. All the bits in the RCR are set to default on device power-up or reset.

Table 15. BINV Configuration Bits

BINV

CR15

CR14

IN

X

OUT

0

1

0

1

0

1

0

Active

X

Active

0

Active

19/51

M58MR016C, M58MR016D

POWER CONSUMPTION

Power-down

rising edge of W. At Power-up the device is config-

ured as:

The memory provides Reset/Power-down control

input RP. The Power-down function can be acti-

vated only if the relevant Read Configuration Reg-

ister bit is set to ’1’. In this case, when the RP

– Page mode: (CR15 = 1)

– Power-down disabled: (CR10 = 0)

– BINV disabled: (CR14 = 0).

All blocks are protected and unlocked.

signal is pulled at V the supply current drops to

SS

typically I

(see Table 26), the memory is dese-

V

, V

and V are independent power sup-

DDQ PP

CC2

DD

lected and the outputs are in high impedance. If

RP is pulled to V during a Program or Erase op-

eration, this operation is aborted and the memory

content is no longer valid (see Reset/Power-down

input description).

plies and can be biased in any order.

SS

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

have the V

itor close to the V , V

rails decoupled with a 0.1µF capac-

DD

Power-up

and V pins. The PCB

DD DDQ

SS

The memory Command Interface is reset on Pow-

er-up to Read Array. Either E or W must be tied to

trace widths should be sufficient to carry the re-

quired V program and erase currents.

DD

V

during Power-up to allow maximum security

IH

and the possibility to write a command on the first

Figure 6. X-Latency Configuration Sequence

K

L

A19-A16

VALID ADDRESS

CONF. CODE 2

VALID ADDRESS

CONFIGURATION CODE 3

ADQ15-ADQ0

VALID DATA VALID DATA VALID DATA VALID DATA

VALID ADDRESS

VALID DATA VALID DATA VALID DATA

CONFIGURATION CODE 4

VALID ADDRESS

VALID DATA VALID DATA

AI05233

20/51

M58MR016C, M58MR016D

Figure 7. Wait Configuration Sequence

K

L

A19-A16

VALID ADDRESS

ADQ15-ADQ0

VALID DATA VALID DATA NOT VALID VALID DATA

WAIT

CR8 = '0'

WAIT

CR8 = '1'

AI05234

21/51

M58MR016C, M58MR016D

COMMON FLASH INTERFACE (CFI)

Tables 17, 18, 19, 20, 21, 22 and 23 show the ad-

dress used to retrieve each data. The CFI data

structure gives information on the device, such as

the sectorization, the command set and some

electrical specifications. The CFI data structure

contains also a security area; in this section, a 64

bit unique security number is written, starting at

address 81h. This area can be accessed only in

read mode and there are no ways of changing the

code after it has been written by ST. Write a read

instruction to return to Read mode (see Table 11).

Refer to the CFI Query instruction to understand

how the M58MR016 enters the CFI Query mode.

The Common Flash Interface (CFI) specification is

a JEDEC approved, standardized data structure

that can be read from the Flash memory device.

CFI allows a system software to query the flash

device to determine various electrical and timing

parameters, density information and functions

supported by the device. CFI allows the system to

easily interface to the Flash memory, to learn

about its features and parameters, enabling the

software to configure itself when necessary.

Table 17. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Security Code Area

Additional information specific to the Alternate

Algorithm (optional)

Lock Protection Register, Unique device Number

and User Programmable OTP

80h

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 18, 19, 20, 21, 22 and 23. Query data are always presented on the lowest order data outputs.

Table 18. CFI Query Identification String

Offset

Sub-section Name

Description

Value

00h

0020h

Manufacturer Code

Device Code

ST

88DEh

88E0h

Top

Bottom

01h

02h

03h

reserved

Reserved

(1)

Die Revision Code

Reserved

DRC

04h-0Fh

10h

reserved

0051h

"Q"

"R"

"Y"

11h

0052h

Query Unique ASCII String "QRY"

12h

0059h

13h

0002h

Primary Algorithm Command Set and Control Interface ID code 16

bit ID code defining a specific algorithm

14h

0000h

15h

offset = P = 0039h

0000h

Address for Primary Algorithm extended Query table (see Table 20)

p = 39h

NA

16h

17h

0000h

Alternate Vendor Command Set and Control Interface ID Code

second vendor - specified algorithm supported ( 0000h means none

exists)

18h

0000h

19h

1Ah

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

(0000h means none exists)

NA

Note: Query data are always presented on the lowest - order data outputs (ADQ0-ADQ7) only. ADQ8-ADQ15 are ‘0’.

1. DRC means Die Revision Code.

23/51

M58MR016C, M58MR016D

Table 19. CFI Query System Interface Information

Offset

Data

Description

Value

V

DD

V

DD

V

PP

V

PP

Logic Supply Minimum Program/Erase or Write voltage

1Bh

0017h

1.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0020h

0017h

00C0h

2V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 millivolts

[Programming] Supply Minimum Program/Erase voltage

1.7V

12V

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 millivolts

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

0000h

0004h

0000h

16µs

1s

Typical timeout per single byte/word program = 2 µs

n

Typical timeout for tetra word program = 2 µs

n

Typical timeout per individual block erase = 2 ms

n

NA

Typical timeout for full chip erase = 2 ms

n

512µs

16s

Maximum timeout for word program = 2 times typical

n

Maximum timeout for tetra word = 2 times typical

n

Maximum timeout per individual block erase = 2 times typical

n

NA

Maximum timeout for chip erase = 2 times typical

24/51

M58MR016C, M58MR016D

Table 20. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0015h

2 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0003h

0000h

n

8 Byte

3

Maximum number of bytes in multi-byte program or page = 2

2Ch

0003h

Number of Erase Block Regions within the device

bit 7 to 0 = x = number of Erase Block Regions

It specifies the number of regions within the device containing one or more

contiguous Erase Blocks of the same size.

2Dh

2Eh

0017h

0000h

Region 1 Information (main block - Bank B)

Number of identical-size erase block = 002Fh+1

24

64 KByte

7

2Fh

30h

0000h

0001h

Region 1 Information (main block - Bank B)

Block size in Region 1 = 0100h * 256 byte

31h

32h

0006h

0000h

Region 2 Information (main block - Bank A)

Number of identical-size erase block = 0006h+1

33h

34h

0000h

0001h

Region 2 Information (main block - Bank A)

Block size in Region 2 = 0100h * 256 byte

64 KByte

8

35h

36h

0007h

0000h

Region 3 Information (parameter block - Bank A)

Number of identical-size erase block = 0007h+1

37h

38h

0020h

0000h

Region 3 Information (parameter block - Bank A)

Block size in Region 3 = 0020h * 256 byte

8 KByte

8

2Dh

2Eh

0007h

0000h

Region 1 Information (parameter block - Bank A)

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information (parameter block - Bank A)

Block size in Region 1 = 0020h * 256 byte

8 KByte

7

31h

32h

0006h

0000h

Region 2 Information (main block - Bank A)

Number of identical-size erase block = 0006h+1

33h

34h

0000h

0001h

Region 2 Information (main block - Bank A)

Block size in Region 2 = 0001h * 256 byte

64 KByte

24

35h

36h

0017h

0000h

Region 3 Information (parameter block - Bank B)

Number of identical-size erase block = 002Fh+1

37h

38h

0000h

0001h

Region 3 Information (parameter block - Bank B)

Block size in Region 3 = 0001h * 256 byte

64 KByte

25/51

M58MR016C, M58MR016D

Table 21. Primary Algorithm-Specific Extended Query Table

Data

0050h

0052h

0049h

0031h

0030h

00E6h

0003h

0000h

Description

Value

"P"

"R"

"I"

Offset

(P)h = 39h

Primary Algorithm extended Query table unique ASCII string “PRI”

(P+3)h = 3Ch

(P+4)h = 3Dh

(P+5)h = 3Eh

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

Chip Erase supported

(1 = Yes, 0 = No)

No

Yes

No

(P+7)h

(P+8)h

Erase Suspend supported

Program Suspend supported

Legacy Lock/Unlock supported

Queued Erase supported

Instant individual block locking supported (1 = Yes, 0 = No)

Protection bits supported

Page mode read supported

Synchronous read supported

Simultaneous operation supported

No

Yes

(1 = Yes, 0 = No)

bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31

bit field of optional features follows at the end of the bit-30

field.

(P+9)h = 42h

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query

Yes

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

(P+A)h = 43h

(P+B)h

0003h

0000h

Block Protect Status

Defines which bits in the Block Status Register section of the Query are

implemented.

bit 0 Block protect Status Register Protect/Unprotect

bit active

(1 = Yes, 0 = No)

Yes

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

(P+C)h = 45h

(P+D)h = 46h

0018h

00C0h

0000h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

1.8V

DD

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

12V

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

(P+E)h = 47h

(P+F)h

Reserved

(P+10)h

(P+11)h

(P+12)h

26/51

M58MR016C, M58MR016D

Table 22. Burst Read Information

Data

Description

Value

Offset

(P)+13h = 48h

0003h

Page-mode read capability

bits 0-7

8 Byte

n

’n’ such that 2 HEX value represents the number of read-

page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates

no read page buffer.

(P+14)h = 49h

(P+15)h = 4Ah

0003h

0001h

Number of synchronous mode read configuration fields that follow. 00h

indicates no burst capability.

3

4

Synchronous mode read capability configuration 1

bit 3-7

bit 0-2

Reserved

n+1

’n’ such that 2

HEX value represents the maximum

number of continuous synchronous reads when the device is

configured for its maximum word width. A value of 07h

indicates that the device is capable of continuous linear bursts

that will output data until the internal burst counter reaches

the end of the device’s burstable address space. This field’s

3-bit value can be written directly to the read configuration

register bit 0-2 if the device is configured for its maximum

word width. See offset 28h for word width to determine the

burst data output width.

(P+16)h = 4Bh

(P+17)h = 4Ch

(P+18)h = 4Dh

(P+19)h = 4Eh

0002h

0007h

0028h

0001h

Synchronous mode read capability configuration 2

Synchronous mode read capability configuration 3

Max operating clock frequency (MHz)

8

Cont.

40 MHz

Supported handshaking signal (WAIT pin)

bit 0

bit 1

during synchronous read

during asynchronous read

(1 = Yes, 0 = No)

Yes

No

Table 23. Security Code Area

Offset

80h

81h

82h

83h

84h

85h

86h

87h

88h

Data

0000-0000-0000-0XX0

XXXX

Description

Lock Protection Register

XXXX

64 bits: unique device number

XXXX

64 bits: User Programmable OTP

XXXX

27/51

M58MR016C, M58MR016D

Table 24. AC Measurement Conditions

Figure 9. AC Testing Load Circuit

Input Rise and Fall Times

≤ 4ns

V

/ 2

DDQ

0 to V

Input Pulse Voltages

DDQ

1N914

V

/2

Input and Output Timing Ref. Voltages

DDQ

3.3kΩ

Figure 8. Testing Input/Output Waveforms

DEVICE

UNDER

TEST

OUT

V

DDQ

C

= 30pF

L

V

/2

DDQ

0V

C

includes JIG capacitance

L

AI05235

AI05236

(1)

Table 25. Capacitance

(T = 25 °C, f = 1 MHz)

A

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

OUT

V

OUT

12

pF

Note: 1. Sampled only, not 100% tested.

28/51

M58MR016C, M58MR016D

Table 26. DC Characteristics

(T = –40 to 85°C; V = V

= 1.7V to 2.0V)

A

DD

DDQ

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Typ

Max

±1

Unit

µA

I

0V ≤ V ≤ V

IN

LI

DDQ

I

LO

0V ≤ V

≤ V

±5

µA

OUT

DDQ

Supply Current

(Asynchronous Read Mode)

E = V , G = V , f = 6MHz

10

20

30

mA

IL

IH

I

DD1

Supply Current

(Synchronous Read Mode

Continuous Burst)

E = V , G = V , f = 40MHz

IL

IH

Supply Current

(Power-down)

I

RP = V ± 0.2V

2

10

50

20

µA

DD2

DD3

SS

E = V ± 0.2V

Supply Current (Standby)

15

10

DD

Supply Current

(Program or Erase)

Word Program, Block Erase

in progress

(1)

mA

I

DD4

Program/Erase in progress

in one Bank, Asynchronous

Read in the other Bank

20

40

mA

Supply Current

(Dual Bank)

(1)

I

DD5

Program/Erase in progress

in one Bank, Synchronous

Read in the other Bank

30

5

50

10

mA

V

Supply Current (Program

PP

I

V

PP

= 12V ± 0.6V

PP1

or Erase)

V

≤ V

CC

0.2

5

µA

V

PP

V

Supply Current (Standby

PP

I

PP2

or Read)

V

= 12V ± 0.6V

100

400

0.4

PP

V

Input Low Voltage

–0.5

IL

V

–0.4

V

+ 0.4

DDQ

Input High Voltage

V

IH

DDQ

V

I

= 100µA

OL

Output Low Voltage

Output High Voltage CMOS

0.1

V

OL

I

= –100µA

V

–0.1

–0.4

V

OH

DDQ

V

Supply Voltage

V

+ 0.4

DDQ

Program, Erase

V

PP1

PP

DDQ

Double/Tetra Word Program

11.4

12.6

1

V

PPH

V

Program or Erase Lockout

V

PPLK

Note: 1. Sampled only, not 100% tested.

2. V may be connected to 12V power supply for a total of less than 100 hrs.

PP

29/51

M58MR016C, M58MR016D

Table 27. Asynchronous Read AC Characteristics

(T = –40 to 85°C; V = V

= 1.7V to 2.0V)

A

DD

DDQ

M58MR016

Symbol

Alt

Parameter

Test Condition

100

120

Unit

Min

Max

Min

Max

Address Valid to Next

Address Valid

t

E = V , G = V

100

120

ns

AVAV

RC

IL

Address valid to Latch

Enable High

t

G = V

IH

10

AVLH

AVAVDH

Address Valid to Output

Valid (Random)

t

E = V , G = V

100

45

120

45

AVQV

ACC

IL

Address Valid to Output

Valid (Page)

t

E = V , G = V

AVQV1

PAGE

IL

Chip Enable High to Output

Transition

t

G = V

0

EHQX

OH

IL

Chip Enable High to Output

Hi-Z

(1)

t

G = V

20

t

HZ

IL

EHQZ

Chip Enable Low to Latch

Enable High

t

E = V , G = V

10

ELLH

ELAVDH

IL

IH

Chip Enable Low to Output

Valid

(2)

t

G = V

100

120

t

CE

IL

ELQV

Chip Enable Low to Output

Transition

(1)

t

G = V

E = V

0

t

LZ

ELQX

Output Enable High to

Output Transition

t

GHQX

OH

Output Enable High to

Output Hi-Z

(1)

t

20

25

20

35

t

DF

GHQZ

Output Enable Low to

Output Valid

(2)

t

OE

GLQV

Output Enable Low to

Output Transition

(1)

t

0

t

OLZ

GLQX

Latch Enable High to

Address Transition

t

E = V , G = V

10

LHAX

AVDHAX

IL

IH

Latch Enable High to

Output Enable Low

t

E = V

10

ns

LHGL

IL

t

E = V , G = V

Latch Enable Pulse Width

LLLH

AVDLAVDH

IL

IH

Latch Enable Low to

Output Valid (Random)

t

E = V

100

45

120

45

LLQV

AVDLQV

IL

Latch Enable Low to

Output Valid (Page)

t

E = V

ns

LLQV1

IL

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV

ELQV GLQV

30/51

M58MR016C, M58MR016D

Figure 10. Asynchronous Read AC Waveforms

31/51

M58MR016C, M58MR016D

Figure 11. Page Read AC Waveforms

32/51

M58MR016C, M58MR016D

Table 28. Synchronous Burst Read AC Characteristics

(T = –40 to 85°C; V = V

= 1.7V to 2.0V)

A

DD

DDQ

M58MR016

Symbol

Alt

Parameter

Test Condition

100

120

Unit

Min

7

Max

Min

7

Max

t

AVCLKH

Address Valid to Clock

Chip Enable Low to Clock

Clock Period

ns

AVK

t

CELCLKH

7

ELK

t

25

13

5

25

13

5

K

CLK

t

E = V , G = V

IH

Clock to Address Transition

Clock High

KAX

CLKHAX

IL

t

KHKL

CLKHCLKL

t

Clock Low

5

KLKH

CLKLCLKH

Clock to Data Valid

Clock to BINV Valid

Clock to WAIT Valid

t

E = V , G = V

20

ns

KQV

CLKHQV

IL

Clock to Output Transition

Clock to BINV Transition

Clock to WAIT Transition

t

E = V

4

KQX

CLKHQX

IL

Latch Enable High to

Address transition

t

13

7

13

7

ns

LHAX

ADVHAX

t

Latch Enable Low to Clock

LLK

AVDLCLKH

33/51

M58MR016C, M58MR016D

Figure 12. Synchronous Burst Read

34/51

M58MR016C, M58MR016D

Table 29. Write AC Characteristics, Write Enable Controlled

(T = –40 to 85 °C; V = V

= 1.7V to 2.0V)

A

DD

DDQ

M58MR016

Symbol

Alt

Parameter

100

120

Unit

Min

100

10

40

10

0

Max

Min

120

10

40

10

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Latch Enable High

Input Valid to Write Enable High

ns

µs

ns

AVAV

t

AVLH

t

DVWH

DS

t

Chip Enable Low to Latch Enable High

Chip Enable Low to Write Enable Low

Output Enable High to Latch Enable Low

Output Enable High to Write Enable Low

Latch Enable High to Address Transition

Latch Enable High to Write Enable High

Latch Enable Pulse Width

ELLH

t

ELWL

CS

t

20

10

50

200

0

20

10

50

200

0

GHLL

t

GHWL

t

LHAX

t

LHWH

t

LLLH

t

V

DD

High to Chip Enable Low

VDHEL

VCS

t

V

PP

High to Write Enable High

VPPHWH

t

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Output Enable Low

Write Enable High to Latch Enable Low

WHDX

DH

t

0

WHEH

CH

t

0

WHGL

OEH

t

0

WHLL

t

Write Enable High to V Low

200

30

200

50

200

30

200

50

200

WHVPPL

PP

t

Write Enable High to Write Enable Low

Write Enable High to Write Protect Valid

Write Enable Low to Write Enable High

Write Protect Valid to Write Enable High

WHWL

WPH

t

WHWPV

t

WLWH

WP

t

WPVWH

35/51

M58MR016C, M58MR016D

Figure 13. Write AC Waveforms, W Controlled

36/51

M58MR016C, M58MR016D

Table 30. Write AC Characteristics, Chip Enable Controlled

(T = –40 to 85 °C; V = V

= 1.7V to 2.0V)

A

DD

DDQ

M58MR016

Symbol

Alt

Parameter

100

120

Unit

Min

100

10

40

0

Max

Min

120

10

40

0

Max

t

WC

Address Valid to Next Address Valid

Address Valid to Latch Enable High

Input Valid to Chip Enable High

ns

µs

ns

AVAV

t

AVLH

t

DVEH

DS

t

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Chip Enable High

Chip Enable Low to Latch Enable High

Output Enable High to Latch Enable Low

Latch Enable High to Address Transition

Latch Enable High to Chip Enable High

Latch Enable Pulse Width

EHDX

DH

t

CPH

30

0

30

0

EHEL

t

WH

EHWH

t

CP

60

10

20

10

50

200

0

60

10

20

10

50

200

0

ELEH

t

ELLH

t

GHLL

t

LHAX

t

LHEH

t

LLLH

t

V

DD

High to Chip Enable Low

VDHEL

VCS

t

V

PP

High to Chip Enable High

VPPHEH

t

Chip Enable High to V Low

EHVPPL

PP

t

Chip Enable High to Write Protect Valid

Chip Enable Low to Chip Enable Low

Write Protect Valid to Chip Enable High

EHWPV

t

WS

WLEL

t

200

WPVEH

37/51

M58MR016C, M58MR016D

Figure 14. Write AC Waveforms, E Controlled

38/51

M58MR016C, M58MR016D

Figure 15. Reset and Power-up AC Waveforms

L, W, E, G

tPHWL

tPHEL

tPHGL

tPHWL

tPHEL

tPHGL

RP

tVDHPH

tPLPH

V

, V

DD DDQ

Power-up

AI05242

Table 31. Reset and Power-up AC Characteristics

Symbol

Parameter

Test Condition

Min

100

50

Unit

ns

(1,2)

RP Pulse Width

t

PLPH

t

During Program and Erase

µs

PHEL

t

Reset High to Device Enabled

PHLL

Other Conditions

30

50

ns

µs

t

PHWL

(3)

Supply Valid to Reset High

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during Power-up or System reset.

Table 32. Program, Erase Times and Program, Erase Endurance Cycles

(T = –40 to 85°C; V = V

= 1.7V to 2.0V, V = V unless otherwise specified)

A

DD

DDQ

PP

DD

Typical after

100k W/E Cycles

(1)

Parameter

Min

Typ

Unit

Max

Parameter Block (4 K-Word) Erase (Preprogrammed)

Main Block (32 K-Word) Erase (Preprogrammed)

Bank Erase (Preprogrammed, Bank A)

2.5

10

0.5

1

3

sec

4

Bank Erase (Preprogrammed, Bank B)

15

(2)

40

20

sec

Chip Program

(2)

Chip Program (DPG, V = 12V)

PP

(3)

200

10

µs

Word Program

Double Word Program

Tetra Word Program

µs

Program/Erase Cycles (per Block)

100,000

cycles

Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or

erase should perform significantly better.

2. Excludes the time needed to execute the sequence for program instruction.

3. Same timing value if V = 12V.

PP

39/51

M58MR016C, M58MR016D

(1)

Figure 16. Program Flowchart and Pseudo Code

Start

Write 40h or 10h

Command

Program instruction:

– write 40h or 10h command

– write Address & Data

(memory enters read status state after

the Program instruction)

Write Address

& Data

do:

NO

Read Status

– read status register (E or G must be

toggled) if PES instruction given execute

suspend program loop

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

YES

while b7 = 1

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

– error handler

b3 = 0

YES

Error (1, 2)

Program

If b4 = 1, Program error:

– error handler

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI05243

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a program sequence.

2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

40/51

M58MR016C, M58MR016D

(1)

Figure 17. Double Word Program and Tetra Word Program Flowchart and Pseudo code

Start

Write 55h

Command

DPG instruction:

– write 30h command

– write Address 1 & Data 1 (3)

– write Address 2 & Data 2 (3)

(memory enters read status state after

the Program instruction)

Write Address 1

& Data 1

Write Address 2

& Data 2

TPG instruction:

– write 55h command

Write Address 3

& Data 3

– write Address 1 & Data 1 (4)

– write Address 2 & Data 2 (4)

– write Address 3 & Data 3 (4)

– write Address 4 & Data 4 (4)

(memory enters read status state after

the Program instruction)

Write Address 4

& Data 4

do:

NO

– read status register (E or G must be

toggled) if PES instruction given execute

suspend program loop

Read Status

Register

Suspend

YES

NO

while b7 = 1

Suspend

Loop

b7 = 1

YES

If b3 = 1, V

invalid error:

V

Invalid

Error (1, 2)

PP

– error handler

PP

b3 = 0

YES

Program

Error (1, 2)

If b4 = 1, Program error:

– error handler

b4 = 0

YES

Program to Protected

Block Error (1, 2)

If b1 = 1, Program to protected block error:

– error handler

b1 = 0

YES

End

AI05244

Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after

a program sequence.

2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations.

3. Address 1 and address 2 must be consecutive addresses differing only for address bit A0.

4. Address, address 2, address 3 and address 4 must be consecutive addresses differing only for address bit A1-A0.

41/51

M58MR016C, M58MR016D

Figure 18. Program Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Command

PES instruction:

Write 70h

– write B0h command

do:

Command

– read status register

(E or G must be toggled)

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

b2 = 1

YES

Program Complete

If b2 = 0 Program completed

Write a read

Command

Read data from

another address

PER instruction:

– write D0h command to resume

the program

Write D0h

Command

Write FFh

Command

– if the program operation completed

then this is not necessary.

The device returns to Read Array as

normal (as if the Program/Erase

suspend was not issued).

Read Data

Program Continues

AI05245

42/51

M58MR016C, M58MR016D

Figure 19. Block Erase Flowchart and Pseudo Code

Start

Write 20h

Command

EE instruction:

– write 20h command

– write Block Address (A12-A19) &

command D0h

(memory enters read status state after

the EE instruction)

Write Block Address

& D0h Command

do:

– read status register (E or G must be

toggled) if PES instruction given execute

suspend erase loop

NO

Read Status

Register

Suspend

YES

NO

Suspend

Loop

b7 = 1

while b7 = 1

YES

NO

V

Invalid

If b3 = 1, V

invalid error:

PP

Error (1)

PP

– error handler

b3 = 0

YES

Command

Sequence Error (1)

If b4, b5 = 1, Command sequence error:

– error handler

b4, b5 = 0

YES

If b5 = 1, Erase error:

– error handler

b5 = 0

YES

Erase Error (1)

Erase to Protected

Block Error (1)

If b1 = 1, Erase to protected block error:

– error handler

b1 = 0

YES

End

AI05246

43/51

M58MR016C, M58MR016D

Figure 20. Erase Suspend & Resume Flowchart and Pseudo Code

Start

Write B0h

Command

PES instruction:

– write B0h command

do:

Write 70h

Command

– read status register

(E or G must be toggled)

Read Status

Register

NO

b7 = 1

YES

while b7 = 1

b6 = 1

YES

Erase Complete

If b6 = 0, Erase completed

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

PER instruction:

– write D0h command to resume

erasure

Write D0h

Command

Write FFh

Command

– if the erase operation completed

then this is not necessary.

The device returns to Read Array as

normal (as if the Program/Erase

suspend was not issued).

Read Data

Erase Continues

AI05247

44/51

M58MR016C, M58MR016D

Table 33. Command Interface States - Lock table

Current State of the

Current Partition

Command Input to the Current Partition (and Next State of the Current Partition)

Block

Protect-

Unprotect-

Lock

setup

Current

State of

the Other

Partition

Erase

Confirm P/

Memory E Resume

Read

Status

Register

(70h)

Clear

Status

Register

(50h)

Block

Protect

Confirm

(01h)

Block

Lock

Confirm

(2Fh)

Read

elect.

sign. (90h)

Write RCR

Confirm

(03h)

Read CFI

(98h)

Mode

State

Others

Array

(FFH)

BU

Confirm

(D0h)

write RCR

setup

(60h)

Array

CFI

Block

Protect-

Unprotect-

LockSetup

Write RCR

Setup

SEE

Read

Elect.

Sign.

Electronic

Signature

Any State

Read

MODIFY Read Array Read Array Status ReadArray

TABLE

Read CFI

Read Array Read Array Read Array

Register

Status

Block

Protect-

Block

Protect-

Block

Unprotect- Unprotect- Protect- Unprotect- Unprotect- Unprotect- Unprotect- Unprotect- Protect-

Protect-

Setup

Error

Set RCR

LockError LockError Unprotect- LockError LockError LockError LockError LockError Unprotect- Unprotect-

Write RCR Write RCR LockBlock Write RCR Write RCR Write RCR Write RCR Write RCR LockBlock LockBlock

Protect

Error

Any State Unprotect

Lock RCR

Block

Protect-

Unprotect-

LockBlock

Protect-

SEE

Read

Elect.

Sign.

Unprotect-

LockSetup

Write RCR

Setup

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI

Read Array Read Array Read Array

Register

Set RCR

Block

Protect-

SEE

Read

Elect.

Sign.

Protection

Any State

Unprotect-

LockSetup

Write RCR

Setup

Done

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI

Read Array Read Array Read Array

Register

Block

Protect-

Unprotect-

LockSetup

Write RCR

Setup

Program-

Any State Multiple

Program

SEE

Read

Elect.

Sign.

Done

MODIFY Read Array Read Array Status Read Array

TABLE

Register

Setup

Read

Array, CFI,

Elect.

Sign.,

Status

SEE

MODIFY

TABLE

PS Read

Status

Register

PS Read

Elect.

Sign.

Idle

Program

Suspend

PS Read Program

PS Read

Array

PS Read PS Read PS Read PS Read PS Read

Array

(Busy)

CFI

Array

Erase

Suspend

Erase

Error

Erase

Error

Erase

(Busy)

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Erase

Error

Idle

Setup

Error

Block

Block-Bank

Erase

Protect-

SEE

Read

Elect.

Sign.

Unprotect-

LockSetup

Write RCR

Setup

Any State

MODIFY Read Array Read Array Status Read Array

TABLE

Read CFI

Read Array Read Array Read Array

Done

Register

Erase

(Busy)

Setup

Busy

Idle

Block

Read

Array, CFI,

Elect.

Sign.,

Status

ES Read

Array

Protect-

SEE

MADIFY

TABLE

ES Read

Status

Register

ES Read

Elect.

Sign.

Erase

Suspend

ES Read

Array

ES Read

Array

ES Read Unprotect- ES Read ES Read ES Read

CFI

LockSetup

Write RCR

Setup

Array

Erase

(Busy)

Program

Suspend

ES Read

Array

45/51

M58MR016C, M58MR016D

Table 34. Command Interface States - Modify table

Current State of the Current

Command Input to the Current Partition (and Next State of the Current Partition)

Partition

Current State

of the Other

Partition

Multiple

ProgramSetup

(30h/55h)

Program Setup Block Erase Program-Erase

OTP Setup

(C0h)

Bank Erase

Setup (80h)

Mode

State

Others

(10h/40h)

Setup (20h) Suspend (B0h)

Setup

Busy

Read Array

Block Erase

Read Array

OTP Setup

Read Array

Array, CFI,

Electronic

Signature,

Bank Erase

Setup

Idle

SEE LOCK

TABLE

Multiple

Program Setup

Read

Setup

Read Array

Program setup

Erase Suspend

Status Register

Read Array

Program

Suspend

Read Array

Setup

Busy

Read Array

OTP Setup

Read Array

Error, Protect-

Unprotect-

LockBlock, Set

RCR

Protect

Unprotect-Lock/

RCR

Block Erase

Setup

Bank Erase

Setup

Idle

SEE LOCK

TABLE

Multiple

Program Setup

Read Array

Protection

Program setup

Erase Suspend

Read Array

Protection

Read Array

Program

Suspend

Read Array

Protection

Read Array

Protection

Idle

Setup

Busy

Setup

Busy

Protection

Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy) Register (Busy)

Read Array

Protection

Register

Block Erase

Setup

Bank Erase

Setup

Idle

OTP Setup

Multiple

Program Setup

SEE LOCK

TABLE

Program Setup

Done

Read Array

Erase Suspend

Read Array

Program

Suspend

Read Array

Any State

Setup

Busy

Program(Busy)

Program(Busy) Program(Busy) Program(Busy)

Program(Busy) Program (Busy) Program (Busy)

PS Read Status

Register

Idle

Setup

Busy

Read Array

Program Setup

Read Array

OTP Setup

Read Array

Program-

Multiple

Program

Block Erase

Setup

Bank Erase

Setup

Idle

SEE LOCK

TABLE

Multiple

Program Setup

Done

Read Array

Erase Suspend

Read Array

Program

Suspend

Read Array

Setup

Idle

Read Array,

CFI, Elect.

Sign., Status

Register

Program

Suspend

SEE LOCK

TABLE

PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array PS Read Array

Erase Suspend

SEE LOCK

TABLE

Setup

Busy

Erase Error

Erase (Busy)

ES Read Array

Program Setup

ES Read Array

Erase Error

Erase (Busy)

ES Read Array

Erase Error

Block-Bank

Erase

Idle

ES Read Status

Register

Erase (Busy)

Setup

Busy

Read Array,

CFI, Elect.

Sign., Status

Register

SEE LOCK

TABLE

Multiple

Program Setup

Erase Suspend

ES Read Array ES Read Array ES Read Array

ES Read Array

Idle

Program

Suspend

ES Read Array

46/51

M58MR016C, M58MR016D

Table 35. Ordering Information Scheme

Example:

M58MR016C

100 ZC

6

T

Device Type

M58

Architecture

M = Multiplexed Address/Data, Dual Bank, Burst Mode

Operating Voltage

R = 1.8V

Device Function

016C = 16 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Top Boot

016D = 16 Mbit (x16), Dual Bank: 1/4-3/4 partitioning, Bottom Boot

Speed

100 = 100 ns

120 = 120 ns

Package

ZC = TFBGA48: 0.5 mm pitch

Temperature Range

6 = –40 to 85°C

Option

T = Tape & Reel packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

Table 36. Daisy Chain Ordering Scheme

Example:

M58MR016

-ZC T

Device Type

M58MR016

Daisy Chain

-ZC = TFBGA48: 0.5 mm pitch

Option

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

47/51

M58MR016C, M58MR016D

Table 37. Document Revision History

Date

Version

Revision Details

12-Jun-2001

-01

First Issue

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot.(revi-

sion version 01 equals 1.0).

01-Aug-2002

1.1

Supply voltage ranges V and V

modified. Parameters t , t

, t

and t

DD

DDQ

K

KQV KAX LHAX

modified in Table 28, Synchronous Burst Read AC Characteristics.

Document status changed from Product Preview to Preliminary Data.

48/51

M58MR016C, M58MR016D

Table 38. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.300

Typ

Max

A

A1

A2

b

0.950

0.0374

0.0079

0.0472

0.0118

0.200

0.790

0.300

10.530

4.500

6.500

8.500

0.0311

0.0118

0.4146

0.1772

0.2559

0.3346

0.250

0.350

0.0098

0.0138

D

10.480

10.580

0.4126

0.4165

D1

D2

D3

ddd

E

–

0.080

0.0031

6.290

1.500

3.500

5.500

0.500

3.015

2.015

1.015

2.395

1.395

0.395

0.250

6.240

6.340

0.2476

0.0591

0.1378

0.2165

0.0197

0.1187

0.0793

0.0400

0.0943

0.0549

0.0156

0.0098

0.2457

0.2496

E1

E2

E3

e

–

FD

FD1

FD2

FE

FE1

FE2

SD

SE

Figure 21. TFBGA48 - 10 x 4 ball array, 0.5 mm pitch, Bottom View Package Outline

D

D3

D2

D1

FE FE1 FE2

SD

E1 E2 E3

E

e

SE

BALL "A1"

FD2

FD1

FD

b

DUMMY BALLS

ddd

A2

A

A1

BGA-Z17

Drawing is not to scale.

49/51

M58MR016C, M58MR016D

Figure 22. TFBGA48 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

C

D

E

F

G

H

AI90039

Figure 23. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

C

D

E

F

START

POINT

G

H

END

POINT

AI90040

50/51

M58MR016C, M58MR016D

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners

STMicroelectronics GROUP OF COMPANIES

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Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

www.st.com

51/51


型号：	M58LR016C100ZC6T
厂家：	ST
描述：	16 Mbit 1Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory 16兆位1Mb的X16 ，复用I / O ，双行，突发1.8V供应快闪记忆体
文件：	总51页 (文件大小：389K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M58LR016C100ZC6T [STMICROELECTRONICS]

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