M58LSW32B150N6T [STMICROELECTRONICS]
1MX32 FLASH 3V PROM, 150ns, PDSO56, PLASTIC, TSOP-56;
| 型号： | M58LSW32B150N6T |
| 厂家： | 
ST |
| 描述： | 1MX32 FLASH 3V PROM, 150ns, PDSO56, PLASTIC, TSOP-56 可编程只读存储器 光电二极管 |
| 文件： | 总59页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M58LSW32A
M58LSW32B
32 Mbit (2Mb x16 or 1Mb x32, Uniform Block)
3V Supply Flash Memories
PRELIMINARY DATA
FEATURES SUMMARY
■ WIDE x16/x32 DATA BUS for HIGH
Figure 1. Packages
BANDWIDTH
– M58LSW32A x16 DATA BITS
– M58LSW32B x16/x32 DATA BITS
■ SUPPLY VOLTAGE
– V = 2.7 to 3.6V core supply voltage for Pro-
DD
gram, Erase and Read operations
TSOP56 (N)
14 x 20 mm
– V
= 1.8 to V for I/O Buffers
DD
DDQ
■ SYNCHRONOUS/ASYNCHRONOUS READ
– Synchronous Burst read (x16)
TBGA
– Pipelined Synchronous Burst Read (x16)
– Asynchronous Random Read (x16/x32)
– Asynchronous Address Latch Controlled
Read (x16/x32)
TBGA64 (ZA)
8x8 ball array
– Page Read (x16)
■ ACCESS TIME
– Synchronous Burst Read up to 66MHz
TBGA
– Asynchronous Page Mode Read 120/25ns,
150/25ns
TBGA80 (ZA)
8x10 ball array
– Random Read 120ns, 150ns
■ PROGRAMMING TIME
– 8 Word or 4 Double-Word Write Buffer
– 24µs Word effective programming time
■ 64 UNIFORM 32 KWord MEMORY BLOCKS
■ BLOCK PROTECTION/ UNPROTECTION
■ PROGRAM and ERASE SUSPEND
■ OTP SECURITY AREA
■ COMMON FLASH INTERFACE
■ 10,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code M58LSW32A: 16h
– Device Code M58LSW32B: 15h
June 2001
1/59
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M58LSW32A, M58LSW32B
TABLE OF CONTENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. TBGA64 Connections for M58LSW32A (Top view through package) . . . . . . . . . . . . . . . 9
Figure 5. TBGA80 Connections for M58LSW32B (Top view through package) . . . . . . . . . . . . . . 10
Figure 6. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Inputs/Outputs (DQ0-DQ31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Latch Enable (L).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Burst Address Advance (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Word Organization (WORD).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ready/Busy (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program/Erase Enable (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PP
V
DD
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input/Output Supply Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDQ
Ground (V ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SS
Ground (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SSQ
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Latch Controlled Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Asynchronous Latch Controlled Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Automatic Low Power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-Down.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2. Asynchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Synchronous Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Pipelined Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/59
M58LSW32A, M58LSW32B
Table 3. Synchronous Burst Read Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read . . . . . . . . . . . . . 18
Figure 7. Synchronous Burst Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Example Synchronous Pipelined Burst Read Operation . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Example Burst Address Advance and Burst Abort operations. . . . . . . . . . . . . . . . . . . . 19
Burst Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Select Bit (M15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
X-Latency Bits (M14-M11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Y-Latency Bit (M9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Valid Data Ready Bit (M8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Burst Type Bit (M7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Valid Clock Edge Bit (M6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Latch Enable Bit (M3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Burst Length Bit (M2-M0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Burst Configuration Register (x16 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Burst Type Definition (x16 Bus Width). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Burst Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Set Burst Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Block Protect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . 26
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
V
PP
Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/59
M58LSW32A, M58LSW32B
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . 33
Figure 14. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 35
Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 35
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . 37
Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 37
Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 19. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output. . . . . . . . . . . . . . . 40
Table 21. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 43
Table 23. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 43
Figure 23. TBGA64 - 8 x 8 ball array 1mm pitch, Package Outline. . . . . . . . . . . . . . . . . . . . . . . . 44
Table 24. TBGA64 - 8 x 8 ball array, 1 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . . 44
Figure 24. TBGA80 - 8 x 10 ball array, 1mm pitch, Package Outline . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. TBGA80 - 8 x 10 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . . . . . . . 45
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4/59
M58LSW32A, M58LSW32B
APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 29. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 30. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 31. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 32. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 33. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 34. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 25. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 52
Figure 26. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 53
Figure 27. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 28. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 55
Figure 29. Command Interface and Program Erase Controller Flowchart (a). . . . . . . . . . . . . . . . 56
Figure 30. Command Interface and Program Erase Controller Flowchart (b). . . . . . . . . . . . . . . . 57
Figure 31. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 58
5/59
M58LSW32A, M58LSW32B
SUMMARY DESCRIPTION
The M58LSW32 isa 32 Mbit (2Mb x16 or 1Mb x32)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be per-
formed using a single low voltage (2.7V to 3.6V)
core supply. On power-up the memory defaults to
Read mode with an asynchronous bus where it
can be read in the same way as a non-burst Flash
memory.
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked when the Program Erase Enable
input Vpp is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in deep power-down mode. It can also be
used to temporarily disable the protection mecha-
nism.
In asynchronous mode Chip Enable, Output En-
able and Write Enable signals control the bus op-
eration ofthe memory. An Address Latch input can
be used to latch addresses in Latch Controlled
mode. Together they allow simple, yet powerful,
connection to most microprocessors, often without
additional logic.
In synchronous mode all Bus Read operations are
synchronous with the Clock. Chip Enable and Out-
put Enable select the Bus Read operation; the ad-
dress is Latched using the Latch Enable inputs
and the address is advanced using Burst Address
Advance. The signals are compatible with most
microprocessor burst interfaces.
The memory is divided into 64 blocks of 512Kbit
that can be erased independently so it is possible
to preserve valid data while old data is erased.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Programor Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 8 Words (or from 1 to 4 Double
Words) in parallel, both speeding up the program-
ming and freeing up the microprocessor to perform
other work.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 10,000 cy-
cles.
A One Time Programmable (OTP) area is included
for security purposes. Either 2K Words (x16 Bus
Width) or 1K Double-Words (x32 Bus Width) is
available in the OTP area. The process of reading
from and writing to the OTP area is not published
for security purposes; contact STMicroelectronics
for details on how to use the OTP area.
Individual block protection against Program or
Erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
The memory is offered in various packages. The
M58LSW32A is available inTSOP56 (14 x 20 mm)
and TBGA64 (1mm pitch). The M58LSW32B is
available in TBGA80 (1mm pitch).
6/59
M58LSW32A, M58LSW32B
Figure 2. Logic Diagram
Table 1. Signal Names
A1
Address Input (x16 Bus Width only)
Address inputs
V
V
DD DDQ
A2-A21
DQ0-DQ15
21
16
16
Data Inputs/Outputs
A1-A21
DQ0-DQ15
Data Inputs/Outputs (x32 Bus Width of
M58LSW32B only)
DQ16-DQ31
V
PP
DQ16-DQ31(1)
B
Burst Address Advance
Chip Enable
W
E
E
RB
R
G
Output Enable
M58LSW32A
M58LSW32B
K
Clock
G
L
Latch Enable
RP
L
R
Valid Data Ready
Ready/Busy
RB
RP
B
Reset/Power-Down
Program/Erase Enable
Write Enable
K
V
PP
WORD(1)
W
WORD
Word Organization (M58LSW32B only)
Supply Voltage
V
DD
V
V
SS SSQ
AI04347
V
Input/Output Supply Voltage
Ground
DDQ
Note: 1. M58LSW32B only.
V
SS
V
Input/Output Ground
Not Connected Internally
SSQ
NC
7/59
M58LSW32A, M58LSW32B
Figure 3. TSOP56 Connections
NC
R
1
56
NC
W
A21
A20
A19
A18
A17
A16
G
RB
DQ15
DQ7
DQ14
DQ6
V
V
DD
A15
A14
A13
A12
E
SSQ
DQ13
DQ5
DQ12
DQ4
14
15
43
42
V
V
DDQ
SS
M58LSW32A
V
PP
RP
DQ11
A11
A10
A9
DQ3
DQ10
DQ2
A8
V
DD
V
DQ9
DQ1
DQ8
DQ0
B
SS
A7
A6
A5
A4
A3
A2
A1
K
NC
L
28
29
AI04348
8/59
M58LSW32A, M58LSW32B
Figure 4. TBGA64 Connections for M58LSW32A (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A1
A2
A3
A4
DQ8
K
A6
A8
A9
V
A13
A14
V
A18
A19
NC
R
PP
DD
V
E
NC
NC
SS
A7
A10
A11
DQ9
DQ10
DQ2
A12
RP
A15
A20
A21
A17
RB
G
A5
DQ1
DQ0
B
NC
NC
A16
DQ3
DQ11
DQ4
DQ12
DQ5
DQ13
NC
DQ15
NC
NC
G
H
NC
L
V
DQ6
DQ14
DQ7
W
DDQ
NC
V
V
V
SSQ
NC
DD
SS
AI04349
9/59
M58LSW32A, M58LSW32B
Figure 5. TBGA80 Connections for M58LSW32B (Top view through package)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A1
A2
A8
A7
V
E
A13
A14
V
A18
A19
NC
R
SS
DD
A9
A10
A11
DQ19
DQ27
L
A12
A16
A17
A3
A6
V
A15
A20
A21
NC
PP
NC
NC
A4
A5
RP
NC
DQ16
DQ24
DQ17
K
DQ25
DQ18
DQ26
B
WORD
DQ10
DQ3
DQ6
DQ13
DQ5
DQ12
DQ4
DQ28
DQ20
W
DQ22
DQ29
DQ21
RB
DQ31
DQ23
DQ30
G
G
H
J
DQ2
DQ11
DQ15
DQ0
DQ8
DQ1
DQ9
V
V
V
V
DQ7
DQ14
DD
SS
SSQ
SSQ
K
V
V
V
V
V
DD
SS
DDQ
DDQ
DDQ
AI04350
10/59
M58LSW32A, M58LSW32B
Figure 6. Block Addresses
M58LSW32B
Double-Word (x32) Bus Width
M58LSW32A, M58LSW32B
Word (x16) Bus Width
Address lines A1-A21
Address lines A2-A21
(A1 is Don’t Care)
1FFFFFh
0FFFFFh
512 Kbit or
32 KWords
512 Kbit or
16 KDouble-Words
1F8000h
1F7FFFh
0FC000h
0FBFFFh
512 Kbit or
32 KWords
512 Kbit or
16 KDouble-Words
1F0000h
0F8000h
Total of 64
512 Kbit Blocks
00FFFFh
007FFFh
512 Kbit or
32 KWords
512 Kbit or
16 KDouble-Words
008000h
007FFFh
004000h
003FFFh
512 Kbit or
32 KWords
512 Kbit or
16 KDouble-Words
000000h
000000h
AI04351
Note: Also see Appendix A, Table 28 for a full listing of the Block Addresses
11/59
M58LSW32A, M58LSW32B
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
G, can be used to inhibit the data output during a
burst read operation.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Address Inputs (A1-A21). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable must be low when selecting the ad-
dresses.
Reset/Power-Down (RP). The
Reset/Power-
Down pin can be used to apply a Hardware Reset
to the memory or to temporarily unprotect all
blocks that have been protected.
The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a Write operation. The
address latch is transparent when Latch Enable is
A Hardware Reset is achieved by holding Reset/
Power-Down Low, V , for at least t
. When
IL
PLPH
Reset/Power-Down is Low, V , the Status Regis-
IL
ter informationis cleared and the power consump-
tion is reduced to deep power-down level. The
device is deselected and outputs are high imped-
low, V . The address is internally latched in an
IL
Erase or Program operation.
With ax32 Bus Width, WORD = V , Address Input
ance. If Reset/Power-Down goes low, V ,during a
IH
IL
A1 is ignored; the Least Significant Word is output
on DQ0-DQ15 and the Most Significant Word is
output on DQ16-DQ31. With a x16 Bus Width,
Block Erase, a Write to Buffer and Program or a
Block Protect/Unprotect the operation is aborted
and the data may be corrupted. In this case the
WORD = V , the Least Significant Word is output
Ready/Busy pin stays low, V , for a maximum tim-
IL
IL
on DQ0-DQ15 when A1 is low, V and the Most
ing of t
+t
until the completion of the Re-
PHRH,
IL,
PLPH
Significant Word is output on DQ0-DQ15 when A1
set/Power-Down pulse.
is high, V .
IH
After Reset/Power-Down goes High, V , the
IH
Data Inputs/Outputs (DQ0-DQ31). The Data In-
puts/Outputs outputthe data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
memory will be ready for Bus Read and Bus Write
operations after t
or t
, whichever occurs
PHEL
RHEL
last. Note that Ready/Busy does not fall during a
reset, see Ready/Busy Output section.
During power-up Reset/Power-Down must be held
Low, V Furthermore it must stay low for t
IL.
VDHPH
after the Supply Voltage inputs become stable.
The device will then be configured in Asynchro-
nous Random Read mode.
See Table 22 and Figure 21, Reset, Power-Down
and Power-up Characteristics, for more details.
When Chip Enable and Output Enable are both
low, V , the data bus outputs data from the mem-
IL
Holding RP at V will temporarily unprotect the
HH
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the chip is deselected, Output Enable
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
Erase orProgram operation, thememory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
is low, V or the Reset/Power-Down signal is low,
IL,
V . When the Program/Erase Controller is active
IL
the Ready/Busy status is given on DQ7 while
DQ0-DQ6 and DQ8-DQ31 are high impedance.
With a x16 Bus Width, WORD = V , DQ16-DQ31
are not used and are high impedance.
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
IL
Latch Enable (L). The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L. In synchronous bus oper-
ations the address is latched on the active edge of
V
deselects the memory and reduces the power
IH
consumption to the Standby level, I
.
DD1
the Clock when Latch Enable is Low, V . Once
IL
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at V
the outputs are high impedance. Output Enable,
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
IH
Enable is Low, V , the latch is transparent.
IL
12/59
M58LSW32A, M58LSW32B
Clock (K). The Clock, K, is used to synchronize
the memory with the external bus during Synchro-
nous Bus Read operations. The Clock can be con-
figured to have an active rising or falling edge. Bus
signals are latched on the active edge of the Clock
during synchronous bus operations. In Synchro-
nous Burst Read mode the address is latched on
the first active clock edge when Latch Enable is
When the system clock frequency is between
33MHz and 50MHz and the Y latency is set to 2,
values of B sampled on odd clock cycles, starting
from the first read are not considered.
The Valid Data Ready, R, output has an internal
pull-up resistor of approximately 1 MΩ powered
from V
, designers should use an external pull-
DDQ
up resistor of the correct valueto meet the external
low, V , or on the rising edge of Latch Enable,
IL
timing requirements for Valid Data Ready rising.
whichever occurs first.
Word Organization (WORD). The Word Organi-
zation input, WORD, selects the x16 or x32 Bus
Width on the M58LSW32B. The Word Organiza-
tion input is not available on the M58LSW32A.
During asynchronous bus operations the Clock is
not used.
Burst Address Advance (B). The Burst Address
Advance, B, controls the advancing of the address
by the internal address counter during synchro-
nous bus operations.
When WORD is Low, V , Word-wide x16 Bus
IL
Width is selected; data is read and written to DQ0-
DQ15; DQ16-DQ31 are at high impedance and A1
is the LSB of the address bus. When WORD is
Burst Address Advance, B, is only sampled on the
active clock edge of the Clock when the X- or Y-
latency time has expired. If Burst Address Ad-
High, V , the Double-Word wide x32 Bus Width is
IH
selected and the data is read and written to on
DQ0-DQ31; A2 is the LSB of the address bus and
A1 is don’t care.
vance is Low, V , the internal address counter ad-
IL
vances. If Burst Address Advance is High, V , the
IH
internal address counter does not change; the
same data remains on the Data Inputs/Outputs
and Burst Address Advance is not sampled until
the Y-latency expires.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the Program/Erase Controller is currently active.
When Ready/Busy is high impedance, the memo-
ry is ready for any Read, Program or Erase opera-
The Burst Address Advance, B, may be tied to V .
IL
tion. Ready/Busy is Low, V , during Program and
OL
Valid Data Ready (R). The Valid Data Ready
output, R, is an open drain output that can be used
to identify if the memory is ready to output data or
not. The Valid Data Ready output is only active
during Synchronous Burst Read operations when
the Burst Length is set to Continuous. The Valid
Data Ready output can be configured to be active
on the clock edge of the invalid data read cycle or
Erase operations. When the device is busy it will
not accept any additional Program or Erase com-
mands except Program/Erase Suspend. When the
Program/Erase Controller is idle, or suspended,
Ready Busy can float High through a pull-up resis-
tor.
The useof an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
one cycle before. Valid Data Ready Low, V , in-
OL
dicates that the data is not, or will not be valid. Val-
id Data Ready in a high-impedance state indicates
that valid data is or will be available.
Ready/Busy is not Low during a reset unless the
reset was applied when the Program/Erase Con-
troller was active; Ready/Busy can rise before Re-
set/Power-Down rises.
If the memory is configured for Synchronous Burst
Read operations with Burst Length set to Continu-
ous then the value of Valid Data Ready, will de-
pend on the starting address. If the starting
address is aligned to a four Word boundary then
the continuous burst mode will run without activat-
ing the Valid Data Ready output. If the starting ad-
dress is not aligned to a four Word boundary, Valid
Data Ready is Low at the beginning of the contin-
uous burst read to indicate that the memory needs
an internal delay to read the content of the four
successive words in the array.
Program/Erase Enable (V ). The
Program/
PP
Erase Enable input, V
is used to protect all
PP,
blocks, preventing Program and Erase operations
from affecting their data.
When Program/Erase Enable is Low, V , any Pro-
IL
gram or Erase operations sent to the command in-
terface will cause the V Status bit in the Status
PP
Register to be set. When Program/Erase Enable is
High, V , Program and Erase operations can be
IH
Unless the Burst Length is set to Continuous and
Synchronous Burst Read has been selected, Valid
Data Ready is high-impedance. It may be tied to
other components with the same Valid Data
Ready signal to create a unique System Ready
signal.
performed on unprotected blocks.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
V
Supply Voltage. The Supply Voltage, V
,
DD
DD
is the core power supply. All internal circuits draw
13/59
M58LSW32A, M58LSW32B
their current from the V
gram/Erase Controller.
pin, including the Pro-
The Input/Output Supply Voltage, V
, must al-
Supply Volt-
DD
DDQ
ways be equal or less than the V
age, including during Power-Up.
DD
A 0.1µF capacitor should be connected between
the Supply Voltage, V , and the Ground, V , to
A 0.1µF capacitor should be connected between
the Input/Output Supply Voltage, V , and the
DD
SS
decouple the current surges from the power sup-
ply. The PCB track widths must be sufficient to
carry the currents required during all operations of
the parts, see Table 15, DC Characteristics, for
maximum current supply requirements.
DDQ
Ground, V
from the power supply. If V
nected together then only one decoupling capaci-
tor is required.
, to decouple the current surges
SSQ
and V are con-
DDQ
DD
Input/Output Supply Voltage (V
). The In-
Ground (V ). Ground, V
all core power supply voltages.
is the reference for
SS,
DDQ
SS
put/Output Supply Voltage, V , is the input/out-
DDQ
put buffer power supply. All input and output pins
and voltage references are powered and mea-
sured relative to the Input/Output Supply Voltage
Ground (V ). Ground, V
is the reference
SSQ,
SSQ
for input/output voltage measurements. It is es-
sential to connect V and V to the same
SS
SSQ
pin, V
.
DDQ
ground
.
14/59
M58LSW32A, M58LSW32B
BUS OPERATIONS
There are 12 bus operations that control the mem-
ory. Each of these is described in this section, see
Tables 2 and 3, Bus Operations, for a summary.
The bus operation is selected through the Burst
Configuration Register; the bits in this register are
described at the end of this section.
Characteristics for details on when the output be-
comes valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, V , Asynchronous Bus Read
IL
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Bus Read and Asyn-
chronous Bus Write, no other bus operation can
be performed until the Burst Control Register has
been configured.
Synchronous Read operations and Latch Con-
trolled Bus Read operations can only be used to
read the memory array. The Electronic Signature,
CFI or Status Register will be read in asynchro-
nous mode regardless of the Burst Control Regis-
ter settings.
operations by holding Latch Enable Low, V
throughout the bus operation.
IL
Asynchronous Page Read. Asynchronous Page
Read operations are used to read from several ad-
dresses within the same memory page. Each
memory page is 2 Words and has the same A2-
A21, only A1 may change. Asynchronous Page
Read is only available for x16 bus width.
Valid bus operations are the same as Asynchro-
nous Bus Read operations but with different tim-
ings. The first read operation within the page has
identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. See Figure 14, Asynchronous Page
Read AC Waveforms and Table 18, Asynchro-
nous Page Read AC Characteristics for details on
when the outputs become valid.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus Operations
For asynchronous bus operations refer to Table 3
together with the text below.
Asynchronous Bus Read. Asynchronous Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Status
Register, CFI and Block Protection Status) in the
Command Interface. A valid bus operation in-
volves setting the desired address on the Address
Asynchronous Bus Write. Asynchronous Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
Inputs, applying a Low signal, V , to Chip Enable
IL
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
and Output Enable and keeping Write Enable
High, V . The Data Inputs/Outputs will output the
IH
puts and setting Latch Enable Low, V . The Ad-
IL
value, see Figure 12, Asynchronous Bus Read AC
Waveforms, and Table 16, Asynchronous Bus
Read AC Characteristics, for details of when the
output becomes valid.
dress Inputs are latched by the Command
Interface on the rising edge of Chip Enable or
Write Enable, whichever occurs first. The Data In-
puts/Outputs are latched by the Command Inter-
face on the rising edge of Chip Enable or Write
Enable, whichever occurs first. Output Enable
Asynchronous Latch Controlled Bus Read.
Asynchronous Latch Controlled Bus Read opera-
tions read from the memory cells or specific regis-
ters in the Command Interface. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses. Asynchronous Latch Controlled
Bus Read is available for x16 and x32 bus widths.
must remain High, V , during the whole Asyn-
IH
chronous Bus Write operation. See Figures 15,
and 17, Asynchronous Write AC Waveforms, and
Tables 19 and 20, Asynchronous Write and Latch
Controlled Write AC Characteristics, for details of
the timing requirements.
Asynchronous Latch Controlled Bus Write.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
Asynchronous Latch Controlled Bus Write opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data to program. Bus Write op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
able and Address Latch Low, V and keeping
IL
Write Enable High, V ; the address is latched on
IH
the rising edge of Address Latch. Once latched,
the Address Inputs can change. Set Output En-
able Low, V , to read the data on the Data Inputs/
IL
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
the Address Inputs and pulsing Latch Enable Low,
Outputs; see Figure 13, Asynchronous Latch Con-
trolled Bus Read AC Waveforms and Table 17,
Asynchronous Latch Controlled Bus Read AC
V . The Address Inputs are latched by the Com-
IL
15/59
M58LSW32A, M58LSW32B
mand Interface on the rising edge of Latch Enable.
The Data Inputs/Outputs are latched by the Com-
mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. OutputEn-
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Current, I
, for Program or Erase operations un-
DD3
til the operation completes.
able must remain High, V , during the whole
IH
Automatic Low Power. If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Asynchronous Bus Write operation. See Figures
16 and 18 Asynchronous Latch Controlled Write
AC Waveforms, and Tables 19 and 20, Asynchro-
nous Write and Latch Controlled Write AC Charac-
teristics, for details of the timing requirements.
Supply Current, I
. The Data Inputs/Outputs will
DD5
Output Disable. The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Standby. When Chip Enable is High, V , the
IH
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
, and the outputs are high impedance,
DD2
Standby Supply Current, I
.
DD1
independent of Chip Enable, Output Enable or
Write Enable.
Table 2. Asynchronous Bus Operations
(2)
Bus Operation
Step
E
G
W
RP
L
A1-A22
Address
Address
X
DQ0-DQ31
Data Output
High Z
M3
0
V
V
V
Asynchronous Bus Read
High
High
High
High
High
X
IL
IL
IL
IL
IL
IL
IL
IL
IL
IH
IH
IH
IH
V
V
V
V
V
V
V
V
V
V
V
V
Address Latch
Read
1
IL
Asynchronous Latch
Controlled Bus Read
V
1
Data Output
Data Output
Data Input
IH
Asynchronous Page Read
Asynchronous Bus Write
0
X
Address
Address
V
V
V
V
X
IH
IH
IH
IL
IL
IL
IL
Asynchronous Latch
Controlled Bus Write
Address Latch
V
V
V
High
X
Address
Data Input
IL
IL
Output Disable
Standby
V
V
V
High
High
X
X
X
X
X
X
X
High Z
High Z
High Z
IH
X
X
X
X
IH
V
Power-Down
X
X
X
IL
Note: 1. X = Don’t Care V or V . High = V or V .
HH
IL
IH
IH
2. M15 = 1, Bits M15 and M3 are in the Burst Configuration Register.
16/59
M58LSW32A, M58LSW32B
Synchronous Bus Operations
Ready output timing (bit M8) can be changed in
the Burst Configuration Register.
For synchronous bus operations refer to Table 3
together with the text below.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 19, 20
and Table 21.
Synchronous Pipelined Burst Read. Synchro-
nous Burst Read operations can be overlapped to
avoid or reduce the X-latency. Pipelined opera-
tions should only be used with Burst Configuration
Register bit M9 = 0 (Y-latency setting).
A valid Synchronous Pipelined Burst Read opera-
tion occurs during a Synchronous Burst Read op-
eration when the new address is set on the
Address Inputs and a Low pulse isapplied to Latch
Enable. The data for the new address becomes
valid after the X-latency specified in the Burst Con-
figuration Register has expired.
For optimum operation the address should be
latched on the correct clock cycle. Table 4 gives
the clock cycle for each valid X- and Y-latency set-
ting. Only these settings are valid, other settings
must not be used. There is always one Y-Latency
period where the data is not valid. If the address is
latched later than the clock cycle specified in Ta-
bles 4 then additional cycles where the data is not
valid are inserted. Synchronous Pipelined Burst
Read operations should only be performed on
Burst Lengths of 4 with a x16 bus width.
Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external ref-
erence clock. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion. Synchronous Burst Read is only available for
x16 bus width.
A valid Synchronous Burst Read operation begins
when the address is set on the Address Inputs,
Write Enable is High, V , and Chip Enable and
IH
Latch Enable are Low, V , during the active edge
IL
of the Clock. The address is latched on the first ac-
tive clock edge when Latch Enable is low, or on
the rising edge of Latch Enable, whichever occurs
first. The data becomes available for output after
the X-latency specified in the Burst Control Regis-
ter has expired. The output buffers are activated
by setting Output Enable Low, V . See Figure 7
IL
for an example of a Synchronous Burst Read op-
eration.
The Burst Address Advance input and the Y-laten-
cy specified in the Burst Control Register deter-
mine whether the internal address counter is
advanced on the active edge of the Clock. When
the internal address counter is advanced the Data
Inputs/Outputs change to output the value for the
next address.
Suspending a Pipelined Synchronous Burst Read
operation is not recommended.
Synchronous Burst Read Suspend. During
a
In Continuous Burst mode (Burst Length Bit M2-
M0 is set to ‘111’), one Burst Read operation can
access the entire memory sequentially and wrap
at the last address. The Burst Address Advance,
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is sus-
pended when both Output Enable and Burst Ad-
B, must be kept low, V , for the appropriate num-
IL
ber of clock cycles. If Burst Address Advance, B,
dress Advance are High, V . The Burst Address
IH
is pulled High, V , the Burst Read will be sus-
IH
Advance going High, V , stops the burst counter
IH
pended.
and the Output Enable going High, V , inhibits the
IH
In Continuous Burst Mode, if the starting address
is not associated with a page (2 Word) boundary
data outputs. The Synchronous Burst Read oper-
ation can be resumed by setting Output Enable
Low. See Figure 7 for an example of a Synchro-
nous Burst Read Suspend operation.
the Valid Data Ready, R, output goes Low, V , to
IL
indicate that the data will not be ready in time and
additional wait-states are required. The Valid Data
17/59
M58LSW32A, M58LSW32B
Table 3. Synchronous Burst Read Bus Operations
A1-A21
DQ0-DQ31
(3)
Bus Operation
Step
Address Latch
E
G
RP
L
B
K
V
V
V
IL
X
T
X
Address Input
Data Output
Data Output
High Z
IL
IL
IL
IL
IH
V
V
V
V
V
V
IH
Read (no address advance)
Read (with address advance)
Read Suspend
T
T
X
X
X
X
IL
IL
IH
V
V
V
V
V
IH
IL
Synchronous Burst Read
V
IH
IH
IH
IH
Pipelined Synchronous
Burst Read
Read Resume (no address
advance)
V
V
V
V
T
X
Data Output
IL
IL
IL
IL
IH
Read Resume (with address
advance)
V
V
V
V
V
IL
T
X
X
X
Data Output
High Z
IH
V
X
Read Abort
X
IH
IH
Note: 1. X = Don’t Care, V or V
.
IL
IH
2. M15 = 0, Bit M15 is in the Burst Configuration Register.
3. T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.
Table 4. Address Latch Cycle for Optimum Pipelined Synchronous Burst Read
Address Latch Clock Cycle
X-Latency
Y-Latency
Burst Length = 4
8
9
1
1
2
6
7
15
11
Figure 7. Synchronous Burst Read Operation
1
0
X-1
X
X+1
K
Address
Inputs
Q1
L
tBHKH
tBLKH
Q1
tBHKH
B
tBHKH
Data Inputs/
Outputs
Q2
Q3 Q4 Q5 Q5 Q5 Q6 Q7 Q7 Q8 Q8
AI03454b
Note: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words), M6 = 1 (Valid Clock Edge = Rising
Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11 = 0011 (X-Latency = 8) and M15
= 0 (Read Select = Synchronous Burst Read), other bits are don’t care.
18/59
M58LSW32A, M58LSW32B
Figure 8. Example Synchronous Pipelined Burst Read Operation
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
K
Address
Inputs
Q1
R1
S1
L
E
G
B
Data
Q1 Q2 Q3 Q4 NV R1 R2 R3 R4 NV S1 S2 S3
Inputs/ Outputs
NV= Not Valid
AI03455
Note: In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words or Double Words), M6 = 1 (Valid
Clock Edge = Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 0 (Y-Latency = 1), M14-M11 = 0011 (X-
Latency = 8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.
Figure 9. Example Burst Address Advance and Burst Abort operations
1
0
X-2
X
X+2
X+4
X+6
X+8
X+10
X+12
K
Address
Inputs
Q1
L
tBHKH
tBLKH
tBHKH
B
tBHKH
Q2
Data Inputs/
Outputs
Q1
Q3
Q3
Q4
Q4
Q4
AI03457b
Note: 1. In this example the Burst Configuration Register is set with M2-M0 = 001 (Burst Length = 4 Words), M6 = 1 (Valid Clock Edge =
Rising Clock Edge), M7 = 0 or 1 (Burst Type = Interleaved or Sequential), M9 = 1 (Y-Latency = 2), M14-M11 = 0011 (X-Latency =
8) and M15 = 0 (Read Select = Synchronous Burst Read), other bits are don’t care.
2. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock
cycles, starting from the first read are not considered.
19/59
M58LSW32A, M58LSW32B
Burst Configuration Register
The Burst Configuration Register is used to config-
ure the type of bus access that the memory will
perform.
The Burst Configuration Register is set through
the Command Interface and will retain its informa-
tion until it is re-configured, the device is reset, or
the device goes into Reset/Power-Down mode.
The Burst Configuration Register bits are de-
scribed in Table 5. They specify the selection of
the burst length, burst type, burst X and Y laten-
cies and the Read operation.
Read Select Bit (M15). The Read Select bit,
M15, is used to switch between asynchronous and
synchronous Bus Read operations. When the
Read Select bit is set to ’1’, Bus Read operations
are asynchronous; when the Read Select but is
set to ’0’, Bus Read operations are synchronous.
Valid Data Ready Bit (M8). The
Valid
Data
Ready bit controls the timing of the Valid Data
Ready output pin, R. When the Valid Data Ready
bit is ’0’ the Valid Data Ready output pin is driven
Low for the active clock edge when invalid data is
output on the bus. When the Valid Data Ready bit
is ’1’ theValid Data Ready output pin is driven Low
one clock cycle prior to invalid data being output
on the bus.
Burst Type Bit (M7). The Burst Type bit is used
to configure the sequence of addresses read as
sequential or interleaved. When the Burst Type bit
is ’0’ the memory outputs from interleaved ad-
dresses; when the Burst Type bit is ’1’ the memory
outputs from sequential addresses. See Table 6,
Burst Type Definition, for the sequence of ad-
dresses output from a given starting address.
Valid Clock Edge Bit (M6). The Valid Clock Edge
bit, M6, is used to configure the active edge of the
Clock, K, during Synchronous Burst Read opera-
tions. When the Valid Clock Edge bit is ’0’ the fall-
ing edge of the Clock is the active edge; when the
Valid Clock Edge bit is ’1’ the rising edge of the
Clock is active.
Latch Enable Bit (M3). The Latch Enable bit is
used to select between Asynchronous Random
Read and Asynchronous Latch Enable Controlled
Read. When the Latch Enable bit is set to ‘0’ Ran-
dom read is selected; when it is set to ‘1’ Latch En-
able Controlled Read is selected. To enable these
Asynchronous Read configurations M15 must be
set to ‘1’.
Burst Length Bit (M2-M0). The Burst Length bits
set the maximum number of Words or Double-
Words that can be output during a Synchronous
Burst Read operation before the address wraps.
Table 5, Burst Configuration Register gives the
valid combinations of the Burst Length bits that the
memory accepts; Table 6, Burst Type Definition,
gives the sequence of addresses output from a
given starting address for each length.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous accesses.
X-Latency Bits (M14-M11). The X-Latency bits
are used during Synchronous Bus Read opera-
tions to set the number of clock cycles between
the address being latched and the first data be-
coming available. For correct operation the X-La-
tency bits can only assume the values in Table 5,
Burst Configuration Register. The X-Latency bits
should also be selected in conjunction with Table
7, Burst Performance to ensure valid settings.
Y-Latency Bit (M9). The Y-Latency bit is used
during Synchronous Bus Read operations to set
the number of clock cycles between consecutive
reads. The Y-Latency value depends on both the
X-Latency value and the setting in M9.
When the Y-Latency is 1 the data changes each
clock cycle; when the Y-Latency is 2 the data
changes every second clock cycle. See Table 5,
Burst Configuration Register and Table 7, Burst
Performance, for valid combinations of the Y-La-
tency, the X-Latency and the Clock frequency.
M10, M5 and M4 are reserved for future use.
20/59
M58LSW32A, M58LSW32B
Table 5. Burst Configuration Register (x16 Bus Width)
Address
Bit
Reset
Value
Mnemonic
Bit Name
Value
Description
0
Synchronous Burst Read
16
M15
Read Select
1
1
Asynchronous Bus Read
0010
0011
0100
1011
1101
X-Latency = 7, use only with Continuous Burst Length
X-Latency = 8
15
to
12
X-Latency = 9
M14-M11
X-Latency
XXXX
X-Latency = 14, use only with Continuous Burst Length
X-Latency = 15
Others Reserved, Do Not Use.
When X-Latency < 13, Y-Latency = 1
When X-Latency ≥ 13, Y-Latency = 2
0
1
10
M9
Y-Latency
X
When X-Latency < 13, Y-Latency = 2
When X-Latency ≥ 13, do not use.
0
1
R valid Low during valid Clock edge
R valid Low one cycle before valid Clock edge
Interleaved
Valid Data
Ready
9
8
7
5
M8
M7
M6
M3
X
X
X
0
0
Burst Type
1
Sequential
0
Falling Clock edge
Rising Clock edge
Random Read
Valid Clock
Edge
1
0
Latch Enable
1
Latch Enable Controlled Read
1 Word
100
101
001
111
2 Words
3
to
1
M2-M0
Burst Length
XXX
4 Words
Continuous
Others Reserved, Do Not Use.
21/59
M58LSW32A, M58LSW32B
Table 6. Burst Type Definition (x16 Bus Width)
Starting Address
Sequential
(decimal)
Interleaved
(decimal)
(binary)
Burst Length
A2 A1
X0
0, 1
1, 0
0, 1
2
X1
1, 0
00
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
A, A+1, A+2...
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
Not Valid
01
4
10
11
Continuous
A
Note: X = 0 or 1.
Table 7. Burst Performance
Clock Frequency
Continuous Burst Length
Y-Latency
1 or 2
Other Burst Length
X-Latency
X-Latency
Y-Latency
≤33 MHz
≥ 7
≥ 8
1 or 2
2
33 MHz ≤ f ≤66 MHz
≥ 13
2
15
22/59
M58LSW32A, M58LSW32B
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. The Commands are summarized in Table
8, Commands. Refer to Table 8 in conjunction with
the text descriptions below.
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register until another com-
mand is issued.
The Status Register information is present on the
output data bus (DQ1-DQ7) when both Chip En-
After power-up or a Reset operation the memory
enters Read mode.
able and Output Enable are low, V . In Synchro-
IL
nous Burst mode the Status Register information
is output on the active clock edge when Latch En-
Synchronous Read operations and Latch Con-
trolled Bus Read operations can only be used to
read the memory array. The Electronic Signature,
CFI or Status Register will be read in asynchro-
nous mode regardless of the Burst Control Regis-
ter settings. Once the memory returns to Read
Memory Array mode the bus will resume the set-
ting in the Burst Configuration Register automati-
cally.
Read Memory Array Command. The Read Mem-
ory Array command returns the memory to Read
mode. One Bus Write cycle is required to issue the
Read Memory Array command and return the
memory to Read mode. Once the command is is-
sued the memory remains in Read mode until an-
other command is issued. From Read mode Bus
Read commands will access the memory array.
able is low, V , or on the rising edge of Latch En-
IL
able, whichever occurs first.
See the section on the Status Register and Table
11 for details on the definitions of the Status Reg-
ister bits
Clear Status Register Command. The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear StatusRegister
command. Once the command is issued the mem-
ory returns to its previous mode, subsequent Bus
Read operationscontinue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Write to
Buffer and Program, Erase, Block Protect or Block
Unprotect command is issued. If any error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program,
Erase or Resume command.
While the Program/Erase Controller is executing a
Program, Erase, Block Protect or Blocks Unpro-
tect operation the memory will not accept the Read
Memory Array command until the operation com-
pletes.
ReadElectronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code, the Device Code and the
Block Protection Status. One Bus Write cycle is re-
quired to issue the Read Electronic Signature
command. Once the command is issued subse-
quent Bus Read operations read the Manufacturer
Code, the Device Code or the Block Protection
Status until another command is issued; see Table
9, Read Electronic Signature.
Block Erase Command. The Block Erase com-
mand can be used to erase a block. It sets all of
the bits in the block to ‘1’. All previous data in the
block is lost. If the block is protected then the
Erase operation will abort, the data in the block will
not be changed and the Status Register will output
the error.
Two Bus Write operations are required to issue the
command; the second Bus Write cycle latches the
block address in the internal state machine and
starts the Program/Erase Controller. Once the
command is issued subsequent Bus Read opera-
tions read the Status Register. See the section on
the Status Register for details on the definitions of
the Status Register bits.
Read Query Command. The Read Query Com-
mand is used to read data from the Common Flash
Interface (CFI) Memory Area. One Bus Write cycle
is required to issue the Read Query Command.
Once the command is issued subsequent Bus
Read operations read from the Common Flash In-
terface Memory Area. See Appendix B, Tables 29,
30, 31, 32, 33 and 34 for details on the information
contained in the Common Flash Interface (CFI)
memory area.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 10.
Note that the addresses for the Common Flash In-
terface Memory Area are A1-A21 for the
M58LSW32A and A2-A21 for the M58LSW32B,
regardless of the bus width selected.
See Appendix C, Figure 27, Block Erase Flow-
chart and Pseudo Code, for a suggested flowchart
on using the Block Erase command.
Write to Buffer and Program Command. The
Write to Buffer and Program command is used to
program the memory array. Up to 8 Words (or 4
Read Status Register Command. The Read Sta-
tus Register command is used to read the Status
23/59
M58LSW32A, M58LSW32B
Double Words)can be loaded into the Write Buffer
and programmed into the memory. Each Word has
the same A5-A21.
Four successive steps are required to issue the
command.
Program/Erase Controller has paused; no other
commands will be accepted until the Program/
Erase Controller has paused. After the Program/
Erase Controller has paused, the memory will con-
tinue to output the Status Register until another
command is issued.
1. One Bus Write operation is required to set up
the Write to Buffer and Program Command. Is-
sue the set up command with the selected
memory Block Address where the program op-
eration should occur (any address in the block
where the values will be programmed can be
used). Any Bus Read operations will start to out-
put the Status Register after the 1st cycle.
During the polling period between issuing the Pro-
gram/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the op-
eration to complete. Once the Program/Erase
Controller Status bit (bit 7) indicates that the Pro-
gram/Erase Controller is no longer active, the Pro-
gram Suspend Status bit (bit 2) or the Erase
Suspend Status bit (bit 6) can be used to deter-
mine if the operation has completed or is suspend-
ed. For timing on the delay between issuing the
Program/Erase Suspend command and the Pro-
gram/Erase Controller pausing see Table 10.
2. Use one Bus Write operation to write the same
block address along with the value N on the
Data Inputs/Output, where N+1 is the number of
Words (x16 Bus Width) or Double Words (x32
Bus Width) to be programmed.
During Program/Erase Suspend the Read Memo-
ry Array, Read Status Register, Read Electronic
Signature, Read Query and Program/Erase Re-
sume commands will be accepted by the Com-
mand Interface. Additionally, if the suspended
operation was Erase then the Write to Buffer and
Program, and the Program Suspend commands
will also be accepted. When a program operation
is completed inside a Block Erase Suspend the
Read Memory Array command must be issued to
reset the device in Read mode, then the Erase Re-
sume command can be issued to complete the
whole sequence. Only the blocks not being erased
may be read or programmed correctly.
3. Use N+1 Bus Write operations to load the ad-
dress and data for each Word or Double Word
into the Write Buffer. See the constraints on the
address combinations listed below. The ad-
dresses must have the same A5-A21.
4. Finally, use one Bus Write operation to issue the
final cycle to confirm the command and start the
Program operation.
Invalid address combinations or failing to follow
the correct sequence of Bus Write cycles will set
an error in the Status Register and abort the oper-
ation without affecting the data in the memory ar-
ray. The Status Register should be cleared before
re-issuing the command.
If the block being programmed is protected an er-
ror will be set in the Status Register and the oper-
ation will abort without affecting the data in the
memory array. The block must be unprotected us-
ing the Blocks Unprotect command or by using the
Blocks Temporary Unprotect feature of the Reset/
Power-Down pin, RP.
See Appendix C, Figure 26, Program Suspend &
Resume Flowchart and Pseudo Code, and Figure
28, Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after
Pro-
a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Pro-
gram/Erase Resume command. Once the com-
mand is issued subsequent Bus Read operations
read the Status Register.
See Appendix C, Figure 25, Write to Buffer and
Program Flowchart and Pseudo Code, for a sug-
gested flowchart on using the Write to Buffer and
Program command.
Program/Erase Suspend Command. The
Pro-
Set Burst Configuration Register Command.
gram/Erase Suspend command is used to pause a
Write to Buffer and Program or Erase operation.
The command will only be accepted during a Pro-
gram or an Erase operation. It can be issued at
any time during an Erase operation but will only be
accepted during a Write to Buffer and Program
command if the Program/Erase Controller is run-
ning.
The Set Burst Configuration Register command is
used to write a new value to the Burst Configura-
tion Control Register which defines the burst
length, type, X and Y latencies, Synchronous/
Asynchronous Read mode and the valid Clock
edge configuration.
One Bus Write cycle is required to issue the Set
Burst Configuration Register command. Once the
command is issued the memory returns to Read
mode as if a Read Memory Array command had
been issued.
One Bus Write cycle is required to issue the Pro-
gram/Erase Suspend command and pause the
Program/Erase Controller. Once the command is
issued it is necessary to poll the Program/Erase
Controller Status bit (bit 7) to find out when the
24/59
M58LSW32A, M58LSW32B
The value for the Burst Configuration Register is
always presented on A2-A17, regardless of the
bus width that is selected. M0 is on A2, M1 on A3,
etc.; the other address bits are ignored.
The Block Protection bits are non-volatile, once
set they remain set through reset and power-
down/power-up. They are cleared by a Blocks Un-
protect command or temporary disabled by raising
the Reset/Power-Down pin to V and holding it at
HH
Block Protect Command. The Block Protect
command is used to protect a block and prevent
Program or Erase operations from changing the
data in it. Two Bus Write cycles are required to is-
sue the Block Protect command; the second Bus
Write cycle latches the block address in the inter-
nal state machine and starts the Program/Erase
Controller. Once the command is issued subse-
quent Bus Read operations read the Status Reg-
ister. See the section on the Status Register for
details on the definitions of the Status Register
bits.
that level throughout a Block Erase or Write to
Buffer and Program command.
Blocks Unprotect Command. The Blocks Un-
protect command is used to unprotect all of the
blocks. Two Bus Write cycles are required to issue
the Blocks Unprotect command; the second Bus
Write cycle starts the Program/Erase Controller.
Once the command is issued subsequent Bus
Read operations read the Status Register. See the
section on the Status Register for details on the
definitions of the Status Register bits.
During theBlock Protect operation the memory will
only accept the Read Status Register command.
All other commands will be ignored. Typical Block
Protection times are given in Table 10.
During the Block Protect operation the memory will
only accept the Read Status Register command.
All other commands will be ignored. Typical Block
Protection times are given in Table 10.
25/59
M58LSW32A, M58LSW32B
Table 8. Commands
Command
Bus Write Operations
2nd Subsequent
1st
Final
Addr
X
Data
FFh
90h
98h
70h
50h
20h
E8h
B0h
D0h
60h
60h
60h
Addr
Data
Addr
Data
Addr
Data
Read Memory Array
Read Electronic Signature
Read Query
1
1
1
1
1
2
X
X
Read Status Register
Clear Status Register
Block Erase
X
X
X
BA
BA
D0h
N
Write to Buffer and Program
Program/Erase Suspend
Program/Erase Resume
Set Burst Configuration Register
Block Protect
4 + N
BA
X
PA
PD
X
D0h
1
1
2
2
2
X
BCR
BA
X
BCR
BA
X
03h
01h
D0h
Blocks Unprotect
Note: X Don’t Care; PA Program Address; PD Program Data; BA Any address in the Block; N+1 Number of Addresses to Program;
BCR Burst Configuration Register value.
Table 9. Read Electronic Signature
Address (A21-A1,
x16 Bus Width)
Address (A21-A2,
x32 Bus Width)
Data
(DQ31-DQ8)
Data
(DQ7-DQ0)
Code
Manufacturer Code
Device Code
000000h
000001h
000000h
000001h
000000h
000000h
20h
16h (M58LSW32A)
15h (M58LSW32B)
00h (Block Unprotected)
01h (Block Protected)
(1)
BA OR 02h
BA OR 02h
000000h
Block Protection Status
Note: BA is any address in the block. Use the Logical OR operator to ensure that the two LSBs of the address are ’1’.
Table 10. Program, Erase Times and Program Erase Endurance Cycles
M58LSW32A/B
Parameters
Unit
Typical after
10k W/E Cycles
Min
Typ
Max
Block (512 Kbit) Erase
Chip Program
0.75
54
0.75
54
5
s
s
Program Write Buffer
192
3
192
µs
Program Suspend Latency Time
Erase Suspend Latency Time
Block Protect Time
10
30
µs
10
µs
192
0.75
µs
Blocks Unprotect Time
Program/Erase Cycles (per Block)
s
10,000
cycles
Note: (T = 0 to 70°C; V = 2.7V to 3.6V; V =1.8V)
DDQ
A
DD
26/59
M58LSW32A, M58LSW32B
STATUS REGISTER
The Status Register provides information on the
current or previous Program, Erase, Block Protect
or Blocks Unprotect operation. The various bits in
the Status Register convey information and errors
on the operation. They are output on DQ7-DQ0.
To read the Status Register the Read Status Reg-
ister command can be issued. The Status Register
is automatically read after Program, Erase, Block
Protect, Blocks Unprotect and Program/Erase Re-
sume commands. The Status Register can be
read from any address.
The Status Register can only be read using Asyn-
chronous Bus Read operations. Once the memory
returns to Read Memory Array mode the bus will
resume the setting in the Burst Configuration Reg-
ister automatically.
When the Erase Suspend Status bit is Low, V
,
OL
the Program/EraseController is active or has com-
pleted its operation; when the bit is High, V , a
OH
Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has failed to verify
that the block has erased correctly or that all
blocks have been unprotected successfully. The
Erase Status bit should be read once the Program/
Erase Controller Status bit is High (Program/Erase
Controller inactive).
When the Erase Status bit is Low, V , the mem-
OL
The contents of the Status Register can be updat-
ed during an Erase or Program operation by tog-
gling the Output Enable pin or by dis-activating
ory has successfully verified that the block has
erased correctlyor all blocks have been unprotect-
ed successfully. When the Erase Status bit is
(Chip Enable, V ) and then reactivating (Chip En-
High, V , the Program/Erase Controller has ap-
IH
OH
able and Output Enable, V ) the device.
plied the maximum number of pulses to the block
and still failed to verify that the block has erased
correctly or that all the blocks have been unpro-
tected successfully.
IL
The Status Register bits are summarized in Table
11, Status Register Bits. Refer to Table 11 in con-
junction with the following text descriptions.
Once set High, the Erase Status bit can only be re-
set Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
Program Status (Bit 4). The Program Status bit
is used to identify a Program or Block Protect fail-
ure. The Program Status bit should be read once
the Program/Erase Controller Status bit is High
(Program/Erase Controller inactive).
Program/Erase Controller Status (Bit 7). ThePro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Low, V , the Program/Erase Controller is active;
OL
when the bit is High, V , the Program/Erase
OH
Controller is inactive.
The Program/Erase Controller Status is Low im-
mediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
When the Program Status bit is Low, V , the
OL
memory has successfully verified that the Write
Buffer has programmed correctly or the block is
protected. When the Program Status bit is High,
During Program, Erase, Block Protect and Blocks
Unprotect operations the Program/Erase Control-
ler Status bit can be polled to find the end of the
operation. The other bits in the Status Register
should not be tested until the Program/Erase Con-
troller completes the operation and the bit is High.
V
, the Program/Erase Controller has applied
OH
the maximum number of pulses to the byte and still
failed to verify that the Write Buffer has pro-
grammed correctly or that the Block is protected.
Once set High, the Program Status bit can only be
reset Low by a Clear Status Register command or
a hardware reset. If set High it should be reset be-
fore a new Program or Erase command is issued,
otherwise the new command will appear to fail.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, V
PP
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Sus-
pend Status bit indicates that an Erase operation
has been suspended and is waiting to be re-
sumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Con-
troller Status bit is High (Program/Erase Controller
inactive); after a Program/Erase Suspend com-
mand is issued the memory may still complete the
operation rather than entering the Suspend mode.
V
Status (Bit 3). The V
Status bit can be
PP
PP
used to identify an invalid voltage on the V pin
PP
during Program, Erase, Block Protect and Blocks
Unprotect operations. The V pin is only sampled
PP
at thebeginning of a Program, Erase Block Protect
or Blocks Unprotect operation. Indeterminate re-
sults can occur if V becomes invalid during an
PP
operation.
27/59
M58LSW32A, M58LSW32B
When the V Status bit is Low, V , the voltage
a Program/Erase Suspend command has been is-
sued and the memory is waiting for a Program/
Erase Resume command.
When a Program/Erase Resume command is is-
sued the Program Suspend Status bit returns Low.
PP
OL
on the V
pin was sampled at a valid voltage;
PP
when the V Status bit is High, V , the V pin
PP
OH
PP
has a voltage that is below the V Lockout Volt-
PP
age, V
, the memory is protected; Program
PPLK
Erase, Block Protect and Blocks Unprotect opera-
tion cannot be performed.
Block Protection Status (Bit 1). The Block Pro-
tection Status bit can be used to identify if a Pro-
gram or Erase operation has tried to modify the
contents of a protected block.
Once setHigh, theV Status bit can only be reset
PP
Low by a Clear Status Register command or a
hardware reset. If set High it should be reset be-
fore a new Program, Erase, Block Protect or
Blocks Unprotect command is issued, otherwise
the new command will appear to fail.
When the Block Protection Status bit is Low, V
,
OL
no Program or Erase operations have been at-
tempted to protected blocks since the last Clear
Status Register command or hardware reset;
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program oper-
ation has been suspended and is waiting to be re-
sumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is High (Program/Erase Con-
troller inactive); after a Program/Erase Suspend
command is issued the memory may still complete
the operation rather than entering the Suspend
mode.
when the Block Protection Status bit is High, V ,
IH
a Programor Erase operation has been attempted
on a protected block.
Once set High, the Block Protection Status bit can
only be reset Low by a Clear Status Register com-
mand or a hardware reset. If set High it should be
reset before a new Program or Erase command is
issued, otherwise the new command will appear to
fail.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
When the Program Suspend Status bit is Low,
V
, the Program/Erase Controller is active or has
OL
completed its operation; when the bit is High, V
,
OH
Table 11. Status Register Bits
Operation
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RB
V
Program/Erase Controller Active
Write Buffer not ready
‘0’
‘0’
‘1’
Not Valid
Not Valid
OL
V
OL
(1)
(1)
(1)
Write Buffer ready
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
Hi-Z
Hi-Z
Hi-Z
X
X
X
Program suspended
‘1’
‘1’
Program/Block Protect completed successfully
Program/Block Protect failure due to incorrect command
sequence
(1)
’1’
‘1’
‘1’
‘0’
‘0’
‘0’
Hi-Z
X
(1)
(1)
(1)
Program/Block Protect failure due to V Error
‘1’
‘1’
‘1’
‘0’
‘0’
‘0’
‘1’
‘1’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
Hi-Z
Hi-Z
Hi-Z
PP
X
X
X
Program failure due to Block Protection
Program/Block Protect failure due cell failure or unerased cell
Erase suspended
‘1’
‘1’
‘1’
‘1’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
‘0’
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Erase/Blocks Unprotect completed successfully
‘0’
‘0’
‘0’
‘0’
Erase/Blocks Unprotect failure due to V Error
PP
Erase failure due to Block Protection
Erase/Blocks Unprotect failure due to failed cell(s) in block
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
28/59
M58LSW32A, M58LSW32B
MAXIMUM RATING
Stressing the device above the ratings listed in Ta-
ble 12, Absolute Maximum Ratings, may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 12. Absolute Maximum Ratings
Value
Symbol
Parameter
Temperature Under Bias
Unit
Min
–40
–55
Max
125
T
BIAS
°C
°C
°C
V
T
Storage Temperature
150
STG
T
Maximum TLEAD Temperature during soldering
Input or Output Voltage
t.b.a.
LEAD
V
V
+0.6
–0.6
–0.6
–0.6
IO
DDQ
V
, V
DD DDQ
Supply Voltage
5.0
V
(1)
V
RP Hardware Block Unlock Voltage
V
HH
10
Note: 1. Cumulative time at a high voltage level of 10V should not exceed 80 hours on RP pin.
29/59
M58LSW32A, M58LSW32B
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC characteristics Tables that follow, are de-
rived from tests performed under the Measure-
ment Conditions summarized in Table 13,
Operating and AC Measurement Conditions. De-
signers should check that the operating conditions
in their circuit match the measurement conditions
when relying on the quoted parameters.
Table 13. Operating and AC Measurement Conditions
M58LSW32
Parameter
120
150
Units
Min
Max
3.6
Min
2.7
1.8
0
Max
Supply Voltage (V
)
2.7
1.8
0
3.6
V
V
DD
Input/Output Supply Voltage (V
)
V
DD
V
DD
DDQ
Grade 1
Grade 6
70
70
°C
°C
pF
ns
ns
V
Ambient Temperature (T )
A
–40
85
–40
85
Load Capacitance (C )
30
30
L
Clock Rise and Fall Times
Input Rise and Fall Times
Input Pulses Voltages
3
4
3
4
0 to V
0.5 V
0 to V
0.5 V
DDQ
DDQ
Input and Output Timing Ref. Voltages
V
DDQ
DDQ
Figure 10. AC Measurement Input Output
Waveform
Figure 11. AC Measurement Load Circuit
1.3V
1N914
V
DDQ
V
DD
3.3kΩ
V
DDQ
0.5 V
DDQ
DEVICE
UNDER
TEST
DQ
S
0V
C
L
AI00610
0.1µF
0.1µF
C
includes JIG capacitance
L
AI03459
Table 14. Capacitance
Symbol
Parameter
Test Condition
Typ
6
Max
8
Unit
pF
pF
C
IN
Input Capacitance
Output Capacitance
V
= 0V
= 0V
IN
C
OUT
V
OUT
8
12
Note: 1. T = 25°C, f = 1 MHz
A
2. Sampled only, not 100% tested.
30/59
M58LSW32A, M58LSW32B
Table 15. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
±1
±5
30
50
40
2
Unit
µA
I
0V≤V ≤V
DDQ
Input Leakage Current
LI
IN
I
LO
0V≤V
≤V
Output Leakage Current
µA
OUT DDQ
I
E = V , G = V , f
= 6MHz
Supply Current (Random Read)
Supply Current (Burst Read)
Supply Current (Standby)
mA
mA
µA
DD
IL
IH add
I
E = V , G = V , f = 50MHz
IH clock
DDB
IL
I
E = V , RP = V
DD1
IH
IH
IH
I
E = V , RP = V
Supply Current (Auto Low-Power)
Supply Current (Reset/Power-Down)
mA
µA
DD5
IL
I
I
RP = V
1
DD2
DD3
IL
Supply Current (Program or Erase,
Set Lock Bit, Erase Lock Bit)
Program or Erase operation in
progress
50
mA
mA
Supply Current
(Erase/Program Suspend)
I
E = V
50
DD4
IH
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.5
0.8
V
V
V
V
IL
V
V
V
–0.8
V
+ 0.5
DDQ
IH
DDQ
V
V
I
= 100µA
OL
0.1
OL
I
= –100µA
–0.1
DDQ
OH
OH
RP Hardware Block Unprotect
Voltage
Block Erase in progress,
Write to Buffer and Program
(1)
8.5
9.5
1
V
µA
V
V
HH
RP Hardware Block Unprotect
Current
I
RP = V
HH
HH
V
Supply Voltage (Erase and
DD
V
2.2
LKO
Program lockout)
Note: 1. Biasing RP pin to V is allowed for a maximum cumulative period of 80 hours.
HH
31/59
M58LSW32A, M58LSW32B
Figure 12. Asynchronous Bus Read AC Waveforms
tAVAV
A1-A21
VALID
tELQV
tELQX
tAXQX
E
tEHQZ
tEHQX
tGLQV
tGLQX
G
tAVQV
tGHQZ
tGHQX
DQ0-DQx
OUTPUT
AI04353
Note: Asynchronous Read (M15 = 1), Random Read (M3 = 0)
Table 16. Asynchronous Bus Read AC Characteristics.
M58LSW32
120 150
Symbol
Parameter
Test Condition
Unit
t
Address Valid to Address Valid
E = V , G = V
Min
Max
Min
Max
Min
Max
Min
Min
Min
Max
Max
120
120
0
150
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
IL
IL
IL
t
E = V , G = V
IL
Address Valid to Output Valid
AVQV
t
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Transition
Output Enable High to Output Transition
Address Transition to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
G = V
G = V
E = V
ELQX
IL
IL
t
120
0
150
0
ELQV
GLQX
GLQV
t
t
t
IL
IL
E = V
50
0
50
0
G = V
E = V
EHQX
GHQX
IL
t
0
0
IL
t
E = V , G = V
0
0
AXQX
EHQZ
IL
IL
t
G = V
10
10
10
10
IL
t
E = V
GHQZ
IL
32/59
M58LSW32A, M58LSW32B
Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms
A1-A21
VALID
tAVHL
tLHAX
tAVLL
L
tLHLL
tLLLH
tEHLX
tELLH
tELLL
E
tGLQV
tGLQX
tEHQZ
tEHQX
G
tLLQX
tLLQV
tGHQZ
tGHQX
DQ0-DQx
OUTPUT
AI04354
Note: Asynchronous Read (M15 = 1), Latch Enable Controlled (M3 = 1)
Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics
M58LSW32
Symbol
Parameter
Test Condition
Unit
120
0
150
t
E = V
Address Valid to Latch Enable Low
Address Valid to Latch Enable High
Latch Enable High to Latch Enable Low
Latch Enable Low to Latch Enable High
Chip Enable Low to Latch Enable Low
Chip Enable Low to Latch Enable High
Latch Enable Low to Output Transition
Latch Enable Low to Output Valid
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
0
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLL
IL
t
E = V
10
10
10
0
AVLH
IL
t
LHLL
t
E = V
LLLH
IL
t
ELLL
t
10
0
10
0
ELLH
t
E = V , G = V
IL IL
LLQX
t
E = V , G = V
120
10
0
150
10
0
LLQV
IL
IL
t
t
Latch Enable High to Address Transition
Output Enable Low to Output Transition
Output Enable Low to Output Valid
E = V
E = V
E = V
LHAX
IL
IL
IL
GLQX
t
20
20
GLQV
Chip Enable High to Latch Enable
Transition
t
Min
0
0
ns
EHLX
Note: For other timings see Table 16, Asynchronous Bus Read Characteristics.
33/59
M58LSW32A, M58LSW32B
Figure 14. Asynchronous Page Read AC Waveforms
A1-A2
VALID
VALID
A3-A21
VALID
tAVQV
tELQV
tELQX
tAXQX
E
tAVQV1
tAXQX1
tEHQZ
tEHQX
tGLQV
tGLQX
G
tGHQZ
tGHQX
DQ0-DQx
OUTPUT
OUTPUT
AI04355
Note: Asynchronous Read (M15 = 1), Random (M3 = 0)
Table 18. Asynchronous Page Read AC Characteristics
M58LSW32
Symbol
Parameter
Test Condition
E = V , G = V
Unit
120
150
6
t
Address Transition to Output Transition
Address Validto Output Valid
Min
6
ns
ns
AXQX1
IL
IL
t
E = V , G = V
IL
Max
25
25
AVQV1
IL
Note: For other timings see Table 16, Asynchronous Bus Read Characteristics.
34/59
M58LSW32A, M58LSW32B
Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled
A1-A21
VALID
tAVWH
tWHAX
tWHEH
E
tELWL
G
tWHGL
tGHWL
tWLWH
tWHWL
W
tDVWH
INPUT
DQ0-DQn
tWHDX
RB
tVPHWH
tWHBL
V
PP
AI04356
Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled
A1-A21
VALID
tAVWH
tAVLH
tLHAX
L
tWHAX
tELLL
tLLLH
tLHWH
tLHGL
E
tELWL
tGHWL
tWHEH
G
tWHGL
tWLWH
tWHWL
W
tDVWH
INPUT
DQ0-DQn
tWHDX
RB
tVPHWH
tWHBL
V
PP
AI04357
35/59
M58LSW32A, M58LSW32B
Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Controlled.
M58LSW32
Symbol
Parameter
Test Condition
Min
Unit
120
10
50
50
0
150
10
50
50
0
t
Address Valid to Latch Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLH
t
Address Valid to Write Enable High
E = V
E = V
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
Min
Min
AVWH
IL
IL
t
Data Input Valid to Write Enable High
Chip Enable Low to Write Enable Low
Chip Enable Low to Latch Enable Low
Latch Enable High to Address Transition
Latch Enable High to Output Enable Low
Latch Enable High to Write Enable High
Latch Enable low to Latch Enable High
Latch Enable Low to Write Enable High
Program/Erase Enable High to Write Enable High
Write Enable High to Address Transition
Write Enable High to Ready/Busy low
Write Enable High to Input Transition
Write Enable High to Chip Enable High
Output Enable High to Write Enable Low
Write Enable High to Output Enable Low
Write Enable High to Write Enable Low
Write Enable Low to Write Enable High
DVWH
t
ELWL
t
0
0
ELLL
LHAX
LHGL
t
t
3
3
35
0
35
0
t
LHWH
t
10
50
0
10
50
0
LLLH
t
LLWH
t
VPHWH
t
E = V
E = V
10
90
10
0
10
90
10
0
WHAX
IL
IL
t
t
WHBL
WHDX
WHEH
GHWL
WHGL
t
t
t
20
35
30
70
20
35
30
70
t
WHWL
t
E = V
WLWH
IL
36/59
M58LSW32A, M58LSW32B
Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled
A1-A21
VALID
tAVEH
tEHAX
W
G
tWLEL
tEHWH
tGHEL
tELEH
tEHEL
tEHGL
E
tDVEH
INPUT
DQ0-DQn
tEHDX
RB
tVPHEH
tEHBL
V
PP
AI04358
Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled
A1-A21
VALID
tAVLH
tAVEH
tLHAX
tEHAX
L
tLLLH
tLHGL
tWLLL
tLHEH
W
G
tWLEL
tGHEL
tEHWH
tELEH
tDVEH
tEHEL
tEHGL
E
DQ0-DQn
INPUT
tEHDX
RB
tVPHEH
tEHBL
V
PP
AI04359
37/59
M58LSW32A, M58LSW32B
Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled
M58LSW32
Symbol
Parameter
Test Condition
Min
Unit
120
10
50
50
0
150
10
50
50
0
t
Address Valid to Latch Enable High
Address Valid to Chip Enable High
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLH
t
W = V
W = V
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
Min
Min
AVEH
IL
IL
t
t
Data Input Valid to Chip Enable High
Write Enable Low to Chip Enable Low
Write Enable Low to Latch Enable Low
Latch Enable High to Address Transition
Latch Enable High to Output Enable Low
Latch Enable High to Chip Enable High
Latch Enable low to Latch Enable High
Latch Enable Low to Chip Enable High
Program/Erase Enable High to Chip Enable High
Chip Enable High to Address Transition
Chip Enable High to Ready/Busy low
Chip Enable High to Input Transition
Chip Enable High to Write Enable High
Output Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
Chip Enable High to Chip Enable Low
Chip Enable Low to Chip Enable High
DVEH
WLEL
t
0
0
WLLL
t
3
3
LHAX
t
35
0
35
0
LHGL
t
LHEH
t
10
50
0
10
50
0
LLLH
t
LLEH
t
VPHEH
t
W = V
W = V
10
90
10
0
10
90
10
0
EHAX
IL
IL
t
EHBL
t
EHDX
t
EHWH
t
20
35
30
70
20
35
30
70
GHEL
EHGL
t
t
EHEL
t
W = V
ELEH
IL
38/59
M58LSW32A, M58LSW32B
Figure 19. Synchronous Burst Read AC Waveform
Note: Valid Clock Edge = Rising (M6 = 1)
39/59
M58LSW32A, M58LSW32B
Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
(2)
Output
R
V
V
V
NV
NV
V
V
tRLKH
(3)
AI03696
Note: 1. Valid Data Ready = Valid Low during valid clock edge (M8 = 0)
2. V= Valid output, NV= Not Valid output.
3. R is an open drain output with an internal pull up resistor of 1MΩ. Depending on the Valid Data Ready pin capacitance load an
external pull up resistor must be chosen according to the system clock period.
4. When the system clock frequency is between 33MHz and 50MHz and the Y latency is set to 2, values of B sampled on odd clock
cycles, starting from the first read are not considered.
40/59
M58LSW32A, M58LSW32B
Table 21. Synchronous Burst Read AC Characteristics
M58LSW32
Symbol
Parameter
Test Condition
Unit
120
10
10
10
10
10
10
20
10
0
150
10
10
10
10
10
10
20
10
0
t
E = V
E = V
Address Valid to Active Clock Edge
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVKH
IL
IL
t
Address Valid to Latch Enable High
AVLH
t
E = V , G = V , L = V
IL IL
Burst Address Advance High to Active Clock Edge
Burst Address Advance Low to Active Clock Edge
Chip Enable Low to Active Clock Edge
Chip Enable Low to Latch Enable High
Output Enable Low to Valid Clock Edge
Valid Clock Edge to Address Transition
Valid Clock Edge to Latch Enable Low
Valid Clock Edge to Latch Enable High
Valid Clock Edge to Output Transition
Latch Enable Low to Valid Clock Edge
Latch Enable Low to Latch Enable High
ValidClock Edge to Output Valid
BHKH
IH
IH
t
E = V , G = V , L = V
BLKH
IL
IL
IL
IL
t
E = V
E = V
ELKH
t
ELLH
t
E = V , L = V
IL IH
GLKH
t
E = V
E = V
E = V
KHAX
IL
IL
IL
t
KHLL
KHLH
t
0
0
t
E = V , G = V , L = V
3
3
KHQX
IL
IL
IL
IL
IH
t
E = V
E = V
10
10
20
5
10
10
20
5
LLKH
t
LLLH
KHQV
QVKH
t
t
E = V , G = V , L = V
IL IL
IH
IH
IH
IH
IH
E = V , G = V , L = V
Output Valid to Active Clock Edge
IL
IL
t
E = V , G = V , L = V
IL IL
Valid Data Ready Low to Valid Clock Edge
5
5
RLKH
t
Active Clock Edge to Burst Address Advance Low E = V , G = V , L = V
0
0
KHBL
KHBH
IL
IL
t
E = V , G = V , L = V
IL IL
Active Clock Edge to Burst Address Advance High
0
0
Note: For other timings see Table 16, Asynchronous Bus Read Characteristics.
41/59
M58LSW32A, M58LSW32B
Figure 21. Reset, Power-Down and Power-up AC Waveform
W, E, G
tPHWL
tPHEL
tPHGL
tRHWL
tRHEL
tRHGL
RB
tPLRH
tPHWL
tPHEL
tPHGL
RP
tVDHPH
tPLPH
VDD, VDDQ
Power-Up
Reset
AI03453
Table 22. Reset, Power-Down and Power-up AC Characteristics
M58LSW32
Symbol
Parameter
Unit
120
150
t
t
t
PHWL
Reset/Power-Down High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
Min
10
10
µs
PHEL
PHGL
t
t
RHWL
Ready/Busy High to Write Enable Low, Chip Enable Low, Output
Enable Low
(Program/Erase Controller Active)
t
10
10
µs
RHEL
RHGL
t
Reset/Power-Down Low to Reset/Power-Down High
Reset/Power-Down Low to Ready High
Min
Max
Min
100
30
1
100
30
1
ns
µs
µs
PLPH
t
PLRH
t
Supply Voltages High to Reset/Power-Down High
VDHPH
42/59
M58LSW32A, M58LSW32B
PACKAGE MECHANICAL
Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
A1
α
L
Note: Drawing is not to scale.
Table 23. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm
Min
inches
Min
Symbol
Typ
Max
1.20
0.15
1.05
0.27
0.21
20.20
18.50
14.10
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
0.5551
–
A
A1
A2
B
0.05
0.95
0.17
0.10
19.80
18.30
13.90
–
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
0.5472
–
C
D
D1
E
e
0.50
0.0197
L
0.50
0°
0.70
5°
0.0197
0°
0.0276
5°
α
N
56
56
CP
0.10
0.0039
43/59
M58LSW32A, M58LSW32B
Figure 23. TBGA64 - 8 x 8 ball array 1mm pitch, Package Outline
D
D1
FD
FE
SD
SE
E
E1
ddd
BALL ”A1”
A
e
b
A2
A1
BGA-Z23
Note: Drawing is not to scale.
Table 24. TBGA64 - 8 x 8 ball array, 1 mm pitch, Package Mechanical Data
millimeters
Symbol
inches
Min
Typ
Min
Max
1.200
0.350
0.850
0.500
10.100
–
Typ
Max
A
A1
A2
b
0.0472
0.300
0.200
0.0118
0.0079
0.0138
0.0335
0.400
9.900
–
0.0157
0.3898
–
0.0197
D
10.000
7.000
0.3937
0.2756
0.3976
D1
ddd
e
–
0.100
–
0.0039
1.000
13.000
7.000
1.500
3.000
0.500
0.500
–
0.0394
0.5118
0.2756
0.0591
0.1181
0.0197
0.0197
–
–
E
12.900
13.100
–
0.5079
0.5157
E1
FD
FE
SD
SE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
44/59
M58LSW32A, M58LSW32B
Figure 24. TBGA80 - 8 x 10 ball array, 1mm pitch, Package Outline
D
D1
FD
FE
SD
SE
E
E1
BALL ”A1”
ddd
e
e
b
A
A2
A1
BGA-Z27
Note: Drawing is not to scale.
Table 25. TBGA80 - 8 x 10 ball array, 1mm pitch, Package Mechanical Data
millimeters
Min
inches
Symbol
Typ
Max
1.200
0.350
0.850
0.500
10.100
–
Typ
Min
Max
A
A1
A2
b
0.0472
0.300
0.200
0.0118
0.0079
0.0138
0.0335
0.400
9.900
–
0.0157
0.3898
–
0.0197
D
10.000
7.000
0.3937
0.2756
0.3976
D1
ddd
E
–
0.100
13.100
–
0.0039
13.000
9.000
1.000
1.500
2.000
0.500
0.500
12.900
0.5118
0.3543
0.0394
0.0591
0.0787
0.0197
0.0197
0.5079
0.5157
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
–
–
–
–
45/59
M58LSW32A, M58LSW32B
PART NUMBERING
Table 26. Ordering Information Scheme
Example:
M58LSW32A
120
N
1
T
Device Type
M58
Architecture
L = Multi-Bit Cell or Multi-Bit Compatible, Burst Mode,
Page Mode
S = Special
Operating Voltage
W = V = 2.7V to 3.6V; V
= 1.8 to V
DD
DD
DDQ
Device Function
32A = 32 Mbit (x16), Equal Block, Boot Block
32B = 32 Mbit (x16/x32), Equal Block, Boot Block
Speed
120 = 120 ns
150 = 150 ns
Package
N = TSOP56: 14 x 20 mm (M58LSW32A)
ZA = TBGA64: 1mm pitch (M58LSW32A)
ZA = TBGA80: 1mm pitch (M58LSW32B)
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Note: Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
46/59
M58LSW32A, M58LSW32B
REVISION HISTORY
Table 27. Document Revision History
Date
Version
Revision Details
06-Apr-2001
05-Jun-2001
-01
First Issue.
150ns speed class added, corrections Figures 7 , 8, 9, 15, 16, 17 and 18.
-02
47/59
M58LSW32A, M58LSW32B
APPENDIX A. BLOCK ADDRESS TABLE
Table 28. Block Addresses
Block
Number
Address Range
(x16 Bus Width)
Address Range
(x32 Bus Width)
Block
Address Range
(x16 Bus Width)
Address Range
(x32 Bus Width)
Number
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
0F8000h-0FFFFFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
0A0000h-0A7FFFh
098000h-09FFFFh
090000h-097FFFh
088000h-08FFFFh
080000h-087FFFh
078000h-07FFFFh
070000h-077FFFh
068000h-06FFFFh
060000h-067FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
000000h-007FFFh
07C000h-07FFFFh
078000h-07BFFFh
074000h-077FFFh
070000h-073FFFh
06C000h-06FFFFh
068000h-06BFFFh
064000h-067FFFh
060000h-063FFFh
05C000h-05FFFFh
058000h-05BFFFh
054000h-057FFFh
050000h-053FFFh
04C000h-04FFFFh
048000h-04BFFFh
044000h-047FFFh
040000h-043FFFh
03C000h-03FFFFh
038000h-03BFFFh
034000h-037FFFh
030000h-033FFFh
02C000h-02FFFFh
028000h-02BFFFh
024000h-027FFFh
020000h-023FFFh
01C000h-01FFFFh
018000h-01BFFFh
014000h-017FFFh
010000h-013FFFh
00C000h-00FFFFh
008000h-00BFFFh
004000h-007FFFh
000000h-003FFFh
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1F8000h-1FFFFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
1A0000h-1A7FFFh
198000h-19FFFFh
190000h-197FFFh
188000h-18FFFFh
180000h-187FFFh
178000h-17FFFFh
170000h-177FFFh
168000h-16FFFFh
160000h-167FFFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
0FC000h-0FFFFFh
0F8000h-0FBFFFh
0F4000h-0F7FFFh
0F0000h-0F3FFFh
0EC000h-0EFFFFh
0E8000h-0EBFFFh
0E4000h-0E7FFFh
0E0000h-0E3FFFh
0DC000h-0DFFFFh
0D8000h-0DBFFFh
0D4000h-0D7FFFh
0D0000h-0D3FFFh
0CC000h-0CFFFFh
0C8000h-0CBFFFh
0C4000h-0C7FFFh
0C0000h-0C3FFFh
0BC000h-0BFFFFh
0B8000h-0BBFFFh
0B4000h-0B7FFFh
0B0000h-0B3FFFh
0AC000h-0AFFFFh
0A8000h-0ABFFFh
0A4000h-0A7FFFh
0A0000h-0A3FFFh
09C000h-09FFFFh
098000h-09BFFFh
094000h-097FFFh
090000h-093FFFh
08C000h-08FFFFh
088000h-08BFFFh
084000h-087FFFh
080000h-083FFFh
8
7
6
5
4
3
2
1
48/59
M58LSW32A, M58LSW32B
APPENDIX B. COMMON FLASH INTERFACE - CFI
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command (RCFI) is issued
the device enters CFI Query mode and the data
structure is read from the memory. Tables 29, 30,
31, 32, 33 and 34 show the addresses used to re-
trieve the data.
Table 29. Query Structure Overview
Offset
00h
Sub-section Name
Description
Manufacturer Code
01h
Device Code
10h
CFI Query Identification String
Command set ID and algorithm data offset
Device timing and voltage information
Flash memory layout
1Bh
27h
System Interface Information
Device Geometry Definition
Additional information specific to the Primary
Algorithm (optional)
(1)
Primary Algorithm-specific Extended Query table
Alternate Algorithm-specific Extended Query table
P(h)
Additional information specific to the Alternate
Algorithm (optional)
(2)
A(h)
(BA+2)h Block Status Register
Block-related Information
Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table.
2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
Table 30. CFI - Query Address and Data Output
(4)
Address
Data
Instruction
A21-A1 (M58LSW32A)
A21-A2 (M58LSW32B)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
51h
52h
59h
”Q”
”R”
”Y”
51h; ”Q”
52h; ”R”
59h; ”Y”
Query ASCII String
Primary Vendor:
20h
00h
31h
00h
00h
00h
31h
Command Set and Control Interface ID Code
Primary algorithm extended Query Address Table: P(h)
Alternate Vendor:
Command Set and Control Interface ID Code
Alternate Algorithm Extended Query address Table
(5)
00h
1Ah
Note: 1. The x8 or Byte Address mode is not available.
2. With the x16 Bus Width, the value of the address location of the CFI Query is independent of A1 pad (M58LSW32B).
3. Query Data are always presented on DQ7-DQ0. DQ31-DQ8 are set to ’0’.
4. For M58LSW32B, A1 = Don’t Care.
5. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
49/59
M58LSW32A, M58LSW32B
Table 31. CFI - Device Voltage and Timing Specification
(4)
Address
Data
Description
A21-A1 (M58LSW32A)
A21-A2 (M58LSW32B)
(1)
V
V
V
V
Min, 2.7V
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
DD
DD
PP
PP
27h
36h
00h
00h
00h
(1)
(2)
(2)
(3)
max, 3.6V
min – Not Available
max – Not Available
n
2 ms typical time-out for Word, DWord prog – Not Available
n
07h
0Ah
2 ms, typical time-out for max buffer write
n
2 ms, typical time-out for Erase Block
(3)
n
00h
00h
2 ms, typical time-out for chip erase – Not Available
(3)
n
2 x typical for Word Dword time-out max – Not Available
n
04h
04h
2 x typical for buffer write time-out max
n
2 x typical for individual block erase time-out maximum
(3)
n
00h
2 x typical for chip erase max time-out – Not Available
Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV.
3. Not supported.
4. For M58LSW32B, A1 = Don’t Care.
Table 32. Device Geometry Definition
(1)
Address
Data
Description
A21-A1 (M58LSW32A)
A21-A2 (M58LSW32B)
n
27h
17h
2 number of bytes memory Size
Device Interface Sync./Async.
Organization Sync./Async.
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
01h.
00h
05h
00h
01h
3Fh
00h
00h
02h
n
Maximum number of bytes in Write Buffer, 2
Bit7-0 = number of Erase Block Regions in device
Number (n-1) of Erase Blocks of identical size; n=64
Erase Block Region Information
Erase block (64K bytes)
Note: 1. For M58LSW32B, A1 = Don’t Care.
50/59
M58LSW32A, M58LSW32B
Table 33. Block Status Register
Address
A21-A1 (M58LSW32A)
A21-A2 (M58LSW32B)
Data
Selected Block Information
0
1
Block Unlocked
Block Locked
bit0
(2)
(1)
0
1
0
Last erase operation ended successfully
(BA+2)h
bit1
(2)
Last erase operation not ended successfully
Reserved for future features
bit7-2
Note: 1. BA specifies the block address location, A21-A17.
2. Not Supported.
Table 34. Extended Query information
M58LSW32B – x32 Bus Width
M58LSW32A – x16 Bus Width
M58LSW32B –
x16 Bus Width
Description
Address Address
Data (Hex)
Address
A21-A1
Data
offset
A21-A2
x32 Bus Width
(P)h
31h
50h
52h
49h
”P”
”R”
”Y”
62h, 63h
64h, 65h
66h, 67h
68h, 69h
6Ah, 6Bh
50h
52h
49h
31h
31h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
32h
Query ASCII string - Extended Table
33h
34h
31h
31h
Major version number
Minor version number
35h
Optional Feature: (1=yes, 0=no)
bit0, Chip Erase Supported (0=no)
bit1, Suspend Erase Supported (1=yes)
bit2, Suspend Program Supported (1=yes)
bit3, Lock/Unlock Supported (1=yes)
bit4, Queue Erase Supported (0=no)
Bit 31-5 reserved for future use
(P+5)h
36h
0Eh
6Ch, 6Dh
0Eh
(P+6)h
(P+7)h
(P+8)h
37h
38h
39h
00h
00h
00h
6Eh, 6Fh
70h, 71h
72h, 73h
00h
00h
00h
Optional Features
Function allowed after Suspend:
(P+9)h
3Ah
01h
74h, 75h
00h
Program allowed after Erase Suspend (1=yes)
Bit 7-1 reserved for future use
(2)
(2)
(P+A)h
3Bh
76h, 77h
Block Status Register Mask
00h
00h
33h
V
V
OPTIMUM Program/Erase voltage conditions
OPTIMUM Program/Erase voltage conditions
(P+C)h
(P+D)h
(P+E)h
(P+F)h
3Ch
3Dh
3Eh
3Fh
33h
50h
00h
00h
78h, 79h
7Ah, 7Bh
7Ch, 7Dh
7Dh, 7Fh
DD
PP
50h
00h
00h
Reserved for future use
Reserved for future use
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
2. Not supported.
51/59
M58LSW32A, M58LSW32B
APPENDIX C. FLOW CHARTS
Figure 25. Write to Buffer and Program Flowchart and Pseudo Code
Start
Write to Buffer E8h
Command, Block Address
Read Status
Register
NO
NO
YES
Write to Buffer
Timeout
b7 = 1
YES
Write Word or Double
Word, Block Address
Try Again Later
Write Buffer Data,
Start Address
X = 0
YES
X = N
NO
Write Next Buffer Data,
Device Address
X = X + 1
Program Buffer to Flash
Confirm D0h
Read Status
Register
NO
b7 = 1
YES
Full StatusCheck
(Optional)
End
AI03635
52/59
M58LSW32A, M58LSW32B
Figure 26. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
Read Status
Register
– read status register
NO
NO
b7 = 1
YES
while b7 = 1
If b4 = 0, Program completed
b2 = 1
YES
Program Complete
Read Memory Array instruction:
– write FFh
Write FFh
– one or more data reads
from other blocks
Read data from
another block
Program Erase Resume Command:
– write D0h
to resume erasure
– if the program operation completed
then this is not necessary. The device
returns to Read Array as normal
(as if the Program/Erase Suspend
command was not issued).
Write D0h
Write FFh
Read Data
Program Continues
AI00612
53/59
M58LSW32A, M58LSW32B
Figure 27. Erase Flowchart and Pseudo Code
Start
Erase command:
– write 20h
Write 20h
– write D0h to Block Address
(A12-A17)
(memory enters read Status
Register after the Erase command)
Write D0h to
Block Address
NO
do:
Read Status
– read status register
– if Program/Erase Suspend command
given execute suspend erase loop
Register
Suspend
YES
NO
Suspend
Loop
b7 = 1
while b7 = 1
YES
NO
NO
NO
NO
V
Invalid
If b3 = 1, V
invalid error:
– error handler
PP
Error (1)
PP
b3 = 0
YES
Command
Sequence Error
If b4, b5 = 1, Command Sequence error:
– error handler
b4, b5 = 0
YES
Erase
Error (1)
If b5 = 1, Erase error:
– error handler
b5 = 0
YES
Erase to Protected
Block Error
If b1 = 1, Erase to Protected Block Error:
– error handler
b1 = 0
YES
End
AI00613B
Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase oper-
ations.
54/59
M58LSW32A, M58LSW32B
Figure 28. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend Command:
– write B0h
– write 70h
Write 70h
do:
Read Status
Register
– read status register
NO
NO
b7 = 1
YES
while b7 = 1
If b6 = 0, Erase completed
b6 = 1
YES
Erase Complete
Read Memory Array command:
– write FFh
Write FFh
– one o more data reads
from other blocks
Read data from
another block
or Program
Program/Erase Resume command:
– write D0h to resume the Erase
operation
– if the Program operation completed
then this is not necessary. The device
returns to Read mode as normal
(as if the Program/Erase suspend
was not issued).
Write D0h
Write FFh
Read Data
Erase Continues
AI00615
55/59
M58LSW32A, M58LSW32B
Figure 29. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR
COMMAND
WRITE
NO
90h
YES
READ
SIGNATURE
NO
98h
YES
CFI
QUERY
NO
70h
YES
READ
ARRAY
READ
STATUS
NO
50h
YES
CLEAR
STATUS
NO
E8h
YES
PROGRAM
BUFFER
LOAD
NO
(1)
20h
YES
ERASE
NO
FFh
YES
SET-UP
NO
D0h
YES
C
NO
PROGRAM
COMMAND
ERROR
D0h
YES
ERASE
COMMAND
ERROR
A
B
AI03618
Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
56/59
M58LSW32A, M58LSW32B
Figure 30. Command Interface and Program Erase Controller Flowchart (b)
A
B
ERASE
(READ STATUS)
Program/Erase Controller
Status bit in the Status
Register
YES
READ
STATUS
READY
?
NO
READ
ARRAY
NO
B0h
YES
YES
READ
STATUS
NO
FFh
ERASE
SUSPEND
NO
YES
ERASE
SUSPENDED
READY
?
NO
READ
STATUS
YES
WAIT FOR
COMMAND
WRITE
YES
YES
YES
YES
READ
STATUS
70h
NO
READ
SIGNATURE
90h
NO
CFI
QUERY
98h
NO
PROGRAM
BUFFER
LOAD
E8h
NO
NO
PROGRAM
COMMAND
ERROR
YES
READ
STATUS
D0h
D0h
NO
(ERASE RESUME)
YES
READ
ARRAY
c
AI03619
57/59
M58LSW32A, M58LSW32B
Figure 31. Command Interface and Program Erase Controller Flowchart (c).
B
C
PROGRAM
(READ STATUS)
YES
Program/Erase Controller
Status bit in the Status
Register
READ
STATUS
READY
?
NO
READ
ARRAY
NO
B0h
YES
YES
NO
READ
STATUS
FFh
PROGRAM
SUSPEND
NO
YES
PROGRAM
SUSPENDED
READY
?
NO
YES
WAIT FOR
COMMAND
WRITE
READ
STATUS
YES
YES
YES
NO
READ
STATUS
70h
NO
READ
SIGNATURE
90h
NO
CFI
QUERY
98h
NO
YES
READ
ARRAY
READ
STATUS
D0h
(PROGRAM RESUME)
AI00618
58/59
M58LSW32A, M58LSW32B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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59/59
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