M58WR064FB60ZB6E_技术文档

M58WR064FT

M58WR064FB

64 Mbit (4Mb x16, Multiple Bank, Burst)

1.8V Supply Flash Memory

FEATURES SUMMARY

■

SUPPLY VOLTAGE

Figure 1. Package

–

V_DD= 1.7V to 2V for Program, Erase and

Read

–

V_DDQ= 1.7V to 2.24V for I/O Buffers

V_PP= 12V for fast Program (optional)

■

SYNCHRONOUS / ASYNCHRONOUS READ

–

Synchronous Burst Read mode: 66MHz

Asynchronous/ Synchronous Page Read

mode

FBGA

–

Random Access: 60ns, 70ns, 80ns

■

SYNCHRONOUS BURST READ SUSPEND

PROGRAMMING TIME

–

8µs by Word typical for Fast Factory

Program

Double/Quadruple Word Program option

Enhanced Factory Program options

VFBGA56 (ZB)

7.7 x 9 mm

–

■

MEMORY BLOCKS

–

Multiple Bank Memory Array: 4 Mbit

Banks

■

ELECTRONIC SIGNATURE

–

Parameter Blocks (Top or Bottom

location)

–

Manufacturer Code: 20h

Device Codes:

M58WR064FT (Top): 8810h

M58WR064FB (Bottom): 8811h

DUAL OPERATIONS

–

Program Erase in one Bank while Read in

others

PACKAGE

–

No delay between Read and Write

operations

–

Compliant with Lead-Free Soldering

Processes

■

BLOCK LOCKING

–

Lead-Free Versions

–

All blocks locked at Power up

Any combination of blocks can be locked

WP for Block Lock-Down

SECURITY

–

128 bit user programmable OTP cells

64 bit unique device number

■

COMMON FLASH INTERFACE (CFI)

100,000 PROGRAM/ERASE CYCLES per

BLOCK

October 2004

1/87

M58WR064FT, M58WR064FB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. VFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

_DDSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

_DDQSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V_PPProgram Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

V_SSQGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/87

M58WR064FT, M58WR064FB

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Protection Register Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Lock Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Quadruple Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Factory Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program/Erase Controller Status Bit (SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

V

_PPStatus Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Program Suspend Status Bit (SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Wait Polarity Bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3/87

M58WR064FT, M58WR064FB

Data Output Configuration Bit (CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Burst length Bits (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9. Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Synchronous Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Unlocked State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. Program/Erase Times and Endurance Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 15. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 16. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 17. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 18. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 19. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 10.Asynchronous Random Access Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 11.Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 20. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4/87

M58WR064FT, M58WR064FB

Figure 12.Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 13.Single Synchronous Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 14.Synchronous Burst Read Suspend AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 15.Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 21. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 16.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 22. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 17.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 23. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 18.Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 19.VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline . . . 53

Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data . . . . . . 53

Figure 20.VFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 54

Figure 21.VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . . 55

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

APPENDIX A.BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 28. Top Boot Block Addresses, M58WR064FT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 29. Bottom Boot Block Addresses, M58WR064FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

APPENDIX B.COMMON FLASH INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 31. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 33. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 35. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 36. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 37. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 38. Bank and Erase Block Region 1 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 39. Bank and Erase Block Region 2 Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

APPENDIX C.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 23.Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 24.Quadruple Word Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 25.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 73

Figure 26.Block Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 27.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 75

5/87

M58WR064FT, M58WR064FB

Figure 28.Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 29.Protection Register Program Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . 77

Figure 30.Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 31.Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Quadruple Enhanced Factory Program Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

APPENDIX D.COMMAND INTERFACE STATE TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 40. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 41. Command Interface States - Modify Table, Next Output. . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 42. Command Interface States - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 43. Command Interface States - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 85

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Table 44. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6/87

M58WR064FT, M58WR064FB

SUMMARY DESCRIPTION

The M58WR064FT/B is a 64 Mbit (4Mbit x16) non-

volatile Flash memory that may be erased electri-

cally at block level and programmed in-system on

a Word-by-Word basis using a 1.7V to 2V V_DD

supply for the circuitry and a 1.7V to 2.24V V_DDQ

supply for the Input/Output pins. An optional 12V

V_PPpower supply is provided to speed up custom-

er programming. The V_PPpin can also be used as

a control pin to provide absolute protection against

program or erase.

The device features an asymmetrical block archi-

tecture. M58WR064FT/B has an array of 135

blocks, and is divided into 4 Mbit banks. There are

15 banks each containing 8 main blocks of 32

KWords, and one parameter bank containing 8 pa-

rameter blocks of 4 KWords and 7 main blocks of

32 KWords. The Multiple Bank Architecture allows

Dual Operations, while programming or erasing in

one bank, Read operations are possible in other

banks. Only one bank at a time is allowed to be in

Program or Erase mode. It is possible to perform

burst reads that cross bank boundaries. The bank

architecture is summarized in Table 2., and the

memory maps are shown in Figure 4. The Param-

eter Blocks are located at the top of the memory

address space for the M58WR064FT, and at the

bottom for the M58WR064FB.

The device supports Synchronous Burst Read and

Asynchronous Read from all blocks of the memory

array; at power-up the device is configured for

Asynchronous Read. In Synchronous Burst mode,

data is output on each clock cycle at frequencies

of up to 66MHz. The Synchronous Burst Read op-

eration can be suspended and resumed.

The device features an Automatic Standby mode.

When the bus is inactive during Asynchronous

Read operations, the device automatically switch-

es to the Automatic Standby mode. In this condi-

tion the power consumption is reduced to the

standby value I_DD4and the outputs are still driven.

The M58WR064FT/B features an instant, individu-

al block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

When V_PP≤ V_PPLKall blocks are protected against

program or erase. All blocks are locked at Power-

Up.

The device includes a Protection Register to in-

crease the protection of a system’s design. The

Protection Register is divided into two segments:

a 64 bit segment containing a unique device num-

ber written by ST, and a 128 bit segment One-

Time-Programmable (OTP) by the user. The user

programmable segment can be permanently pro-

tected. Figure 5. shows the Protection Register

Memory Map.

Each block can be erased separately. Erase can

be suspended, in order to perform program in any

other block, and then resumed. Program can be

suspended to read data in any other block and

then resumed. Each block can be programmed

and erased over 100,000 cycles using the supply

voltage V_DD. There are two Enhanced Factory

programming commands available to speed up

programming.

The memory is offered in a VFBGA56, 7.7 x 9mm,

8x7 active ball array, 0.75 mm pitch package.

In addition to the standard version, the package is

also available in Lead-free version, in compliance

with JEDEC Std J-STD-020B, the ST ECOPACK

7191395 Specification, and the RoHS (Restriction

of Hazardous Substances) directive. All packages

are compliant with Lead-free soldering processes.

Program and Erase commands are written to the

Command Interface of the memory. An internal

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified in the

Status Register. The command set required to

control the memory is consistent with JEDEC stan-

dards.

The memory is supplied with all the bits erased

(set to ’1’).

7/87

M58WR064FT, M58WR064FB

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A21

Address Inputs

Data Input/Outputs, Command

Inputs

DQ0-DQ15

V

DD DDQ PP

E

Chip Enable

Output Enable

Write Enable

Reset

22

16

G

A0-A21

DQ0-DQ15

WAIT

W

E

RP

WP

K

M58WR064FT

M58WR064FB

Write Protect

Clock

G

RP

WP

L

Latch Enable

Wait

WAIT

V

Supply Voltage

DD

K

Supply Voltage for Input/Output

Buffers

V

DDQ

PP

V

SSQ

SS

Optional Supply Voltage for

Fast Program & Erase

AI07747c

V

Ground

SS

Ground Input/Output Supply

Not Connected Internally

SSQ

NC

8/87

M58WR064FT, M58WR064FB

Figure 3. VFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

A11

A12

A13

A15

A8

A9

V

A18

A17

A19

WP

A6

A5

A4

A3

A2

A1

A0

G

SS

DD

K

PP

A20

A21

RP

W

A10

L

A7

A14

WAIT

DQ6

DQ13

DQ5

A16

DQ4

DQ12

DQ2

DQ10

DQ3

NC

E

V

DQ15

DQ14

DQ1

DQ9

DDQ

V

DQ11

DQ0

DQ8

SS

G

DQ7

V

SSQ

DD

DDQ

AI06189

Table 2. Bank Architecture

Number

Bank Size

Parameter Blocks

Main Blocks

Parameter Bank

4 Mbits

8 blocks of 4 KWords

7 blocks of 32 KWords

8 blocks of 32 KWords

Bank 1

Bank 2

Bank 3

-

Bank 14

Bank 15

4 Mbits

-

8 blocks of 32 KWords

9/87

M58WR064FT, M58WR064FB

Figure 4. Memory Map

M58WR064FT - Top Boot Block

M58WR064FB - Bottom Boot Block

Address lines A21-A0

000000h

007FFFh

000000h

000FFFh

32 KWord

4 KWord

8 Main

Blocks

8 Parameter

Blocks

Bank 15

038000h

03FFFFh

007000h

007FFFh

008000h

00FFFFh

32 KWord

4KWord

Parameter

Bank

32 KWord

7 Main

Blocks

038000h

03FFFFh

040000h

047FFFh

32 KWord

300000h

307FFFh

32 KWord

8 Main

Blocks

8 Main

Blocks

Bank 3

Bank 2

Bank 1

Bank 2

Bank 3

338000h

33FFFFh

340000h

347FFFh

078000h

07FFFFh

080000h

087FFFh

32 KWord

8 Main

Blocks

8 Main

Blocks

378000h

37FFFFh

380000h

387FFFh

0B8000h

0BFFFFh

0C0000h

0C7FFFh

32 KWord

8 Main

Blocks

8 Main

Blocks

3B8000h

3BFFFFh

3C0000h

3C7FFFh

0F8000h

0FFFFFh

32 KWord

7 Main

Blocks

3F0000h

3F7FFFh

3F8000h

3F8FFFh

32 KWord

4 KWord

Parameter

Bank

3C0000h

3C7FFFh

32 KWord

8 Parameter

Blocks

8 Main

Blocks

Bank 15

3FF000h

3FFFFFh

3F8000h

3FFFFFh

4 KWord

AI07748c

10/87

M58WR064FT, M58WR064FB

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram and Table 1., Signal

Names, for a brief overview of the signals connect-

ed to this device.

Latch Enable (L). Latch Enable latches the ad-

dress bits on its rising edge. The address

latch is transparent when Latch Enable is at

V_ILand it is inhibited when Latch Enable is at

V_IH. Latch Enable can be kept Low (also at

board level) when the Latch Enable function

is not required or supported.

Clock (K). The clock input synchronizes the

memory to the microcontroller during synchronous

read operations; the address is latched on a Clock

edge (rising or falling, according to the configura-

tion settings) when Latch Enable is at V_IL. Clock is

don't care during asynchronous read and in write

operations.

Address Inputs (A0-A21). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

Data Input/Output (DQ0-DQ15). The Data I/O

output the data stored at the selected address dur-

ing a Bus Read operation or input a command or

the data to be programmed during a Bus Write op-

eration.

Wait (WAIT). Wait is an output signal used during

synchronous read to indicate whether the data on

the output bus are valid. This output is high imped-

ance when Chip Enable is at V_IHor Reset is at V_IL.

It can be configured to be active during the wait cy-

cle or one clock cycle in advance. The WAIT signal

is not gated by Output Enable.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

at V_ILand Reset is at V_IHthe device is in active

mode. When Chip Enable is at V_IHthe memory is

deselected, the outputs are high impedance and

the power consumption is reduced to the standby

level.

V_DDSupply Voltage . V_DDprovides the power

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

Output Enable (G). The Output Enable input

controls data outputs during the Bus Read opera-

tion of the memory.

V

_DDQSupply Voltage. V_DDQprovides the power

Write Enable (W). The Write Enable input con-

trols the Bus Write operation of the memory’s

Command Interface. The data and address inputs

are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.

supply to the I/O pins and enables all Outputs to

be powered independently of V_DD. V_DDQcan be

tied to V_DDor can use a separate supply.

V_PPProgram Supply Voltage. V_PPis a power

supply pin. The Supply Voltage V_DDand the Pro-

gram Supply Voltage V_PPcan be applied in any or-

der. The pin can also be used as a control input.

Write Protect (WP). Write Protect is an input

that gives an additional hardware protection for

each block. When Write Protect is at V_IL, the Lock-

Down is enabled and the protection status of the

Locked-Down blocks cannot be changed. When

Write Protect is at V_IH, the Lock-Down is disabled

and the Locked-Down blocks can be locked or un-

locked. (refer to Table 13., Lock Status).

Reset (RP). The Reset input provides a hard-

ware reset of the memory. When Reset is at V_IL,

the memory is in reset mode: the outputs are high

impedance and the current consumption is re-

duced to the Reset Supply Current I_DD2. Refer to

Table 18., DC Characteristics - Currents, for the

value of I_DD2.After Reset all blocks are in the

Locked state and the Configuration Register is re-

set. When Reset is at V_IH, the device is in normal

operation. Exiting reset mode the device enters

asynchronous read mode, but a negative transi-

tion of Chip Enable or Latch Enable is required to

ensure valid data outputs.

In the device the two functions are selected by the

voltage range applied to the pin. If V_PPis kept in a

low voltage range (0V to V_DDQ) V_PPis seen as a

control input. In this case a voltage lower than V_P-

_PLKgives an absolute protection against program

or erase, while V_PP> V_PP1enables these func-

tions (see Tables 18 and 19, DC Characteristics

for the relevant values). V_PPis only sampled at the

beginning of a program or erase; a change in its

value after the operation has started does not

have any effect and program or erase operations

continue.

If V_PPis in the range of V_PPHit acts as a power

supply pin. In this condition V_PPmust be stable un-

til the Program/Erase algorithm is completed.

V_SSGround. V_SSground is the reference for the

core supply. It must be connected to the system

ground.

The Reset pin can be interfaced with 3V logic with-

out any additional circuitry. It can be tied to V_RPH

(refer to Table 19., DC Characteristics - Voltages).

V

_SSQGround. V_SSQground is the reference for

the input/output circuitry driven by V_DDQ. V_SSQ

must be connected to V_SS

11/87

M58WR064FT, M58WR064FB

Note: Each device in a system should have

age). See Figure 9., AC Measurement Load Cir-

cuit. The PCB track widths should be sufficient

to carry the required V_PPprogram and erase

currents.

V

_DD, V_DDQand V_PPdecoupled with a 0.1µF ce-

ramic capacitor close to the pin (high frequen-

cy, inherently low inductance capacitors

should be as close as possible to the pack-

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Ad-

dress Latch, Output Disable, Standby and Reset.

See Table 3., Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect Bus Write operations.

the Latch Enable should be tied to V_IHduring the

bus write operation.

See Figures 16 and 17, Write AC Waveforms, and

Tables 22 and 23, Write AC Characteristics, for

details of the timing requirements.

Address Latch. Address latch operations input

valid addresses. Both Chip enable and Latch En-

able must be at V_ILduring address latch opera-

tions. The addresses are latched on the rising

edge of Latch Enable.

Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Elec-

tronic Signature, the Status Register and the

Common Flash Interface. Both Chip Enable and

Output Enable must be at V_ILin order to perform a

read operation. The Chip Enable input should be

used to enable the device. Output Enable should

be used to gate data onto the output. The data

read depends on the previous command written to

the memory (see Command Interface section).

See Figures 10, 11, 12 and 13 Read AC Wave-

forms, and Tables 20 and 21 Read AC Character-

istics, for details of when the output becomes

valid.

Bus Write. Bus Write operations write Com-

mands to the memory or latch Input Data to be

programmed. A bus write operation is initiated

when Chip Enable and Write Enable are at V_ILwith

Output Enable at V_IH. Commands, Input Data and

Addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first. The

addresses can also be latched prior to the write

operation by toggling Latch Enable. In this case

Output Disable. The outputs are high imped-

ance when the Output Enable is at V_IH.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

when Chip Enable and Reset are at V_IH. The pow-

er consumption is reduced to the stand-by level

and the outputs are set to high impedance, inde-

pendently from the Output Enable or Write Enable

inputs. If Chip Enable switches to V_IHduring a pro-

gram or erase operation, the device enters Stand-

by mode when finished.

Reset. During Reset mode the memory is dese-

lected and the outputs are high impedance. The

memory is in Reset mode when Reset is at V_IL.

The power consumption is reduced to the Standby

level, independently from the Chip Enable, Output

Enable or Write Enable inputs. If Reset is pulled to

V_SSduring a Program or Erase, this operation is

aborted and the memory content is no longer valid.

Table 3. Bus Operations

(4)

Operation

Bus Read

E

G

W

L

RP

DQ15-DQ0

Data Output

Data Input

WAIT

(2)

V

IL

IH

V

IH

IL

(2)

V

Bus Write

IH

IL

IH

IL

(3)

V

Address Latch

Output Disable

Standby

X

IL

IH

IL

IH

Data Output or Hi-Z

V

X

Hi-Z

IH

V

X

Hi-Z

IH

V

IL

Reset

X

Note: 1. X = Don't care.

2. L can be tied to V if the valid address has been previously latched.

IH

3. Depends on G.

4. WAIT signal polarity is configured using the Set Configuration Register command.

12/87

M58WR064FT, M58WR064FB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time to monitor

the progress or the result of the operation.

Table 4. Command Codes

Hex Code

01h

Command

Block Lock Confirm

03h

Set Configuration Register Confirm

Alternative Program Setup

Block Erase Setup

10h

20h

The Command Interface is reset to read mode

when power is first applied, when exiting from Re-

set or whenever V_DDis lower than V_LKO. Com-

mand sequences must be followed exactly. Any

invalid combination of commands will be ignored.

Refer to Table 4., Command Codes, and APPEN-

DIX D., Tables 40, 41, 42 and 43, Command Inter-

face States - Modify and Lock Tables, for a

summary of the Command Interface.

2Fh

Block Lock-Down Confirm

Enhanced Factory Program Setup

Double Word Program Setup

Program Setup

30h

35h

40h

50h

Clear Status Register

56h

Quadruple Word Program Setup

The Command Interface is split into two types of

commands: Standard commands and Factory

Program commands. The following sections ex-

plain in detail how to perform each command.

Block Lock Setup, Block Unlock Setup,

Block Lock Down Setup and Set

Configuration Register Setup

60h

70h

75h

Read Status Register

Quadruple Enhanced Factory Program

Setup

80h

90h

98h

B0h

C0h

Bank Erase Setup

Read Electronic Signature

Read CFI Query

Program/Erase Suspend

Protection Register Program

Program/Erase Resume, Block Erase

Confirm, Bank Erase Confirm, Block

Unlock Confirm or Enhanced Factory

Program Confirm

D0h

FFh

Read Array

13/87

M58WR064FT, M58WR064FB

COMMAND INTERFACE - STANDARD COMMANDS

The following commands are the basic commands

used to read, write to and configure the device.

Refer to Table 5., Standard Commands, in con-

junction with the following text descriptions.

Read CFI Query Command

The Read CFI Query command is used to read

data from the Common Flash Interface (CFI). The

Read CFI Query Command consists of one Bus

Write cycle, to an address within one of the banks.

Once the command is issued subsequent Bus

Read operations in the same bank read from the

Common Flash Interface.

If a Read CFI Query command is issued in a bank

that is executing a Program or Erase operation the

bank will go into Read CFI Query mode, subse-

quent Bus Read cycles will output the CFI data

and the Program/Erase controller will continue to

Program or Erase in the background. This mode

supports asynchronous or single synchronous

reads only, it does not support page mode or syn-

chronous burst reads.

Read Array Command

The Read Array command returns the addressed

bank to Read Array mode. One Bus Write cycle is

required to issue the Read Array command and re-

turn the addressed bank to Read Array mode.

Subsequent read operations will read the ad-

dressed location and output the data. A Read Ar-

ray command can be issued in one bank while

programming or erasing in another bank. However

if a Read Array command is issued to a bank cur-

rently executing a Program or Erase operation the

command will be executed but the output data is

not guaranteed.

Read Status Register Command

The status of the other banks is not affected by the

command (see Table 11.). After issuing a Read

CFI Query command, a Read Array command

should be issued to the addressed bank to return

the bank to Read Array mode.

See APPENDIX B., COMMON FLASH INTER-

FACE, Tables 30, 31, 32, 33, 34, 35, 36, 37, 38

and 39 for details on the information contained in

the Common Flash Interface memory area.

The Status Register indicates when a Program or

Erase operation is complete and the success or

failure of operation itself. Issue a Read Status

Register command to read the Status Register

content. The Read Status Register command can

be issued at any time, even during Program or

Erase operations.

The following read operations output the content

of the Status Register of the addressed bank. The

Status Register is latched on the falling edge of E

or G signals, and can be read until E or G returns

to V_IH. Either E or G must be toggled to update the

latched data. See Table 8. for the description of

the Status Register Bits. This mode supports

asynchronous or single synchronous reads only.

Clear Status Register Command

The Clear Status Register command can be used

to reset (set to ‘0’) error bits SR1, SR3, SR4 and

SR5 in the Status Register. One bus write cycle is

required to issue the Clear Status Register com-

mand. The Clear Status Register command does

not change the Read mode of the bank.

The error bits in the Status Register do not auto-

matically return to ‘0’ when a new command is is-

sued. The error bits in the Status Register should

be cleared before attempting a new Program or

Erase command.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes, the Block

Locking Status, the Protection Register, and the

Configuration Register.

The Read Electronic Signature command consists

of one write cycle to an address within one of the

banks. A subsequent Read operation in the same

bank will output the Manufacturer Code, the De-

vice Code, the protection Status of the blocks in

the targeted bank, the Protection Register, or the

Configuration Register (see Table 6.).

If a Read Electronic Signature command is issued

in a bank that is executing a Program or Erase op-

eration the bank will go into Read Electronic Sig-

nature mode, subsequent Bus Read cycles will

output the Electronic Signature data and the Pro-

gram/Erase controller will continue to program or

erase in the background. This mode supports

asynchronous or single synchronous reads only, it

does not support page mode or synchronous burst

reads.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error. The Block

Erase command can be issued at any moment, re-

gardless of whether the block has been pro-

grammed or not.

Two Bus Write cycles are required to issue the

command.

■

The first bus cycle sets up the Erase

command.

■

The second latches the block address in the

Program/Erase Controller and starts it.

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M58WR064FT, M58WR064FB

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits SR4 and SR5 are set

and the command aborts. Erase aborts if Reset

turns to V_IL. As data integrity cannot be guaran-

teed when the Erase operation is aborted, the

block must be erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register mode un-

til a Read Array, Read CFI Query or Read Elec-

tronic Signature command is issued.

During Erase operations the bank containing the

block being erased will only accept the Read Ar-

ray, Read Status Register, Read Electronic Signa-

ture, Read CFI Query and the Program/Erase

Suspend command, all other commands will be ig-

nored. Refer to Dual Operations section for de-

tailed information about simultaneous operations

allowed in banks not being erased. Typical Erase

times are given in Table 14., Program/Erase

Times and Endurance Cycles.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Block Erase operation. A

Bank Erase operation cannot be suspended.

One bus write cycle is required to issue the Pro-

gram/Erase command. Once the Program/Erase

Controller has paused bits SR7, SR6 and/ or SR2

of the Status Register will be set to ‘1’. The com-

mand can be addressed to any bank.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array (cannot read the erase-suspended

block or the program-suspended Word), Read

Status Register, Read Electronic Signature and

Read CFI Query commands. Additionally, if the

suspend operation was Erase then the Clear sta-

tus Register, Program, Block Lock, Block Lock-

Down or Block Unlock commands will also be ac-

cepted. The block being erased may be protected

by issuing the Block Lock, Block Lock-Down or

Protection Register Program commands. Only the

blocks not being erased may be read or pro-

grammed correctly. When the Program/Erase Re-

sume command is issued the operation will

complete. Refer to the Dual Operations section for

detailed information about simultaneous opera-

tions allowed during Program/Erase Suspend.

See APPENDIX C., Figure 26., Block Erase Flow-

chart and Pseudo Code, for a suggested flowchart

for using the Block Erase command.

Program Command

The memory array can be programmed word-by-

word. Only one Word in one bank can be pro-

grammed at any one time. Two bus write cycles

are required to issue the Program Command.

During a Program/Erase Suspend, the device can

be placed in standby mode by taking Chip Enable

to V_IH. Program/Erase is aborted if Reset turns to

V_IL.

See APPENDIX C., Figure 25., Program Suspend

& Resume Flowchart and Pseudo Code, and Fig-

ure 27., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Suspend command.

■

The first bus cycle sets up the Program

command.

■

The second latches the Address and the Data

to be written and starts the Program/Erase

Controller.

After programming has started, read operations in

the bank being programmed output the Status

Register content.

Program/Erase Resume Command

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend command has paused

it. One Bus Write cycle is required to issue the

command. The command can be written to any

address.

The Program/Erase Resume command does not

change the read mode of the banks. If the sus-

pended bank was in Read Status Register, Read

Electronic signature or Read CFI Query mode the

bank remains in that mode and outputs the corre-

sponding data. If the bank was in Read Array

mode subsequent read operations will output in-

valid data.

If a Program command is issued during a Block

Erase Suspend, then the erase cannot be re-

sumed until the programming operation has com-

pleted. It is possible to accumulate suspend

operations. For example: suspend an erase oper-

ation, start a programming operation, suspend the

During Program operations the bank being pro-

grammed will only accept the Read Array, Read

Status Register, Read Electronic Signature, Read

CFI Query and the Program/Erase Suspend com-

mand. Refer to Dual Operations section for de-

tailed information about simultaneous operations

allowed in banks not being programmed. Typical

Program times are given in Table 14., Program/

Erase Times and Endurance Cycles.

Programming aborts if Reset goes to V_IL. As data

integrity cannot be guaranteed when the program

operation is aborted, the memory location must be

reprogrammed.

See APPENDIX C., Figure 22., Program Flow-

chart and Pseudo Code, for the flowchart for using

the Program command.

15/87

M58WR064FT, M58WR064FB

programming operation then read the array. See

APPENDIX C., Figure 25., Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

27., Erase Suspend & Resume Flowchart and

Pseudo Code, for flowcharts for using the Pro-

gram/Erase Resume command.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

Protection Register Program Command

The Protection Register Program command is

used to Program the 128 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister and the Protection Register Lock. The

segment is programmed 16 bits at a time. When

shipped all bits in the segment are set to ‘1’. The

user can only program the bits to ‘0’.

■

The first bus cycle sets up the Block Lock

command.

The second Bus Write cycle latches the block

address.

■

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 13. shows the Lock Status after issuing a

Block Lock command.

Two write cycles are required to issue the Protec-

tion Register Program command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Block Unlock

command. Refer to the section, Block Locking, for

a detailed explanation. See APPENDIX C., Figure

28., Locking Operations Flowchart and Pseudo

Code, for a flowchart for using the Lock command.

■

The first bus cycle sets up the Protection

Register Program command.

The second latches the Address and the Data

to be written to the Protection Register and

starts the Program/Erase Controller.

■

Read operations output the Status Register con-

tent after the programming has started.

Block Unlock Command

The segment can be protected by programming bit

1 of the Protection Lock Register (see Figure

5., Protection Register Memory Map). Attempting

to program a previously protected Protection Reg-

ister will result in a Status Register error. The pro-

tection of the Protection Register is not reversible.

The Block Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Block Unlock command.

■

The first bus cycle sets up the Block Unlock

command.

The Protection Register Program cannot be sus-

■

The second Bus Write cycle latches the block

address.

pended.

See

APPENDIX

C.,

Figure

29., Protection Register Program Flowchart and

Pseudo Code, for a flowchart for using the Protec-

tion Register Program command.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table 13. shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation and AP-

PENDIX C., Figure 28., Locking Operations Flow-

chart and Pseudo Code, for a flowchart for using

the Unlock command.

Set Configuration Register Command

The Set Configuration Register command is used

to write a new value to the Configuration Register

which defines the burst length, type, X latency,

Synchronous/Asynchronous Read mode and the

valid Clock edge configuration.

Two Bus Write cycles are required to issue the Set

Configuration Register command.

Block Lock-Down Command

A locked or unlocked block can be locked-down by

issuing the Block Lock-Down command. A locked-

down block cannot be programmed or erased, or

have its protection status changed when WP is

low, V_IL. When WP is high, V_IH,the Lock-Down

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

■

The first cycle writes the setup command and

the address corresponding to the

Configuration Register content.

■

The second cycle writes the Configuration

Register data and the confirm command.

Read operations output the memory array content

after the Set Configuration Register command is

issued.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

The value for the Configuration Register is always

presented on A0-A15. CR0 is on A0, CR1 on A1,

etc.; the other address bits are ignored.

■

The first bus cycle sets up the Block Lock

command.

The second Bus Write cycle latches the block

address.

■

16/87

M58WR064FT, M58WR064FB

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table 13. shows the Lock Status af-

ter issuing a Block Lock-Down command. Refer to

the section, Block Locking, for a detailed explana-

tion and APPENDIX C., Figure 28., Locking Oper-

ations Flowchart and Pseudo Code, for a flowchart

for using the Lock-Down command.

Table 5. Standard Commands

Commands

Bus Operations

1st Cycle

Add

2nd Cycle

Add

Op.

Write

Data

FFh

70h

90h

98h

50h

20h

Op.

Data

RD

Read Array

1+

1

BKA

WA

Read

(2)

Read Status Register

Read Electronic Signature

Read CFI Query

SRD

ESD

QD

BKA

(2)

BKA

(2)

BKA

Clear Status Register

Block Erase

BKA

(3)

2

Write

BA

D0h

PD

BKA or BA

Program

2

1

2

Write

40h or 10h

B0h

WA

BKA or WA

Program/Erase Suspend

Program/Erase Resume

Protection Register Program

Set Configuration Register

X

D0h

PRA

CRD

C0h

Write

PRA

CRD

BA

PRD

03h

01h

60h

(3)

Block Lock

2

Write

60h

BKA or BA

(3)

Block Unlock

Block Lock-Down

Write

BA

D0h

2Fh

Note: 1. X = Don't Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data,

QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection

Register Data, CRD=Configuration Register Data.

2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6.

3. Any address within the bank can be used.

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M58WR064FT, M58WR064FB

Table 6. Electronic Signature Codes

Code

Address (h)

Data (h)

0020

Manufacturer Code

Bank Address + 00

Bank Address + 01

Top (M58WR064FT)

8810

Device Code

Bottom(M58WR064FB)

Locked

8811

0001

Unlocked

0000

Block Protection

Block Address + 02

Locked and Locked-Down

Unlocked and Locked-Down

0003

0002

Reserved

Bank Address + 03

Bank Address + 05

Reserved

CR

Configuration Register

ST Factory Default

0002

Protection Register Lock

Bank Address + 80

OTP Area Permanently Locked

0000

Bank Address + 81 Unique Device

Bank Address + 84

Number

Protection Register

Bank Address + 85

Bank Address + 8C

OTP Area

Note: CR=Configuration Register.

Figure 5. Protection Register Memory Map

PROTECTION REGISTER

8Ch

User Programmable OTP

Unique device number

85h

84h

81h

80h

Protection Register Lock

1

0

AI08149

18/87

M58WR064FT, M58WR064FB

COMMAND INTERFACE - FACTORY PROGRAM COMMANDS

The Factory Program commands are used to

speed up programming. They require V_PPto be at

V_PPHexcept for the Bank Erase command which

also operates at V_PP= V_DD. Refer to Table

7., Factory Program Commands, in conjunction

with the following text descriptions.

Dual Operations are not supported during Bank

Erase operations and the command cannot be

suspended.

Typical Erase times are given in Table

14., Program/Erase Times and Endurance Cy-

cles.

The use of Factory Program commands requires

certain operating conditions.

Double Word Program Command

The Double Word Program command improves

the programming throughput by writing a page of

two adjacent words in parallel. The two words

must differ only for the address A0.

Three bus write cycles are necessary to issue the

Double Word Program command.

■

V_PPmust be set to V_PPH(except for Bank

Erase comand),

■

V_DDmust be within operating range,

Ambient temperature, T_Amust be 25°C ± 5°C,

The targeted block must be unlocked.

■

The first bus cycle sets up the Double Word

Program Command.

The second bus cycle latches the Address and

the Data of the first word to be written.

The third bus cycle latches the Address and

the Data of the second word to be written and

starts the Program/Erase Controller.

Bank Erase Command

The Bank Erase command can be used to erase a

bank. It sets all the bits within the selected bank to

’1’. All previous data in the bank is lost. The Bank

Erase command will ignore any protected blocks

within the bank. If all blocks in the bank are pro-

tected then the Bank Erase operation will abort

and the data in the bank will not be changed. The

Status Register will not output any error.

Read operations in the bank being programmed

output the Status Register content after the pro-

gramming has started.

Bank Erase operations can be performed at both

V_PP= V_PPHand V_PP= V_DD.

During Double Word Program operations the bank

being programmed will only accept the Read Ar-

ray, Read Status Register, Read Electronic Signa-

ture and Read CFI Query command, all other

commands will be ignored. Dual operations are

not supported during Double Word Program oper-

ations and the command cannot be suspended.

Typical Program times are given in Table

14., Program/Erase Times and Endurance Cy-

cles.

Programming aborts if Reset goes to V_IL. As data

integrity cannot be guaranteed when the program

operation is aborted, the memory locations must

be reprogrammed.

Two Bus Write cycles are required to issue the

command.

■

The first bus cycle sets up the Bank Erase

command.

■

The second latches the bank address in the

Program/Erase Controller and starts it.

If the second bus cycle is not Write Bank Erase

Confirm (D0h), Status Register bits SR4 and SR5

are set and the command aborts. Erase aborts if

Reset turns to V_IL. As data integrity cannot be

guaranteed when the Erase operation is aborted,

the bank must be erased again.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read. At the end of the operation the

bank will remain in Read Status Register mode un-

til a Read Array, Read CFI Query or Read Elec-

tronic Signature command is issued.

During Bank Erase operations the bank being

erased will only accept the Read Array, Read Sta-

tus Register, Read Electronic Signature and Read

CFI Query command, all other commands will be

ignored.

See APPENDIX C., Figure 23., Double Word Pro-

gram Flowchart and Pseudo code, for the flow-

chart for using the Double Word Program

command.

Quadruple Word Program Command

The Quadruple Word Program command im-

proves the programming throughput by writing a

page of four adjacent words in parallel. The four

words must differ only for the addresses A0 and

A1.

Five bus write cycles are necessary to issue the

Quadruple Word Program command.

For optimum performance, Bank Erase com-

mands should be limited to a maximum of 100 Pro-

gram/Erase cycles per Block. After 100 Program/

Erase cycles the internal algorithm will still operate

properly but some degradation in performance

may occur.

■

The first bus cycle sets up the Double Word

Program Command.

■

The second bus cycle latches the Address and

the Data of the first word to be written.

19/87

M58WR064FT, M58WR064FB

■

The third bus cycle latches the Address and

the Data of the second word to be written.

The fourth bus cycle latches the Address and

the Data of the third word to be written.

The fifth bus cycle latches the Address and the

Data of the fourth word to be written and starts

the Program/Erase Controller.

■

The first bus cycle sets up the Enhanced

Factory Program command.

The second bus cycle confirms the command.

The Status Register P/E.C. Bit SR7 should be

read to check that the P/E.C. is ready. After the

confirm command is issued, read operations

output the Status Register data. The read Status

Register command must not be issued as it will be

interpreted as data to program.

Program Phase. The Program Phase requires

n+1 cycles, where n is the number of Words (refer

to Table 7., Factory Program Commands, and Fig-

ure 30., Enhanced Factory Program Flowchart).

Three successive steps are required to issue and

execute the Program Phase of the command.

1. Use one Bus Write operation to latch the Start

Address and the first Word to be programmed.

The Status Register Bank Write Status bit SR0

should be read to check that the P/E.C. is

ready for the next Word.

2. Each subsequent Word to be programmed is

latched with a new Bus Write operation. The

address can either remain the Start Address,

in which case the P/E.C. increments the

address location or the address can be

incremented in which case the P/E.C. jumps to

the new address. If any address that is not in

the same block as the Start Address is given

with data FFFFh, the Program Phase

Read operations to the bank being programmed

output the Status Register content after the pro-

gramming has started.

Programming aborts if Reset goes to V_IL. As data

integrity cannot be guaranteed when the program

operation is aborted, the memory locations must

be reprogrammed.

During Quadruple Word Program operations the

bank being programmed will only accept the Read

Array, Read Status Register, Read Electronic Sig-

nature and Read CFI Query command, all other

commands will be ignored.

Dual operations are not supported during Quadru-

ple Word Program operations and the command

cannot be suspended. Typical Program times are

given in Table 14., Program/Erase Times and En-

durance Cycles.

See APPENDIX C., Figure 24., Quadruple Word

Program Flowchart and Pseudo Code, for the

flowchart for using the Quadruple Word Program

command.

Enhanced Factory Program Command

terminates and the Verify Phase begins. The

Status Register bit SR0 should be read

between each Bus Write cycle to check that

the P/E.C. is ready for the next Word.

The Enhanced Factory Program command can be

used to program large streams of data within any

one block. It greatly reduces the total program-

ming time when a large number of Words are writ-

ten to a block at any one time.

Dual operations are not supported during the En-

hanced Factory Program operation and the com-

mand cannot be suspended.

For optimum performance the Enhanced Factory

Program commands should be limited to a maxi-

mum of 10 program/erase cycles per block. If this

limit is exceeded the internal algorithm will contin-

ue to work properly but some degradation in per-

formance is possible. Typical Program times are

given in Table 14.

The Enhanced Factory Program command has

four phases: the Setup Phase, the Program Phase

to program the data to the memory, the Verify

Phase to check that the data has been correctly

programmed and reprogram if necessary and the

Exit Phase. Refer to Table 7., Factory Program

Commands, and Figure 30., Enhanced Factory

Program Flowchart.

3. Finally, after all Words have been pro-

grammed, write one Bus Write operation with

data FFFFh to any address outside the block

containing the Start Address, to terminate the

programming phase. If the data is not FFFFh,

the command is ignored.

The memory is now set to enter the Verify Phase.

Verify Phase. The Verify Phase is similar to the

Program Phase in that all Words must be resent to

the memory for them to be checked against the

programmed data. The Program/Erase Controller

checks the stream of data with the data that was

programmed in the Program Phase and repro-

grams the memory location if necessary.

Three successive steps are required to execute

the Verify Phase of the command.

1. Use one Bus Write operation to latch the Start

Address and the first Word, to be verified. The

Status Register bit SR0 should be read to

check that the Program/Erase Controller is

ready for the next Word.

Setup Phase. The Enhanced Factory Program

command requires two Bus Write operations to ini-

tiate the command.

2. Each subsequent Word to be verified is

latched with a new Bus Write operation. The

20/87

M58WR064FT, M58WR064FB

Words must be written in the same order as in

the Program Phase. The address can remain

the Start Address or be incremented. If any

address that is not in the same block as the

Start Address is given with data FFFFh, the

Verify Phase terminates. Status Register bit

SR0 should be read to check that the P/E.C. is

ready for the next Word.

to exit the Load phase until all four Words have

been written.

Two successive steps are required to issue and

execute the Load Phase of the Quadruple En-

hanced Factory Program command.

1. Use one Bus Write operation to latch the Start

Address and the first Word of the first Page to

be programmed. For subsequent Pages the

first Word address can remain the Start

3. Finally, after all Words have been verified,

write one Bus Write operation with data FFFFh

to any address outside the block containing

the Start Address, to terminate the Verify

Phase.

If the Verify Phase is successfully completed the

memory remains in Read Status Register mode. If

the Program/Erase Controller fails to reprogram a

given location, the error will be signaled in the Sta-

tus Register.

Exit Phase. Status Register P/E.C. bit SR7 set to

‘1’ indicates that the device has returned to Read

mode. A full Status Register check should be done

to ensure that the block has been successfully pro-

grammed. See the section on the Status Register

for more details.

Address (in which case the next Page is

programmed) or can be any address in the

same block. If any address with data FFFFh is

given that is not in the same block as the Start

Address, the device enters the Exit Phase. For

the first Load Phase Status Register bit SR7

should be read after the first Word has been

issued to check that the command has been

accepted (bit SR7 set to ‘0’). This check is not

required for subsequent Load Phases.

2. Each subsequent Word to be programmed is

latched with a new Bus Write operation. The

address is only checked for the first Word of

each Page as the order of the Words to be

programmed is fixed.

Quadruple Enhanced Factory Program

Command

The memory is now set to enter the Program and

Verify Phase.

The Quadruple Enhanced Factory Program com-

mand can be used to program one or more pages

of four adjacent words in parallel. The four words

must differ only for the addresses A0 and A1.

Dual operations are not supported during Quadru-

ple Enhanced Factory Program operations and

the command cannot be suspended.

Program and Verify Phase. In the Program and

Verify Phase the four Words that were loaded in

the Load Phase are programmed in the memory

array and then verified by the Program/Erase Con-

troller. If any errors are found the Program/Erase

Controller reprograms the location. During this

phase the Status Register shows that the Pro-

gram/Erase Controller is busy, Status Register bit

SR7 set to ‘0’, and that the device is not waiting for

new data, Status Register bit SR0 set to ‘1’. When

Status Register bit SR0 is set to ‘0’ the Program

and Verify phase has terminated.

Once the Verify Phase has successfully complet-

ed subsequent pages in the same block can be

loaded and programmed. The device returns to

the beginning of the Load Phase by issuing one

Bus Write operation to latch the Address and the

first of the four new Words to be programmed.

Exit Phase. Finally, after all the pages have been

programmed, write one Bus Write operation with

data FFFFh to any address outside the block con-

taining the Start Address, to terminate the Load

and Program and Verify Phases.

Status Register bit SR7 set to ‘1’ and bit SR0 set

to ‘0’ indicate that the Quadruple Enhanced Facto-

ry Program command has terminated. A full Status

Register check should be done to ensure that the

block has been successfully programmed. See the

section on the Status Register for more details.

The Quadruple Enhanced Factory Program com-

mand has four phases: the Setup Phase, the Load

Phase where the data is loaded into the buffer, the

combined Program and Verify Phase where the

loaded data is programmed to the memory and

then automatically checked and reprogrammed if

necessary and the Exit Phase. Unlike the En-

hanced Factory Program it is not necessary to re-

submit the data for the Verify Phase. The Load

Phase and the Program and Verify Phase can be

repeated to program any number of pages within

the block.

Setup Phase. The Quadruple Enhanced Factory

Program command requires one Bus Write opera-

tion to initiate the load phase. After the setup

command is issued, read operations output the

Status Register data. The Read Status Register

command must not be issued as it will be

interpreted as data to program.

Load Phase. The Load Phase requires 4 cycles

to load the data (refer to Table 7., Factory Pro-

gram Commands and Figure 31., Quadruple En-

hanced Factory Program Flowchart). Once the

first Word of each Page is written it is impossible

If the Program and Verify Phase has successfully

completed the memory returns to Read mode. If

21/87

M58WR064FT, M58WR064FB

the P/E.C. fails to program and reprogram a given

location, the error will be signaled in the Status

Register.

Table 7. Factory Program Commands

Bus Write Operations

3rd

Command

Phase

1st

2nd

Add

Final -1

Final

Add

Data

Add

Data

Add Data Add

Data

Bank Erase

2

3

BKA

80h

BKA

D0h

BKA or

(4)

35h

56h

30h

PD1

75h

WA1

PD1

D0h

PD2

PD1

WA2

PD2

PD1

PD3

PD2

Double Word Program

Quadruple Word

(8)

WA1

BKA or

5

WA1

WA3 PD3 WA4

PD4

FFFFh

PD4

(5)

(8)

Program

WA1

BKA or

BA or

NOT

Setup,

2+

n+1

(2)

(3)

Enhanced

PAn

PD3

WA1

WA3

WA2

WAn

WA3

(8)

(9)

(2)

Program

Factory

WA1

(6)

Program

NOT

(2)

(3)

(2)

(3)

(7)

(3)

(7)

Verify, Exit

n+1

5

WA1

WA2

(2)

WA1

WA4

BKA or

Setup,

(7)

WA1

(8)

first Load

WA1

First

Program &

Automatic

Verify

Quadruple

Enhanced

Factory

Program

(5,6)

Subsequent

Loads

WA1i

WA2i

(7)

WA3i

WA4i

(7)

4

1

PD1i

PD2i

PD3i

PD4i

(2)

(7)

Subsequent

Program &

Verify

Automatic

NOT

WA1

(2)

Exit

FFFFh

Note: 1. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address.

2. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1.

3. Address can remain Starting Address WA1 or be incremented.

4. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0.

5. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.

6. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and

check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed.

7. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent

Words in each Page can be written to any address.

8. Any address within the bank can be used.

9. Any address within the block can be used.

22/87

M58WR064FT, M58WR064FB

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operations.

Issue a Read Status Register command to read

the contents of the Status Register, refer to Read

Status Register Command section for more de-

tails. To output the contents, the Status Register is

latched and updated on the falling edge of the

Chip Enable or Output Enable signals and can be

read until Chip Enable or Output Enable returns to

V_IH. The Status Register can only be read using

single asynchronous or single synchronous reads.

Bus Read operations from any address within the

bank, always read the Status Register during Pro-

gram and Erase operations.

The various bits convey information about the sta-

tus and any errors of the operation. Bits SR7, SR6,

SR2 and SR0 give information on the status of the

device and are set and reset by the device. Bits

SR5, SR4, SR3 and SR1 give information on er-

rors, they are set by the device but must be reset

by issuing a Clear Status Register command or a

hardware reset. If an error bit is set to ‘1’ the Status

Register should be reset before issuing another

command. SR7 to SR1 refer to the status of the

device while SR0 refers to the status of the ad-

dressed bank.

pended in the addressed block. When the Erase

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

SR7 is set within the Erase Suspend Latency time

of the Program/Erase Suspend command being

issued therefore the memory may still complete

the operation rather than entering the Suspend

mode.

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status Bit (SR5). The Erase Status bit

can be used to identify if the memory has failed to

verify that the block or bank has erased correctly.

When the Erase Status bit is High (set to ‘1’), the

Program/Erase Controller has applied the maxi-

mum number of pulses to the block or bank and

still failed to verify that it has erased correctly. The

Erase Status bit should be read once the Program/

Erase Controller Status bit is High (Program/Erase

Controller inactive).

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status Bit (SR4). The Program Status

bit is used to identify a Program failure or an at-

tempt to program a ‘1’ to an already programmed

The bits in the Status Register are summarized in

Table 8., Status Register Bits. Refer to Table 8. in

conjunction with the following text descriptions.

Program/Erase Controller Status Bit (SR7). The

Program/Erase Controller Status bit indicates

whether the Program/Erase Controller is active or

inactive in any bank. When the Program/Erase

Controller Status bit is Low (set to ‘0’), the Pro-

gram/Erase Controller is active; when the bit is

High (set to ‘1’), the Program/Erase Controller is

inactive, and the device is ready to process a new

command.

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

After the Program/Erase Controller completes its

operation the Erase Status, Program Status, V_PP

Status and Block Lock Status bits should be tested

for errors.

bit when V_PP= V_PPH

.

When the Program Status bit is High (set to ‘1’),

the Program/Erase Controller has applied the

maximum number of pulses to the byte and still

failed to verify that it has programmed correctly.

After an attempt to program a '1' to an already pro-

grammed bit, the Program Status bit SR4 only

goes High (set to '1') if V_PP= V_PPH(if V_PPis differ-

ent from V_PPH, SR4 remains Low (set to '0') and

the attempt is not shown).

The Program Status bit should be read once the

Program/Erase Controller Status bit is High (Pro-

gram/Erase Controller inactive).

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

V_PPStatus Bit (SR3). The V_PPStatus bit can be

used to identify an invalid voltage on the V_PPpin

during Program and Erase operations. The V_PP

pin is only sampled at the beginning of a Program

Erase Suspend Status Bit (SR6). The

Suspend Status bit indicates that an Erase opera-

tion has been suspended or is going to be sus-

Erase

23/87

M58WR064FT, M58WR064FB

or Erase operation. Indeterminate results can oc-

cur if V_PPbecomes invalid during an operation.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

When the V_PPStatus bit is Low (set to ‘0’), the volt-

age on the V_PPpin was sampled at a valid voltage;

when the V_PPStatus bit is High (set to ‘1’), the V_PP

pin has a voltage that is below the V_PPLockout

Voltage, V_PPLK, the memory is protected and Pro-

gram and Erase operations cannot be performed.

Once set High, the V_PPStatus bit can only be reset

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Bank Write/Multiple Word Program Status Bit

(SR0). The Bank Write Status bit indicates wheth-

er the addressed bank is programming or erasing.

In Enhanced Factory Program mode the Multiple

Word Program bit shows if a Word has finished

programming or verifying depending on the phase.

The Bank Write Status bit should only be consid-

ered valid when the Program/Erase Controller Sta-

tus SR7 is Low (set to ‘0’).

When both the Program/Erase Controller Status bit

and the Bank Write Status bit are Low (set to ‘0’),

the addressed bank is executing a Program or

Erase operation. When the Program/Erase Con-

troller Status bit is Low (set to ‘0’) and the Bank

Write Status bit is High (set to ‘1’), a Program or

Erase operation is being executed in a bank other

than the one being addressed.

Program Suspend Status Bit (SR2). The Pro-

gram Suspend Status bit indicates that a Program

operation has been suspended in the addressed

block. When the Program Suspend Status bit is

High (set to ‘1’), a Program/Erase Suspend com-

mand has been issued and the memory is waiting

for a Program/Erase Resume command. The Pro-

gram Suspend Status should only be considered

valid when the Program/Erase Controller Status

bit is High (Program/Erase Controller inactive).

SR2 is set within the Program Suspend Latency

time of the Program/Erase Suspend command be-

ing issued therefore the memory may still com-

plete the operation rather than entering the

Suspend mode.

In Enhanced Factory Program mode if Multiple

Word Program Status bit is Low (set to ‘0’), the de-

vice is ready for the next Word, if the Multiple Word

Program Status bit is High (set to ‘1’) the device is

not ready for the next Word.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status Bit (SR1). The Block

Protection Status bit can be used to identify if a

Program or Block Erase operation has tried to

modify the contents of a locked block.

Note: Refer to APPENDIX C., FLOWCHARTS

AND PSEUDO CODES, for using the Status Reg-

ister.

24/87

M58WR064FT, M58WR064FB

Table 8. Status Register Bits

Bit

Name

Type LogicLevel

Definition

'1'

Ready

SR7 P/E.C. Status

Status

'0'

Busy

'1'

Erase Suspended

SR6 Erase Suspend Status

SR5 Erase Status

Status

'0'

Erase In progress or Completed

Erase Error

'1'

Error

'0'

Erase Success

'1'

Program Error

SR4 Program Status

Error

'0'

Program Success

V

Invalid, Abort

OK

'1'

PP

V

PP

Status

SR3

Error

'0'

V

'1'

Program Suspended

SR2 Program Suspend Status Status

'0'

'1'

'0'

Program In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

SR7 = ‘1’ Not Allowed

SR1 Block Protection Status

Error

'1'

Program or erase operation in a bank other than

the addressed bank

SR7 = ‘0’

Bank Write Status

Status

SR7 = ‘1’ No Program or erase operation in the device

SR7 = ‘0’ Program or erase operation in addressed bank

SR7 = ‘1’ Not Allowed

'0'

'1'

'0'

SR0

Multiple Word Program

Status (Enhanced

Factory Program mode)

SR7 = ‘0’ the device is NOT ready for the next word

SR7 = ‘1’ the device is exiting from EFP

Status

SR7 = ‘0’ the device is ready for the next Word

Note: Logic level '1' is High, '0' is Low.

25/87

M58WR064FT, M58WR064FB

CONFIGURATION REGISTER

The Configuration Register is used to configure

the type of bus access that the memory will per-

form. Refer to Read Modes section for details on

read operations.

The Configuration Register is set through the

Command Interface. After a Reset or Power-Up

the device is configured for asynchronous page

read (CR15 = 1). The Configuration Register bits

are described in Table 9. They specify the selec-

tion of the burst length, burst type, burst X latency

and the Read operation. Refer to Figures 6 and 7

for examples of synchronous burst configurations.

Refer to Figure 6., X-Latency and Data Output

Configuration Example.

Wait Polarity Bit (CR10)

In synchronous burst mode the Wait signal indi-

cates whether the output data are valid or a WAIT

state must be inserted. The Wait Polarity bit is

used to set the polarity of the Wait signal. When

the Wait Polarity bit is set to ‘0’ the Wait signal is

active Low. When the Wait Polarity bit is set to ‘1’

the Wait signal is active High.

Data Output Configuration Bit (CR9)

The Data Output Configuration bit determines

whether the output remains valid for one or two

clock cycles. When the Data Output Configuration

Bit is ’0’ the output data is valid for one clock cycle,

when the Data Output Configuration Bit is ’1’ the

output data is valid for two clock cycles.

Read Select Bit (CR15)

The Read Select bit, CR15, is used to switch be-

tween asynchronous and synchronous Bus Read

operations. When the Read Select bit is set to ’1’,

read operations are asynchronous; when the

Read Select bit is set to ’0’, read operations are

synchronous. Synchronous Burst Read is support-

ed in both parameter and main blocks and can be

performed across banks.

The Data Output Configuration depends on the

condition:

■

t_K> t_KQV+ t_{QVK_CPU}

where t_Kis the clock period, t_{QVK_CPU}is the data

setup time required by the system CPU and t_KQV

is the clock to data valid time. If this condition is not

satisfied, the Data Output Configuration bit should

be set to ‘1’ (two clock cycles). Refer to Figure

6., X-Latency and Data Output Configuration Ex-

ample.

On reset or power-up the Read Select bit is set

to’1’ for asynchronous access.

X-Latency Bits (CR13-CR11)

The X-Latency bits are used during Synchronous

Read operations to set the number of clock cycles

between the address being latched and the first

data becoming available. For correct operation the

X-Latency bits can only assume the values in Ta-

ble 9., Configuration Register.

The correspondence between X-Latency settings

and the maximum sustainable frequency must be

calculated taking into account some system pa-

rameters. Two conditions must be satisfied:

Wait Configuration Bit (CR8)

In burst mode the Wait bit controls the timing of the

Wait output pin, WAIT. When WAIT is asserted,

Data is Not Valid and when WAIT is deasserted,

Data is Valid. When the Wait bit is ’0’ the Wait out-

put pin is asserted during the wait state. When the

Wait bit is ’1’ the Wait output pin is asserted one

clock cycle before the wait state.

1. Depending on whether t_{AVK_CPU}or t_DELAYis

supplied either one of the following two

equations must be satisfied:

Burst Type Bit (CR7)

The Burst Type bit is used to configure the se-

quence of addresses read as sequential or inter-

leaved. When the Burst Type bit is ’0’ the memory

outputs from interleaved addresses; when the

Burst Type bit is ’1’ the memory outputs from se-

quential addresses. See Table 10., Burst Type

Definition, for the sequence of addresses output

from a given starting address in each mode.

(n + 1) t_K≥ t_ACC- t_{AVK_CPU}+ t_{QVK_CPU}

(n + 2) t_K≥ t_ACC+ t_DELAY+ t_{QVK_CPU}

2. and also

t_K> t_KQV+ t_{QVK_CPU}

where

n is the chosen X-Latency configuration code

t_Kis the clock period

Valid Clock Edge Bit (CR6)

t_{AVK_CPU}is clock to address valid, L Low, or E

Low, whichever occurs last

t_DELAYis address valid, L Low, or E Low to clock,

whichever occurs last

t_{QVK_CPU}is the data setup time required by the

system CPU,

t_KQVis the clock to data valid time

The Valid Clock Edge bit, CR6, is used to config-

ure the active edge of the Clock, K, during Syn-

chronous Burst Read operations. When the Valid

Clock Edge bit is ’0’ the falling edge of the Clock is

the active edge; when the Valid Clock Edge bit is

’1’ the rising edge of the Clock is active.

Wrap Burst Bit (CR3)

The burst reads can be confined inside the 4 or 8

Word boundary (wrap) or overcome the boundary

t_ACCis the random access time of the device.

26/87

M58WR064FT, M58WR064FB

(no wrap). The Wrap Burst bit is used to select be-

tween wrap and no wrap. When the Wrap Burst bit

is set to ‘0’ the burst read wraps; when it is set to

‘1’ the burst read does not wrap.

vice asserts the WAIT output to indicate that a de-

lay is necessary before the data is output.

If the starting address is aligned to a 4 Word

boundary no wait states are needed and the WAIT

output is not asserted.

Burst length Bits (CR2-CR0)

The Burst Length bits set the number of Words to

be output during a Synchronous Burst Read oper-

ation as result of a single address latch cycle.

They can be set for 4 Words, 8 Words, 16 Words

or continuous burst, where all the words are read

sequentially.

If the starting address is shifted by 1,2 or 3 posi-

tions from the four word boundary, WAIT will be

asserted for 1, 2 or 3 clock cycles when the burst

sequence crosses the first 16 Word boundary, to

indicate that the device needs an internal delay to

read the successive words in the array. WAIT will

be asserted only once during a continuous burst

access. See also Table 10., Burst Type Definition.

In continuous burst mode the burst sequence can

cross bank boundaries.

CR14, CR5 and CR4 are reserved for future use.

In continuous burst mode or in 4, 8, 16 Words no-

wrap, depending on the starting address, the de-

Table 9. Configuration Register

Bit

Description

Value

Description

0

1

Synchronous Read

CR15

CR14

Read Select

Asynchronous Read (Default at power-on)

Reserved

010

011

100

101

111

2 clock latency

3 clock latency

4 clock latency

CR13-CR11

X-Latency

5 clock latency

Reserved (default)

Other configurations reserved

0

1

0

1

0

1

0

1

0

1

WAIT is active Low

CR10

CR9

CR8

CR7

Wait Polarity

WAIT is active High (default)

Data held for one clock cycle

Data held for two clock cycles (default)

WAIT is active during wait state

WAIT is active one data cycle before wait state (default)

Interleaved

Data Output

Configuration

Wait Configuration

Burst Type

Sequential (default)

Falling Clock edge

CR6

CR5-CR4

CR3

Valid Clock Edge

Rising Clock edge (default)

Reserved

0

Wrap

Wrap Burst

1

No Wrap (default)

001

010

011

111

4 Words

8 Words

CR2-CR0

Burst Length

16 Words

Continuous (CR7 must be set to ‘1’) (default)

27/87

M58WR064FT, M58WR064FB

Table 10. Burst Type Definition

4 Words

Start

8 Words

Sequential Interleaved

0-1-2-3-4-5- 0-1-2-3-4-5-6-7-8-9-

16 Words

Continuous

Burst

Inter-

Add

Sequen-tial

Sequential Interleaved

leaved

0-1-2-3-4-5-6-7-

8-9-10-11-12-

13-14-15

0

0-1-2-3

0-1-2-3 0-1-2-3-4-5-6-7

1-0-3-2 1-2-3-4-5-6-7-0

2-3-0-1 2-3-4-5-6-7-0-1

3-2-1-0 3-4-5-6-7-0-1-2

0-1-2-3-4-5-6...

6-7

10-11-12-13-14-15

1-2-3-4-5-6-7-8-9- 1-0-3-2-5-4-7-6- 1-2-3-4-5-6-7-

10-11-12-13-14-15- 9-8-11-10-13- ...15-WAIT-16-17-

1-0-3-2-5-4-

7-6

1

2

1-2-3-0

2-3-0-1

3-0-1-2

0

12-15-14

18...

2-3-0-1-6-7-4-5- 2-3-4-5-6-7...15-

10-11-8-9-14- WAIT-WAIT-16-

2-3-0-1-6-7- 2-3-4-5-6-7-8-9-10-

4-5 11-12-13-14-15-0-1

15-12-13

17-18...

3-2-1-0-7-6-5-4- 3-4-5-6-7...15-

11-10-9-8-15-

14-13-12

3-2-1-0-7-6- 3-4-5-6-7-8-9-10-11-

3

WAIT-WAIT-

WAIT-16-17-18...

5-4

12-13-14-15-0-1-2

...

7-8-9-10-11-12-

13-14-15-WAIT-

WAIT-WAIT-16-

17...

7-6-5-4-3-2-1-0-

15-14-13-12-11-

10-9-8

7-6-5-4-3-2- 7-8-9-10-11-12-13-

7

7-4-5-6

7-6-5-4 7-0-1-2-3-4-5-6

1-0

14-15-0-1-2-3-4-5-6

...

12-13-14-15-16-

17-18...

12

13-14-15-WAIT-

16-17-18...

13

14

15

14-15-WAIT-

WAIT-16-17-18....

15-WAIT-WAIT-

WAIT-16-17-18...

28/87

M58WR064FT, M58WR064FB

4 Words

8 Words

Sequential Interleaved

16 Words

Start

Add

Continuous

Burst

Inter-

leaved

Sequen-tial

Sequential

Interleaved

0-1-2-3-4-5-6-7-8-9-

10-11-12-13-14-15

0

1

0-1-2-3

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

1-2-3-4-5-6-7-8-9-

10-11-12-13-14-15-

WAIT-16

1-2-3-4

2-3-4-5

2-3-4-5-6-7-8-9-10-

11-12-13-14-15-

WAIT-WAIT-16-17

2-3-4-5-6-7-8-

9...

2

3-4-5-6-7-8-9-10-11-

12-13-14-15-WAIT-

WAIT-WAIT-

3-4-5-6-7-8-9-

10

3

...

7

3-4-5-6

16-17-18

7-8-9-10-11-12-13-

14-15-WAIT-WAIT-

WAIT-16-17-18-19-

20-21-22

7-8-9-10-11-12-

13-14

Same as for Wrap

(Wrap /No Wrap

has no effect on

Continuous Burst)

7-8-9-10

...

12-13-14-15-16-17-

18-19-20-21-22-23-

24-25-26-27

12-13-14-15-

16-17-18-19

12 12-13-14-15

13-14-15-

WAIT-16-17-

18-19-20

13-14-15-WAIT-16-

17-18-19-20-21-22-

23-24-25-26-27-28

13-14-15-

13

WAIT-16

14-15-WAIT-WAIT-

16-17-18-19-20-21-

22-23-24-25-26-27-

28-29

14-15-

WAIT-

WAIT-16-17

14-15-WAIT-

WAIT-16-17-

18-19-20-21

14

15

15-WAIT-

WAIT-

WAIT-16-

17-18

15-WAIT-WAIT-

WAIT-16-17-18-19-

20-21-22-23-24-25-

26-27-28-29-30

15-WAIT-WAIT-

WAIT-16-17-

18-19-20-21-22

29/87

M58WR064FT, M58WR064FB

Figure 6. X-Latency and Data Output Configuration Example

X-latency

1st cycle

2nd cycle

3rd cycle

4th cycle

K

E

L

A21-A0

tDELAY

VALID ADDRESS

tAVK_CPU

tQVK_CPU

tK

tACC

tKQV

tQVK_CPU

DQ15-DQ0

VALID DATA VALID DATA

Note. Settings shown: X-latency = 4, Data Output held for one clock cycle

AI06182

Figure 7. Wait Configuration Example

E

K

L

A21-A0

VALID ADDRESS

DQ15-DQ0

VALID DATA VALID DATA NOT VALID VALID DATA

WAIT

CR8 = '0'

CR10 = '0'

WAIT

CR8 = '1'

CR10 = '0'

WAIT

CR8 = '0'

CR10 = '1'

WAIT

CR8 = '1'

CR10 = '1'

AI06972

30/87

M58WR064FT, M58WR064FB

READ MODES

Read operations can be performed in two different

ways depending on the settings in the Configura-

tion Register. If the clock signal is ‘don’t care’ for

the data output, the read operation is Asynchro-

nous; if the data output is synchronized with clock,

the read operation is Synchronous.

The Read mode and data output format are deter-

mined by the Configuration Register. (See Config-

uration Register section for details). All banks

supports both asynchronous and synchronous

read operations. The Multiple Bank architecture

allows read operations in one bank, while write op-

erations are being executed in another (see Ta-

bles 11 and 12).

sible to perform burst reads across bank

boundaries.

Synchronous Burst Read mode can only be used

to read the memory array. For other read opera-

tions, such as Read Status Register, Read CFI

and Read Electronic Signature, Single Synchro-

nous Read or Asynchronous Random Access

Read must be used.

In Synchronous Burst Read mode the flow of the

data output depends on parameters that are con-

figured in the Configuration Register.

A burst sequence is started at the first clock edge

(rising or falling depending on Valid Clock Edge bit

CR6 in the Configuration Register) after the falling

edge of Latch Enable or Chip Enable, whichever

occurs last. Addresses are internally incremented

and after a delay of 2 to 5 clock cycles (X latency

bits CR13-CR11) the corresponding data are out-

put on each clock cycle.

The number of Words to be output during a Syn-

chronous Burst Read operation can be configured

as 4, 8, 16 Words, or Continuous (Burst Length

bits CR2-CR0). The data can be configured to re-

main valid for one or two clock cycles (Data Output

Configuration bit CR9).

The order of the data output can be modified

through the Burst Type and the Wrap Burst bits in

the Configuration Register. The burst sequence

may be configured to be sequential or interleaved

(CR7). The burst reads can be confined inside the

4, 8 or 16 Word boundary (Wrap) or overcome the

boundary (No Wrap). If the starting address is

aligned to the Burst Length (4, 8 or 16 Words) the

wrapped configuration has no impact on the output

sequence. Interleaved mode is not allowed in Con-

tinuous Burst Read mode or with No Wrap se-

quences.

A WAIT signal may be asserted to indicate to the

system that an output delay will occur. This delay

will depend on the starting address of the burst se-

quence; the worst case delay will occur when the

sequence is crossing a 16 Word boundary and the

starting address was at the end of a four word

boundary.

WAIT is asserted during X latency, the Wait state

and at the end of 4-, 8- or 16-Word burst. It is only

deasserted when output data are valid. In Contin-

uous Burst Read mode a Wait state will occur

when crossing the first 16 Word boundary. If the

burst starting address is aligned to a 4 Word Page,

the Wait state will not occur.

The WAIT signal can be configured to be active

Low or active High by setting CR10 in the Config-

uration Register. The WAIT signal is meaningful

only in Synchronous Burst Read mode, in other

Asynchronous Read Mode

In Asynchronous Read operations the clock signal

is ‘don’t care’. The device outputs the data corre-

sponding to the address latched, that is the mem-

ory array, Status Register, Common Flash

Interface or Electronic Signature depending on the

command issued. CR15 in the Configuration Reg-

ister must be set to ‘1’ for Asynchronous opera-

tions.

In Asynchronous Read mode a Page of data is in-

ternally read and stored in a Page Buffer. The

Page has a size of 4 Words and is addressed by

A0 and A1 address inputs. The address inputs A0

and A1 are not gated by Latch Enable in Asyn-

chronous Read mode.

The first read operation within the Page has a

longer access time (T_acc, Random access time),

subsequent reads within the same Page have

much shorter access times. If the Page changes

then the normal, longer timings apply again.

Asynchronous Read operations can be performed

in two different ways, Asynchronous Random Ac-

cess Read and Asynchronous Page Read. Only

Asynchronous Page Read takes full advantage of

the internal page storage so different timings are

applied.

During Asynchronous Read operations, after a

bus inactivity of 150ns, the device automatically

switches to the Automatic Standby mode. In this

condition the power consumption is reduced to the

standby value and the outputs are still driven.

In Asynchronous Read mode, the WAIT signal is

always asserted.

See Table 20., Asynchronous Read AC Charac-

teristics, Figure 10., Asynchronous Random Ac-

cess Read AC Waveforms, and Figure

11., Asynchronous Page Read AC Waveforms, for

details.

Synchronous Burst Read Mode

In Synchronous Burst Read mode the data is out-

put in bursts synchronized with the clock. It is pos-

31/87

M58WR064FT, M58WR064FB

modes, WAIT is always asserted (except for Read

Array mode).

See Table 21., Synchronous Read AC Character-

istics, and Figure 12., Synchronous Burst Read

AC Waveforms, for details.

WAIT being gated by E remains active and will not

revert to high-impedance when G goes high. So if

two or more devices are connected to the system’s

READY signal, to prevent bus contention the

WAIT signal of the Flash memory should not be di-

rectly connected to the system’s READY signal.

See Table 21., Synchronous Read AC Character-

istics and Figure 14., Synchronous Burst Read

Suspend AC Waveforms, for details.

Synchronous Burst Read Suspend. A

Syn-

chronous Burst Read operation can be suspend-

ed, freeing the data bus for other higher priority

devices. It can be suspended during the initial ac-

cess latency time (before data is output) in which

case the initial latency time can be reduced to ze-

ro, or after the device has output data. When the

Synchronous Burst Read operation is suspended,

internal array sensing continues and any previous-

ly latched internal data is retained. A burst se-

quence can be suspended and resumed as often

as required as long as the operating conditions of

the device are met.

Single Synchronous Read Mode

Single Synchronous Read operations are similar

to Synchronous Burst Read operations except that

only the first data output after the X latency is valid.

Synchronous Single Reads are used to read the

Electronic Signature, Status Register, CFI, Block

Protection Status, Configuration Register Status

or Protection Register. When the addressed bank

is in Read CFI, Read Status Register or Read

Electronic Signature mode, the WAIT signal is al-

ways asserted.

A Synchronous Burst Read operation is suspend-

ed when E is low and the current address has

been latched (on a Latch Enable rising edge or on

a valid clock edge). The clock signal is then halted

at V_IHor at V_IL, and G goes high.

See Table 21., Synchronous Read AC Character-

istics and Figure 13., Single Synchronous Read

AC Waveforms, for details.

When G becomes low again and the clock signal

restarts, the Synchronous Burst Read operation is

resumed exactly where it stopped.

32/87

M58WR064FT, M58WR064FB

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE

The Multiple Bank Architecture of the

M58WR064FT/B provides flexibility for software

developers by allowing code and data to be split

with 4Mbit granularity. The Dual Operations fea-

ture simplifies the software management of the de-

vice and allows code to be executed from one

bank while another bank is being programmed or

erased.

The Dual operations feature means that while pro-

gramming or erasing in one bank, Read opera-

tions are possible in another bank with zero

latency (only one bank at a time is allowed to be in

Program or Erase mode). If a Read operation is re-

quired in a bank which is programming or erasing,

the Program or Erase operation can be suspend-

ed. Also if the suspended operation was Erase

then a Program command can be issued to anoth-

er block, so the device can have one block in

Erase Suspend mode, one programming and oth-

er banks in Read mode. Bus Read operations are

allowed in another bank between setup and con-

firm cycles of program or erase operations. The

combination of these features means that read op-

erations are possible at any moment.

Tables 11 and 12 show the dual operations possi-

ble in other banks and in the same bank. For a

complete list of possible commands refer to AP-

PENDIX D., COMMAND INTERFACE STATE TA-

BLES.

Table 11. Dual Operations Allowed In Other Banks

Commands allowed in another bank

Read

Status

Register

Read

CFI

Query

Read

Electronic Program

Signature

Program/ Program/

Erase Erase

Suspend Resume

Status of bank

Read

Array

Block

Erase

Idle

Yes

–

Yes

–

Yes

–

Yes

–

Programming

Yes

Erasing

Yes

–

Program Suspended

Erase Suspended

Yes

–

Yes

–

Table 12. Dual Operations Allowed In Same Bank

Commands allowed in same bank

Read

Status

Register

Program/ Program/

Erase Erase

Suspend Resume

Status of bank

Read

Array

Read

Block

Electronic Program

Signature

CFI Query

Erase

Idle

Yes

–

Yes

–

Yes

–

(2)

Programming

–

(2)

Erasing

–

(1)

Program Suspended

Erase Suspended

Yes

–

Yes

(1)

Yes

Note: 1. Not allowed in the Block or Word that is being erased or programmed.

2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed.

33/87

M58WR064FT, M58WR064FB

BLOCK LOCKING

The M58WR064FT/B features an instant, individu-

al block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their protection status can-

not be changed using software commands alone.

A Locked or Unlocked block can be Locked-Down

by issuing the Lock-Down command. Locked-

Down blocks revert to the Locked state when the

device is reset or powered-down.

■

Lock/Unlock - this first level allows software-

only control of block locking.

■

Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■

V_PP≤ V_PPLK- the third level offers a complete

The Lock-Down function is dependent on the WP

input pin. When WP=0 (V_IL), the blocks in the

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

WP=1 (V_IH) the Lock-Down function is disabled

(1,1,x) and Locked-Down blocks can be individual-

ly unlocked to the (1,1,0) state by issuing the soft-

ware command, where they can be erased and

programmed. These blocks can then be re-locked

(1,1,1) and unlocked (1,1,0) as desired while WP

remains high. When WP is Low, blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WP was High. Device reset or power-down

resets all blocks, including those in Lock-Down, to

the Locked state.

hardware protection against program and

erase on all blocks.

The protection status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 13., de-

fines all of the possible protection states (WP,

DQ1, DQ0), and APPENDIX C., Figure 28., shows

a flowchart for the locking operations.

Reading a Block’s Lock Status

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 6.,

will output the protection status of that block. The

lock status is represented by DQ0 and DQ1. DQ0

indicates the Block Lock/Unlock status and is set

by the Lock command and cleared by the Unlock

command. It is also automatically set when enter-

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the lock status will be changed. After complet-

ing any desired lock, read, or program operations,

resume the erase operation with the Erase Re-

sume command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operations cannot be performed during a

program suspend. Refer to APPENDIX

D., COMMAND INTERFACE STATE TABLES, for

detailed information on which commands are valid

during erase suspend.

The following sections explain the operation of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

Unlocked State

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

34/87

M58WR064FT, M58WR064FB

Table 13. Lock Status

Current

(1)

Next Protection Status

(WP, DQ1, DQ0)

(1)

Protection Status

(WP, DQ1, DQ0)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

Allowed

After

WP transition

Current State

1,0,0

yes

1,0,1

1,0,0

1,1,1

0,0,0

(2)

no

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,1

0,1,1

1,0,0

1,0,1

1,1,0

1,1,1

0,0,0

yes

(2)

no

0,0,1

0,1,1

0,0,0

0,1,1

1,0,1

0,0,1

(3)

0,1,1

1,1,1 or 1,1,0

Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read

in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

35/87

M58WR064FT, M58WR064FB

PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES

The Program and Erase times and the number of

Program/ Erase cycles per block are shown in Ta-

ble 14. Exact erase times may change depending

on the memory array condition. The best case is

when all the bits in the block or bank are at ‘0’ (pre-

programmed). The worst case is when all the bits

in the block or bank are at ‘1’ (not prepro-

grammed). Usually, the system overhead is negli-

gible with respect to the erase time.

In the M58WR064FT/B the maximum number of

Program/ Erase cycles depends on the V_PPvolt-

age supply used.

Table 14. Program/Erase Times and Endurance Cycles

Typicalafter

100k W/E

Cycles

Parameter

Condition

Min

Typ

Max

Unit

(2)

0.3

0.8

1

3

2.5

4

s

Parameter Block (4 KWord)

Preprogrammed

Main Block (32 KWord)

Erase

Not Preprogrammed

Preprogrammed

4

s

4.5

6

s

Bank (4Mbit)

Not Preprogrammed

s

Word Program

10

32

256

5

10

100

µs

ms

µs

cycles

(3)

Parameter Block (4 KWord)

Main Block (32 KWord)

Program

10

20

Suspend

Latency

Erase

5

Program/

Erase Cycles

(per Block)

Main Blocks

100,000

Parameter Blocks

cycles

Parameter Block (4 KWord)

Main Block (32 KWord)

Bank (4Mbit)

0.25

0.8

6

2.5

4

s

Erase

s

(4)

8

100

µs

Word/ Double Word/ Quadruple Word

(4)

8

ms

Quadruple Word

Word

Parameter Block (4

KWord)

32

64

Quadruple Word

Word

(3)

Program

Main Block (32 KWord)

Bank (4Mbit)

256

Quad-Enhanced

0.7

0.5

s

(4)

Factory Program

(4)

Quadruple Word

Program/

Erase Cycles

(per Block)

Main Blocks

1000 cycles

2500 cycles

Parameter Blocks

Note: 1. T = –40 to 85°C; V = 1.7V to 2.2V; V = 2.2V to 3.3V.

DDQ

A

DD

2. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms).

3. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution).

4. Measurements performed at 25°C. T = 25°C ±5°C for Quadruple Word, Double Word and Quadruple Enhanced Factory Program.

A

36/87

M58WR064FT, M58WR064FB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 15. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

–40

–65

Max

85

T

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

°C

V

A

T

125

155

(1)

BIAS

T

STG

T

Lead Temperature During Soldering

Input or Output Voltage

Supply Voltage

LEAD

V

IO

V

+0.6

–0.5

–0.2

DDQ

V

DD

2.45

14

V

Input/Output Supply Voltage

Program Voltage

V

DDQ

V

PP

V

I

Output Short Circuit Current

Time for V at V

100

mA

hours

O

t

VPPH

PP

PPH

Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,

and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

37/87

M58WR064FT, M58WR064FB

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 16., Operating

and AC Measurement Conditions. Designers

should check that the operating conditions in their

circuit match the operating conditions when rely-

ing on the quoted parameters.

Table 16. Operating and AC Measurement Conditions

M58WR064FT, M58WR064FB

60

70

80

Parameter

Units

Min

1.7

Max

Min

1.7

Max

2

Min

1.7

Max

2

V

Supply Voltage

2

V

DD

1.7

2.24

12.6

1.7

2.24

12.6

1.7

2.24

12.6

DDQ

Supply Voltage (Factory environment)

11.4

PP

V

DDQ

V

DDQ

V

DDQ

+0.4

V

Supply Voltage (Application environment)

-0.4

V

+0.4

Ambient Operating Temperature

– 40

85

– 40

85

– 40

85

°C

pF

ns

V

Load Capacitance (C )

30

L

Input Rise and Fall Times

5

0 to V

DDQ

Input Pulse Voltages

DDQ

V /2

DDQ

V

/2

DDQ

V

/2

DDQ

Input and Output Timing Ref. Voltages

V

Figure 8. AC Measurement I/O Waveform

Figure 9. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DD

0V

16.7kΩ

AI06161

DEVICE

UNDER

TEST

C

L

16.7kΩ

0.1µF

C

includes JIG capacitance

L

AI06162

Table 17. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

8

Unit

C

V

IN

= 0V

6

8

pF

IN

C

V

OUT

12

OUT

Note: Sampled only, not 100% tested.

38/87

M58WR064FT, M58WR064FB

Table 18. DC Characteristics - Currents

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

Min

Typ

Max

±1

Unit

µA

I

LI

0V ≤ V ≤ V

IN

DDQ

I

LO

0V ≤ V

≤ V

OUT DDQ

±1

µA

Supply Current

Asynchronous Read (f=6MHz)

E = V , G = V

3

6

mA

IL

IH

4 Word

8 Word

7

16

18

22

25

17

20

25

30

50

15

20

15

20

mA

µA

10

12

13

8

Supply Current

Synchronous Read (f=54MHz)

16 Word

Continuous

4 Word

I

DD1

8 Word

11

14

16

10

8

Supply Current

Synchronous Read (f=66MHz)

16 Word

Continuous

I

RP = V ± 0.2V

Supply Current (Reset)

DD2

DD3

DD4

SS

E = V ± 0.2V

Supply Current (Standby)

µA

DD

E = V , G = V

Supply Current (Automatic Standby)

µA

IL

IH

V

= V

PPH

mA

PP

Supply Current (Program)

Supply Current (Erase)

V

= V

10

8

PP

DD

(1)

I

DD5

V

PP

PPH

V

= V

DD

10

PP

Program/Erase in one

Bank, Asynchronous

Read in another Bank

13

26

mA

Supply Current

(Dual Operations)

(1,2)

(1)

I

DD6

Program/Erase in one

Bank, Synchronous

Read in another Bank

23

10

45

50

mA

µA

Supply Current Program/ Erase

Suspended (Standby)

E = V ± 0.2V

I

DD

DD7

V

PP

= V

PPH

2

5

mA

µA

mA

µA

V

Supply Current (Program)

Supply Current (Erase)

PP

V

= V

0.2

2

PP

DD

(1)

PP1

V

PP

PPH

V

= V

0.2

PP

DD

I

V

Supply Current (Read)

V

≤ V

PP2

PP

(1)

Supply Current (Standby)

V

PP

I

PP

DD

PP3

Note: 1. Sampled only, not 100% tested.

2. V Dual Operation current is the sum of read and program or erase currents.

DD

39/87

M58WR064FT, M58WR064FB

Table 19. DC Characteristics - Voltages

Symbol

Parameter

Input Low Voltage

Test Condition

Min

Typ

Max

Unit

V

IL

–0.5

0.4

V

–0.4

V

+ 0.4

DDQ

Input High Voltage

Output Low Voltage

Output High Voltage

V

IH

DDQ

V

I

= 100µA

OL

0.1

V

OL

V

I

= –100µA

OH

–0.1

V

OH

DDQ

V

Program Voltage-Logic

Program Voltage Factory

Program, Erase

1.1

1.8

12

3.3

12.6

0.4

V

PP1

PP

V

PP

11.4

V

PPH

V

Program or Erase Lockout

V Lock Voltage

DD

V

PPLK

V

LKO

1

V

RP pin Extended High Voltage

3.3

V

RPH

40/87

M58WR064FT, M58WR064FB

Figure 10. Asynchronous Random Access Read AC Waveforms

41/87

M58WR064FT, M58WR064FB

Figure 11. Asynchronous Page Read AC Waveforms

42/87

M58WR064FT, M58WR064FB

Table 20. Asynchronous Read AC Characteristics

M58WR064FT/B

Unit

Symbol

Alt

Parameter

60

20

70

20

80

25

t

Address Valid to Next Address Valid

Address Valid to Output Valid (Random)

Address Valid to Output Valid (Page)

Address Transition to Output Transition

Chip Enable Low to Wait Valid

Min

Max

Min

ns

AVAV

RC

t

ACC

AVQV

t

PAGE

AVQV1

(1)

t

0

11

60

0

14

70

0

14

80

0

t

OH

AXQX

t

Max

ELTV

(2)

t

Chip Enable Low to Output Valid

t

CE

ELQV

(1)

t

Chip Enable Low to Output Transition

Chip Enable High to Wait Hi-Z

Min

Max

Min

Max

Min

ns

LZ

ELQX

t

14

0

17

0

17

0

EHTZ

(1)

(2)

(1)

t

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

t

OH

EHQX

EHQZ

GLQV

GLQX

t

14

20

0

17

20

0

17

25

0

HZ

t

Output Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable High to Output Transition

OE

t

OLZ

t

0

OH

GHQX

t

Output Enable High to Output Hi-Z

Address Valid to Latch Enable High

Chip Enable Low to Latch Enable High

Latch Enable High to Address Transition

Latch Enable Pulse Width

Max

Min

Max

Min

14

7

14

9

14

9

ns

t

DF

GHQZ

t

AVLH

ELLH

AVADVH

ELADVH

t

10

7

10

9

10

9

LHAX

ADVHAX

t

ADVLADVH

7

9

LLLH

LLQV

t

Latch Enable Low to Output Valid (Random)

Latch Enable High to Output Enable Low

60

0

70

0

80

0

ADVLQV

t

LHGL

ADVHGL

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV GLQV

ELQV

43/87

M58WR064FT, M58WR064FB

Figure 12. Synchronous Burst Read AC Waveforms

44/87

M58WR064FT, M58WR064FB

Figure 13. Single Synchronous Read AC Waveforms

45/87

M58WR064FT, M58WR064FB

Figure 14. Synchronous Burst Read Suspend AC Waveforms

46/87

M58WR064FT, M58WR064FB

Figure 15. Clock input AC Waveform

tKHKL

tKHKH

tr

tf

tKLKH

AI06981

Table 21. Synchronous Read AC Characteristics

M58WR064FT/B

Unit

Symbol

Alt

Parameter

60

7

70

80

t

Address Valid to Clock High

Chip Enable Low to Clock High

Chip Enable Low to Wait Valid

Min

Max

9

ns

AVKH

AVCLKH

t

7

9

ELKH

ELCLKH

t

11

14

ELTV

Chip Enable Pulse Width

(subsequent synchronous reads)

Min

14

ns

EHEL

t

Chip Enable High to Wait Hi-Z

Clock High to Address Transition

Max

Min

11

7

14

9

14

9

ns

EHTZ

t

KHAX

CLKHAX

t

Clock High to Output Valid

Clock High to WAIT Valid

KHQV

t

Max

Min

11

14

4

14

4

ns

CLKHQV

KHTV

t

Clock High to Output Transition

Clock High to WAIT Transition

KHQX

3

7

CLKHQX

t

KHTX

t

ADVLCLKH

Latch Enable Low to Clock High

Clock Period (f=54MHz)

Min

9

ns

LLKH

18.5

t

CLK

KHKH

Clock Period (f=66MHz)

15

t

Clock High to Clock Low

Clock Low to Clock High

KHKL

Min

3.5

4.5

3

4.5

3

ns

t

KLKH

t

f

Clock Fall or Rise Time

Max

3

t

r

Note: 1. Sampled only, not 100% tested.

2. For other timings please refer to Table 20., Asynchronous Read AC Characteristics.

47/87

M58WR064FT, M58WR064FB

Figure 16. Write AC Waveforms, Write Enable Controlled

48/87

M58WR064FT, M58WR064FB

Table 22. Write AC Characteristics, Write Enable Controlled

M58WR064FT/B

Unit

Symbol

Alt

Parameter

60

7

70

9

80

9

t

Address Valid to Next Address Valid

Address Valid to Latch Enable High

Min

ns

AVAV

WC

t

AVLH

(3)

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Min

40

10

0

45

10

0

50

10

0

ns

t

WC

AVWH

t

DVWH

DS

t

Chip Enable Low to Latch Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

Chip Enable Low to Clock Valid

ELLH

t

ELWL

CS

t

60

7

70

9

80

9

ELQV

t

ELKV

t

Output Enable High to Write Enable Low

Latch Enable High to Address Transition

Latch Enable Pulse Width

14

7

17

9

17

9

GHWL

t

LHAX

t

7

9

LLLH

(3)

Write Enable High to Address Valid

Min

0

ns

t

WHAV

(3)

t

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Min

0

ns

AH

WHAX

t

WHDX

DH

CH

t

0

WHEH

(2)

20

25

t

WHEL

t

Write Enable High to Output Enable Low

Write Enable High to Latch Enable Low

Write Enable High to Write Enable Low

Write Enable High to Output Valid

Min

0

ns

WHGL

t

WHLL

t

WPH

20

80

40

0

25

95

45

0

25

105

50

0

WHWL

t

WHQV

t

Write Enable Low to Write Enable High

WLWH

WP

t

Output (Status Register) Valid to V Low

QVVPL

PP

Output (Status Register) Valid to Write Protect

Low

t

Min

0

ns

QVWPL

t

V

High to Write Enable High

Min

200

ns

VPHWH

VPS

PP

t

Write Enable High to V Low

WHVPL

PP

t

Write Enable High to Write Protect Low

Write Protect High to Write Enable High

WHWPL

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

WHEL

software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a

different bank t is 0ns.

WHEL

3. Meaningful only if L is always kept low.

49/87

M58WR064FT, M58WR064FB

Figure 17. Write AC Waveforms, Chip Enable Controlled

50/87

M58WR064FT, M58WR064FB

Table 23. Write AC Characteristics, Chip Enable Controlled

M58WR064FT/B

Unit

Symbol

Alt

Parameter

60

40

7

70

45

9

80

50

9

t

Address Valid to Next Address Valid

Address Valid to Chip Enable High

Address Valid to Latch Enable High

Data Valid to Chip Enable High

Min

ns

AVAV

WC

t

AVEH

t

AVLH

t

40

0

45

0

50

0

DVEH

DS

AH

DH

t

Chip Enable High to Address Transition

Chip Enable High to Input Transition

Chip Enable High to Chip Enable Low

Chip Enable High to Output Enable Low

Chip Enable High to Write Enable High

Chip Enable Low to Clock Valid

EHAX

t

0

EHDX

t

CPH

20

0

25

0

25

0

EHEL

t

EHGL

t

0

EHWH

CH

t

7

9

ELKV

ELEH

t

Chip Enable Low to Chip Enable High

Chip Enable Low to Latch Enable High

Chip Enable Low to Output Valid

40

10

60

14

7

45

10

70

17

9

50

10

80

17

9

CP

t

ELLH

ELQV

GHEL

t

Output Enable High to Chip Enable Low

Latch Enable High to Address Transition

Latch Enable Pulse Width

t

LHAX

t

7

9

LLLH

(2)

Write Enable High to Chip Enable Low

Write Enable High to Output Valid

Write Enable Low to Chip Enable Low

Min

20

80

0

25

95

0

25

105

0

ns

t

WHEL

t

WHQV

t

WLEL

CS

t

Chip Enable High to V Low

200

0

200

0

200

0

EHVPL

PP

t

Chip Enable High to Write Protect Low

EHWPL

t

Output (Status Register) Valid to V Low

QVVPL

PP

Output (Status Register) Valid to Write Protect

Low

t

Min

0

ns

QVWPL

t

V

High to Chip Enable High

Min

200

ns

VPHEH

VPS

PP

t

Write Protect High to Chip Enable High

WPHEH

Note: 1. Sampled only, not 100% tested.

2. t has the values shown when reading in the targeted bank. System designers should take this into account and may insert a

WHEL

software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a

different bank t is 0ns.

WHEL

51/87

M58WR064FT, M58WR064FB

Figure 18. Reset and Power-up AC Waveforms

tPHWL

tPHEL

tPHGL

tPHLL

tPLWL

tPLEL

tPLGL

tPLLL

W, E, G, L

RP

tVDHPH

tPLPH

VDD, VDDQ

Power-Up

Reset

AI06976

Table 24. Reset and Power-up AC Characteristics

Symbol

Parameter

Test Condition

During Program

60

10

20

70

10

20

80

10

20

Unit

µs

Reset Low to

Min

t

PLWL

Write Enable Low,

Chip Enable Low,

Output Enable Low,

Latch Enable Low

t

PLEL

During Erase

Min

µs

t

PLGL

t

Other Conditions

80

ns

PLLL

Reset High to

t

PHWL

Write Enable Low

Chip Enable Low

Output Enable Low

Latch Enable Low

t

PHEL

Min

30

t

PHGL

t

PHLL

(1,2)

(3)

RP Pulse Width

Min

50

ns

µs

t

PLPH

Supply Voltages High to Reset

High

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 50ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset.

52/87

M58WR064FT, M58WR064FB

PACKAGE MECHANICAL

Figure 19. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

E

E1

ddd

BALL "A1"

e

b

A

A2

A1

BGA-Z38

Note: Drawing is not to scale.

Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.000

0.0394

0.200

0.0079

0.660

0.350

7.700

5.250

0.0260

0.0138

0.3031

0.2067

0.300

7.600

–

0.400

0.0118

0.2992

–

0.0157

D

7.800

0.3071

D1

ddd

e

–

0.080

0.0031

0.750

9.000

4.500

1.225

2.250

0.375

–

0.0295

0.3543

0.1772

0.0482

0.0886

0.0148

–

E

8.900

9.100

0.3504

0.3583

E1

FD

FE

SD

–

53/87

M58WR064FT, M58WR064FB

Figure 20. VFBGA56 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

G

AI07731b

54/87

M58WR064FT, M58WR064FB

Figure 21. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package)

1

2

3

4

5

6

7

8

START POINT

A

B

C

D

E

F

G

END POINT

AI07755

55/87

M58WR064FT, M58WR064FB

PART NUMBERING

Table 26. Ordering Information Scheme

Example:

M58WR064FT

70 ZB

6

T

Device Type

M58

Architecture

W = Multiple Bank, Burst Mode

Operating Voltage

R = V = 1.7V to 2V, V

= 1.7V to 2.24V

DDQ

DD

Device Function

064FT = 64 Mbit (x16), Top Boot

064FB = 64 Mbit (x16), Bottom Boot

Speed

60 = 60ns

70 = 70ns

80 = 80ns

Package

ZB = VFBGA56: 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch

Temperature Range

6 = –40 to 85°C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free and RoHS Package, Standard Packing

F = Lead-Free and RoHS Package, Tape & Reel Packing

56/87

M58WR064FT, M58WR064FB

Table 27. Daisy Chain Ordering Scheme

Example:

M58WR064F

-ZB T

Device Type

M58WR064F

Daisy Chain

ZB = VFBGA56: 7.7 x 9mm, 8x7 active ball array, 0.75 mm pitch

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-Free and RoHS Package, Standard Packing

F = Lead-Free and RoHS Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-

tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST

Sales Office nearest to you.

57/87

M58WR064FT, M58WR064FB

APPENDIX A. BLOCK ADDRESS TABLES

Table 28. Top Boot Block Addresses,

M58WR064FT

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

32

2F8000-2FFFFF

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

2B8000-2BFFFF

2B0000-2B7FFF

2A8000-2AFFFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-20FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

Size

(KWord)

Bank

#

Address Range

0

4

3FF000-3FFFFF

3FE000-3FEFFF

3FD000-3FDFFF

3FC000-3FCFFF

3FB000-3FBFFF

3FA000-3FAFFF

3F9000-3F9FFF

3F8000-3F8FFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

1

4

2

4

3

4

5

4

6

4

7

4

8

32

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

58/87

M58WR064FT, M58WR064FB

79

80

32

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

32

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

000000-007FFF

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

Note: There are two Bank Regions: Bank Region 1 contains all the

banks that are made up of main blocks only; Bank Region 2

contains the banks that are made up of the parameter and

main blocks (Parameter Bank).

59/87

M58WR064FT, M58WR064FB

Table 29. Bottom Boot Block Addresses,

M58WR064FB

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

32

2B8000-2BFFFF

2B0000-2B7FFF

2A8000-2AFFFF

2A0000-2A7FFF

298000-29FFFF

290000-297FFF

288000-28FFFF

280000-287FFF

278000-27FFFF

270000-277FFF

268000-26FFFF

260000-267FFF

258000-25FFFF

250000-257FFF

248000-24FFFF

240000-247FFF

238000-23FFFF

230000-237FFF

228000-22FFFF

220000-227FFF

218000-21FFFF

210000-217FFF

208000-20FFFF

200000-207FFF

1F8000-1FFFFF

1F0000-1F7FFF

1E8000-1EFFFF

1E0000-1E7FFF

1D8000-1DFFFF

1D0000-1D7FFF

1C8000-1CFFFF

1C0000-1C7FFF

1B8000-1BFFFF

1B0000-1B7FFF

1A8000-1AFFFF

1A0000-1A7FFF

198000-19FFFF

190000-197FFF

188000-18FFFF

180000-187FFF

Size

Bank

#

Address Range

(KWord)

32

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

3F8000-3FFFFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

2F8000-2FFFFF

2F0000-2F7FFF

2E8000-2EFFFF

2E0000-2E7FFF

2D8000-2DFFFF

2D0000-2D7FFF

2C8000-2CFFFF

2C0000-2C7FFF

98

97

96

95

60/87

M58WR064FT, M58WR064FB

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

32

178000-17FFFF

170000-177FFF

168000-16FFFF

160000-167FFF

158000-15FFFF

150000-157FFF

148000-14FFFF

140000-147FFF

138000-13FFFF

130000-137FFF

128000-12FFFF

120000-127FFF

118000-11FFFF

110000-117FFF

108000-10FFFF

100000-107FFF

0F8000-0FFFFF

0F0000-0F7FFF

0E8000-0EFFFF

0E0000-0E7FFF

0D8000-0DFFFF

0D0000-0D7FFF

0C8000-0CFFFF

0C0000-0C7FFF

0B8000-0BFFFF

0B0000-0B7FFF

0A8000-0AFFFF

0A0000-0A7FFF

098000-09FFFF

090000-097FFF

088000-08FFFF

080000-087FFF

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32

4

078000-07FFFF

070000-077FFF

068000-06FFFF

060000-067FFF

058000-05FFFF

050000-057FFF

048000-04FFFF

040000-047FFF

038000-03FFFF

030000-037FFF

028000-02FFFF

020000-027FFF

018000-01FFFF

010000-017FFF

008000-00FFFF

007000-007FFF

006000-006FFF

005000-005FFF

004000-004FFF

003000-003FFF

002000-002FFF

001000-001FFF

000000-000FFF

8

7

6

4

5

4

3

4

2

4

1

4

0

4

Note: There are two Bank Regions: Bank Region 2 contains all the

banks that are made up of main blocks only; Bank Region 1

contains the banks that are made up of the parameter and

main blocks (Parameter Bank).

61/87

M58WR064FT, M58WR064FB

APPENDIX B. COMMON FLASH INTERFACE

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

When the Read CFI Query Command is issued

the device enters CFI Query mode and the data

structure is read from the memory. Tables 30, 31,

32, 33, 34, 35, 36, 37, 38 and 39 show the ad-

dresses used to retrieve the data. The Query data

is always presented on the lowest order data out-

puts (DQ0-DQ7), the other outputs (DQ8-DQ15)

are set to 0.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Figure 5., Protection Register Memory

Map). This area can be accessed only in Read

mode by the final user. It is impossible to change

the security number after it has been written by

ST. Issue a Read Array command to return to

Read mode.

Table 30. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Lock Protection Register

Unique device Number and

User Programmable OTP

80h

Security Code Area

Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections

detailed in Tables 31, 32, 33 and 34. Query data is always presented on the lowest order data outputs.

Table 31. CFI Query Identification String

Offset

Sub-section Name

Description

Value

00h

0020h

Manufacturer Code

Device Code

ST

8810h

8811h

Top (M58WR064FT)

Bottom (M58WR064FB)

01h

02h

03h

reserved

0051h

Reserved

04h-0Fh

10h

"Q"

"R"

"Y"

11h

0052h

Query Unique ASCII String "QRY"

12h

0059h

13h

0003h

Primary Algorithm Command Set and Control Interface

ID code 16 bit ID code defining a specific algorithm

14h

0000h

15h

offset = P = 0039h

0000h

Address for Primary Algorithm extended Query table

(see Table 34.)

p = 39h

NA

16h

17h

0000h

Alternate Vendor Command Set and Control Interface

ID Code second vendor - specified algorithm supported

18h

0000h

19h

value = A = 0000h

0000h

Address for Alternate Algorithm extended Query table

NA

1Ah

62/87

M58WR064FT, M58WR064FB

Table 32. CFI Query System Interface Information

Offset

Data

Description

Value

V

Logic Supply Minimum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 millivolts

DD

1Bh

0017h

1.7V

2V

Logic Supply Maximum Program/Erase or Write voltage

bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 millivolts

DD

1Ch

1Dh

1Eh

0020h

00B4h

00C6h

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 millivolts

PP

11.4V

12.6V

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4 HEX value in volts

PP

bit 3 to 0 BCD value in 100 millivolts

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

0000h

000Ah

0000h

0003h

0000h

0002h

0000h

16µs

NA

Typical time-out per single byte/word program = 2 µs

n

Typical time-out for multi-Byte programming = 2 µs

n

1s

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

128µs

NA

Maximum time-out for word program = 2 times typical

n

Maximum time-out for multi-Byte programming = 2 times typical

n

4s

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

63/87

M58WR064FT, M58WR064FB

Table 33. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0017h

8 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0000h

n

NA

2

Maximum number of bytes in multi-byte program or page = 2

Number of identical sized erase block regions within the device

bit 7 to 0 = x = number of Erase Block Regions

2Ch

0002h

2Dh

2Eh

007Eh

0000h

Region 1 Information

Number of identical-size erase blocks = 007Eh+1

127

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

64 KByte

8

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase blocks = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8 KByte

NA

35h

38h

reserved Reserved for future erase block region information

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

8

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8 KByte

127

31h

32h

007Eh

0000h

Region 2 Information

Number of identical-size erase block = 007Eh+1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64 KByte

NA

35h

38h

reserved Reserved for future erase block region information

64/87

M58WR064FT, M58WR064FB

Table 34. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(P)h = 39h

0050h

0052h

0049h

0031h

0033h

00E6h

0003h

0000h

"P"

Primary Algorithm extended Query table unique ASCII string “PRI”

"R"

"I"

(P+3)h = 3Ch

(P+4)h = 3Dh

(P+5)h = 3Eh

Major version number, ASCII

Minor version number, ASCII

"1"

"3"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

bit 9

Chip Erase supported

(1 = Yes, 0 = No)

No

Yes

No

(P+7)h = 40h

(P+8)h = 41h

Erase Suspend supported

Program Suspend supported

Legacy Lock/Unlock supported

Queued Erase supported

Instant individual block locking supported(1 = Yes, 0 = No)

Protection bits supported

Page mode read supported

Synchronous read supported

Simultaneous operation supported

No

Yes

(1 = Yes, 0 = No)

bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another

31 bit field of optional features follows at the end of the bit-30

field.

(P+9)h = 42h

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query

Yes

bit 0

Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1 Reserved; undefined bits are ‘0’

(P+A)h = 43h

(P+B)h = 44h

0003h

0000h

Block Protect Status

Defines which bits in the Block Status Register section of the Query are

implemented.

bit 0 Block protect Status Register Lock/Unlock

bit active

(1 = Yes, 0 = No)

Yes

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

V

Logic Supply Optimum Program/Erase voltage (highest performance)

DD

(P+C)h = 45h

(P+D)h = 46h

0018h

00C0h

1.8V

12V

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

Supply Optimum Program/Erase voltage

PP

bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

65/87

M58WR064FT, M58WR064FB

Table 35. Protection Register Information

Offset

Data

Description

Value

Number of protection register fields in JEDEC ID space. 0000h indicates that

256 fields are available.

(P+E)h = 47h

0001h

1

(P+F)h = 48h

(P+10)h = 49h

(P+11)h = 4Ah

(P+12)h= 4Bh

0080h

0000h

0003h

0004h

Protection Field 1: Protection Description

0080h

Bits 0-7 Lower byte of protection register address

Bits 8-15 Upper byte of protection register address

n

8 Bytes

Bits 16-23 2 bytes in factory pre-programmed region

n

Bits 24-31 2 bytes in user programmable region

16 Bytes

Table 36. Burst Read Information

Offset

Data

Description

Value

(P+13)h = 4Ch

0003h

Page-mode read capability

8 Bytes

n

bits 0-7

’n’ such that 2 HEX value represents the number of read-

page bytes. See offset 28h for device word width to

determine page-mode data output width.

(P+14)h = 4Dh

(P+15)h = 4Eh

0004h

0001h

Number of synchronous mode read configuration fields that follow.

4

Synchronous mode read capability configuration 1

bit 3-7

bit 0-2

Reserved

n+1

’n’ such that 2

HEX value represents the maximum

number of continuous synchronous reads when the device is

configured for its maximum word width. A value of 07h

indicates that the device is capable of continuous linear

bursts that will output data until the internal burst counter

reaches the end of the device’s burstable address space.

This field’s 3-bit value can be written directly to the read

configuration register bit 0-2 if the device is configured for its

maximum word width. See offset 28h for word width to

determine the burst data output width.

(P+16)h = 4Fh

(P+17)h = 50h

(P+18)h = 51h

0002h

0003h

0007h

Synchronous mode read capability configuration 2

Synchronous mode read capability configuration 3

Synchronous mode read capability configuration 4

8

16

Cont.

Table 37. Bank and Erase Block Region Information

M58WR064FT(top)

M58WR064FB (bottom)

Description

Offset

Data

Offset

Data

(P+19)h = 52h

02h

(P+19)h = 52h

02h

Number of Bank Regions within the device

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, see Table 28. and Table 29.

66/87

M58WR064FT, M58WR064FB

Table 38. Bank and Erase Block Region 1 Information

M58WR064FT (top)

M58WR064FB (bottom)

Description

Offset

Data

0Fh

00h

Offset

Data

01h

00h

(P+1A)h = 53h

(P+1B)h = 54h

(P+1A)h = 53h

(P+1B)h = 54h

Number of identical banks within Bank Region 1

Number of program or erase operations allowed in region 1:

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+1C)h = 55h

(P+1D)h = 56h

11h

00h

(P+1C)h = 55h

(P+1D)h = 56h

11h

00h

Number of program or erase operations allowed in other banks

while a bank in same region is programming

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

Number of program or erase operations allowed in other banks

while a bank in this region is erasing

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+1E)h = 57h

(P+1F)h = 58h

00h

01h

(P+1E)h = 57h

(P+1F)h =58h

00h

02h

Types of erase block regions in region 1

n = number of erase block regions with contiguous same-size

erase blocks.

(2)

Symmetrically blocked banks have one blocking region.

(P+20)h = 59h

(P+21)h = 5Ah

(P+22)h = 5Bh

(P+23)h = 5Ch

(P+24)h = 5Dh

(P+25)h = 5Eh

07h

00h

01h

64h

00h

(P+20)h = 59h

(P+21)h = 5Ah

(P+22)h = 5Bh

(P+23)h = 5Ch

(P+24)h = 5Dh

(P+25)h = 5Eh

07h

00h

20h

00h

64h

00h

Bank Region 1 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 1 (Erase Block Type 1)

Minimum block erase cycles × 1000

Bank Region 1 (Erase Block Type 1): BIts per cell, internal

ECC

(P+26)h = 5Fh

(P+27)h = 60h

01h

03h

(P+26)h = 5Fh

(P+27)h = 60h

01h

03h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved 5Eh 01 5Eh 01

Bank Region 1 (Erase Block Type 1): Page mode and

synchronous mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+28)h = 61h

(P+29)h = 62h

(P+2A)h = 63h

(P+2B)h = 64h

(P+2C)h = 65h

(P+2D)h = 66h

06h

00h

01h

64h

00h

Bank Region 1 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 1 (Erase Block Type 2)

Minimum block erase cycles × 1000

67/87

M58WR064FT, M58WR064FB

M58WR064FT (top)

Offset Data

M58WR064FB (bottom)

Description

Offset

Data

Bank Regions 1 (Erase Block Type 2): BIts per cell, internal

ECC

(P+2E)h = 67h

01h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

Bank Region 1 (Erase Block Type 2): Page mode and

synchronous mode capabilities

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+2F)h = 68h

03h

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, see Table 28. and Table 29.

Table 39. Bank and Erase Block Region 2 Information

M58WR064FT (top)

M58WR064FB (bottom)

Description

Offset

Data

01h

00h

Offset

Data

0Fh

00h

(P+28)h = 61h

(P+29)h = 62h

(P+30)h = 69h

(P+31)h = 6Ah

Number of identical banks within bank region 2

Number of program or erase operations allowed in bank region

2:

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

(P+2A)h = 63h

(P+2B)h = 64h

(P+2C)h = 65h

(P+2D)h = 66h

11h

00h

02h

(P+32)h = 6Bh

(P+33)h = 6Ch

(P+34)h = 6Dh

(P+35)h = 6Eh

11h

00h

01h

Number of program or erase operations allowed in other banks

while a bank in this region is programming

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

Number of program or erase operations allowed in other banks

while a bank in this region is erasing

Bits 0-3: Number of simultaneous program operations

Bits 4-7: Number of simultaneous erase operations

Types of erase block regions in region 2

n = number of erase block regions with contiguous same-size

erase blocks.

(2)

Symmetrically blocked banks have one blocking region.

(P+2E)h = 67h

(P+2F)h = 68h

(P+30)h = 69h

(P+31)h = 6Ah

(P+32)h = 6Bh

(P+33)h = 6Ch

06h

00h

01h

64h

00h

(P+36)h = 6Fh

(P+37)h = 70h

(P+38)h = 71h

(P+39)h = 72h

(P+3A)h = 73h

(P+3B)h = 74h

07h

00h

01h

64h

00h

Bank Region 2 Erase Block Type 1 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 2 (Erase Block Type 1)

Minimum block erase cycles × 1000

Bank Region 2 (Erase Block Type 1): BIts per cell, internal

ECC

(P+34)h = 6Dh

01h

(P+3C)h = 75h

01h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

68/87

M58WR064FT, M58WR064FB

M58WR064FT (top)

M58WR064FB (bottom)

Description

Offset

Data

Offset

Data

Bank Region 2 (Erase Block Type 1): Page mode and

synchronous mode capabilities (defined in Table 36.)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+35)h = 6Eh

03h

(P+3D)h = 76h

03h

(P+36)h = 6Fh

(P+37)h = 70h

(P+38)h = 71h

(P+39)h = 72h

(P+3A)h = 73h

(P+3B)h = 74h

07h

00h

20h

00h

64h

00h

Bank Region 2 Erase Block Type 2 Information

Bits 0-15: n+1 = number of identical-sized erase blocks

Bits 16-31: n×256 = number of bytes in erase block region

Bank Region 2 (Erase Block Type 2)

Minimum block erase cycles × 1000

Bank Region 2 (Erase Block Type 2): BIts per cell, internal

ECC

(P+3C)h = 75h

01h

Bits 0-3: bits per cell in erase region

Bit 4: reserved for “internal ECC used”

BIts 5-7: reserved

Bank Region 2 (Erase Block Type 2): Page mode and

synchronous

mode capabilities (defined in Table 36.)

Bit 0: Page-mode reads permitted

Bit 1: Synchronous reads permitted

Bit 2: Synchronous writes permitted

Bits 3-7: reserved

(P+3D)h = 76h

03h

(P+3E)h = 77h

(P+3F)h = 78h

(P+3E)h = 77h

(P+3F)h = 78h

Feature Space definitions

Reserved

Note: 1. The variable P is a pointer which is defined at CFI offset 15h.

2. Bank Regions. There are two Bank Regions, see Table 28. and Table 29.

69/87

M58WR064FT, M58WR064FB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 22. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

"

writeToFlash (addressToProgram, 0x40);

/*writeToFlash (addressToProgram, 0x10);*/

/*see note (3)*/

Write 40h or 10h (3)

"

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register (3)

status_register=readFlash (addressToProgram);

"see note (3)";

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

V

Invalid

if (status_register.SR3==1) /*V

invalid error */

PP

SR3 = 0

YES

Error (1, 2)

error_handler ( ) ;

NO

Program

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

SR4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06170b

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Any address within the bank can equally be used.

70/87

M58WR064FT, M58WR064FB

Figure 23. Double Word Program Flowchart and Pseudo code

Start

Write 35h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (addressToProgram1, 0x35);

/*see note (4)*/

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3, 4)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (addressToProgram) ;

"see note (4)"

/* E or G must be toggled*/

Read Status

Register (4)

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

V

Invalid

if (status_register.SR3==1) /*V

error_handler ( ) ;

invalid error */

PP

SR3 = 0

YES

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

Program

SR4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06171b

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

4. Any address within the bank can equally be used.

71/87

M58WR064FT, M58WR064FB

Figure 24. Quadruple Word Program Flowchart and Pseudo Code

Start

quadruple_word_program_command (addressToProgram1, dataToProgram1,

Write 56h

addressToProgram2, dataToProgram2,

addressToProgram3, dataToProgram3,

addressToProgram4, dataToProgram4)

{

Write Address 1

& Data 1 (3, 4)

writeToFlash (addressToProgram1, 0x56);

/*see note (4) */

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 2

& Data 2 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

writeToFlash (addressToProgram3, dataToProgram3) ;

/*see note (3) */

Write Address 3

& Data 3 (3)

writeToFlash (addressToProgram4, dataToProgram4) ;

/*see note (3) */

Write Address 4

& Data 4 (3)

/*Memory enters read status state after

the Program command*/

do {

status_register=readFlash (addressToProgram) ;

/"see note (4) "/

/* E or G must be toggled*/

Read Status

Register (4)

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

V

Invalid

if (status_register.SR3==1) /*V

PP

invalid error */

PP

SR3 = 0

YES

Error (1, 2)

error_handler ( ) ;

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

Program

SR4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.SR==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06977b

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1.

4. Any address within the bank can equally be used.

72/87

M58WR064FT, M58WR064FB

Figure 25. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

program has already completed */

Write 70h

do {

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

SR2 = 1

Program Complete

Write FFh

if (status_register.SR2==0) /*program completed */

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ) ;

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Read Data

YES

}

else

Write FFh

{ writeToFlash (bank_address, 0xFF) ;

Read data from

another address

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

writeToFlash (bank_address, 0x70) ;

/*read status register to check if program has completed */

Write 70h⁽¹⁾

}

Program Continues with

Bank in Read Status

Register Mode

}

AI10117b

Note: The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command.

73/87

M58WR064FT, M58WR064FB

Figure 26. Block Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (blockToErase, 0x20) ;

/*see note (2) */

Write 20h (2)

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A21 are significant */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register (2)

status_register=readFlash (blockToErase) ;

/* see note (2) */

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

YES

NO

V

Invalid

if (status_register.SR3==1) /*V

error_handler ( ) ;

invalid error */

PP

Error (1)

PP

SR3 = 0

YES

if ( (status_register.SR4==1) && (status_register.SR5==1) )

/* command sequence error */

Command

Sequence Error (1)

SR4, SR5 = 1

NO

error_handler ( ) ;

if ( (status_register.SR5==1) )

/* erase error */

SR5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI10526

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations.

2. Any address within the bank can be used also.

74/87

M58WR064FT, M58WR064FB

Figure 27. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

writeToFlash (bank_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (bank_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (bank_address) ;

/* E or G must be toggled*/

NO

} while (status_register.SR7== 0) ;

SR7 = 1

YES

SR6 = 1

Erase Complete

Write FFh

if (status_register.SR6==0) /*erase completed */

{ writeToFlash (bank_address, 0xFF) ;

read_data ( ) ;

Read Data

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

YES

}

else

Write FFh

{ writeToFlash (bank_address, 0xFF) ;

read_program_data ( );

Read data from another block

or

Program/Protection Register Program

or

/*read or program data from another block*/

Block Lock/Unlock/Lock-Down

writeToFlash (bank_address, 0xD0) ;

/*write 0xD0 to resume erase*/

Write D0h

writeToFlash (bank_address, 0x70) ;

/*read status register to check if erase has completed */

Write 70h⁽¹⁾

}

Erase Continues with

Bank in Read Status

Register Mode

AI10116b

Note: The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command.

75/87

M58WR064FT, M58WR064FB

Figure 28. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

Write 60h (1)

writeToFlash (address, 0x60) ; /*configuration setup*/

/* see note (1) */

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (address, 0x90) ;

/*see note (1) */

Write 90h (1)

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/

/*see note (1) */

Write FFh (1)

}

End

AI06176b

Note: 1. Any address within the bank can equally be used.

76/87

M58WR064FT, M58WR064FB

Figure 29. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

writeToFlash (addressToProgram, 0xC0) ;

/*see note (3) */

Write C0h (3)

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register (3)

status_register=readFlash (addressToProgram) ;

/* see note (3) */

/* E or G must be toggled*/

NO

SR7 = 1

YES

} while (status_register.SR7== 0) ;

NO

V

Invalid

if (status_register.SR3==1) /*VPP invalid error */

error_handler ( ) ;

PP

SR3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.SR4==1) /*program error */

error_handler ( ) ;

SR4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.SR1==1) /*program to protect block error */

error_handler ( ) ;

SR1 = 0

YES

End

}

AI06177b

Note: 1. Status check of SR1 (Protected Block), SR3 (V Invalid) and SR4 (Program Error) can be made after each program operation or

PP

after a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

3. Any address within the bank can equally be used.

77/87

M58WR064FT, M58WR064FB

Figure 30. Enhanced Factory Program Flowchart

SETUP PHASE

Start

VERIFY PHASE

Write PD1

Address WA1

Write 30h

Address WA1

1)

(

Write D0h

Address WA1

Read Status

Register

Read Status

Register

NO

SR0 = 0?

YES

NO

SR7 = 0?

Check SR4, SR3

Write PD2

Address WA2

YES

1)

(

and SR1 for program,

V

and Lock Errors

PP

NO

SR0 = 0?

YES

Exit

Read Status

Register

Write PD1

Address WA1

PROGRAM PHASE

NO

SR0 = 0?

Read Status

Register

YES

Write PDn

Address WAn

NO

1)

(

SR0 = 0?

YES

Read Status

Register

Write PD2

Address WA2

1)

(

NO

Read Status

Register

SR0 = 0?

YES

NO

Write FFFFh

SR0 = 0?

Address Block WA1

=

/

YES

EXIT PHASE

Write PDn

Address WAn

1)

(

Read Status

Register

Read Status

Register

NO

SR7 = 1?

YES

NO

SR0 = 0?

YES

Check Status

Register for Errors

Write FFFFh

=

Address Block WA1

/

End

AI06160

Note: 1. Address can remain Starting Address WA1 or be incremented.

78/87

M58WR064FT, M58WR064FB

Enhanced Factory Program Pseudo Code

efp_command(addressFlow,dataFlow,n)

/* n is the number of data to be programmed */

{

/* setup phase */

writeToFlash(addressFlow[0],0x30);

writeToFlash(addressFlow[0],0xD0);

status_register=readFlash(any_address);

if (status_register.SR7==1){

/*EFP aborted for an error*/

if (status_register.SR4==1) /*program error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR1==1) /*program to protect block error*/

error_handler();

}

else{

/*Program Phase*/

do{

status_register=readFlash(any_address);

/* E or G must be toggled*/

} while (status_register.SR0==1)

/*Ready for first data*/

for (i=0; i++; i< n){

writeToFlash(addressFlow[i],dataFlow[i]);

/* status register polling*/

do{

status_register=readFlash(any_address);

/* E or G must be toggled*/

} while (status_register.SR0==1);

/* Ready for a new data */

}

writeToFlash(another_block_address,FFFFh);

/* Verify Phase */

for (i=0; i++; i< n){

writeToFlash(addressFlow[i],dataFlow[i]);

/* status register polling*/

do{

status_register=readFlash(any_address);

/* E or G must be toggled*/

} while (status_register.SR0==1);

/* Ready for a new data */

}

writeToFlash(another_block_address,FFFFh);

/* exit program phase */

/* Exit Phase */

/* status register polling */

do{

status_register=readFlash(any_address);

/* E or G must be toggled */

} while (status_register.SR7==0);

if (status_register.SR4==1) /*program failure error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR1==1) /*program to protect block error*/

error_handler();

}

79/87

M58WR064FT, M58WR064FB

Figure 31. Quadruple Enhanced Factory Program Flowchart

SETUP PHASE

Start

LOAD PHASE

Write PD1

Address WA1⁽

1)

Write 75h

Address WA1

FIRST

LOAD PHASE

Write PD2

Address WA2⁽

Write PD1

Address WA1

2)

Read Status

Register

Write PD3

Address WA3⁽

2)

NO

SR7 = 0?

YES

Write PD4

Address WA4⁽

2)

EXIT PHASE

Check SR4, SR3

and SR1 for program,

V_PPand Lock Errors

PROGRAM AND

VERIFY PHASE

Read Status

Register

Write FFFFh

Address =Block WA1

/

Exit

Check SR4 for

Programming Errors

NO

SR0 = 0?

YES

End

Last Page?

YES

AI06178b

Note: 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the same block.

2. The address is only checked for the first Word of each Page as the order to program the Words is fixed, so subsequent Words in

each Page can be written to any address.

80/87

M58WR064FT, M58WR064FB

Quadruple Enhanced Factory Program Pseudo Code

quad_efp_command(addressFlow,dataFlow,n)

/* n is the number of pages to be programmed.*/

{

/* Setup phase */

writeToFlash(addressFlow[0],0x75);

for (i=0; i++; i< n){

/*Data Load Phase*/

/*First Data*/

writeToFlash(addressFlow[i],dataFlow[i,0]);

/*at the first data of the first page, Quad-EFP may be aborted*/

if (First_Page) {

status_register=readFlash(any_address);

if (status_register.SR7==1){

/*EFP aborted for an error*/

if (status_register.SR4==1) /*program error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR1==1) /*program to protect block er-

ror*/

error_handler();

}

/*2nd data*/

writeToFlash(addressFlow[i],dataFlow[i,1]);

/*3rd data*/

writeToFlash(addressFlow[i],dataFlow[i,2]);

/*4th data*/

writeToFlash(addressFlow[i],dataFlow[i,3]);

/* Program&Verify Phase */

do{

status_register=readFlash(any_address);

/* E or G must be toggled*/

}while (status_register.SR0==1)

}

/* Exit Phase */

writeToFlash(another_block_address,FFFFh);

/* status register polling */

do{

status_register=readFlash(any_address);

/* E or G must be toggled */

} while (status_register.SR7==0);

if (status_register.SR1==1) /*program to protected block error*/

error_handler();

if (status_register.SR3==1) /*VPP invalid error*/

error_handler();

if (status_register.SR4==1) /*program failure error*/

error_handler();

}

81/87

M58WR064FT, M58WR064FB

APPENDIX D. COMMAND INTERFACE STATE TABLES

Table 40. Command Interface States - Modify Table, Next State

Command Input

Erase

Confirm

P/E

Block

Erase,

Bank

Erase

Setup

(3,4)

Read

DWP,

QWP

Setup

(3,4)

(35h,

56h)

Clear

status

Register

(5)

Quad- Resume, Program/ Read

Electronic

signature,

Read CFI

Query

WP

setup

(3,4)

Read

EFP

Setup

(30h)

Current CI State

EFP

Setup

(75h)

Block

Erase

Status

(2)

Array

(FFh)

Unlock Suspend Register

confirm,

EFP

Confirm

(D0h)

(10/40h)

(B0h)

(70h)

(50h)

(20h,

80h)

(90h, 98h)

Program

Setup

Program

Setup

Quad-EFP

Setup

Ready

Erase Setup EFP Setup

Ready

Lock/CR Setup

Ready (Lock Error)

Ready

Ready (Lock Error)

Setup

OTP

OTP Busy

Busy

Setup

Program Busy

Program

Suspended

Busy

Program Busy

Program

Busy

Suspend

Setup

Program Suspended

Ready (error)

Program Suspended

Ready (error)

Erase Busy

Erase

Suspended

Busy

Erase Busy

EraseBusy

Erase

Program in

Erase

Suspend

Erase

Suspended

Suspend

Setup

Erase Suspended

Erase Busy

Erase Suspended

Program Busy in Erase Suspend

Program

Suspend in

Erase

Busy

Program Busy in Erase Suspend

Program

in Erase

Suspend

Program

Busy in

Erase

Suspend

Program Suspend in Erase Suspend

Suspend

Lock/CR Setup

in Erase Suspend

Erase

Suspend

EraseSuspend(Lock Error)

Ready (error)

Erase Suspend (Lock Error)

Ready (error)

Setup

EFP Busy

(6)

Busy

Verify

Setup

Busy

EFP

EFP Busy

EFP Verify

(6)

Quad EFP Busy

Quad

EFP

Quad EFP Busy

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.

2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data out-

put.

3. The two cycle command should be issued to the same bank address.

4. If the P/E.C. is active, both cycles are ignored.

5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.

6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is

first EFP Address. Any other commands are treated as data.

82/87

M58WR064FT, M58WR064FB

Table 41. Command Interface States - Modify Table, Next Output

(6)

Command Input

Erase

Confirm

P/E

Resume, Program/

Block

Unlock

confirm,

EFP

Confirm

(D0h)

Block

Erase,

Bank

Erase

Setup

(3,4)

Read

DWP,

QWP

Setup

(3,4)

Clear status

Register

(5)

Quad-

EFP

Setup

(75h)

Read

Status

Suspend Register

Electronic

signature,

Read CFI

Query

Read

EFP

Setup

(30h)

Current CI State

Erase

(2)

Array

(FFh)

(B0h)

(70h)

(50h)

(35h, 56h)

(90h, 98h)

(20h, 80h)

Program Setup

Erase Setup

OTP Setup

Program in

Erase Suspend

EFP Setup

EFP Busy

Status Register

EFP Verify

Quad EFP Setup

Quad EFP Busy

Lock/CR Setup

in Erase

Suspend

Status

Register

OTP Busy

Ready

Program Busy

Erase Busy

Status

Register

Output

Unchanged

Array

Status Register

Output Unchanged

Electronic

Signature/

CFI

Program/Erase

Program Busy in

Erase Suspend

Program

Suspend in

Erase Suspend

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller.

2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data out-

put.

3. The two cycle command should be issued to the same bank address.

4. If the P/E.C. is active, both cycles are ignored.

5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended.

6. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A

bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode, depending on the

command issued. Each bank remains in its last output state until a new command is issued. The next state does not depend on the

bank’s output state.

83/87

M58WR064FT, M58WR064FB

Table 42. Command Interface States - Lock Table, Next State

Command Input

Block

Lock/CR

OTP

EFP Exit,

Quad EFP

Block Lock

Confirm

(01h)

Set CR

Confirm

(03h)

P/E. C.

Operation

Completed

Illegal

Command

(5)

Current CI State

Lock-Down

Confirm

(2Fh)

(4)

Setup

(60h)

Setup

(C0h)

(3)

Exit

Lock/CR

Setup

Ready

OTP Setup

Ready

N/A

Lock/CR Setup

Ready (Lock error)

Ready

Ready (Lock error)

N/A

Setup

OTP

OTP Busy

Busy

Ready

N/A

Setup

Program Busy

Program

Erase

Busy

Suspend

Setup

Ready

N/A

Program Suspended

Ready (error)

N/A

Busy

Erase Busy

Ready

Lock/CR

Setup in

Erase

Suspend

Erase Suspended

N/A

Suspend

Setup

Busy

Program Busy in Erase Suspend

Program Suspend in Erase Suspend

Erase Suspend

Program in

Erase

Suspended

Suspend

N/A

Lock/CR Setup

in Erase Suspend

Erase Suspend (Lock

error)

Erase Suspend (Lock error)

N/A

Setup

Ready (error)

N/A

(2)

Busy

Verify

Setup

EFP Verify

Ready

EFP

EFP Busy

(2)

Ready

N/A

EFP Verify

(2)

Quad EFP Busy

QuadEFP

Quad EFP

(2)

Busy

Ready

Quad EFP Busy

(2)

Busy

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, P/E. C. = Program/Erase Controller.

2. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’. EFP and Quad EFP are busy if Block Address is

first EFP Address. Any other commands are treated as data.

3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.

4. If the P/E.C. is active, both cycles are ignored.

5. Illegal commands are those not defined in the command set.

84/87

M58WR064FT, M58WR064FB

Table 43. Command Interface States - Lock Table, Next Output

Command Input

Block

Lock/CR

EFP Exit,

Quad EFP

Block Lock

Confirm

(01h)

Set CR

Confirm

(03h)

P/E. C.

Operation

Completed

Illegal

Command

(4)

(3)

Current CI State

Lock-Down

Confirm

(2Fh)

OTPSetup

(C0h)

(3)

Setup

(60h)

(2)

Exit

Program Setup

Erase Setup

OTP Setup

Program in Erase

Suspend

Status Register

EFP Setup

EFP Busy

EFP Verify

Quad EFP Setup

Quad EFP Busy

Lock/CR Setup

Output

Unchanged

Status Register

Array

Status Register

Lock/CR Setup in

Erase Suspend

OTP Busy

Ready

Program Busy

EraseBusy

Program/Erase

Output

Unchanged

Status Register

Output Unchanged

Array

Program Busy in

Erase Suspend

Program Suspend in

Erase Suspend

Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Fac-

tory Program, P/E. C. = Program/Erase Controller.

2. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh.

3. If the P/E.C. is active, both cycles are ignored.

4. Illegal commands are those not defined in the command set.

85/87

M58WR064FT, M58WR064FB

REVISION HISTORY

Table 44. Document Revision History

Date

Version

Revision Details

18-Oct-2002

1.0

First Issue

Synchronous Burst Read Suspend and Figure 14., Synchronous Burst Read Suspend

AC Waveforms, added. 16-Word burst and 16 Word boundary added. Security Block

removed from the document.

Automatic Standby mode explained under Asynchronous Read Mode. Minor text

change in Clear Status Register Command.

Bank Erase Command moved to Factory Program Commands section. Number of

Bank Erase cycles limited to 100. Erase replaced by Block Erase in Tables 11 and 12,

Dual Operations Allowed in Other Banks and the Same Bank, respectively.

12-Mar-2003

2.0

V

PP

= V

test condition for I

removed from Table 18., DC Characteristics -

PPH

PP2

Currents. Overbar removed from WAIT signal in Read AC Waveforms (Figures 10, 11,

12 and 13). t parameter changed for 70 and 80 class speeds in Table

EHEL

21., Synchronous Read AC Characteristics. Package mechanical data corrected

(Table 25.). Data reserved at addresses 35h and 38h (Table 33). Data and Value

modified at address offset (P+14)h = 4Dh. 16 Word burst added to Table 36., Burst

Read Information, and subsequent address offsets shifted by one (Tables 37, 38 and

39). Note to Table 30., Query Structure Overview, modified.

V

and V

voltage ranges limited to 1.7V to 2V and 1.7V to 2.24V, respectively;

DDQ

DD

max modified accordingly in Table 15., Absolute Maximum Ratings.

DDQ

PP1

parameter modified in Table 19., DC Characteristics - Voltages. Alt symbols for

t

and t

corrected in Table 23., Write AC Characteristics, Chip Enable

EHEL

ELEH

Controlled. Cross-references corrected.

Address lines corrected in Figure 14., Synchronous Burst Read Suspend AC

Waveforms. Connection added to Figure 20., VFBGA56 Daisy Chain - Package

Connections (Top view through package).

12-May-2003

2.1

Lead-free package options added to Table 26., Ordering Information Scheme, and

Table 27., Daisy Chain Ordering Scheme.

CFI information modified: at addresses 1Ch, 1Dh, 1Eh, 20h and 24h in Table Table 32.;

at address 2Ah in Table 33.; at address (P+4)h = 3Dh in Table 34.; at address (P+18)h

= 51h in Table 36. and at address (P+38)h = 71h in Table 39.

M58WR064FP and M58WR064FQ Part Numbers added. V protection feature

PP

disabled in the M58WR064FP and M58WR064FQ.

Set Configuration Register Command clarified. PROGRAM AND ERASE TIMES AND

ENDURANCE CYCLES section modified.

16 Word burst test condition added for f=40MHz and f=54MHz, and 66MHz burst

frequency added in Table 18., DC Characteristics - Currents.

11-Dec-2003

3.0

V

PP1

Min and V

Max corrected in Table 19., DC Characteristics - Voltages.

PPLK

t

parameter corrected for speed classes 70ns and 80ns in Table

GHQZ

20., Asynchronous Read AC Characteristics.

M58WR064FP and M58WR064FQ Part Numbers removed.

Typical values for Bank Erase and Main Block Erase (not preprogrammed), and for

Parameter and Main Block Program when V = V modified in Table 14., Program/

PP

DD

Erase Times and Endurance Cycles. Typical values for Erase and Bank Program when

15-Apr-2004

08-Oct-2004

4.0

5.0

V

PP

= V

modified in Table 14., Program/Erase Times and Endurance Cycles.

PPH

I

parameters for Synchronous Read at f = 40MHz removed from Table 18., DC

DD1

Characteristics - Currents. Small text changes.

Document status promoted from Product Preview to Preliminary Data.

I

values for Program/Erase in one Bank, Synchronous Read in another Bank

DD6

modified in Table 18., DC Characteristics - Currents.

AC Waveforms simplified. APPENDIX C. and APPENDIX D. revised.

Small text changes. Product fully Compliant with the ST ECOPACK specification.

Document Status promoted from Preliminary Data to Full Datasheet.

86/87

M58WR064FT, M58WR064FB

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

87/87


型号：	M58WR064FB60ZB6E
厂家：	ST
描述：	64 Mbit (4Mb x16, Multiple Bank, Burst) 1.8V Supply Flash Memory 64兆位（ 4Mb的X16 ，多个银行，连拍） 1.8V供应快闪记忆体闪存存储内存集成电路
文件：	总87页 (文件大小：570K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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