M68AR256ML70ZB6T [STMICROELECTRONICS]

256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TFBGA-48;


型号：	M68AR256ML70ZB6T
厂家：	ST
描述：	256KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 7 MM, 0.75 MM PITCH, TFBGA-48 静态存储器内存集成电路
文件：	总21页 (文件大小：112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M68AR256M

4 Mbit (256K x16) 1.8V Asynchronous SRAM

FEATURES SUMMARY

■

SUPPLY VOLTAGE: 1.65 to 1.95V

256K x 16 bits SRAM with OUTPUT ENABLE

EQUAL CYCLE and ACCESS TIME: 55ns,

70ns

Figure 1. Packages

FBGA

■

SINGLE BYTE READ/WRITE

LOW STANDBY CURRENT

LOW V_CCDATA RETENTION: 1.0V

TRI-STATE COMMON I/O

AUTOMATIC POWER DOWN

TFBGA48 PACKAGE

TFBGA48 (ZB)

6x7mm

–

Compliant with Lead-Free Soldering Pro-

cesses

–

Standard or Lead-Free Option

September 2004

1/21

M68AR256M

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Output Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Standby/Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . 12

Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . 12

Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12.UB/LB Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13.Low VCC Data Retention AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 9. Low V_CCData Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14.TFBGA48 6x7mm - 6x8 active ball array, 0.75mm pitch, Bottom View Package Outline 18

Table 10. TFBGA48 6x7mm - 6x8 active ball array, 0.75mm pitch, Package Mechanical Data . . . 18

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/21

M68AR256M

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3/21

M68AR256M

SUMMARY DESCRIPTION

The M68AR256M is a 4 Mbit (4,194,304 bit)

CMOS SRAM, organized as 262,144 words by 16

bits.

The M68AR256M has an automatic power-down

feature, reducing the power consumption by over

99%.

The device features fully static operation requiring

no external clocks or timing strobes, with equal ad-

dress access and cycle times. It operates from a

single 1.8V (±150mV) supply voltage.

The M68AR256M is available in TFBGA48 (0.75

mm pitch) package. In addition to the standard ver-

sion, the TFBGA48 package is also available in

Lead-free version, in compliance with the ST ECO-

PACK 7191395 Specification and the RoHS (Re-

striction of Hazardous Substances) directive.

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A17

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

Output Enable

A0-A17

DQ0-DQ15

Write Enable

Upper Byte Enable Input

Lower Byte Enable Input

Supply Voltage

M68AR256M

Ground

Not Connected Internally

Don’t Use as Internally Connected

AI04890C

4/21

M68AR256M

Figure 3. TFBGA Connections (Top view through package)

DQ8

DQ9

DQ0

DQ2

DQ10

DQ11

DQ12

DQ13

DQ1

DQ3

DQ4

DQ5

A17

A16

A15

A13

A10

DQ14

DQ15

A14

A12

DQ6

DQ7

A11

AI04882b

5/21

M68AR256M

Figure 4. Block Diagram

A17

ROW

DECODER

MEMORY

ARRAY

DQ15

(8)

I/O CIRCUITS

COLUMN

DECODER

DQ0

(8)

AI04833

6/21

M68AR256M

OPERATION

The M68AR256M has four standard operating

modes: Output Disabled, Read, Write and Stand-

by/Power-Down. These modes are determined by

the control inputs G, W, E, LB and UB as summa-

rized in Table 2., Operating Modes.

Output Disabled. The Output Enable signal, G,

provides high-speed tri-state control of DQ0-

DQ15, allowing fast read/write cycles on the com-

mon I/O data bus. The device is in Output Dis-

abled mode when Output Enable, G, is High. In

this mode, LB and UB are Don’t care and DQ0-

DQ15 are high impedance.

Read Mode. Read operations are used to output

the contents of the SRAM Array. The M68AR256M

is in the Read mode whenever Write Enable (W) is

High, V_IH, with Output Enable (G) Low, V_IL, Chip

Enables (E) is asserted and at least one of the

Byte Enable inputs, UB and LB, is at V_IL.

If only one of the Byte Enable inputs (UB or LB), is

at V_IL, the M68AR256M is in Byte Read mode. If

the two Byte Enable inputs (UB or LB) are at V_IL,

the M68AR256M is in Word Read mode. So de-

pending on the status of the UB and LB signals,

valid data will be available on the lower eight, the

upper eight or all sixteen output pins, t_AVQVafter

the last stable address providing G is Low and E is

Low.

Write Mode. Write operations are used to write

data to the SRAM. The M68AR256M is in the

Write mode whenever the W and E are Low, V_IL.

Either the Chip Enable input (E) or the Write

Enable input (W) must be de-asserted during

Address transitions for subsequent write cycles.

When E (W) is Low, and UB or LB is Low, write

cycle begins on the falling edge of W (E). When E

and W are Low, and UB = LB = High, write cycle

begins on the first falling edge of UB or LB.

Therefore, address setup time is referenced to

Write Enable, Chip Enable or UB/LB as t_AVWL

_AVELand t_AVBLrespectively, and is determined by

the latter occurring edge.

The Write cycle can be terminated by the earlier

rising edge of E, W or UB/LB.

If the Output is enabled (E = Low, G = Low, LB or

UB = Low), then W will return the outputs to high

impedance within t_WLQZof its falling edge. Care

must be taken to avoid bus contention in this type

of operation. Data input must be valid for t_DVWH

before the rising edge of Write Enable, or for t_DVEH

before the rising edge of E, or for t_DVBHbefore the

rising edge of UB/LB whichever occurs first, and

remain valid for t_WHDX, t_EHDXand t_BHDXrespec-

tively.

Standby/Power-Down Mode. The M68AR256M

has a Chip Enable Power-Down feature which in-

vokes an automatic standby mode whenever ei-

ther Chip Enable is de-asserted (E = High) or LB

and UB are de-asserted (LB and UB = High).

If either of E, G and UB/LB is asserted after t_AVQV

has elapsed, data access will be measured from

the limiting parameter (t_ELQV, t_GLQVor t_BLQV) rath-

er than the address.Data out may be indetermi-

nate at t_ELQX, t_GLQXand t_BLQX, but data lines will

An Output Enable (G) signal provides a high

speed tri-state control, allowing fast read/write cy-

cles to be achieved with the common I/O data bus.

Operational modes are determined by device con-

trol inputs W, E, LB and UB as summarized in the

Operating Modes table (see Table 2).

always be valid at t_AVQV

7/21

M68AR256M

Table 2. Operating Modes

Operation

DQ0-DQ7

Hi-Z

DQ8-DQ15

Hi-Z

Power

Standby (I

Active (I

)

Standby (Deselected)

Hi-Z

)

Lower Byte Read

Lower Byte Write

Output Disabled

Upper Byte Read

Upper Byte Write

Word Read

Data Output

Data Input

Hi-Z

Active (I

Hi-Z

)

Hi-Z

Data Output

Data Input

Data Output

Data Input

Hi-Z

Data Output

Data Input

Hi-Z

Word Write

Output Disabled

X = V or V .

8/21

M68AR256M

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 3. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

(1)

Output Current

Ambient Operating Temperature

Storage Temperature

–55 to 125

–65 to 150

°C

STG

(2)

(3)

LEAD

Lead Temperature during Soldering

Supply Voltage

260

–0.5 to 2.5

(4)

–0.5 to V + 0.5

Input or Output Voltage

Power Dissipation

Note: 1. One output at a time, not to exceed 1 second duration.

2. Compliant with the ST 7191395 specification for Lead-free soldering processes.

3. Not exceeding 250°C for more than 30s, and peaking at 260°C.

4.Up to a maximum operating V of 1.95V only.

9/21

M68AR256M

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 4. Operating and AC Measurement Conditions

Parameter

M68AR256M

Supply Voltage

1.65 to 1.95V

Range 1

Range 6

0 to 70°C

–40 to 85°C

30pF

Ambient Operating Temperature

Load Capacitance (C )

Output Circuit Protection Resistance (R )

15.3kΩ

Load Resistance (R )

11.3kΩ

Input Rise and Fall Times

1ns/V

0 to V

Input Pulse Voltages

Input and Output Timing Ref. Voltages

Output Transition Timing Ref. Voltages

= 0.3V ; V = 0.7V

CC RH CC

Figure 5. AC Measurement I/O Waveform

Figure 6. AC Measurement Load Circuit

I/O Timing Reference Voltage

DEVICE

UNDER

TEST

OUT

Output Timing Reference Voltage

0.7V

0.3V

AI04831

includes probe and 1TTL capacitance

AI03853

10/21

M68AR256M

Table 5. Capacitance

Symbol

Test

Condition

(1,2)

Min

Max

Unit

Parameter

= 0V

Input Capacitance on all pins (except DQ)

Output Capacitance

OUT

Note: 1. Sampled only, not 100% tested.

2.At T = 25°C, f = 1 MHz, V = 1.8V.

Table 6. DC Characteristics

M68AR256M

Symbol

Parameter

Test Condition

-L

-N

Min

Max

Min

Max

Unit

f = 1/t

= 1.95V,

55ns

70ns

Operating Supply

Current

CC1

(1,2)

AVAV

= 0mA

OUT

= 1.95V, f = 1MHz,

Operating Supply

Current

(3)

CC2

= 0mA

OUT

0V ≤ V ≤ V

Input Leakage Current

Output Leakage Current

–1

µA

(4)

(3)

0V ≤ V

≤ V

OUT

= 1.95V,

Standby Supply Current

CMOS

E ≥ V –0.2V or

LB=UB ≥ V –0.2V, f = 0

µA

+ 0.4

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

1.4

–0.5

1.5

1.4

–0.5

1.5

0.4

= –100µA

= 100µA

0.2

Note: 1. Average AC current, cycling at t

minimum.

AVAV

2. E = V , LB or/and UB = V , V = V or V .

3.E ≤ 0.2V, LB or/and UB ≤ 0.2V, V ≤ 0.2V or V_IN≥ V –0.2V.

4. Output disabled.

Figure 7. Address Controlled, Read Mode AC Waveforms

tAVAV

A0-A17

VALID

tAVQV

tAXQX

DQ0-DQ7 and/or DQ8-DQ15

DATA VALID

AI03956b

Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.

11/21

M68AR256M

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

tAVAV

A0-A17

VALID

tAVQV

tELQV

tAXQX

tEHQZ

tELQX

tGLQV

tGHQZ

tGLQX

DQ0-DQ15

VALID

tBLQV

tBHQZ

UB, LB

tBLQX

AI03957

Note: Write Enable (W) = High.

Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms

E, UB, LB

tPU

tPD

50%

AI03856

12/21

M68AR256M

Table 7. Read and Standby Mode AC Characteristics

M68AR256M

Symbol

Parameter

Unit

Read Cycle Time

Min

AVAV

Address Valid to Output Valid

Max

AVQV

(1)

Data hold from address change

Min

Max

Min

AXQX

(2,3)

Upper/Lower Byte Enable High to Output Hi-Z

Upper/Lower Byte Enable Low to Output Valid

Upper/Lower Byte Enable Low to Output Transition

Chip Enable High to Output Hi-Z

BHQZ

BLQV

(1)

BLQX

(2,3)

Max

Min

EHQZ

Chip Enable Low to Output Valid

ELQV

(1)

Chip Enable Low to Output Transition

Output Enable High to Output Hi-Z

ELQX

(2,3)

Max

Min

GHQZ

Output Enable Low to Output Valid

GLQV

(2)

Output Enable Low to Output Transition

Chip Enable or UB/LB High to Power Down

Chip Enable or UB/LB Low to Power Up

GLQX

(4)

Max

Min

(4)

Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V

2. At any given temperature and voltage condition, t

any given device.

is less than t

, t

is less than t

and t

is less than t

for

GHQZ

GLQX BHQZ

BLQX

EHQZ

ELQX

3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

4.Tested initially and after any design or process changes that may affect these parameters.

13/21

M68AR256M

Figure 10. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A17

VALID

tAVWH

tELWH

tWHAX

tWLWH

tAVWL

tWLQZ

tWHQX

tWHDX

DQ0-DQ15

UB, LB

DATA INPUT

tDVWH

tBLWH

AI03958b

Figure 11. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A17

VALID

tAVEH

tELEH

tAVEL

tEHAX

tWLEH

tEHDX

DQ0-DQ15

DATA INPUT

tDVEH

tBLEH

UB, LB

AI03959b

14/21

M68AR256M

Figure 12. UB/LB Controlled, Write AC Waveforms

tAVAV

A0-A17

VALID

tAVBH

tBHAX

tELBH

tWLBH

tBHDX

DQ0-DQ15

DATA ⁽¹⁾

DATA INPUT

tDVBH

tAVBL

tBLBH

UB, LB

AI03987b

Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.

15/21

M68AR256M

Table 8. Write Mode AC Characteristics

M68AR256M

Symbol

Parameter

-L

-N

Unit

Write Cycle Time

Min

AVAV

Address Valid to LB, UB High

AVBH

Addess Valid to LB, UB Low

AVBL

Address Valid to Chip Enable High

Address valid to Chip Enable Low

Address Valid to Write Enable High

Address Valid to Write Enable Low

LB, UB High to Address Transition

LB, UB High to Input Transition

LB, UB Low to LB, UB High

AVEH

AVEL

AVWH

AVWL

BHAX

BHDX

BLBH

LB, UB Low to Chip Enable High

LB, UB Low to Write Enable High

Input Valid to LB, UB High

BLEH

BLWH

DVBH

Input Valid to Chip Enable High

Input Valid to Write Enable High

Chip Enable High to Address Transition

Chip enable High to Input Transition

Chip Enable Low to LB, UB High

Chip Enable Low to Chip Enable High

Chip Enable Low to Write Enable High

Write Enable High to Address Transition

Write Enable High to Input Transition

DVEH

DVWH

EHAX

EHDX

ELBH

ELEH

ELWH

WHAX

WHDX

(1)

Write Enable High to Output Transition

Write Enable Low to LB, UB High

Write Enable Low to Chip Enable High

Write Enable Low to Output Hi-Z

Min

Max

WHQX

WLBH

WLEH

(1,2)

WLQZ

Write Enable Low to Write Enable High

Min

WLWH

Note: 1. At any given temperature and voltage condition, t

is less than t

for any given device.

WHQX

WLQZ

2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

16/21

M68AR256M

Figure 13. Low V_CCData Retention AC Waveforms

DATA RETENTION MODE

1.95V

1.65V

> 1.0V

tCDR

E ≥ V

– 0.2V or UB = LB ≥ V

– 0.2V

E or UB/LB

AI03859

Table 9. Low V_CCData Retention Characteristics

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

= 1.0V, E ≥ V –0.2V or

(1)

Supply Current (Data Retention)

0.5

µA

CCDR

(3)

UB = LB ≥ V –0.2V, f = 0

Chip Deselected to Data

Retention Time

(1,2)

CDR

(2)

Operation Recovery Time

AVAV

E ≥ V –0.2V or

(1)

Supply Voltage (Data Retention)

1.0

UB = LB ≥ V –0.2V, f = 0

Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.

2. Tested initially and after any design or process changes that may affect these parameters. t

is Read cycle time.

AVAV

3. No input may exceed V +0.2V.

17/21

M68AR256M

PACKAGE MECHANICAL

Figure 14. TFBGA48 6x7mm - 6x8 active ball array, 0.75mm pitch, Bottom View Package Outline

BALL "A1"

ddd

BGA-Z43

Note: Drawing is not to scale.

Table 10. TFBGA48 6x7mm - 6x8 active ball array, 0.75mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.400

Typ

Max

0.0472

0.0157

0.250

0.0098

0.790

0.400

6.000

3.750

0.0311

0.0157

0.2362

0.1476

0.350

5.900

0.450

6.100

0.0138

0.2323

0.0177

0.2402

ddd

0.100

7.100

0.0039

0.2795

7.000

5.250

0.750

1.125

0.875

0.375

6.900

–

0.2756

0.2067

0.0295

0.0443

0.0344

0.0148

0.2717

–

18/21

M68AR256M

PART NUMBERING

Table 11. Ordering Information Scheme

Example:

M68AR256

55 ZB

Device Type

M68

Mode

A = Asynchronous

Operating Voltage

R = 1.65 to 1.95V

Array Organization

256 = 4 Mbit (256K x16)

Option 1

M = 1 Chip Enable; Write and Standby from UB and LB

Option 2

L = L-Die

N= N-Die

Speed Class

55 = 55 ns

70 = 70 ns

Package

ZB = TFBGA48 6x7mm, 0.75mm pitch

Operative Temperature

1 = 0 to 70 °C

6 = –40 to 85 °C

Shipping

Blank = Standard Packing (Tray)

T = Tape and Reel Packing

E = Lead-Free Package, Standard Packing (Tray)

F = Lead-Free Package, Tape and Reel Packing

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

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M68AR256M

REVISION HISTORY

Table 12. Document Revision History

Date

July 2001

Version

-01

Revision Details

First Issue

23-Oct-2001

20-May-2002

-02

Speed class changed from 80 to 70ns

Document globally revised

-03

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 03 equals 3.0)

01-Oct-2002

09-Oct-2002

3.1

3.2

Part number changed

Part number clarified

N-die added.

TFBGA48 7 x 8mm replaced by TFBGA48 6 x 7mm

and I updated in Table 6.DC Characteristics.

CC1

20-Feb-2004

4.0

N-die AC Write Characteristics added in Table 8. Write Mode AC Characteristics.

Minor content modifications.

Lead-free package option added in Table 11.Ordering Information Scheme.

Connection E3 updated in Figure 3., TFBGA Connections (Top view through

package).

03-Aug-2004

27-Sep-2004

5.0

6.0

and t modified in Table 7., Read and Standby Mode AC Characteristics.

Document structure updated without modifications of the content.

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M68AR256M

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

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