M68AR256ML80ZB6T [STMICROELECTRONICS]
256KX16 STANDARD SRAM, 80ns, PBGA48, 0.75 MM PITCH, TFBGA-48;
| 型号： | M68AR256ML80ZB6T |
| 厂家： | 
ST |
| 描述： | 256KX16 STANDARD SRAM, 80ns, PBGA48, 0.75 MM PITCH, TFBGA-48 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：119K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M68AR256ML
4 Mbit (256K x16) 1.8V Asynchronous SRAM
FEATURES SUMMARY
■ SUPPLY VOLTAGE: 1.65 to 1.95V
■ 256K x 16 bits SRAM with OUTPUT ENABLE
■ EQUAL CYCLE and ACCESS TIME: 55ns
■ LOW STANDBY CURRENT
Figure 1. Packages
BGA
■ LOW V
DATA RETENTION: 1.0V
CC
■ TRI-STATE COMMON I/O
TFBGA48 (ZB)
6 x 8 solder balls
■ AUTOMATIC POWER DOWN
July 2001
1/17
M68AR256ML
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . 9
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9
Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . . . . . . . . . . 15
TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . 15
PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
M68AR256ML
SUMMARY DESCRIPTION
The M68AR256ML is a 4 Mbit (4,194,304 bit)
CMOS SRAM, organized as 262,144 words by 16
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 1.8V (±150mV) supply. This device has an
automatic power-down feature, reducing the pow-
er consumption by over 99% when deselected.
The M68AR256ML is available in TFBGA48 (0.75
mm pitch) package.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ15
Data Input/Output
Chip Enable
V
CC
E
G
Output Enable
18
16
A0-A17
DQ0-DQ15
W
UB
LB
Write Enable
Upper Byte Enable Input
Lower Byte Enable Input
Supply Voltage
W
E
M68AR256ML
V
CC
G
V
SS
Ground
UB
LB
NC
DU
Not Connected Internally
Don’t Use as Internally Connected
V
SS
AI04890
3/17
M68AR256ML
Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A2
E
NC
A
B
C
D
E
F
LB
G
A0
A3
A1
A4
A6
DQ8
DQ9
DQ0
DQ2
UB
DQ10
DQ11
DQ12
DQ13
NC
A5
DQ1
DQ3
DQ4
DQ5
W
A7
V
A17
NC
A14
A12
A9
V
SS
CC
V
A16
A15
A13
A10
V
CC
SS
DQ14
DQ15
NC
DQ6
DQ7
DU
G
H
A8
A11
AI04882
4/17
M68AR256ML
Figure 4. Block Diagram
V
V
CC
SS
A17
A7
ROW
DECODER
MEMORY
ARRAY
DQ15
UB
(8)
(8)
I/O CIRCUITS
COLUMN
DECODER
DQ0
LB
A0
A6
(8)
(8)
UB
LB
W
E
UB
LB
G
AI04833
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
20
Unit
mA
°C
°C
V
(1)
Output Current
I
O
T
A
Ambient Operating Temperature
Storage Temperature
Supply Voltage
–55 to 125
–65 to 150
–0.5 to 2.5
T
STG
V
CC
(2)
–0.5 to V + 0.5
Input or Output Voltage
Power Dissipation
V
V
IO
CC
P
1
W
D
Note: 1. One output at a time, not to exceed 1 second duration.
2. Up to a maximum operating V of 1.95V only.
CC
5/17
M68AR256ML
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M68AR256ML
1.65 to 1.95V
–40 to 85°C
30 or 5pF
15.3kΩ
V
CC
Supply Voltage
Ambient Operating Temperature
Load Capacitance (C )
L
Output Circuit Protection Resistance (R )
1
Load Resistance (R )
11.3kΩ
2
Input Rise and Fall Times
≤ 4ns
0 to V
Input Pulse Voltages
CC
V
/2
Input and Output Timing Ref. Voltages
Input and Output Transition Timing Ref. Voltages
CC
V
OL
= 0.3V ; V = 0.7V
CC OH CC
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
V
CC
1N914
I/O Timing Reference Voltage
V
CC
R
1
V
/2
CC
0V
DEVICE
UNDER
TEST
OUT
C
L
I/O Transition Timing Reference Voltage
R
2
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
C
includes JIG capacitance
L
AI03853
6/17
M68AR256ML
Table 4. Capacitance
Symbol
Test
Condition
(1,2)
Min
Max
Unit
Parameter
C
V
= 0V
= 0V
Input Capacitance on all pins (except DQ)
Output Capacitance
6
8
pF
pF
IN
(3)
IN
V
C
OUT
OUT
Note: 1. Sampled only, not 100% tested.
2. At T = 25°C, f = 1 MHz, V = 1.8V.
A
CC
3. Outputs deselected.
Table 5. DC Characteristics
Symbol
Parameter
Test Condition
= 1.95V, f = 1/t
Min
Typ
Max
Unit
V
,
AVAV
CC
(1)
Operating Supply Current
3
1
7
mA
I
CC1
I
= 0mA
OUT
V
= 1.95V, f = 1MHz,
CC
I
Operating Supply Current
2
mA
CC2
I
= 0mA
OUT
I
0V ≤ V ≤ V
IN
Input Leakage Current
Output Leakage Current
–1
–1
1
1
µA
µA
LI
CC
(3)
I
0V ≤ V
≤ V
LO
OUT
CC
V
= 1.95V,
CC
(2)
Standby Supply Current CMOS
1
µA
I
SB
E ≥ V –0.15V, f = 0
CC
V
V
CC
– 0.4
V
CC
+ 0.4
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
V
V
V
V
IH
V
–0.5
1.5
0.4
0.2
IL
V
OH
V
= 1.65V, I = –100µA
CC
OH
V
V
= 1.65V, I = 100µA
OL
CC
OL
Note: 1. Average AC current, cycling at t
minimum.
AVAV
2. All other Inputs at V ≤ 0.15V or V ≥ V –0.15V.
IL
IH
CC
3. Output disabled.
7/17
M68AR256ML
OPERATION
The M68AR256ML has a Chip Enable power
down feature which invokes an automatic standby
mode whenever either Chip Enable is de-asserted
(E = High) or LB and UB are de-asserted (LB and
UB = High). An Output Enable (G) signal provides
a high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus. Operational modes are determined by
device control inputs W, E, LB and UB as summa-
rized in the Operating Modes table (see Table 6).
Table 6. Operating Modes
Operation
Deselected/Power-down
Deselected/Power-down
Lower Byte Read
Lower Byte Write
Output Disabled
Output Disabled
Upper Byte Read
Upper Byte Write
Word Read
E
W
X
G
X
X
LB
UB
DQ0-DQ7
Hi-Z
DQ8-DQ15
Hi-Z
Power
Standby (I
Standby (I
Active (I
V
)
SB
X
X
IH
V
V
IH
)
SB
X
X
Hi-Z
Hi-Z
IH
V
V
IH
V
V
IL
V
IH
)
)
)
)
)
)
)
)
Data Output
Data Input
Hi-Z
Hi-Z
IL
IL
IL
IL
IL
IL
IL
IL
IL
CC
V
V
V
V
V
V
V
V
V
IL
V
IH
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
Active (I
X
Hi-Z
IL
CC
CC
CC
CC
CC
CC
CC
V
IH
V
IL
X
X
Hi-Z
V
IH
V
IL
X
X
Hi-Z
Hi-Z
V
IH
V
V
IH
V
IL
Hi-Z
Data Output
Data Input
Data Output
Data Input
IL
IL
V
V
V
IH
V
IL
X
Hi-Z
IL
V
V
IL
V
IL
Data Output
Data Input
IH
V
V
IL
V
IL
Word Write
X
IL
X = V or V
.
IL
IH
Read Mode
The M68AR256ML is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enables (E) is asserted. This pro-
vides access to data from eight or sixteen, de-
pending on the status of the signal UB and LB, of
the 4,194,304 locations in the static memory array,
specified by the 18 address inputs. Valid data will
be available at the eight or sixteen output pins
within t
after the last stable address, provid-
AVQV
ing G is Low and E is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (t
,
ELQV
t
or t
) rather than the address. Data out
GLQV
BLQV
may be indeterminate at t
, t
and t
,
ELQX BLQX
GLQX
but data lines will always be valid at t
.
AVQV
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A17
VALID
tAVQV
tAXQX
DQ0-DQ15
DATA VALID
AI03956
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
8/17
M68AR256ML
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
A0-A17
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ15
VALID
tBLQV
tBHQZ
UB, LB
tBLQX
AI03957
Note: Write Enable (W) = High.
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
E, UB, LB
tPU
tPD
I
CC
50%
I
SB
AI03856
9/17
M68AR256ML
Table 7. Read and Standby Mode AC Characteristics
M68AR256ML
Symbol
Parameter
Unit
55
80
80
80
10
t
Read Cycle Time
Min
Max
Min
55
55
10
ns
ns
ns
AVAV
t
Address Valid to Output Valid
Data hold from address change
AVQV
t
AXQX
(1, 2)
Upper/Lower Byte Enable High to Output Hi-Z
Upper/Lower Byte Enable Low to Output Valid
Upper/Lower Byte Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Max
Max
Min
20
55
5
20
80
10
25
ns
ns
ns
ns
t
t
BHQZ
t
BLQV
t
BLQX
(1, 2)
Max
20
EHQZ
t
Chip Enable Low to Output Valid
Max
Min
Max
Max
Min
Max
Min
55
10
20
80
10
25
35
5
ns
ns
ns
ns
ns
ns
ns
ELQV
t
Chip Enable Low to Output Transition
Output Enable High to Output Hi-Z
Output Enable Low to Output Valid
Output Enable Low to Output Transition
Chip Enable or UB/LB High to Power Down
Chip Enable or UB/LB Low to Power Up
ELQX
(1, 2)
t
GHQZ
t
20
5
GLQV
t
GLQX
t
t
55
0
80
PD
PU
0
Note: 1. At any given temperature and voltage condition, t
any given device.
is less than t
, t
is less than t
and t
is less than t
for
GHQZ
GLQX BHQZ
BLQX
EHQZ
ELQX
2. C = 5pF.
L
10/17
M68AR256ML
Write Mode
The M68AR256ML is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB.
If the Output is enabled (E = Low, G = Low, LB or
UB = Low), then W will return the outputs to high
asserted
during
Address
transitions
for
subsequent write cycles. When E (W) is Low, and
UB or LB is Low, write cycle begins on the W (E)'s
falling edge. When E and W are Low, and UB = LB
= High, write cycle begins on the first falling edge
of UB or LB. Therefore, address setup time is
referenced to Write Enable, Chip Enable or UB/LB
impedance within t
of its falling edge. Care
WLQZ
must be taken to avoid bus contention in this type
of operation. Data input must be valid for t
DVWH
before the rising edge of Write Enable, or for t
DVEH
before the rising edge of E, or for t
before the
DVBH
rising edge of UB/LB whichever occurs first, and
as t
, t
and t
respectively, and is
AVWL AVEL
AVBL
remain valid for t
tively.
, t
and t
respec-
WHDX EHDX
BHDX
determined by the latter occurring edge.
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ15
UB, LB
DATA INPUT
tDVWH
tBLWH
AI03958
11/17
M68AR256ML
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A17
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ15
DATA INPUT
tDVEH
tBLEH
UB, LB
AI03959
Figure 12. UB/LB Controlled, Write AC Waveforms
tAVAV
VALID
tAVBH
A0-A17
E
tBHAX
tAVWL
W
tWLQZ
tBHDX
DQ0-DQ15
DATA (2)
DATA INPUT
tDVBH
tAVBL
tBLBH
UB, LB
AI03987
Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.
12/17
M68AR256ML
Table 8. Write Mode AC Characteristics
M68AR256ML
Symbol
Parameter
Unit
55
55
40
0
80
80
70
0
t
Write Cycle Time
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to LB, UB High
AVBH
t
Addess Valid to LB, UB Low
AVBL
t
Address Valid to Chip Enable High
Address valid to Chip Enable Low
Address Valid to Write Enable High
Address Valid to Write Enable Low
LB, UB High to Address Transition
LB, UB High to Input Transition
LB, UB Low to LB, UB High
40
0
70
0
AVEH
t
AVEL
t
40
0
70
0
AVWH
t
AVWL
t
0
0
BHAX
t
0
0
BHDX
t
40
40
40
20
20
20
0
70
70
70
25
25
25
0
BLBH
t
LB, UB Low to Chip Enable High
LB, UB Low to Write Enable High
Input Valid to LB, UB High
BLEH
t
BLWH
t
DVBH
t
Input Valid to Chip Enable High
Input Valid to Write Enable High
Chip Enable High to Address Transition
Chip enable High to Input Transition
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Write Enable High to Input Transition
DVEH
t
DVWH
t
EHAX
t
0
0
EHDX
t
40
0
70
0
ELEH
t
WHAX
t
0
0
WHDX
(1)
Write Enable High to Output Transition
Write Enable Low to Output Hi-Z
Min
5
5
ns
ns
ns
t
WHQX
(1,2)
Max
20
40
20
60
t
WLQZ
t
Write Enable Low to Write Enable High
Min
WLWH
Note: 1. At any given temperature and voltage condition, t
is less than t
for any given device.
WLQX
WHQZ
2. C = 5pF
L
13/17
M68AR256ML
Figure 13. Low V Data Retention AC Waveforms
CC
DATA RETENTION MODE
1.9V
1.8V
V
CC
V
> 1.0V
DR
tCDR
tR
E ≥ V
– 0.2V
DR
E
AI03859
Table 9. Low V Data Retention Characteristics
CC
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
(1)
(3)
Supply Current (Data Retention)
0.1
1
µA
I
V
CC
= 1.0V, E ≥ V –0.3V, f = 0
CCDR
CC
Chip deselected to Data
Retention Time
(1,2)
E ≥ V –0.3V, f = 0
0
ns
t
CC
CDR
(2)
t
Operation Recovery Time
ns
V
t
AVAV
R
(1)
E ≥ V –0.3V, f = 0
Supply Voltage (Data Retention)
1.0
1.95
V
CC
DR
Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.
IH
CC
IL
2. See Figure 6 for measurement points. Guaranteed but not tested. t
is Read cycle time.
AVAV
3. No input may exceed V +0.3V.
CC
14/17
M68AR256ML
PACKAGE MECHANICAL
Figure 14. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline
D
D1
FD
FE
SD
SE
BALL "A1"
E
E1
ddd
e
e
b
A
A2
A1
BGA-Z22
Note: Drawing is not to scale.
Table 10. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.200
0.0472
0.260
0.0102
0.900
0.0354
0.350
6.900
–
0.450
0.0138
0.2717
–
0.0177
D
7.000
3.750
7.100
0.2756
0.1476
0.2795
D1
ddd
E
–
–
0.100
0.0039
8.000
5.250
0.750
1.625
1.375
0.375
0.375
7.900
8.100
0.3150
0.2067
0.0295
0.0640
0.0541
0.0148
0.0148
0.3110
0.3189
E1
e
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
FD
FE
SD
SE
15/17
M68AR256ML
PART NUMBERING
Table 11. Ordering Information Scheme
Example:
M68AR256
M
L
55 ZB
6
T
Device Type
M68
Mode
A = Asynchronous
Operating Voltage
R = 1.65 to 1.95V
Array Organization
256 = 4 Mbit (256K x16)
Option 1
M = 1 Chip Enable; Write and Standby from UB and LB
Option 2
L = Low Leakage
Speed Class
55 = 55 ns
80 = 80 ns
Package
ZB = TFBGA48: 0.75 mm pitch
Operative Temperature
6 = –40 to 85 °C
Shipping
T = Tape & Reel Packing
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
REVISION HISTORY
Table 12. Document Revision History
Date
July 2001
Version
Revision Details
-01
First Issue
16/17
M68AR256ML
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners.
© 2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
www.st.com
17/17
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