M68AR512D_技术文档

M68AR512D

8 Mbit (512K x16) 1.8V Asynchronous SRAM

FEATURES SUMMARY

■ SUPPLY VOLTAGE: 1.65 to 1.95V

■ 512K x 16 bits SRAM with OUTPUT ENABLE

■ EQUAL CYCLE and ACCESS TIMES: 70ns

■ SINGLE BYTE READ/WRITE

Figure 1. Packages

BGA

■ LOW STANDBY CURRENT

■ LOW V

DATA RETENTION: 1.0V

CC

TFBGA48 (ZB)

6 x 7mm

■ TRI-STATE COMMON I/O

■ AUTOMATIC POWER DOWN

■ DUAL CHIP ENABLE for EASY DEPTH

EXPANSION

BGA

TFBGA48 (ZB)

8 x 10mm

October 2002

1/19

M68AR512D

TABLE OF CONTENTS

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DC and AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . 9

Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9

Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 11. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 13. E1 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

Figure 14. E2 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

Table 9. Low VCC Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PACKAGE MECHANICAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . . . . . . . . . 15

TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . . 15

TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . . . . . . . . 16

TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . 16

PART NUMBERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/19

M68AR512D

SUMMARY DESCRIPTION

The M68AR512D is an 8 Mbit (8,388,608 bit)

CMOS SRAM, organized as 524,288 words by 16

bits. The device features fully static operation re-

quiring no external clocks or timing strobes, with

equal address access and cycle times. It requires

a single 1.8V (±150mV) supply. This device has a

Chip Select pin (E2) for easy memory expansion;

when it is active (E2 high) the device has an auto-

matic power-down feature, reducing the power

consumption by over 99%.

The M68AR512D is available in TFBGA48

(6x7mm and 8x10mm, 6x8 active ball array, 0.75

mm ball pitch) package. See the Ordering Informa-

tion Scheme (Table 12) for details.

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A18

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

V

CC

E1, E2

G

19

16

Output Enable

A0-A18

W

DQ0-DQ15

W

Write Enable

UB

LB

Upper Byte Enable Input

Lower Byte Enable Input

Supply Voltage

E1

E2

M68AR512D

V

CC

V

Ground

G

SS

NC

DU

Not Connected

UB

LB

Don’t Use as Internally Connected

V

SS

AI03953C

3/19

M68AR512D

Figure 3. TFBGA Connections (Top view through package)

1

2

3

4

5

6

A2

E1

E2

A

B

C

D

E

F

LB

G

A0

A3

A1

A4

A6

DQ8

DQ9

DQ0

DQ2

UB

DQ10

DQ11

DQ12

DQ13

NC

A5

DQ1

DQ3

DQ4

DQ5

W

A7

V

A17

V

SS

CC

V

A16

A15

A13

A10

V

CC

SS

DQ14

DQ15

A18

A14

A12

A9

DQ6

DQ7

DU

G

H

A8

A11

AI03960

4/19

M68AR512D

Figure 4. Block Diagram

A18

A8

ROW

DECODER

MEMORY

ARRAY

DQ15

UB

(8)

I/O CIRCUITS

COLUMN

DECODER

DQ0

LB

E1

E2

Ex

UB

LB

A0

A7

(8)

UB

LB

W

G

AI05452

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

20

Unit

mA

°C

V

(1)

Output Current

I

O

T

A

Ambient Operating Temperature

Storage Temperature

Supply Voltage

–55 to 125

–65 to 150

–0.5 to 2.5

T

STG

V

CC

(2)

–0.5 to V +0.5

Input or Output Voltage

V

IO

CC

P

D

Power Dissipation

1

W

Note: 1. One output at a time, not to exceed 1 second duration.

2. Up to a maximum operating V of 1.95V only.

CC

5/19

M68AR512D

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. Operating and AC Measurement Conditions

Parameter

M68AR512D

V

Supply Voltage

1.65 to 1.95V

CC

Range 1

Range 6

0 to 70°C

–40 to 85°C

30pF

Ambient Operating Temperature

Load Capacitance (C )

L

Output Circuit Protection Resistance (R )

15.3kΩ

1

Load Resistance (R )

11.3kΩ

2

Input Rise and Fall Times

1ns/V

0 to V

Input Pulse Voltages

CC

V

/2

Input and Output Timing Ref. Voltages

Output Transition Timing Ref. Voltages

CC

V

= 0.3V ; V = 0.7V

CC RH CC

RL

Figure 5. AC Measurement I/O Waveform

Figure 6. AC Measurement Load Circuit

V

CC

I/O Timing Reference Voltage

R

1

V

CC

V

/2

CC

DEVICE

UNDER

TEST

OUT

0V

C

L

Output Timing Reference Voltage

R

2

V

CC

0.7V

0.3V

CC

0V

AI04831

C

includes probe and 1TTL capacitance

L

AI03853

6/19

M68AR512D

Table 4. Capacitance

Symbol

Test

Condition

(1,2)

Min

Max

Unit

Parameter

C

V

= 0V

Input Capacitance on all pins (except DQ)

Output Capacitance

6

8

pF

IN

C

V

OUT

Note: 1. Sampled only, not 100% tested.

2. At T = 25°C, f = 1 MHz, V = 1.8V.

A

CC

Table 5. DC Characteristics

Symbol

Parameter

Test Condition

= 1.95V, f = 1/t

Min

Typ

Max

Unit

V

CC

,

AVAV

(1,2)

Operating Supply Current

12

mA

I

CC1

I

= 0mA

OUT

V

CC

= 1.95V, f = 1MHz,

(3)

Operating Supply Current

2

mA

I

CC2

I

= 0mA

OUT

I

0V ≤ V ≤ V

IN CC

Input Leakage Current

Output Leakage Current

–1

1

µA

LI

(4)

I

0V ≤ V ≤ V

OUT CC

LO

V

= 1.95V,

CC

E1 ≥ V –0.2V or

CC

(3)

Standby Supply Current CMOS

1

15

µA

SB

E2 ≤ 0.2V or

UB=LB ≥ V –0.2V, f = 0

CC

V

CC

+ 0.4

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

1.4

–0.5

1.5

V

IH

V

0.4

0.2

IL

V

OH

I

= –100µA

= 100µA

OH

V

I

OL

Note: 1. Average AC current, cycling at t

minimum.

AVAV

2. E1 = V , E2 = V , UB or/and LB = V , V = V or V .

IL

IH

IL

IN

IH

IL

3. E1 ≤ 0.2V or E2 ≥ V –0.2V, LB or/and UB ≤ 0.2V, V ≤ 0.2V or V_IN≥ V –0.2V.

CC

IN

CC

4. Output disabled.

7/19

M68AR512D

OPERATION

The M68AR512D has a Chip Enable power down

feature which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E1 = High)

or Chip Select is asserted (E2 = Low), or UB/LB

are de-asserted (UB/LB = High). An Output En-

able (G) signal provides a high speed tri-state con-

trol, allowing fast read/write cycles to be achieved

with the common I/O data bus. Operational modes

are determined by device control inputs W, E1, LB

and UB as summarized in the Operating Modes ta-

ble (see Table 6).

Table 6. Operating Modes

Operation

Deselected/Power-down

Lower Byte Read

Lower Byte Write

Output Disabled

E1

E2

W

X

G

X

LB

X

UB

X

DQ0-DQ7

Hi-Z

DQ8-DQ15

Hi-Z

Power

Standby (I

Active (I

V

IH

)

X

SB

V

X

Hi-Z

IL

SB

V

IH

X

Hi-Z

IH

SB

V

IH

V

IH

V

IL

V

IL

V

IH

)

Data Output

Data Input

Hi-Z

IL

CC

V

IH

V

IL

V

IL

V

IH

Active (I

)

X

Hi-Z

IL

CC

V

IH

V

IH

X

)

X

Hi-Z

IL

CC

V

IH

V

IH

V

IL

V

IH

V

IL

Upper Byte Read

Upper Byte Write

Word Read

Hi-Z

Data Output

Data Input

IL

V

IH

V

IH

V

IL

X

Hi-Z

IL

V

IH

V

IL

V

IL

V

IL

Data Output Data Output

Data Input Data Input

IL

IH

V

IH

V

IL

V

IL

V

IL

Word Write

X

IL

Note: X = V or V .

IH

IL

Read Mode

The M68AR512D, when Chip Select (E2) is High,

is in the read mode whenever Write Enable (W) is

High with Output Enable (G) Low, and Chip En-

able (E1) is asserted. This provides access to data

from eight or sixteen, depending on the status of

the signal UB and LB, of the 8,388,608 locations in

the static memory array, specified by the 19 ad-

dress inputs. Valid data will be available at the

eight or sixteen output pins within t

after the

AVQV

last stable address, providing G is Low and E1 is

Low. If Chip Enable or Output Enable access

times are not met, data access will be measured

from the limiting parameter (t

, t

or t

)

ELQV GLQV

BLQV

rather than the address. Data out may be indeter-

minate at t

will always be valid at t

, t

and t

, but data lines

ELQX GLQX

BLQX

.

AVQV

Figure 7. Address Controlled, Read Mode AC Waveforms

tAVAV

A0-A18

VALID

tAVQV

tAXQX

DQ0-DQ7 and/or DQ8-DQ15

DATA VALID

AI03961

Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low.

8/19

M68AR512D

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

tAVAV

A0-A18

VALID

tAVQV

tELQV

tAXQX

tEHQZ

E1

E2

tELQX

tGLQV

tGHQZ

G

tGLQX

DQ0-DQ15

VALID

tBLQV

tBHQZ

UB, LB

tBLQX

AI05994

Note: Write Enable (W) = High

Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms

E1, UB, LB

E2

tPU

tPD

I

CC

50%

I

SB

AI05990

9/19

M68AR512D

Table 7. Read and Standby Mode AC Characteristics

M68AR512D

70

Symbol

Parameter

Unit

t

Read Cycle Time

Min

Max

Min

70

5

ns

AVAV

t

Address Valid to Output Valid

AVQV

(1)

Data hold from address change

t

AXQX

(2, 3)

Upper/Lower Byte Enable High to Output Hi-Z

Upper/Lower Byte Enable Low to Output Valid

Upper/Lower Byte Enable Low to Output Transition

Chip Enable High to Output Hi-Z

Max

Min

25

70

5

ns

t

BHQZ

t

BLQV

(1)

t

BLQX

(2, 3)

Max

Min

25

70

5

EHQZ

t

Chip Enable Low to Output Valid

ELQV

(1)

Chip Enable Low to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

Chip Enable High to Power Down

Chip Enable Low to Power Up

t

ELQX

(2, 3)

Max

Min

25

35

5

t

GHQZ

t

GLQV

(1)

t

GLQX

(4)

Max

Min

0

t

PD

(4)

70

PU

Note: 1. Test conditions assume transition timing reference level = 0.3V

to 0.7V

.

CCQ

2. At any given temperature and voltage condition, t

any given device.

is less than t

, t

is less than t

and t

is less than t

for

GHQZ

GLQX BHQZ

BLQX

EHQZ

ELQX

3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

4. Tested initially and after any design or process changes that may affect these parameters.

10/19

M68AR512D

Write Mode

The M68AR512D, when Chip Select (E2) is High,

is in the Write Mode whenever the W and E1 are

Low. Either the Chip Enable Input (E1) or the Write

Enable input (W) must be de-asserted during Ad-

dress transitions for subsequent write cycles.

When E1 or W is Low, and UB or LB is Low, write

cycle begins on the W or E1 falling edge. When E1

and W are Low, and UB = LB = High, write cycle

begins on the first falling edge of UB or LB. There-

fore, address setup time is referenced to Write En-

The Write cycle can be terminated by the earlier

rising edge of E1, W, UB and LB.

If the Output is enabled (E1 = Low, E2 = High, G =

Low, LB or UB = Low), then W will return the out-

puts to high impedance within t

of its falling

WLQZ

edge. Care must be taken to avoid bus contention

in this type of operation. Data input must be valid

for t

or for t

before the rising edge of Write Enable,

DVWH

before the rising edge of E1 or for t

DVEH

D-

before the rising edge of UB/LB, whichever

VBH

able, Chip Enables and UB/LB as t

, t

and

AVWL AVEL

occurs first, and remain valid for t

, t

and

WHDX EHDX

t

respectively, and is determined by the latter

AVBL

t

respectively.

BHDX

occurring falling edge.

Figure 10. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A18

VALID

tAVWH

tAVEL

tELWH

tWHAX

E1

E2

tWLWH

tAVWL

W

tWLQZ

tWHQX

tWHDX

DATA INPUT

tDVWH

DQ0-DQ15

UB, LB

tBLBH

AI05995

11/19

M68AR512D

Figure 11. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A18

VALID

tAVEH

tELEH

tAVEL

tEHAX

E1

E2

tAVWL

tWLEH

W

tEHDX

DQ0-DQ15

UB, LB

DATA INPUT

tDVEH

tBLBH

AI05996

Figure 12. UB/LB Controlled, Write AC Waveforms

tAVAV

A0-A18

VALID

tAVBH

tBHAX

E1

E2

tAVWL

tWLBH

W

tWLQZ

tBHDX

DQ0-DQ15

DATA ⁽¹⁾

DATA INPUT

tDVBH

tAVBL

tBLBH

UB, LB

AI05997

Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.

12/19

M68AR512D

Table 8. Write Mode AC Characteristics

M68AR512D

Symbol

Parameter

Unit

70

60

0

t

Write Cycle Time

Min

Max

Min

ns

AVAV

t

Address Valid to LB, UB High

AVBH

t

Address Valid to LB, UB Low

AVBL

t

Address Valid to Chip Enable High

Address valid to Chip Enable Low

Address Valid to Write Enable High

Address Valid to Write Enable Low

LB, UB High to Address Transition

LB, UB High to Input Transition

LB, UB Low to LB, UB High

60

0

AVEH

t

AVEL

t

60

0

AVWH

t

AVWL

t

0

BHAX

t

0

BHDX

t

60

30

0

BLBH

t

LB, UB Low to Chip Enable High

LB, UB Low to Write Enable High

Input Valid to LB, UB High

BLEH

t

BLWH

t

DVBH

t

Input Valid to Chip Enable High

Input Valid to Write Enable High

Chip Enable High to Address Transition

Chip enable High to Input Transition

Chip Enable Low to LB, UB High

Chip Enable Low to Chip Enable High

Chip Enable Low to Write Enable High

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Output Transition

Write Enable Low to LB, UB High

Write Enable Low to Chip Enable High

Write Enable Low to Output Hi-Z

Write Enable Low to Write Enable High

DVEH

t

DVWH

t

EHAX

t

0

EHDX

t

60

0

ELBH

t

ELEH

t

ELWH

t

WHAX

t

0

WHDX

(1)

5

t

WHQX

t

60

20

60

WLBH

t

WLEH

(1, 2)

t

WLQZ

t

WLWH

Note: 1. At any given temperature and voltage condition, t

is less than t

for any given device.

WLQX

WHQZ

2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

13/19

M68AR512D

Figure 13. E1 Controlled, Low V Data Retention AC Waveforms

CC

DATA RETENTION MODE

1.95V

V

1.8V

CC

V

> 1.0V

DR

tCDR

tR

E1 ≥ V

– 0.2V

DR

E1

AI05455

Figure 14. E2 Controlled, Low V Data Retention AC Waveforms

CC

DATA RETENTION MODE

1.95V

V

1.65V

CC

V

> 1.0V

DR

tCDR

tR

E2

E2 ≤ 0.2V

AI05475

Table 9. Low V Data Retention Characteristics

CC

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

V

= 1.0V, E1 ≥ V –0.2V or

CC

(1)

E2 ≤ 0.2V or

Supply Current (Data Retention)

0.1

8

µA

I

CCDR

(3)

UB/LB ≥ V –0.2V, f = 0

CC

Chip deselected to Data

Retention Time

(2)

0

ns

t

CDR

(2)

t

Operation Recovery Time

t

R

AVAV

E1 ≥ V –0.2V or

CC

E2 ≤ 0.2V or

(1)

Supply Voltage (Data Retention)

1.0

V

DR

UB/LB ≥ V –0.2V,

CC

f = 0

Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.

IH

CC

IL

2. Tested initially and after any design or process changes that may affect these parameters. t

AVAV

is Read cycle time.

3. No input may exceed V +0.3V.

CC

14/19

M68AR512D

PACKAGE MECHANICAL

Figure 15. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

SE

E

E1

BALL "A1"

ddd

e

b

A

A2

A1

BGA-Z43

Note: Drawing is not to scale.

Table 10. TFBGA48 6x7mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.400

Typ

Max

A

A1

A2

b

0.0472

0.0157

0.250

0.0098

0.790

0.400

6.000

3.750

0.0311

0.0157

0.2362

0.1476

0.350

5.900

0.450

6.100

0.0138

0.2323

0.0177

0.2402

D

D1

ddd

E

0.100

7.100

0.0039

0.2795

7.000

5.250

0.750

1.125

0.875

0.375

6.900

–

0.2756

0.2067

0.0295

0.0443

0.0344

0.0148

0.2717

–

E1

e

–

FD

FE

SD

SE

–

15/19

M68AR512D

Figure 16. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline

D

D1

FD

FE

SD

SE

E

E1

ddd

BALL "A1"

A

e

b

A2

A1

BGA-Z28

Note: Drawing is not to scale.

Table 11. TFBGA48 8x10mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

0.900

0.0354

0.350

7.900

–

0.450

0.0138

0.3110

–

0.0177

D

8.000

3.750

8.100

0.3150

0.1476

0.3189

D1

ddd

E

–

0.100

0.0039

10.000

5.250

0.750

2.125

2.375

0.375

9.900

10.100

0.3937

0.2067

0.0295

0.0837

0.0935

0.0148

0.3898

0.3976

E1

e

–

FD

FE

SD

SE

16/19

M68AR512D

PART NUMBERING

Table 12. Ordering Information Scheme

Example:

M68AR512

D

N

70 ZB

6

T

Device Type

M68

Mode

A = Asynchronous

Operating Voltage

R = 1.65 to 1.95V

Array Organization

512 = 8 Mbit (512K x16)

Option 1

D = 2 Chip Enable; Write and Standby from UB and LB

Option 2

L = L-Die

N = N-Die

Speed Class

70 = 70 ns

Package

(1)

ZB = TFBGA48, 6x7mm, 6x8 ball array 0.75 mm pitch

ZB = TFBGA48, 8x10mm, 6x8 ball array 0.75 mm pitch

(2)

Operative Temperature

1 = 0 to 70 °C

6 = –40 to 85 °C

Shipping

T = Tape & Reel Packing

Note: 1. TFBGA48, 6x7mm is available only for the M68AR512DN part.

2. TFBGA48, 8x10mm is available only for the M68AR512DL part.

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

17/19

M68AR512D

REVISION HISTORY

Table 13. Document Revision History

Date

Version

-01

Revision Details

August 2001

08-Oct-2001

First Issue

-02

Document status moved to Preliminary Data

Document status moved to Data Sheet

Temperature range 1 (0 to 70°C) added

Tables 3, 5, 6, 7, 8 and 9 clarified

18-Mar-2002

17-May-2002

02-Oct-2002

-03

-04

4.1

Figures 7, 8, 9, 10, 11 and 12 clarified

Document globally revised

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 04 equals 4.0).

Part number changed.

Part number changed and new salestype added

TFBGA48 8x10mm package added (Figure 16, Table 11)

09-Oct-2002

4.2

18/19

M68AR512D

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

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www.st.com

19/19


型号：	M68AR512D
厂家：	ST
描述：	8 Mbit 512K x16 1.8V Asynchronous SRAM 8兆位512K x16的1.8V异步SRAM 静态存储器
文件：	总19页 (文件大小：142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M68AR512D [STMICROELECTRONICS]

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