M68AW127BL70N6 [STMICROELECTRONICS]

128KX8 STANDARD SRAM, 70ns, PDSO32, 8 X 20 MM, PLASTIC, TSOP-32;


型号：	M68AW127BL70N6
厂家：	ST
描述：	128KX8 STANDARD SRAM, 70ns, PDSO32, 8 X 20 MM, PLASTIC, TSOP-32 静态存储器光电二极管内存集成电路
文件：	总22页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M68AW127B

1Mbit (128K x8), 3.0V Asynchronous SRAM

FEATURES SUMMARY

■

SUPPLY VOLTAGE: 2.7 to 3.6V

Figure 1. Packages

128K x 8 bits SRAM with OUTPUT ENABLE

EQUAL CYCLE and ACCESS TIMES: 70ns

LOW STANDBY CURRENT

LOW V DATA RETENTION: 1.5V

TRI-STATE COMMON I/O

LOW ACTIVE and STANDBY POWER

SO32 (MC)

TSOP32

8 x 20mm

(N)

TSOP32

8 x 13.4mm

(NK)

September 2004

1/22

M68AW127B

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . . 11

Figure 10.Chip Enable Controlled, Standby Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 11.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13.E1 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 14.E2 Controlled, Low V Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Low V Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 15.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . 17

Figure 16.TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline . . . . . . . . . . . . . . . 18

Table 11. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data . . . . . . . . 18

Figure 17.TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline . . . . . . . . . . . . . . 19

Table 12. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data . . . . . . 19

2/22

M68AW127B

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3/22

M68AW127B

SUMMARY DESCRIPTION

The M68AW127B is a 1Mbit (1,048,576 bit) CMOS

SRAM, organized as 131,072 words by 8 bits. The

device features fully static operation requiring no

external clocks or timing strobes, with equal ad-

dress access and cycle times. It requires a single

2.7 to 3.6V supply.

This device has an automatic power-down feature,

reducing the power consumption by over 99%

when deselected.

The M68AW127B is available in SO32, TSOP32

8x20mm and TSOP32 8x13.4mm packages.

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A16

Address Inputs

Data Input/Output

Chip Enable

Output Enable

Write Enable

Supply Voltage

Ground

DQ0-DQ7

A0-A16

DQ0-DQ7

M68AW127B

AI05972b

4/22

M68AW127B

Figure 3. SO Connections

Figure 4. TSOP Connections

A11

A16

A14

A12

A15

A10

A13

DQ7

DQ6

DQ5

DQ4

DQ3

A13

A15

A11

M68AW127B

A16

A14

A12

DQ2

DQ1

DQ0

A10

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

AI05973c

AI05931b

5/22

M68AW127B

Figure 5. Block Diagram

A16

ROW

DECODER

MEMORY

ARRAY

DQ7

I/O CIRCUITS

COLUMN

DECODER

DQ0

AI05471

6/22

M68AW127B

OPERATION

The M68AW127B has a Chip Enable power down

feature which invokes an automatic standby mode

whenever Chip Enable is de-asserted (E1 = High),

or Chip Select is asserted (E2 = Low). An Output

Enable (G) signal provides a high-speed, tri-state

control, allowing fast read/write cycles to be

achieved with the common I/O data bus. Opera-

tional modes are determined by device control in-

puts W and E1 as summarized in the Operating

Modes table (Table 2).

Read Mode

The M68AW127B is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, Chip Enable (E1) is asserted and Chip Select

(E2) is de-asserted. This provides access to data

from eight of the 1,048,576 locations in the static

memory array, specified by the 17 address inputs.

Valid data will be available at the eight output pins

within t

after the last stable address, provid-

AVQV

ing G is Low and E1 is Low. If Chip Enable or Out-

put Enable access times are not met, data access

will be measured from the limiting parameter

or t

) rather than the address. Data out

ELQV

GLQV

may be indeterminate at t

lines will always be valid at t

and t

, but data

GLQX

ELQX

AVQV

Write Mode

The M68AW127B is in the Write mode whenever

the W and E1 pins are Low and the E2 pin is High.

Either the Chip Enable input (E1) or the Write En-

able input (W) must be de-asserted during Ad-

dress transitions for subsequent write cycles.

Write begins with the concurrence of E1 being ac-

tive with W low. Therefore, address setup time is

referenced to Write Enable and Chip Enable as

The Write cycle can be terminated by the earlier

rising edge of E1, or W.

If the Output is enabled (E1 = Low, E2 = High and

G = Low), then W will return the outputs to high im-

pedance within t

of its falling edge. Care must

WLQZ

be taken to avoid bus contention in this type of op-

eration. Data input must be valid for t

the rising edge of Write Enable, or for t

before

DVWH

DVEH

and t

, respectively, and is determined

the rising edge of E1, whichever occurs first, and

AVWL

AVEH

by the latter occurring edge.

remain valid for t

or t

WHDX

EHDX

Table 2. Operating Modes

Operation

DQ0-DQ7

Power

Active (I

)

Read

Hi-Z

Active (I

Read

Data Output

Data Input

Hi-Z

)

Write

Standby (I

)

Deselect

Hi-Z

X = V or V .

7/22

M68AW127B

MAXIMUM RATING

Stressing the device above the rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice

reliability.

Refer

also

the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 3. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

(1)

Output Current

Ambient Operating Temperature

Storage Temperature

Supply Voltage

–55 to 125

–65 to 150

–0.3 to 4.6

STG

(2)

–0.5 to V +0.5

Input or Output Voltage

Power Dissipation

Note: 1. One output at a time, not to exceed 1 second duration.

2. Up to a maximum operating V of 3.6V only.

8/22

M68AW127B

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 4. Operating and AC Measurement Conditions

Parameter

M68AW127B

Supply Voltage

2.7 to 3.6V

Range 1

Range 6

0 to 70°C

–40 to 85°C

100pF

Ambient Operating Temperature

Load Capacitance (C )

Output Circuit Protection Resistance (R )

3.0kΩ

Load Resistance (R )

3.1kΩ

Input Rise and Fall Times

1ns/V

0 to V

Input Pulse Voltages

Input and Output Timing Ref. Voltages

Output Transition Timing Ref. Voltages

= 0.3V ; V = 0.7V

CC RH CC

Figure 6. AC Measurement I/O Waveform

Figure 7. AC Measurement Load Circuit

I/O Timing Reference Voltage

DEVICE

UNDER

TEST

OUT

Output Transition Timing Reference Voltage

0.7V

0.3V

AI04831

includes JIG capacitance

AI05814

9/22

M68AW127B

Table 5. Capacitance

Symbol

Test

Condition

(1,2)

Min

Max

Unit

Parameter

= 0V

Input Capacitance on all pins (except DQ)

Output Capacitance

OUT

Note: 1. Sampled only, not 100% tested.

2. At T = 25°C, f = 1MHz, V = 3.0V.

Table 6. DC Characteristics

Symbol

Parameter

Test Condition

= 3.6V, f = 1/t

Min

Typ

Max

Unit

6.0

AVAV

(1,2)

Supply Current

CC1

= 0mA

OUT

100

= 3.6V, f = 1MHz,

Operating Supply Current

= 0mA

OUT

Operating Supply Current

(READ)

(3)

1.5

CC2

= 3.6V, f = 1MHz,

= 0mA

100

OUT

Operating Supply Current

(WRITE)

0V ≤V ≤V

IN CC

Input Leakage Current

Output Leakage Current

–1

µA

(4)

0V ≤V

≤V

OUT

= 3.6V, E1 ≥ V –

2.5

0.3

Standby Supply Current

CMOS

0.2V,

E2 ≤0.2V, f = 0

100

+ 0.3

Input High Voltage

Input Low Voltage

2.2

–0.3

2.4

100

0.8

0.6

= –1mA

Output High Voltage

Output Low Voltage

100

2.2

= 2.1mA

0.4

Note: 1. Average AC current, cycling at t

minimum.

AVAV

2. E1 = V , E2 = V , V = V or V .

3. E1 ≤0.2V or E2 ≥ V –0.2V, V ≤0.2V or V_IN≥ V –0.2V.

4. Output disabled.

10/22

M68AW127B

Figure 8. Address Controlled, Read Mode AC Waveforms

tAVAV

A0-A16

VALID

tAVQV

tAXQX

DQ0-DQ7

DATA VALID

AI05474

Note: E1 = Low, E2 = High, G = Low, W = High.

Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.

tAVAV

A0-A16

VALID

tAVQV

tELQV

tAXQX

tEHQZ

tELQX

tGLQV

tGHQZ

tGLQX

DQ0-DQ7

VALID

AI05476

Note: Write Enable (W) = High.

11/22

M68AW127B

Figure 10. Chip Enable Controlled, Standby Mode AC Waveforms

tPU

tPD

50%

AI05477

12/22

M68AW127B

Table 7. Read and Standby Mode AC Characteristics

M68AW127B

Symbol

Parameter

Unit

100

Read Cycle Time

Min

Max

Min

AVAV

Address Valid to Output Valid

AVQV

(1)

Data hold from address change

Chip Enable High to Output Hi-Z

Chip Enable Low to Output Valid

Chip Enable Low to Output Transition

AXQX

(2,3)

Max

Min

EHQZ

100

ELQV

(1)

ELQX

(2,3)

Output Enable High to Output Hi-Z

Max

Min

GHQZ

Output Enable Low to Output Valid

GLQV

(2)

Output Enable Low to Output Transition

Chip Enable or UB/LB High to Power Down

Chip Enable or UB/LB Low to Power Up

GLQX

Max

Min

Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V

2. At any given temperature and voltage condition, t

is less than t

and t

is less than t

for any given device.

ELQX

GHQZ

GLQX

EHQZ

3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

13/22

M68AW127B

Figure 11. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A16

VALID

tAVWH

tAVEL

tELWH

tWHAX

tWLWH

tAVWL

tWLQZ

tWHQX

tWHDX

DQ0-DQ7

DATA INPUT

tDVWH

AI05478

Figure 12. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A16

VALID

tAVEH

tELEH

tAVEL

tEHAX

tAVWL

tWLEH

tEHDX

DQ0-DQ7

DATA INPUT

tDVEH

AI05479

14/22

M68AW127B

Table 8. Write Mode AC Characteristics

M68AW127B

Symbol

Parameter

Unit

100

Write Cycle Time

Min

Max

AVAV

Address Valid to Chip Enable High

Address valid to Chip Enable Low

Address Valid to Write Enable High

Address Valid to Write Enable Low

Input Valid to Chip Enable High

AVEH

AVEL

AVWH

AVWL

DVEH

Input Valid to Write Enable High

Chip Enable High to Address Transition

Chip enable High to Input Transition

Chip Enable Low to Chip Enable High

Chip Enable Low to Write Enable High

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Output Transition

Write Enable Low to Chip Enable High

Write Enable Low to Output Hi-Z

DVWH

EHAX

EHDX

ELEH

ELWH

WHAX

WHDX

(1)

WHQX

WLEH

(1,2)

WLQZ

Write Enable Low to Write Enable High

Min

WLWH

Note: 1. At any given temperature and voltage condition, t

is less than t

for any given device.

WLQZ

WHQX

2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

15/22

M68AW127B

Figure 13. E1 Controlled, Low V Data Retention AC Waveforms

DATA RETENTION MODE

3.6V

2.7V

> 1.5V ⁽¹⁾

tCDR

E1 ≥ V

– 0.2V

AI05980

Note: 1. For 100ns speed class V ≥ 2.0V.

Figure 14. E2 Controlled, Low V Data Retention AC Waveforms

DATA RETENTION MODE

3.6V

2.7V

> 1.5V ⁽¹⁾

tCDR

E2 ≤ 0.2V

AI05957B

Note: 1. For 100ns speed class V ≥ 2.0V.

Table 9. Low V

Symbol

Data Retention Characteristics

Parameter

Test Condition

Min

Typ

Max

Unit

µA

4.5

= 1.5V, E1 ≥ V –0.2V or

Supply Current

(1)

CCDR

(Data Retention)

E2 ≤0.2V, f = 0

100

µA

Chip Deselected to Data

Retention Time

(1,2)

CDR

100

AVAV

(2)

Operation Recovery Time

1.5

2.0

E1 ≥ V –0.2V or

E2 ≤0.2V, f = 0

Supply Voltage

(Data Retention)

(1)

100

Note: 1. All other Inputs at V ≥ V –0.2V or V ≤0.2V.

2. Tested initially and after any design or process that may affect these parameters. t

is Read cycle time.

AVAV

3. No input may exceed V +0.2V.

16/22

M68AW127B

PACKAGE MECHANICAL

Figure 15. SO32 - 32 lead Plastic Small Outline, Package Outline

SO-C

Note: Drawing is not to scale.

Table 10. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data

millimeters

Symbol

inches

Min

Typ

Min

Max

Typ

Max

2.997

0.118

0.102

2.565

0.356

0.152

20.142

11.176

13.868

–

0.004

0.101

0.014

0.006

0.793

0.440

0.546

–

2.819

0.508

0.305

20.752

11.430

14.376

–

0.111

0.020

0.012

0.817

0.450

0.566

–

1.270

0.050

0.584

1.194

0.991

1.600

0.10

0.023

0.047

0.039

0.063

0.004

17/22

M68AW127B

Figure 16. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Outline

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

Table 11. TSOP32 - 32 lead Plastic Small Outline 8x20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.250

0.210

0.100

20.200

18.500

8.100

–

Typ

Max

0.0472

0.0059

0.0413

0.0098

0.0083

0.0039

0.7953

0.7283

0.3189

–

0.050

0.950

0.170

0.100

0.0020

0.0374

0.0067

0.0039

19.800

18.300

7.900

–

0.7795

0.7205

0.3110

–

0.500

0.0197

0.500

0°

0.700

5°

0.0197

0°

0.0276

5°

18/22

M68AW127B

Figure 17. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Outline

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

Table 12. TSOP32 - 32 lead Plastic Small Outline 8x13.4mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.20

0.15

1.05

Typ

Max

0.0472

0.0059

0.0413

0.05

0.91

0.0020

0.0358

0.22

0.0087

0.10

0.21

0.0039

0.0083

13.40

11.80

8.00

–

0.5276

0.4646

0.3150

0.0197

–

0.50

–

0.0157

–

0.0236

0.40

0.60

0.10

0.0039

19/22

M68AW127B

PART NUMBERING

Table 13. Ordering Information Scheme

Example:

M68AW127

70 N 6T

Device Type

M68

Mode

A = Asynchronous

Operating Voltage

W = 2.7 to 3.6V

Array Organization

127 = 1Mbit (128K x8)

Option 1

B = 2 Chip Enable

Option 2

L = L-Die

M = M-Die

Speed Class

70 = 70ns

10 = 100ns

Package

MC = SO32

N = TSOP32 (8 x 20mm)

NK = TSOP32 (8 x 13.4mm)

Operative Temperature

1 = 0 to 70°C

6 = –40 to 85°C

Shipping

T = Tape & Reel Packing

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

20/22

M68AW127B

REVISION HISTORY

Table 14. Document Revision History

Date

Version

Revision Details

January 2002

1.0

First Issue

DC Characteristics table clarified (Table 6)

E1 Controlled, Low V Data Retention AC Waveforms clarified (Figure 13)

09-May-2002

2.0

Low V Data Retention Characteristics table clarified (Table 9)

Ordering Information Scheme clarified (Table 13)

70ns speed class added

SO32 and TSOP32 8x13.4mm package options added

01-Jul-2002

3.0

11-Sep-2002

02-Oct-2002

09-Oct-2002

16-Apr-2003

21-Aug-2003

4.0

4.1

4.2

4.3

4.4

Commercial code clarified

Title and header layout modified.

Commercial code modified.

Label corrected on “E2 Controlled, Low V Data Retention AC Waveforms” figure

TSOP Package connections modified (Figure 5)

Document structure modified:

–

Chapter OPERATION moved before chapter MAXIMUM RATING.

AC Characteristics Tables and waveforms moved to the DC/AC PARAMETERS

section.

24-Sep-2004

ad t updated in Table 7.

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M68AW127B

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to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

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M68AW127BL70N6 [STMICROELECTRONICS]

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