M68AW256MN70ND1T [STMICROELECTRONICS]

4 Mbit (256K x16) 3.0V Asynchronous SRAM; 4兆位（ 256K ×16） 3.0V异步SRAM


型号：	M68AW256MN70ND1T
厂家：	ST
描述：	4 Mbit (256K x16) 3.0V Asynchronous SRAM 4兆位（ 256K ×16） 3.0V异步SRAM 存储内存集成电路静态存储器光电二极管
文件：	总20页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M68AW256M

4 Mbit (256K x16) 3.0V Asynchronous SRAM

FEATURES SUMMARY

■ SUPPLY VOLTAGE: 2.7 to 3.6V

■ 256K x 16 bits SRAM with OUTPUT ENABLE

■ EQUAL CYCLE and ACCESS TIME: 55ns

■ SINGLE BYTE READ/WRITE

Figure 1. Packages

■ LOW STANDBY CURRENT

■ LOW V

DATA RETENTION: 1.5V

■ TRI-STATE COMMON I/O

TSOP44 Type II (ND)

■ AUTOMATIC POWER DOWN

BGA

TFBGA48 (ZB)

7 x 8 mm

October 2002

1/20

M68AW256M

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 5. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 6. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . 10

Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . 10

Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 11. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 12. Chip Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 13. UB/LB Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 14. Low V

Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 9. Low V

Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . . . . . . . . . . 16

TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . . . . . 16

TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline. . . . . . . . . . . . . 17

TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . . . . . . . . . 17

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/20

M68AW256M

SUMMARY DESCRIPTION

The M68AW256M is a 4 Mbit (4,194,304 bit)

CMOS SRAM, organized as 262,144 words by 16

bits. The device features fully static operation re-

quiring no external clocks or timing strobes, with

equal address access and cycle times. It requires

a single 2.7 to 3.6V supply. This device has an au-

tomatic power-down feature, reducing the power

consumption by over 99% when deselected.

The M68AW256 is available in TFBGA48 (0.75 mm

pitch) and in TSOP44 Type II packages.

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A17

Address Inputs

DQ0-DQ15

Data Input/Output

Chip Enable

Output Enable

A0-A17

DQ0-DQ15

Write Enable

Upper Byte Enable Input

Lower Byte Enable Input

Supply Voltage

M68AW256M

Ground

Not Connected Internally

Don’t Use as Internally Connected

AI04870b

3/20

M68AW256M

Figure 3. TSOP Connections

DQ0

DQ1

DQ2

DQ3

DQ15

DQ14

DQ13

DQ12

M68AW256M

DQ4

DQ5

DQ6

DQ7

DQ11

DQ10

DQ9

DQ8

A16

A15

A14

A13

A12

A10

A11

A17

AI04871b

4/20

M68AW256M

Figure 4. TFBGA Connections (Top view through package)

DQ8

DQ9

DQ0

DQ2

DQ10

DQ11

DQ12

DQ13

DQ1

DQ3

DQ4

DQ5

A17

A14

A12

A16

A15

A13

A10

DQ14

DQ15

DQ6

DQ7

A11

AI03955

5/20

M68AW256M

Figure 5. Block Diagram

A17

ROW

DECODER

MEMORY

ARRAY

DQ15

(8)

I/O CIRCUITS

COLUMN

DECODER

DQ0

(8)

AI04833

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

°C

(1)

Output Current

Ambient Operating Temperature

Storage Temperature

Supply Voltage

–55 to 125

–65 to 150

–0.5 to 4.6

STG

(2)

–0.5 to V +0.5

Input or Output Voltage

Power Dissipation

Note: 1. One output at a time, not to exceed 1 second duration.

2. Up to a maximum operating V of 3.6V only.

6/20

M68AW256M

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. Operating and AC Measurement Conditions

Parameter

M68AW256M

Supply Voltage

2.7 to 3.6V

Range 1

Range 6

0 to 70°C

–40 to 85°C

30pF

Ambient Operating Temperature

Load Capacitance (C )

Output Circuit Protection Resistance (R )

3.0kΩ

Load Resistance (R )

3.1kΩ

Input Rise and Fall Times

1ns/V

0 to V

Input Pulse Voltages

Input and Output Timing Ref. Voltages

Output Transition Timing Ref. Voltages

= 0.3V ; V = 0.7V

CC RH CC

Figure 6. AC Measurement I/O Waveform

Figure 7. AC Measurement Load Circuit

I/O Timing Reference Voltage

DEVICE

UNDER

TEST

OUT

Output Timing Reference Voltage

0.7V

0.3V

AI05831

includes probe and 1 TTLcapacitance

AI05832

7/20

M68AW256M

Table 4. Capacitance

Symbol

Test

Condition

(1,2)

Min

Max

Unit

Parameter

= 0V

Input Capacitance on all pins (except DQ)

Output Capacitance

OUT

Note: 1. Sampled only, not 100% tested.

2. At T = 25°C, f = 1 MHz, V = 3.0V.

Table 5. DC Characteristics

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

70ns

55ns

= 3.6V, f = 1MHz,

= 3.6V, f = 1/t

AVAV

(1,2)

Operating Supply Current

CC1

= 0mA

OUT

(3)

Operating Supply Current

µA

CC2

= 0mA

OUT

= 3.6V, f = 0,

E ≥ V –0.2V or

Standby Supply Current CMOS

LB=UB ≥ V –0.2V

0V ≤ V ≤ V

Input Leakage Current

Output Leakage Current

–1

µA

(4)

0V ≤ V

≤ V

OUT

+ 0.3

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

2.2

–0.3

2.4

0.6

= –1.0mA

= 2.1mA

0.4

Note: 1. Average AC current, cycling at t

minimum.

AVAV

2. E = V , LB OR/AND UB = V , V = V OR V

3. E ≤ 0.2V, LB OR/AND UB ≤ 0.2V, V ≤ 0.2V OR V ≥ V –0.2V.

4. Output disabled.

8/20

M68AW256M

OPERATION

The M68AW256M has a Chip Enable power down

feature which invokes an automatic standby mode

whenever either Chip Enable is de-asserted

(E = High) or LB and UB are de-asserted (LB and

UB = High). An Output Enable (G) signal provides

a high speed tri-state control, allowing fast read/

write cycles to be achieved with the common I/O

data bus. Operational modes are determined by

device control inputs W, E, LB and UB as summa-

rized in the Operating Modes table (see Table 6).

Table 6. Operating Modes

Operation

Deselected

DQ0-DQ7

Hi-Z

DQ8-DQ15

Hi-Z

Power

Standby (I

Active (I

)

Deselected

Hi-Z

)

Lower Byte Read

Lower Byte Write

Output Disabled

Upper Byte Read

Upper Byte Write

Word Read

Data Output

Data Input

Hi-Z

Active (I

)

Hi-Z

)

Hi-Z

Data Output

Data Input

Data Output

Data Input

Hi-Z

Data Output

Data Input

Word Write

Note: 1. X = V or V .

Read Mode

The M68AW256M is in the Read mode whenever

Write Enable (W) is High with Output Enable (G)

Low, and Chip Enable (E) is asserted. This pro-

vides access to data from eight or sixteen, de-

pending on the status of the signal UB and LB, of

the 4,194,304 locations in the static memory array,

specified by the 18 address inputs. Valid data will

be available at the eight or sixteen output pins

within t

after the last stable address, provid-

AVQV

ing G is Low and E is Low. If Chip Enable or Output

Enable access times are not met, data access will

be measured from the limiting parameter (t

ELQV

or t

) rather than the address. Data out

GLQV

BLQV

may be indeterminate at t

, t

and t

ELQX GLQX BLQX

but data lines will always be valid at t

AVQV

Figure 8. Address Controlled, Read Mode AC Waveforms

tAVAV

A0-A17

VALID

tAVQV

tAXQX

DQ0-DQ7 and/or DQ8-DQ15

DATA VALID

AI03956

Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.

9/20

M68AW256M

Figure 9. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.

tAVAV

A0-A17

VALID

tAVQV

tELQV

tAXQX

tEHQZ

tELQX

tGLQV

tGHQZ

tGLQX

DQ0-DQ15

VALID

tBLQV

tBHQZ

UB, LB

tBLQX

AI03957

Note: Write Enable (W) = High.

Figure 10. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms

E, UB, LB

tPU

tPD

50%

AI03856

10/20

M68AW256M

Table 7. Read and Standby Mode AC Characteristics

M68AW256M

Symbol

Parameter

Unit

Read Cycle Time

Min

AVAV

Address Valid to Output Valid

Max

AVQV

(1)

Data hold from address change

Min

Max

Min

AXQX

(2,3)

Upper/Lower Byte Enable High to Output Hi-Z

Upper/Lower Byte Enable Low to Output Valid

Upper/Lower Byte Enable Low to Output Transition

Chip Enable High to Output Hi-Z

BHQZ

BLQV

(1)

BLQX

(2,3)

Max

Min

EHQZ

Chip Enable Low to Output Valid

ELQV

(1)

Chip Enable Low to Output Transition

Output Enable High to Output Hi-Z

ELQX

(2,3)

Max

Min

GHQZ

Output Enable Low to Output Valid

GLQV

(2)

Output Enable Low to Output Transition

Chip Enable or UB/LB High to Power Down

Chip Enable or UB/LB Low to Power Up

GLQX

(4)

Max

Min

(4)

Note: 1. Test conditions assume transition timing reference level = 0.3V or 0.7V

2. At any given temperature and voltage condition, t

any given device.

is less than t

, t

is less than t

and t

is less than t

for

ELQX

GHQZ

GLQX BHQZ

BLQX

EHQZ

3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

4. Tested initially and after any design or process changes that may affect these parameters.

11/20

M68AW256M

Write Mode

The M68AW256M is in the Write mode whenever

the W and E are Low. Either the Chip Enable input

(E) or the Write Enable input (W) must be de-

The Write cycle can be terminated by the earlier

rising edge of E, W or UB/LB.

If the Output is enabled (E = Low, G = Low, LB or

UB = Low), then W will return the outputs to high

asserted

during

Address

transitions

for

subsequent write cycles. When E (W) is Low, and

UB or LB is Low, write cycle begins on the W (E)’s

falling edge. When E and W are Low, and UB = LB

= High, write cycle begins on the first falling edge

of UB or LB. Therefore, address setup time is

referenced to Write Enable, Chip Enable or UB/LB

impedance within t

must be taken to avoid bus contention in this type

of operation. Data input must be valid for t

before the rising edge of Write Enable, or for t

before the rising edge of E, or for t

rising edge of UB/LB whichever occurs first, and

of its falling edge. Care

WLQZ

DVWH

DVEH

before the

DVBH

as t

, t

and t

respectively, and is

AVWL AVEL

AVBL

remain valid for t

tively.

, t

and t

respec-

WHDX EHDX

BHDX

determined by the latter occurring edge.

Figure 11. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A17

VALID

tAVWH

tELWH

tWHAX

tWLWH

tAVWL

tWLQZ

tWHQX

tWHDX

(1)

DQ0-DQ15

UB, LB

DATA

DATA INPUT

DATA

tDVWH

tBLWH

AI03958

12/20

M68AW256M

Figure 12. Chip Enable Controlled, Write AC Waveforms

tAVAV

A0-A17

VALID

tAVEH

tELEH

tAVEL

tEHAX

tWLEH

tEHDX

DQ0-DQ15

DATA INPUT

tDVEH

tBLEH

UB, LB

AI03959

Figure 13. UB/LB Controlled, Write AC Waveforms

tAVAV

A0-A17

VALID

tAVBH

tBHAX

tELBH

tWLBH

tBHDX

DQ0-DQ15

DATA ⁽¹⁾

DATA INPUT

tDVBH

tAVBL

tBLBH

UB, LB

AI03987

Note: 1. During this period DQ0-DQ15 are in output state and input signals should not be applied.

13/20

M68AW256M

Table 8. Write Mode AC Characteristics

M68AW256M

Symbol

Parameter

Unit

Write Cycle Time

Min

AVAV

Address Valid to LB, UB High

AVBH

Addess Valid to LB, UB Low

AVBL

Address Valid to Chip Enable High

Address valid to Chip Enable Low

Address Valid to Write Enable High

Address Valid to Write Enable Low

LB, UB High to Address Transition

LB, UB High to Input Transition

LB, UB Low to LB, UB High

AVEH

AVEL

AVWH

AVWL

BHAX

BHDX

BLBH

LB, UB Low to Chip Enable High

LB, UB Low to Write Enable High

Input Valid to LB, UB High

BLEH

BLWH

DVBH

Input Valid to Chip Enable High

Input Valid to Write Enable High

Chip Enable High to Address Transition

Chip enable High to Input Transition

Chip Enable Low to LB, UB High

Chip Enable Low to Chip Enable High

Chip Enable Low to Write Enable High

Write Enable High to Address Transition

Write Enable High to Input Transition

Write Enable High to Output Transition

Write Enable Low to LB, UB High

Write Enable Low to Chip Enable High

DVEH

DVWH

EHAX

EHDX

ELBH

ELEH

ELWH

WHAX

WHDX

(1)

WHQX

WLBH

WLEH

(1,2)

Write Enable Low to Output Hi-Z

Max

Min

WLQZ

Write Enable Low to Write Enable High

WLWH

Note: 1. At any given temperature and voltage condition, t

is less than t

for any given device.

WLQZ

WHQX

2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output

voltage levels.

14/20

M68AW256M

Figure 14. Low V Data Retention AC Waveforms

DATA RETENTION MODE

3.6V

2.7V

> 1.5V

tCDR

E ≥ V

– 0.2V or UB=LB ≥ V

– 0.2V

E, UB/LB

AI03989

Table 9. Low V

Symbol

Data Retention Characteristics

Parameter

Test Condition

Min

Typ

Max

Unit

= 1.5V, E ≥ V –0.2V or

(1)

Supply Current (Data Retention)

4.5

µA

CCDR

(3)

UB = LB ≥ V –0.2V, f = 0

Chip Deselected to Data

Retention Time

(1,2)

CDR

(2)

Operation Recovery Time

AVAV

E ≥ V –0.2V or

(1)

Supply Voltage (Data Retention)

1.5

UB = LB ≥ V –0.2V, f = 0

Note: 1. All other Inputs at V ≥ V –0.2V or V ≤ 0.2V.

2. Tested initially and after any design or process changes that may affect these parameters. t

is Read cycle time.

AVAV

3. No input may exceed V +0.2V.

15/20

M68AW256M

PACKAGE MECHANICAL

Figure 15. TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline

N/2

TSOP-d

Note: Drawing is not to scale.

Table 10. TSOP 44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

Typ

Max

0.0472

0.0059

0.0413

0.050

0.950

0.0020

0.0374

0.350

0.0138

0.120

0.210

0.0047

0.0083

18.410

11.760

10.160

0.800

–

0.7248

0.4630

0.4000

0.0315

0.0197

0.0317

–

0.400

–

0.0236

–

0.500

0.600

–

0.0157

alfa

0.805

–

0.100

0.0039

16/20

M68AW256M

Figure 16. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Bottom View Package Outline

BALL "A1"

ddd

BGA-Z22

Note: Drawing is not to scale.

Table 11. TFBGA48 7x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

1.010

1.200

0.0398

0.0102

0.0472

0.260

0.950

0.0374

0.400

7.000

3.750

0.300

6.900

–

0.500

0.0157

0.2756

0.1476

0.0118

0.2717

–

0.0197

7.100

0.2795

ddd

–

0.100

0.0039

8.000

5.250

0.750

1.625

1.375

0.375

7.900

8.100

0.3150

0.2067

0.0295

0.0640

0.0541

0.0148

0.3110

0.3189

–

17/20

M68AW256M

PART NUMBERING

Table 12. Ordering Information Scheme

Example:

M68AW256

55 ZB

Device Type

M68

Mode

A = Asynchronous

Operating Voltage

W = 2.7 to 3.6V

Array Organization

256 = 4 Mbit (256K x16)

Option 1

M = 1 Chip Enable; Write and Standby from UB and LB

Option 2

L = L-Die

N = N-Die

Speed Class

55 = 55 ns

70 = 70 ns

Package

ND = TSOP 44 Type II

ZB = TFBGA48: 0.75 mm pitch

Operative Temperature

1 = 0 to 70 °C

6 = –40 to 85 °C

Shipping

T = Tape & Reel Packing

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

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M68AW256M

REVISION HISTORY

Table 13. Document Revision History

Date

Version

Revision Details

February 2002

-01

First Issue

Tables 3, 7 and 9 clarified

Figure 14 clarified

13-Mar-2002

17-Jun-2002

-02

-03

clarified (Table 9)

clarified (Table 5)

CCDR

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 03 equals 3.0).

09-Oct-2002

3.1

Part number modified.

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to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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