M69KB096AA [STMICROELECTRONICS]
64 Mbit (4M x16) 1.8V Supply, 80MHz Clock Rate, Burst PSRAM; 64兆位（ 4M ×16） 1.8V电源， 80MHz的时钟速率，突发PSRAM
| 型号： | M69KB096AA |
| 厂家： | 
ST |
| 描述： | 64 Mbit (4M x16) 1.8V Supply, 80MHz Clock Rate, Burst PSRAM |
| 文件： | 总48页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M69KB096AA
64 Mbit (4M x16)
1.8V Supply, 80MHz Clock Rate, Burst PSRAM
FEATURES SUMMARY
■
SUPPLY VOLTAGE
Figure 1. Package
–
–
VCC = 1.7 to 1.95V core supply voltage
VCCQ = 1.7 to 3.3V for I/O buffers
■
ASYNCHRONOUS MODES
–
Asynchronous Random Read: 70ns and
85ns access time
–
–
Asynchronous Write
Asynchronous Page Read
Page Size: 16 words
Subsequent read within page: 20ns
■
SYNCHRONOUS BURST READ AND
WRITE MODES
–
–
Burst Write in Continuous Mode
Burst Read:
Wafer
Fixed Length (4, 8, or 16 Words) or
Continuous mde
Maximum Clock Frequency: 66MHz,
80MHz
Burst initial latency: 50ns (4 clock cycles)
at 80MHz
■
■
LOW POWER FEATURES
–
Temperature Compensated Refresh
(TCR)
Output delay: 9ns at 80MHz
–
–
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
■
■
BYTE CONTROL BY LB/UB
LOW POWER CONSUMPTION
OPERATING TEMPERATURE
–30°C to +85°C
–
–
–
Asynchronous Random Read Mode:
< 25mA
Asynchronus Page Read Mode
–
(subsequent read operations): < 15mA
Synchronous Burst Read
Initial access: < 35mA
Continuous Burst Read: < 15mA
–
–
Standby Current: 120µA
Deep Power-Down Current: 10µA (typ)
THE M69KB096AA IS ONLY AVAILABLE AS PART OF A MULTI-CHIP PACKAGE PRODUCT
January 2006
1/48
M69KB096AA
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Upper Byte Enable (UB).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Input (K). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
V
CC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VCCQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
V
SSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Asynchronous Random Read and Write Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Asynchronous Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Synchronous Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mixed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Temperature Compensated Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Partial Array Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Deep Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CONFIGURATION REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Programming and Reading the Configuration Registers using the CR Controlled Method . 13
Programming and Reading the Configuration Registers by the Software Method. . . . . . . . . 13
Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating Mode Bit (BCR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WAIT Configuration Bit (BCR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Configuration Bit (BCR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Driver Strength Bit (BCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/48
M69KB096AA
Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page Mode Operation Bit (RCR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Temperature Compensated Refresh Bits (RCR6-RCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/48
M69KB096AA
SUMMARY DESCRIPTION
The M69KB096AA is a 64 Mbit (67,108,864 bit)
PSRAM, organized as 4,194,304 words by 16 bits.
The memory array is implemented using a one
transistor-per-cell topology, to achieve bigger ar-
ray sizes.
This device is a high-speed CMOS, dynamic ran-
dom-access memory. It provides a high-density
solution for low-power handheld applications.
Figure 2. Logic Diagram
V
V
CCQ
CC
22
16
A0-A21
DQ0-DQ15
WAIT
W
E
The M69KB096AA includes the industry standard
Flash memory burst mode that dramatically in-
creases read/write over that of other low-power
SRAM or PSRAMs.
The PSRAM interface supports both asynchro-
nous and burst-mode transfers. Page mode ac-
cesses are also included as a bandwidth-
enhancing extension to the asynchronous read
protocol.
PSRAMs are based on the DRAM technology, but
have a transparent internal self-refresh mecha-
nism that requires no additional support from the
system memory controller, and has no significant
impact on the device read/write performance.
CR
G
M69KB096AA
UB
LB
K
L
The device has two configuration registers, acces-
sible to the user to define the device operation: the
Bus Configuration Register (BCR) and the Refresh
Configuration Register (RCR). The Bus Configura-
tion Register (BCR) indicates how the device inter-
acts with the system memory bus. Overall, it is
identical to its counterpart in burst-mode Flash
memory devices. The Refresh Configuration Reg-
ister (RCR) is used to control how the memory ar-
ray refresh is performed. At power-up, these
registers are automatically loaded with default set-
tings and can be updated any time during normal
operation.
V
V
SSQ
SS
AI10584b
Table 1. Signal Names
A0-A21
Address Inputs
DQ0-DQ15
Data Inputs/Outputs
Chip Enable Input
E
CR
G
Configuration Register Enable Input
Output Enable Input
Write Enable Input
To minimize the value of the standby current dur-
ing self-refresh operations, the M69KB096AA in-
cludes three system-accessible mechanisms
configured via the Refresh Configuration Register
(RCR):
W
UB
LB
K
Upper Byte Enable Input
Lower Byte Enable Input
Clock Input
■
The Temperature Compensated Refresh
(TCR) is used to adjust the refresh rate
according to the operating temperature. The
refresh rate can be decreased at lower
temperatures to minimize current
consumption during standby.
L
Latch Enable Input
■
■
The Partial Array Refresh (PAR) performs a
limited refresh of the part of the PSRAM array
that contains essential data.
The Deep Power-Down (DPD) mode
completely halts the refresh operation. It is
used when no essential data is being held in
the device.
WAIT
Wait Output
V
Core Supply Voltage
Input/Output Buffers Supply Voltage
Ground
CC
V
CCQ
V
SS
V
Input/Output Buffers Ground
SSQ
4/48
M69KB096AA
SIGNAL DESCRIPTIONS
The signals are summarized in Figure 2., Logic Di-
agram, and Table 1., Signal Names.
Down. It must be kept Low during asynchronous
operations.
Address Inputs (A0-A21). The Address Inputs
select the cells in the memory array to access dur-
ing Read and Write operations.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low. When disabled, the Data In-
puts/Outputs are high impedance.
Configuration Register Enable (CR). When this
signal is driven High, VIH, Write operations load ei-
ther the value of the Refresh Configuration Regis-
ter (RCR) or the Bus configuration register (BCR).
Latch Enable (L). The Latch Enable input is
used to latch the address. Once the first address
has been latched, the state of L controls whether
subsequent addresses come from the address
lines (L = VIL) or from the internal Burst counter (L
= VIH).
Data Inputs/Outputs (DQ0-DQ7). The
Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E). Chip Enable, E, activates the
device when driven Low (asserted). When deas-
serted (VIH), the device is disabled and goes auto-
matically in low-power Standby mode or Deep
Power-down mode.
Output Enable (G). Output Enable, G, provides a
high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus.
Write Enable (W). Write Enable, W, controls the
Bus Write operation of the memory. When assert-
ed (VIL), the device is in Write mode and Write op-
erations can be performed either to the
configuration registers or to the memory array.
Upper Byte Enable (UB). The Upper Byte En-
able, UB, gates the data on the Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte En-
able, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
The Latch Enable signal, L, must be held Low, VIL,
during Asynchronous operations.
Wait (WAIT). The WAIT output signal provides
data-valid feedback during Synchronous Burst
Read and Write operations. The signal is gated by
E. Driving E High while WAIT is asserted may
cause data corruption.
Once a Read or Write operation has been initiated,
the WAIT signal goes active to indicate that the
M69KB096AA device requires additional time be-
fore data can be transferred.
The WAIT signal also is used for arbitration when
a Read or Write operation is launched while an on-
chip refresh is in progress (see Figure 6., Collision
Between Refresh and Read Operation and Figure
7., Collision between Refresh and Write Opera-
tion).
The WAIT signal on the M69KB096AA device is
typically connected to a shared system-level WAIT
signal. The shared WAIT signal is used by the pro-
cessor to coordinate transactions with multiple
memories on the synchronous bus.
See the Operating Modes section for details on the
WAIT signal operation.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Write,
etc.) and for driving the refresh logic, even when
the device is not being accessed.
If both LB and UB are disabled (High) during an
operation, the device will disable the data bus from
receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active
mode as long as E remains Low.
Clock Input (K). The Clock, K, is an input signal
to synchronize the memory to the microcontroller
or system bus frequency during Synchronous
Burst Read and Write operations.
V
CCQ Supply Voltage. VCCQ provides the power
supply for the I/O pins. This allows all Outputs to
be powered independently from the core power
supply, VCC
SS Ground. The VSS Ground is the reference for
all voltage measurements.
SSQ Ground. VSSQ ground is the reference for
the input/output circuitry driven by VCCQ. VSSQ
must be connected to VSS
.
V
V
.
The Clock input is required during all synchronous
operations, except in Standby and Deep Power-
5/48
M69KB096AA
Figure 3. Block Diagram
A21-A0
DQ7-DQ0
Address Decode
Logic
4,096K x 16
I/O
Buffers
MEMORY
ARRAY
DQ15-DQ7
Refresh Configuration
Register (RCR)
Bus Configuration
Register (BCR)
E
W
G
K
Control
Logic
L
CR
WAIT
LB
UB
AI08721c
Note: Functional block diagram illustrates simplified device operation.
6/48
M69KB096AA
Table 2. Bus Modes– Asynchronous Mode
WAIT DQ15-DQ0
MODE
POWER
K
L
E
G
W
CR
LB, UB
NOTES
(2)
(1)
Asynchronous Active >
Read Standby
1
L
L
L
L
H
L
Low Z
Data-Out
3
L
Asynchronous Active >
1
L
L
L
L
X
X
L
L
L
Low Z
High Z
Data-In
High-Z
3
L
Write
Standby
Standby
Standby
X
H
X
X
X
4,5
Write
Configuration
Register
Active
L
L
L
L
H
X
L
H
X
Low Z
High-Z
High-Z
Deep
Power-
Down
Deep Power-
Down (DPD)
X
H
X
X
High-Z
6
Table 3. Bus Modes– Synchronous Burst Mode
WAIT DQ15-DQ0
MODE
POWER
K
L
L
L
E
L
L
G
X
H
W
H
L
CR
L
LB, UB
NOTES
3, 7, 8
3, 7, 8
(2)
(1)
Initial Burst
Read
Active >
Standby
L
Low Z
Data-Out
!
!
Initial Burst
Write
Active >
Standby
L
X
Low Z
Low Z
Low Z
Low Z
Data-In
Subsequent
Burst
Operation
Active >
Standby
Data-In or
Data-Out
H
X
L
L
L
L
X
H
H
X
X
L
X
L
L
X
X
3, 7, 8
3, 7
!
Burst
Suspend
Active >
Standby
(9)
High-Z
High-Z
X
Write
Configuration
Register
Active
H
7, 8
!
Deep
Power-
Down
Deep Power-
Down (DPD)
L
X
H
X
X
X
X
High-Z
High-Z
6
Note: 1. When LB and UB are in select mode (Low), DQ15-DQ0 are affected. When only LB is in select mode, DQ7-DQ0 are affected. When
only UB is in the select mode, DQ15-DQ8 are affected.
2. The WAIT polarity is configured through the Bus Configuration Register (BCR10).
3. The device consumes active power in this mode whenever addresses are changed.
4. When the device is in Standby mode, Address inputs and Data inputs/outputs are internally isolated from any external influence.
5. V = V or 0V.
IN
CC
6. The device remains in Deep Power-Down mode until the RCR register is reconfigured.
7. The Synchronous Burst mode is initialized through the Bus Configuration Register (BCR15).
8. The clock polarity is configured through the Bus Configuration Register (BCR6).
9. The Clock signal, K, must remain stable during Burst Suspend operations.
7/48
M69KB096AA
OPERATING MODES
The M69KB096AA supports Asynchronous Ran-
dom Read, Page Read and Synchronous Burst
Read and Write modes.
The device mode is defined by the value that has
been loaded into the Bus Configuration Register.
The Page mode is controlled by the Refresh Con-
figuration Register (RCR7).
Asynchronous Page Read Mode
The Asynchronous Page read mode gives greater
performance, even than the traditional Asynchro-
nous Random Read mode. The page mode is not
available for write operations.
Asynchronous Page Read mode is enabled by
setting RCR7 to ‘1’. L must be driven Low, VIL, dur-
ing all Asynchronous Page Read operations.
Power-Up
PSRAM devices include an on-chip voltage sen-
sor used to launch the power-up sequence. VCC
and VCCQ must be applied simultaneously. Once
they reach a stable level, equal to or higher than
1.70V, the device will require tVCHEL to complete
its self-initialization process. During the initializa-
tion period, the E signal should remain High. Once
initialization has completed, the device is ready for
normal operation. Initialization will configure the
Bus Configuration Register (BCR) and the Refresh
Configuration Register (RCR) with their default
settings (see Table 5., page 16, and Table
9., Refresh Configuration Register Definition).
In Asynchronous Page Read mode, a Page of
data is internally read. Each memory page con-
sists of 16 Words, and has the same set of values
on A4-A21; only of A0 to A3 differ. The first read
operation within the Page has the normal access
time (tAVQV), subsequent reads within the same
Page have much shorter access times (tAVQV1). If
the Page changes then the normal, longer timings
apply again.
During Asynchronous Page Read mode, the K in-
put must be held Low, VIL. E must be kept Low, VIL
upon completion of an Asynchronous Page Read
operation. The WAIT signal remains active until
valid data is output from the device.
See Figure 34., Power-Up AC Waveforms and Ta-
ble 19., Power-Up AC Characteristics, for details
on the Power-up timing.
See Figure 17. and Table 15. for details of the
Asynchronous Page Read timing requirements.
Asynchronous Random Read and Write Modes
Synchronous Burst Mode
At power-up, the device is in Asynchronous Ran-
dom Read mode. This mode uses the industry
standard control bus (E, G, W, LB, UB). Read op-
erations are initiated by bringing E, G, and LB, UB
Low, VIL, while keeping W High, VIH. Valid data will
be gated through the output buffers after the spe-
cific access time tAVQV has elapsed.
The WAIT signal will remain active until valid data
is output from the device and its state should be ig-
nored.
Burst mode allows high-speed synchronous read
and write operations.
In Synchronous Burst mode, the data is input or
output to or from the memory array in bursts that
are synchronized with the clock. After E goes Low,
the data address is latched on the first rising edge
of the Clock, K. During this first clock rising edge,
the W signal indicates whether the operation is go-
ing to be a Read (W=VIH, Figure 4.) or Write
(W=VIL, Figure 5.).
Write operations occur when E, W, LB and UB are
driven Low. During Asynchronous Random Write
operations, the G signal is “don't care” and W will
override G. The data to be written is latched on the
rising edge of E, W, LB or UB (whichever occurs
first). During Write operations, the WAIT signal in-
dicates to the system memory controller that data
have been programmed into the memory.
In Synchronous Burst mode, the number of Words
to be input or output during a Synchronous Burst
operation can be configured in the Bus Configura-
tion Register, BCR, as fixed length (4 Words, 8
Words or 16 Words) or Continuous. In Synchro-
nous Continuous Burst mode, the entire memory
can be accessed sequentially in one Burst opera-
tion.
During asynchronous operations (Page mode dis-
abled), the L input can either be used to latch the
address or kept Low, VIL, during the entire Read/
Write operation. The Clock input signal K must be
held Low, VIL.
The Latency Counter, stored in the BCR11 to
BCR13 bits of the BCR register, defines how many
clock cycles elapse before the first data value is
transferred between the processor and the
M69KB096AA.
See Figures 15, 16 and Table 15. for details of
Asynchronous Read AC timing requirements.
See Figures 23, 24, 25, 26, and Table 17. for de-
tails of Asynchronous Write AC timing require-
ments.
The WAIT output will be asserted as soon as a
Synchronous Burst operation is initiated and will
be deasserted to indicate when data is to be trans-
ferred into (or out of) the memory array. The WAIT
signal is also asserted when a Continuous Burst
Read or Write operation crosses a row boundary.
The WAIT assertion allows time for the new row to
8/48
M69KB096AA
be accessed. It also allows any pending refresh
operations to be performed (see Figure
22., Continuous Burst Read Showing an Output
Delay for End-of-Row Condition (BCR8=0,1)).
Temperature Compensated Refresh. The
Temperature Compensated Refresh (TCR) is
used to adjust the refresh rate depending on the
device operating temperature.
The processor can access other devices without
being submitted to the initial burst latency by sus-
pending the burst operation. Burst operations can
be suspended by halting the Clock signal, holding
it High or Low. If another device needs to use the
data bus while Burst operations are suspended,
the Output Enable signal, G, should be driven
High, VIH, to disable data outputs; otherwise, G
can remain Low, VIL. The WAIT output will remain
asserted to prevent any other devices from using
the processor WAIT line.
Burst operations can be resumed by taking G Low,
VIL, and then restarting the Clock as soon as valid
data are available on the bus (see Figure
21., Synchronous Burst Read Suspend and Re-
sume Waveforms).
The leakage current of DRAM capacitive storage
elements increases with the temperature. PSRAM
devices, based on a DRAM architecture, conse-
quently require increasingly frequent refresh oper-
ations to maintain data integrity as the
temperature increases. At lower temperatures, the
refresh rate can be decreased to minimize the
standby current.
The TCR mechanism allows adequate refresh
rates to be set at four different temperature thresh-
olds. These are defined by setting the RCR5 and
RCR6 bits of the Refresh Configuration Register,
RCR. To minimize the self refresh current con-
sumption, the selected setting must be higher than
the operating temperature of the PSRAM device.
As an example, if the operating temperature is
+50°C, the +70°C setting must be selected; the
+15°C and +45°C settings would result in inade-
quate refreshing and could cause data corruption.
Mixed Mode
When the BCR register is configured for synchro-
nous operation, the device can support a combina-
tion of Synchronous Burst Read and
Asynchronous Random Write operations.
See Table 9. for the definition of the Refresh Con-
figuration Register bits.
Partial Array Refresh. The Partial Array Refresh
(PAR) performs a limited refresh of part of the
PSRAM array. This mechanism enables the de-
vice to reduce the standby current by refreshing
only the part of the memory array that contains es-
sential data. Different refresh options can be de-
fined by setting the RCR0 to RCR2 bits of the RCR
Register:
The Asynchronous Random Write operation re-
quires that the Clock signal remains Low, VIL, dur-
ing the entire sequence. The L signal can either be
used to latch the target address or remain Low,
VIL, during the entire Write operation. E must re-
turn Low, VIL, during Asynchronous and Burst op-
erations. Note that the time, necessary to assure
adequate refresh, is the same value as that for
Asynchronous Read and Write mode.
■
■
■
■
■
Full array
Mixed-mode operation greatly simplifies the inter-
facing with traditional burst-mode Flash Memory
Controllers.
One half of the array
One quarter of the array
One eighth of the array
None of the array.
Low-Power Modes
Standby Mode. During Standby, the device cur-
rent consumption is reduced to the level neces-
sary to perform the memory array refresh
operation. Standby operation occurs when E is
High, VIH, and no transaction is in progress.
The device will enter Standby mode when a Read
or Write operation is completed, or when the ad-
dress and control inputs remain stable for an ex-
tended period of time. This “active” Standby mode
will continue until address or control inputs
change.
These memory areas can be located either at the
top or bottom of the memory array.
The WAIT signal is used for arbitration when a
read/write operation is launched while an on-chip
refresh is in progress. If locations are addressed
while they are undergoing refresh, the WAIT signal
will be asserted for additional clock cycles, until
the refresh has completed (see Figure 6. and Fig-
ure 7., Collision between Refresh and Read or
Write Operations). When the refresh operation is
completed, the Read or Write operation will be al-
lowed to continue normally.
9/48
M69KB096AA
Deep Power-Down Mode. Deep
power-down
fresh operations have been re-enabled, the device
will be available for normal operations after tVCHEL
(time to perform an initialization sequence). During
this delay, the current consumption will be higher
than the specified standby levels, but considerably
lower than the active current.
(DPD) mode is used by the system memory con-
troller to de-activate the PSRAM device when its
storage capabilities are not needed. All refresh-re-
lated operations are then disabled. When the
Deep Power-Down mode is enabled, the data
stored in the device become corrupted. When re-
Figure 4. Synchronous Burst Read Mode
K
Address
A0-A21
Valid
ADV
Latency Code 2 (3 clocks)
E
G
W
Hi Z
Hi Z
WAIT
DQ3
DQ0-DQ15
LB/UB
DQ1
DQ2
DQ0
Burst Read Identified
(W = High)
AI06774b
Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
10/48
M69KB096AA
Figure 5. Synchronous Burst Write Mode (4-word burst)
K
Address
A0-A21
Valid
L
E
G
W
LB/UB
Hi Z
Hi Z
WAIT
DQ0-DQ15
DQ0
DQ1
DQ2
DQ3
Additional WAIT states inserted
to allow Refresh completion
AI06776c
Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
Figure 6. Collision Between Refresh and Read Operation
K
Address
A0-A21
Valid
L
E
G
W
LB/UB
Hi Z
Hi Z
WAIT
DQ0-DQ15
DQ0
DQ1
DQ2
DQ3
Additional WAIT states inserted
to allow Refresh completion
AI06776b
Note: Additional Wait states inserted to allow Refresh completion.
Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
11/48
M69KB096AA
Figure 7. Collision between Refresh and Write Operation
K
Address
A0-A21
Valid
L
E
G
W
LB/UB
Hi Z
Hi Z
WAIT
DQ0-DQ15
DQ0
DQ3
DQ1
DQ2
Additional WAIT states inserted
to allow Refresh completion
AI06777
Note: Additional Wait states inserted to allow Refresh completion.
Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.
12/48
M69KB096AA
CONFIGURATION REGISTERS
Two write-only user-accessible configuration reg-
isters have been included to define device opera-
tion. These registers are automatically loaded with
default settings during power-up, and can be up-
dated any time the device is operating in a standby
state.
Table 4. Register Selection
Register
Read or Write Operation
A19
0
RCR
BCR
Read/Write
Read/Write
1
The configuration registers (BCR and RCR) can
be programmed and read using two methods:
Programming and Reading the Configuration
Registers by the Software Method
■
The CR Controlled Method (or Hardware
Method)
Each register can be read by issuing a Read Con-
figuration Register sequence (see Figure 9., Read
Configuration Register (Software Method), and
programmed by issuing a Set Configuration Reg-
ister sequence (see Figure 8., Set Configuration
Register (Software Method). Both sequences
must be issued in asynchronous mode.
The timings will be identical to those described in
Table 15., Asynchronous Read AC Characteris-
tics. The Chip Enable input, CR, is ‘don’t care’.
Read Configuration Register and Set Configura-
tion Register sequences both require 4 cycles:
■
The Software Method.
Programming and Reading the Configuration
Registers using the CR Controlled Method
The BCR and the RCR can be programmed and
read using either a Synchronous or an Asynchro-
nous Write and Read operation with the Configu-
ration Register Enable input, CR, at VIH. Address
bit A19 selects the register to be programmed or
read (see Table 4., Register Selection). The val-
ues placed on address lines A0 to A21 are latched
into the register on the rising edge of L, E, or W,
whichever occurs first. LB and UB are “don’t care”.
When CR is at VIL, a Read or Write operation will
access the memory array.
See Figures 27 and 33, Configuration Register
Write in Asynchronous and Synchronous Modes.
■
2 bus read and one bus write cycles to a
unique address location, 3FFFFFh, indicate
that the next operation will read or write to a
configuration register. The data written during
the third cycle must be ‘0000h’ to access the
RCR and ‘0001h’ to access the BCR during
the next cycle.
■
The fourth cycle reads from or writes to the
configuration register.
13/48
M69KB096AA
Figure 8. Set Configuration Register (Software Method)
Addr.
3FFFFFh
3FFFFFh
3FFFFFh
3FFFFFh
(4)
E
tEHEL2
tEHEL2
tEHEL2
G
W
LB, UB
DQ0-DQ15
Don't Care
Don't Care
(2)
CR Data IN
AI10600b
Note: 1. Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified.
2. To program the BCR or the RCR on last bus write cycle, DQ0-DQ15 must be set to ‘0001h’ and ‘000h’ respectively.
3. The highest order address location is not modified during this operation.
4. The third write operation must be controlled by the Chip Enable signal.
Figure 9. Read Configuration Register (Software Method)
Addr.
3FFFFFh
3FFFFFh
tEHEL2
3FFFFFh
tEHEL2
3FFFFFh
tEHEL2
(3)
E
G
W
LB, UB
CR Data
OUT
DQ0-DQ15
Don't Care
Don't Care
(1)
AI10601b
Note: 1. To read the BCR, RCR on last bus read cycle, DQ0-DQ15 must be set to ‘0001h’, ‘000h’ respectively.
2. The highest order address location is not modified during this operation.
3. The Chip Enable signal, E, must be held High for 150ns before reading the content of the Configuration Register.
4. The third write operation must be controlled by the Chip Enable signal.
14/48
M69KB096AA
Bus Configuration Register
When the Wait Configuration bit is set to ‘0’, data
is valid or invalid on the first Clock rising edge im-
mediately after the WAIT signal transition to the
deasserted or asserted state.
When the Wait Configuration bit is set to ‘1’ (de-
fault settings), the WAIT signal transition occurs
one clock cycle prior to the data bus going valid or
invalid.
The Bus Configuration Register (BCR) defines
how the PSRAM interacts with the system memory
bus. Overall, it is identical to its counterpart on
burst mode Flash devices.
At power-up, BCR is initialized to 9D4Fh.
Refer to Table 5. for the description of the Bus
Configuration Register Bits.
See Figure 10., WAIT Configuration Example, and
Figure 11., Example of WAIT Configuration During
Synchronous Burst Operation.
Operating Mode Bit (BCR15). The
Operating
Mode bit allows the Synchronous Burst mode or
the Asynchronous mode (default setting) to be se-
lected.
Clock Configuration Bit (BCR6). The
Clock
Configuration bit is used to configure the activ-
eedge of the Clock signal, K, during Synchronous
Burst Read or Write operations. When the Clock
Configuration bit is set to ’1’ (default setting), the
rising edge of the Clock is active. Configuring the
active clock edge to the falling edge (BCR6 set to
‘0’) is not supported.
All of the waveforms shown in this datasheet cor-
respond to a Clock signal active on the rising
edge.
Driver Strength Bit (BCR5). The Driver Strength
bit allows to set the output drive strength to adjust
to different data bus loading. Normal driver
strength (full drive) and reduced driver strength (a
quarter drive) are available.
By default, outputs are configured at ‘half drive”
strength.
Latency Counter Bits (BCR13-BCR11). The
Latency Counter bits are used to set the number of
clock cycles between the beginning of a Read or
Write operation and the first data becoming avail-
able. For correct operation, the number of clock
cycles can only be equal to 3 or 4 (default settings)
and the Latency Counter bits can only assume the
values shown in Table 5., Bus Configuration Reg-
ister Definition. See also Table 7., Latency
Counter Configuration, and Figure 12., Example
of Latency Counter Configuration).
WAIT Polarity Bit (BCR10). The WAIT Polarity
bit indicates whether the WAIT output signal is ac-
tive High or Low. As a consequence, it also deter-
mines whether the WAIT signal requires a pull-up
or pull-down resistor to maintain the de-asserted
state.
By default, the WAIT output signal is active High.
Burst Wrap Bit (BCR3). The burst reads can be
confined inside the 4, 8 or 16 Word boundary
(wrap) or allowed to step across the boundary (no
wrap). The Burst Wrap bit is used to select be-
tween ‘wrap’ and ‘no wrap’. If the Burst Wrap bit is
set to ‘1’ (no wrap), the device outputs data se-
quentially regardless of burst boundaries. When
Continuous Burst operation is selected, the inter-
nal address switches to 000000h if the read ad-
dress passes the last address. By default, Burst
wrap is selected.
WAIT Configuration Bit (BCR8). The
system
memory controller uses the WAIT signal to control
data transfer during Synchronous Burst Read
Read and Write operations.
The WAIT Configuration bit is used to determine
when the transition of the WAIT output signal be-
tween the asserted and the deasserted state oc-
curs with respect to valid data available on the
data bus.
See also Table 6., Burst Type Definition.
15/48
M69KB096AA
Burst Length Bits (BCR2-BCR0). The
Burst
Continuous Burst (default settings), where all the
Words are read sequentially regardless of address
boundaries. Burst Write operations are always
performed using the Continuous Burst mode.
Length bits set the number of Words to be output
during a Synchronous Burst Read operation. They
can be set for 4 Words, 8 Words, 16 Words or
Table 5. Bus Configuration Register Definition
Bus
Configuration
Register Bit
Address
Bits
Description
Value
Description
A21-A20
-
-
Must be set to ‘0’ Reserved
0
1
Refresh Selected
A19
A18-A16
A15
-
Register Select
-
Bus Configuration Register Selected
-
Must be set to ‘0’ Reserved
0
1
Synchronous Burst mode
Asynchronous mode (default)
Operating Mode
Bit
BCR15
-
A14
-
Must be set to ‘0’ Reserved
010
011
LC = 2 (3 Clock Cycles)
LC= 3 (4 Clock Cycles) (default)
BCR13-
BCR11
Latency Counter
Bits (LC)
A13-A11
Other configurations reserved
0
1
WAIT Active Low
WAIT Active High (default)
A10
A9
BCR10
-
WAIT Polarity Bit
-
Must be set to ‘0’ Reserved
0
1
WAIT Asserted During Delay
Wait
Configuration Bit
A8
BCR8
WAIT Asserted One Clock Cycle Before Delay
(Default)
A7
A6
-
-
Must be set to ‘0’ Reserved
0
1
0
1
Not supported
Clock
Configuration Bit
BCR6
Rising Clock Edge (Default)
Full Drive (default)
1/4 Drive
Driver Strength
Bit
A5
A4
A3
BCR5
-
-
Must be set to ‘0’ Reserved
0
Wrap (default)
BCR3
Burst Wrap Bit
1
No Wrap
001
010
011
111
4 Words
8 Words
A2-A0
BCR2-BCR0
Burst Length Bit
16 Words
Continuous Burst (default)
Note: All Burst Write operations are performed in Synchronous Continuous Burst mode.
16/48
M69KB096AA
Table 6. Burst Type Definition
Start 4 Words
Add (Sequential)
8 Words
16 Words
(Sequential)
Continuous Burst
(Sequential)
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
...
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
...
0-1-2-3-4-5-6...
1-2-3-4-5-6-7...
2
2-3-4-5-6-7-8...
3
3-4-5-6-7-8-9...
4
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
6-7-8-9-10-11-12...
7-8-9-10-11-12-13...
...
5
6
7
...
14
15
0
...
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
14-15-16-17-18-19-20...
15-16-17-18-19-20-21...
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
1
2
3
4
Same as for Wrap
(Wrap /No Wrap
has no effect on
Continuous Burst)
5
5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20
6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21
6
7-8-9-10-11-12-13-
7
7-8-9-10-11-12-13-14-...-17-18-19-20-21-22
14
...
14
15
...
14-15-16-17-18-19...-23-24-25-26-27-28-29
15-16-17-18-19-20...-24-25-26-27-28-29-30
Table 7. Latency Counter Configuration
Latency
Maximum Input Clock Frequency
Access Time 70ns
Unit
Maximum Clock Rate in Burst Mode
Configuration Code
Maximum Clock Rate in Burst Mode
80MHz
66MHz
(1)
2 (3 Clock Cycles)
3 (4 Clock Cycles)
53 (18.75ns)
80 (12.5ns)
MHz
MHz
44 (22.7ns)
66 (15.2ns)
Note: 1. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t
specifications are met.
ELKH
17/48
M69KB096AA
Figure 10. WAIT Configuration Example
K
WAIT
DQ0-DQ15
BCR8='0'
Hi-Z
Hi-Z
Data[0] Data[1]
Data[0]
Data Valid During Current Cycle
DQ0-DQ15
BCR8='1'
Data Valid During Next Cycle
AI06795
Figure 11. Example of WAIT Configuration During Synchronous Burst Operation
K
WAIT
BCR8='0'
Data Valid During Current Cycle
WAIT
BCR8='1'
Data Valid During Next Cycle
Hi-Z
DQ0-DQ15
Data[0]
Data[1] Data[2] Data[3] Data[4]
AI06797
Figure 12. Example of Latency Counter Configuration
K
ADDRESS
VALID
A0-A21
L
3 Clock Cycle Latency
4 Clock Cycle Latency
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ0-DQ15
BCR13-BCR11='010'
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DQ0-DQ15
BCR13-BCR11='011'
AI08900
18/48
M69KB096AA
Refresh Configuration Register
The Refresh Configuration Register (RCR) is used
for two purposes:
selected at one of four different temperature
thresholds: +15°C, +45°C, +70°C, and +85°C. The
default setting is +85°C. See the Temperature
Compensated Refresh section for more details.
Deep Power-Down Bit (RCR4). The Deep Pow-
er-Down bit enables or disables all refresh-related
operations. The Deep Power-Down mode is en-
abled when the RCR4 bit is set to ‘0’, and remains
enabled until this bit is set to ‘1’. At power-up, the
Deep Power-Down mode is disabled.
■
to define how the self refresh of the PSRAM
array is performed
■
to enable Page Read operations.
Altering the self refresh parameters can dramati-
cally reduce current consumption in Standby
mode.
At power-up, RCR is initialized to 0070h.
Refer to Table 9. for the description of the Refresh
Configuration Register Bits.
See the Deep Power-Down section for more de-
tails.
Partial Array Refresh Bits (RCR2-RCR0). The
Partial Array Refresh bits allow refresh operations
to be restricted to a portion of the total PSRAM ar-
ray. The refresh options can be full array, one
eighth, one quarter, one half, or none of the array.
These memory areas can be located either at the
top or bottom of the memory array. By default, the
full memory array is refreshed (see Table
8., Address Patterns for Partial Array Refresh).
Page Mode Operation Bit (RCR7). The
Page
Mode operation bit determines whether the Asyn-
chronous Page Read mode is enabled. At power-
up, the RCR7 bit is set to ‘0’, and so the Asynchro-
nous Page Read mode is disabled.
Temperature Compensated Refresh Bits
(RCR6-RCR5). The Temperature Compensated
Refresh bits allow an adequate refresh rate to be
Table 8. Address Patterns for Partial Array Refresh
Size of
RCR2 RCR1 RCR0
Refreshed Area
Address Space
Refreshe Density
d Area
0
0
0
0
0
1
0
1
0
Full Array (Default)
000000h-3FFFFFh 4 Mbitsx16 64 Mbits
000000h-1FFFFFh 2 Mbitsx16 32 Mbits
000000h-0FFFFFh 1 Mbitsx16 16 Mbits
512Kbitsx
Bottom Half of the Array
Bottom First Quarter of the Array
0
1
1
Bottom First Eighth of the Array
000000h-07FFFFh
8 Mbits
16
1
1
1
0
0
1
0
1
0
None of the Array
0
0
0
Top Half of the Array
Top Quarter of the Array
200000h-3FFFFFh 2 Mbitsx16 32 Mbits
300000h-3FFFFFh 1 Mbitsx16 16 Mbits
512Kbitsx
1
1
1
Top One-Eighth of the Array
380000h-3FFFFFh
8 Mbits
16
Note: RCR4 is set to ‘1’.
19/48
M69KB096AA
Table 9. Refresh Configuration Register Definition
Bus
Configuration
Register Bit
Address
Bits
Description
Value
Description
A21-A20
-
-
Must be set to ‘0’ Reserved
0
1
Refresh Selected
A19
A18-A8
A7
-
-
Register Select
-
Bus Configuration Register Selected
Must be set to ‘0’ Reserved
0
Page Read Mode Disabled (Default)
Page Mode
Operation Bit
RCR7
1
Page Read Mode Enabled
+85°C (Default)
11
00
01
10
0
Temperature
Compensated
Refresh Bits
+70°C
A6-A5
RCR6-RCR5
+45°C
+15°C
Deep Power-Down Enabled
Deep Power-Down Disabled (Default)
Deep Power-
Down Bit
A4
A3
RCR4
-
1
-
Must be set to ‘0’ Reserved
000
001
010
011
Partial Array
Refresh Bits
See Table 8., Address Patterns for Partial
Array Refresh
A2-A0
RCR2-RCR0
100
101
110
111
20/48
M69KB096AA
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 10. Absolute Maximum Ratings
Symbol
Parameter
Ambient Operating Temperature
Min
–30
–55
–0.2
–0.2
Max
85
Unit
°C
°C
V
T
A
T
Storage Temperature
150
2.45
4.0
STG
V
CC
Core Supply Voltage
V
Input/Output Buffer Supply Voltage
V
CCQ
4.0 or
+0.3
CCQ
(1)
V
IO
Input or Output Voltage
–0.5
V
V
Note: 1. Whichever is the lower.
21/48
M69KB096AA
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 11., Operating
and AC Measurement Conditions. Designers
should check that the operating conditions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 11. Operating and AC Measurement Conditions
Parameter
M69KB096AA
Unit
Min
1.7
Max
1.95
3.3
V
V
Supply Voltage
V
V
CC
Input/Output Buffer Supply Voltage
1.7
CCQ
Ambient Operating Temperature
85
°C
pF
kΩ
kΩ
kΩ
V
–30
Load Capacitance (C )
30
2.7
3.7
4.5
L
V
V
V
= 1.8V
= 2.5V
= 3.0V
CCQ
CCQ
CCQ
Output Circuit Protection Resistance (R R )
1,
2
V
Input Pulse Voltages
0
CC
V
/2
Input and Output Timing Ref. Voltages
Output Transition Timing Ref. Voltages
Input Rise and Fall Time (tτ )
V
CC
V
= 0.3V ; V = 0.7V
CC RH CC
V
RL
1.6
ns
Note: 1. All voltages are referenced to V
.
SS
Figure 13. AC Measurement I/O Waveform
Figure 14. AC Measurement Load Circuit
V
CCQ
I/O Timing Reference Voltage
R
1
V
CC
V
/2
CC
DEVICE
0V
UNDER
TEST
OUT
Output Timing Reference Voltage
C
R
2
L
V
CC
0.7V
0.3V
CC
CC
0V
AI04831
AI07222d
Note: 1. Logic states ‘1’ and ‘0’ correspond to AC test inputs driven at VCCQ and VSS respectively. Input timings begin at VCCQ/2 and
output timings end at VCCQ/2. Input rise and fall time (10% to 90%) are lower than 1.6ns.
2. All the tests are performed with the outputs configured as Full drive strength (BCR[5]=0).
22/48
M69KB096AA
Table 12. Capacitance
Symbol
Test
Condition
Parameter
Min
Max
Unit
C
V
= 0V
= 0V
Address Input Capacitance
Data Input/Output Capacitance
6
6
pF
pF
IN1
IN
IO
C
V
IO
Note: 1. These parameters are not fully tested.
Table 13. DC Characteristics
Symbol
Parameter
Test Condition
Min.
Typ
Max.
Unit
Operating Current:
Asynchronous Random
Read/Write
70ns
85ns
25
20
15
12
35
30
mA
mA
mA
mA
mA
mA
(1)
I
CC1
Operating Current:
Asynchronous Page
Read
70ns
(1)
I
CC1P
85ns
V
=V or V ,
IH IL
IN
Operating Current:
Initial Access,
Burst Read/Write
80MHz
66MHz
E = V ,
IL
(1)
I
CC2
I
= 0mA
OUT
80MHz
66MHz
80MHz
66MHz
18
15
35
30
mA
mA
mA
mA
Operating Current:
Continuous Burst Read
(1)
(1)
I
CC3R
Operating Current:
Continuous Burst Write
I
CC3W
V
= V
E = V
or 0V,
IN
CCQ
(2)
V
Standby Current
CC
120
µA
I
SB
IH
I
0V ≤V ≤V
IN CC
Input Leakage Current
Output Leakage Current
1
1
µA
µA
LI
G = V or E = V
IH
I
IH
LO
Deep-Power Down
Current
(3)
10
µA
I
ZZ
V
= V or V
IH IL
IN
V
V
+ 0.2
CCQ
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.4
V
V
V
V
IH
V
0.4
–0.2
IL
V
OH
0.8V
CCQ
I
= –0.2mA
= 0.2mA
OH
V
OL
I
0.2V
CCQ
OL
Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to
drive the output capacitance expected in the actual system.
2. I (Max) values are measured with RCR2 to RCR0 bits set to ‘000’ (full array refresh) and RCR6 to RCR5 bits set to ‘11’ (temper-
SB
ature compensated refresh threshold at +85°C). In order to achieve low standby current, all inputs must be driven either to V
CCQ
or V . ISB may be slightly higher for up to 500 ms after power-up or when entering Standby mode.
SS
3. The Operating Temperature is +25°C.
23/48
M69KB096AA
Table 14. PAR and TCSR Specifications and Conditions
(2)
Maximum Operating Temperature
+45°C +70°C
Refreshed
Memory
Areas
Test
Condition
Symbol
Parameter
Unit
+15°C
+85°C
RCR[6-5]=10 RCR[6-5]=01 RCR[6-5]=00 RCR[6-5]=11
Full
1/2
1/4
1/8
0
70
65
60
57
50
85
80
75
70
55
105
100
95
120
115
110
105
70
Maximum
Standby Current
in TCSR and
PAR Modes
V
IN
= V or
IH
(1)
V ,
µA
I
IL
SB
E = V
IH
90
60
Note: 1. In order to achieve low standby current, all inputs must be driven to either VCCQ or VSS. ISB may be slightly higher for up to 500 ms
after power-up or when entering Standby mode.
2. RCR values for 85°C are 100 percent tested. TCR values for 15°C, 45°C and 70°C are sampled only.
Figure 15. Asynchronous Random Read AC Waveforms
tAVAX
A0-A21
VALID ADDRESS
tAVQV
L
tEHEL
tEHQZ
tBHQZ
tGHQZ
E
tELQV
LB/UB
tBLQV
G
tGHQX
tGLQV
W
tGLQX
tBLQX
Hi-Z
Hi-Z
Hi-Z
VALID
OUTPUT
DQ0-DQ15
tELQX
tELTV
tEHTZ
Hi-Z
WAIT
AI06780b
24/48
M69KB096AA
Figure 16. L Controlled Asynchronous Random Read AC Waveforms
VALID
ADDRESS
A0-A21
tAVQV
tAVLH
tLHAX
tLHLL
L
tLLQV
tLLLH
tEHEL
tELLH
tEHQZ
tBHQZ
tGHQZ
E
tELQV
tBLQV
tGLQV
LB/UB
G
tGHQX
W
tGLQX
tBLQX
Hi-Z
Hi-Z
VALID
OUTPUT
DQ0-DQ15
tELQX
tELTV
tEHTZ
Hi-Z
Hi-Z
WAIT
AI06781b
25/48
M69KB096AA
Figure 17. Asynchronous Page Read AC Waveforms
tAVAX
VALID ADDRESS
A4-A21
A1-A3
L
VALID ADDRESS
VALID
VALID
tAVAV
VALID
tAVQV
tEHEL
tEHQZ
tEHEL
E
tELQV
tBHQZ
tGHQZ
LB/UB
tBLQV
G
tGHQX
tGLQV
W
tGLQX
tBLQX
tAVQV1
tAVQX
Hi-Z
Hi-Z
Hi-Z
VALID
OUTPUT
DQ0-DQ15
WAIT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
tELQX
tELTV
tEHTZ
Hi-Z
AI06782b
26/48
M69KB096AA
Table 15. Asynchronous Read AC Characteristics
M69KB096AA
70ns
Symbol
Alt.
Parameter
85ns
Unit
Min
Max
70
Min
Max
85
t
t
Address Valid to Output Valid
L Low to Output Valid
ns
ns
ns
AVQV
AA
t
t
AADV
70
85
LLQV
t
t
Page Access Time
20
25
AVQV1
APA
t
t
L High to Address Transition
Address Valid to L High
5
5
LHAX
AVH
t
t
10
10
AVLH
AVS
Upper/Lower Byte Enable Low to Output
Valid
t
t
70
8
85
8
ns
ns
ns
ns
BLQV
BA
Upper/Lower Byte Enable High to Output Hi-
Z
(4)
t
t
BHZ
BHQZ
Upper/Lower Byte Enable Low to Output
Transition
(3)
t
10
5
10
5
t
BLZ
BLQX
Chip Enable High between Subsequent
Mixed-Mode Read Operations
t
t
CBPH
EHEL
(2)
t
t
Maximum Chip Enable Pulse Width
Chip Enable Low to WAIT Valid
Chip Enable high to WAIT High-Z
8
7.5
8
8
7.5
8
µs
ns
ns
t
CEM
ELEH
t
1
1
ELTV
CEW
t
EHTZ
Chip Enable Low to Output Valid (Chip
Select Access Time)
t
t
70
85
ns
ELQV
CO
t
t
CVS
Chip Enable Low to L High
10
10
10
10
ns
ns
ELLH
(4)
t
HZ
Chip Enable High to Output Hi-Z
8
8
t
EHQZ
(3)
t
LZ
Chip Enable Low to Output Transition
Output Enable Low to Output Valid
Output Enable High to Output Transition
Data Hold from Address Change
Output Enable High to Output Hi-Z
ns
ns
ns
ns
ns
t
ELQX
t
t
20
20
GLQV
OE
t
t
5
5
5
5
GHQX
OH
t
t
OHA
AVQX
(4)
t
8
8
t
OHZ
GHQZ
(3)
t
Output Enable Low to Output Transition
Page Cycle Time
5
5
ns
t
OLZ
GLQX
t
t
t
20
70
10
10
25
85
10
10
AVAV
AVAX
PC
t
Read Cycle Time
ns
ns
ns
RC
t
t
t
VP
L Pulse Width Low
LLLH
LHLL
t
L Pulse Width High
VPH
Note: 1. All the tests are performed with the outputs configured in “Full drive” strength (BCR5=’0’).
2. The timing is related to Asynchronous Page mode only.
3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a
transition of 100mV between the High-Z level (V /2) and V or V
.
OL
CCQ
OH
4. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a
transition of 100mV between V or V and V /2.
OH
OL
CCQ
27/48
M69KB096AA
Figure 18. Single Access Synchronous Burst Read AC Waveforms
tKHKH
tKHKL
K
tAVKH
tKHAX
ADDRESS
VALID
A0-A21
L
tAVLH
tKHLH
tLLKH
tELKH
tKHEH
tEHQZ
tGHQZ
tKHQV1
E
tGLQV
G
tWHKH
tBLKH
tKHWX tGLQX
tKHBX
W
LB/UB
WAIT
tELTV
tKHTV
Hi Z
Hi-Z
Hi Z
Hi-Z
tKHQV2
tKHQX2
VALID
OUTPUT
DQ0-DQ15
Burst Read Identified
(W = High)
AI06783
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t specifications are met.
ELKH
28/48
M69KB096AA
Figure 19. Synchronous Burst Read (4-word) AC Waveforms
tKHKH
tKHKL
K
tAVKH
tKHAX
tKHLH
VALID
ADDRESS
A0-A21
tAVLH
tLLKH
L
E
tKHEH
tEHEL
tELKH
tKHQV1
tEHQZ
tGHQZ
tGLQV
G
W
tWHKH
tKHWX
tGLQX
tBLKH
tKHBX
LB/UB
tKHTX
tELTV
Hi-Z
Hi-Z
WAIT
tKHQZ
tKHQX2
D0-D15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Hi-Z
READ Burst Identified
(W = High)
AI06784
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t specifications are met.
ELKH
29/48
M69KB096AA
Figure 20. LB/UB Controlled, Synchronous Burst Read (4-word) AC Waveforms
tKHKH
tKHKL
K
tAVKH
tKHAX
tKHLH
VALID
ADDRESS
A0-A21
tAVLH
tLLKH
L
tKHEH
tELKH
tKHQV1
tEHEL
E
tEHQZ
tGLQV
G
W
tKHWX
tWHKH
tGHQZ
tGLQX
tBLKH tKHBX
LB/UB
tELTV
tKHTX
Hi-Z
Hi-Z
WAIT
tKHQZ
tKHQX2
tKHQX1
tKHQZ
tKHQZ
DQ0-DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Hi-Z
Hi-Z
READ Burst Identified
(W = High)
AI06785
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. The Burst Length bits BCR0 to BR2 are set to ‘001’ (4 Words).
3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t
specifications are met.
ELKH
30/48
M69KB096AA
Figure 21. Synchronous Burst Read Suspend and Resume Waveforms
tKLKL
tKHKL
tAVKH
tKHAX
Valid
Address
Valid
0-A21
tAVLH
Address
tLLKH
tKH
L
tLLKH
tKHLH
tEHQZ
tEHEL
tELKH
tGHQZ
tGLQV
tGHQZ
tWHKH
tBLKH
tKHWX
tKHBX
tGLQX
W
tGLQX
B/UB
tGLQV
Hi-Z
Hi-Z
Hi-Z
WAIT
Valid
Valid
Valid
Valid
Valid
Valid
0-D15
Output Output Output Output
Output Output
tKHQV1
tKHQX2
AI08760c
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t specifications are met.
ELKH
31/48
M69KB096AA
Figure 22. Continuous Burst Read Showing an Output Delay for End-of-Row Condition (BCR8=0,1)
tKLKH
K
tKHKH
tF
A0-A21
DON'T CARE
DON'T CARE
L
LB/UB
E
(4)
G
DON'T CARE
tKHTV
DON'T CARE
W
tKHTX
WAIT
(3)
VALID
OUTPUT
VALID
VALID
OUTPUT
VALID
DQ0-DQ15
OUTPUT
OUTPUT
tKHQV2
tKHQX2
WAIT CONFIGIGURED WITH BCR8 = '0'
WAIT CONFIGIGURED WITH BCR8 = '1'
AI06787b
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low, WAIT asserted during delay; Burst Wrap bit BCR3 set
to ‘0’ (wrap).
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t
specifications are met.
ELKH
3. WAIT will be asserted for a maximum of 2xLC Cycles (LC being the Latency code set through BCR[13-11]).
4. E must not remain Low longer that t
.
ELEH
32/48
M69KB096AA
Table 16. Synchronous Burst Read AC Characteristics
M69KB096AA
80MHz 66MHz
Symbol Alt.
Parameter
Unit
Min
Max
46.5
9
Min Max
t
t
t
ABA
Burst Access Time
56
ns
ns
ns
ns
KHQV1
t
Delay From Clock High to Output Valid
Address Valid to L High
11
KHQV2
ACLK
t
t
10
10
AVLH
AVS
t
t
BOE
Delay From Output Enable Low to Output Valid in Burst mode
20
20
GLQV
Chip Enable High between Subsequent Mixed-Mode Read
Operations
(5)
t
5
1
5
ns
t
t
CBPH
EHEL
t
t
CEW
Chip Enable Low to WAIT Valid
Maximum Chip Enable Low Pulse
Clock Period
7.5
8
1
7.5
8
ns
ns
ns
ns
ELTV
(5)
t
CEM
ELEH
(4)
t
12.5
4.5
20
20
15
5
20
20
t
CLK
KHKH
t
t
Chip Enable Low to Clock High
ELKH
CSP
t
t
KHAX
KHBX
t
t
HD
Hold Time From Active Clock Edge
2
2
ns
KHWX
t
KHEH
t
KHLH
(2)
t
Chip Enable High to Output Hi-Z
8
8
ns
ns
t
HZ
EHQZ
t
R
Clock Rise Time
Clock Fall Time
t
1.8
2.0
KHKL
t
F
t
t
Clock High to WAIT Valid
Clock High to WAIT Transition
KHTV
t
9
11
ns
KHTL
KHTX
t
t
KHZ
Clock High to Output Hi-Z
3
2
2
8
5
3
2
2
8
5
ns
ns
ns
KHQZ
KHQX1
KHQX2
t
t
KLZ
Clock High to Output Transition
Output Hold from Clock High
t
t
KOH
t
Clock High to Clock Low
Clock Low to Clock High
KHKL
t
KP
4
5
ns
t
KLKH
(2)
t
Output Enable High to Output Hi-Z
8
8
ns
ns
t
OHZ
GHQZ
(3)
t
Output Enable Low to Output Transition
5
3
5
3
t
OLZ
GLQX
t
t
t
AVKH
LLKH
BLKH
t
SP
Set-up Time to Active Clock Edge
ns
t
WHKH
t
CHKH
Note: 1. All the tests are performed with the outputs configured in “Full drive” strength (BCR5=’0’).
2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a
transition of 100mV between V or V and V /2.
OH
OL
CCQ
3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a
transition of 100mV between the High-Z level (V /2) and V or V
.
OL
CCQ
OH
4. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t
specifications are met.
ELKH
5. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every t . A refresh opportunity is
ELEH
satisfied by either of the following two conditions: E = V during Clock input K rising edge or E = V for longer than 15ns.
IH
IH
33/48
M69KB096AA
Figure 23. Chip Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
A0-A21
VALID ADDRESS
tAVWH
tWHAX
L
tELEH,
tELWH
tAVEL
E
tBLBH
LB/UB
G
tWHWL
tWLWH
W
tDVEH tEHDX
DQ0-DQ15
Hi-Z
VALID INPUT
tELTV
tEHTZ
Hi-Z
WAIT
Hi-Z
AI06788c
Figure 24. LB/UB Controlled, Asynchronous Write AC Waveforms
tAVAX
A0-A21
L
VALID ADDRESS
tAVWH
tWHAX
tELEH, tELWH
tBLBH
E
LB/UB
G
tWHWL
Hi-Z
tWLWH
W
tDVEH
tEHDX
DQ0-DQ15
VALID INPUT
tELTV
Hi-Z
tBHTZ
Hi-Z
WAIT
AI06789d
34/48
M69KB096AA
Figure 25. Write Enable Controlled, Asynchronous Write AC Waveforms
tAVAX
A0-A21
L
VALID ADDRESS
tWHAX
tAVWH
tELEH, tELWH
tBLBH
E
LB/UB
G
tWLWH
tWHWL
W
tAVWL
tDVEH
tEHDX
tWHTZ
DQ0-DQ15
Hi-Z
VALID INPUT
tELTV
WAIT
Hi-Z
Hi-Z
AI06790c
35/48
M69KB096AA
Figure 26. L Controlled, Asynchronous Write AC Waveforms
A0-A21
VALID ADDRESS
tAVLH
tLHAX
tLLWH
tLLLH
tLHLL
L
tAVWH
tELEH, tELWH
E
tBLBH
LB/UB
G
tWLWH
tDVEH
tWHWL
W
tEHDX
DQ0-DQ15
Hi-Z
tELTV
VALID INPUT
tWHTZ
Hi-Z
WAIT
Hi-Z
AI06791c
36/48
M69KB096AA
Figure 27. Configuration Register Write in Asynchronous Mode Followed by Read Operation
K
A0-A21
ADDRESS
ADDRESS
OPCODE
except A19
tAVLH
Select Control Register
A19
CR
tAVLH
tLHLL
L
tEHEL
tLLVH
Initiate Control Register Access
tELWH
E
G
tWLWH
Write Address Bus Value
to Control Register
W
LB/UB
DATA VALID
DQ0-DQ15
AI06778
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; Hold data one clock; WAIT asserted during
delay.
2. A19 = V to load RCR; A19 = V to load BCR.
IL
IH
37/48
M69KB096AA
Figure 28. Asynchronous Write Followed by Synchronous Burst Read (4-word) AC Waveforms
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low; WAIT asserted during delay.
2. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every t . A refresh opportunity is
ELEH
satisfied by either of the following two conditions: E = V during Clock input K rising edge or E = V for longer than 15ns.
IH
IH
3. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t
specifications are met.
ELKH
38/48
M69KB096AA
Figure 29. Synchronous Burst Read (4-word) Followed by Asynchronous Write AC Waveforms
Note: 1. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every t . A refresh opportunity is
ELEH
satisfied by either of the following two conditions: E = V during Clock input K rising edge or E = V for longer than 15ns.
IH
IH
39/48
M69KB096AA
Table 17. Asynchronous Write AC Characteristics
M69KB096AA
70ns 85ns
Symbol
Alt.
Parameter
Unit
Min
Max
Min
Max
t
AVEL
t
AVWL
t
t
t
t
Address Setting Time
0
0
µs
AVBL
LLWL
ELWL
AS
t
t
L High to Address Transition
Address Valid to L High
5
5
ns
ns
LHAX
AVH
t
t
AVS
10
10
AVLH
t
t
Address Valid to Write Enable High
Address Valid to Upper/Lower Byte Enable Transition
AVWH
t
70
85
ns
AW
AVBH
t
t
t
BLBH
BLEH
BLWH
t
Upper/Lower Byte Enable Low to End of Write Operation
Chip Enable Low to WAIT Valid
70
1
85
1
ns
ns
ns
BW
t
t
CEW
7.5
7.5
ELTV
In Mixed-Mode Operation: Delay between Address
Transition in Asynchronous Write mode and Clock High in
Burst Read mode
t
t
70
85
AXCH
CKA
Chip Enable High between Subsequent Asynchronous
Operations
t
t
5
5
ns
ns
ns
EHEL
CPH
t
t
ELLH
BLLH
t
Chip Enable Low to L High
10
70
10
85
CVS
t
ELBH
t
Chip Enable Low to End of Write Operation
CW
t
ELWH
t
EHDX
t
t
t
DH
Input Hold from End of Write Operation
Data to Write Time Overlap
0
0
ns
ns
WHDX
BHDX
t
t
t
DVEH
DVBH
DVWH
t
DW
23
23
t
t
t
VP
L Pulse Width Low
10
10
70
10
10
85
ns
ns
ns
LLLH
LHLL
t
L Pulse Width High
VPH
t
t
L Low to Write Enable High
LLWH
VS
t
AVAX
t
Write Cycle Time
Write Pulse Width
70
46
85
55
ns
ns
WC
t
WHWH
t
WLBH
t
t
WP
WLEH
t
WLWH
t
t
Write Enable Pulse Width High
Write Enable High to Address Transition
Write Enable Low to Data Valid
10
0
10
0
ns
ns
ns
WHWL
WPH
t
t
WHAX
WR
t
t
WHZ
8
8
WLDV
40/48
M69KB096AA
M69KB096AA
70ns 85ns
Symbol
Alt.
Parameter
Unit
Min
Max
Min
Max
t
AVEL
t
AVWL
t
t
t
t
Address Setting Time
0
5
0
5
µs
AVBL
LLWL
ELWL
AS
t
t
L High to Address Transition
ns
ns
LHAX
AVH
t
t
Chip Enable High to WAIT Hi-Z
LB/UB High to WAIT Hi-Z
EHTZ
t
8
8
BHTZ
HZ
Write Enable High to WAIT Hi-Z
t
WHTZ
Note: 1. WE# LOW time must be limited to t
(8 µs).
CEM
2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14. The transition timings measure a
transition of 100 mV between the High-Z level (V ) and V or V
.
OL
CCQ/2
OH
3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14. The High-Z timings measure a tran-
sition of 100 mV between V or V and V
.
CCQ/2
OH
OL
Figure 30. Synchronous Burst Write AC Waveform
tKHKH
K
VALID
ADDRESS
A0-A21
tAVKH
tKHLH
tLLKH
L
tBLKH
tKHBH
LB/UB
tKHEH
tELKH
tEHEL
tELEH
E
G
tWHKH
tELTV
tKHWH
W
tKHTV
Hi-Z
Hi-Z
WAIT
tDVKH tKHDX
VALID
INPUT
VALID
INPUT
D0-D15
VALID
INPUT
VALID
INPUT
Hi-Z
WRITE Burst Identified
(W = Low)
AI06792b
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; WAIT asserted during delay.
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t specifications are met.
ELKH
41/48
M69KB096AA
Figure 31. Continuous Burst Write Showing an Output Delay for End-of-R ow Condition (BCR8=0)
tKLKH
K
tKHKH
tF
A0-A21
DON'T CARE
DON'T CARE
L
LB/UB
E
G
DON'T CARE
tKHTV
DON'T CARE
W
tKHTX
WAIT
(3)
tKHDX
tDVKH
VALID
INPUT D[n]
VALID
INPUT D[n+1]
VALID
VALID
VALID
INPUT D[n+2]
DQ0-DQ15
INPUT D[n+3] INPUT D[n+4]
End of Row
AI06793b
Note: 1. Non default BCR Register settings: 3 clock cycle latency; WAIT active Low, Burst Wrap bit BCR3 set to ‘0’ (wrap).
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t specifications are met.
ELKH
3. WAIT will be asserted for a maximum of (2xLC)+1 cycles (LC being the Latency Code set through BCR[13-11])
4. Taking E high or L Low will abort the Burst operation and the writing of the first data.
42/48
M69KB096AA
Figure 32. Synchronous Burst Write Followed by Read AC Waveforms (4 Words)
tKHKH
tKLKH
K
tKHAX
tKHAX
tAVKH
tKHKL
tAVKH
Addr.
tKHLH
tLLKH
tKHLL
tKHEH
tKHLH
L
tELKH
tKHEH
tGHQZ
tEHEL
E
(2)
tELKH
tGLQX
G
tWLKH
tWHKH
tKHWL
W
tKHWH
UB, LB
WAIT
tKHTX
tKHTX
tDVKH
tKHDX
tKHQX2
DQ0-
DQ15
D
D
D
D
D
D
D
IN3
D
O0
O1
O2
O3
IN0
IN1
IN2
ai11313
Note: 1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal
is active Low (BCR10=0), and is asserted during delay (BCR8=0). In fixed Latency mode, row boundary crossing
2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than t
.
ELEH
43/48
M69KB096AA
Figure 33. Configuration Register Write in Synchronous Mode Followed by Read Operation
K
Latch Control Register Value
A0-A21
ADDRESS
OPCODE
except A19
tAVKH
Latch Control Register Address
ADDRESS
A19
CR
L
tRHKH
tCHKH
tELKH
tKHRL
tKHLH
tEHEL
E
G
W
tKHLH
tWLKH
LB/UB
WAIT
tELTV
Hi-Z
Hi-Z
DQ0-DQ15
AI06779b
Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; Hold data one clock; WAIT asserted during
delay.
2. A19 = V to load RCR; A19 = V to load BCR.
IL
IH
44/48
M69KB096AA
Table 18. Synchronous Burst Write AC Characteristics
M69KB096AA
80MHz 66MHz
Min Max Min Max
Symbol
Alt.
Parameter
Unit
Chip Enable High between Subsequent Mixed-Mode Read
Operations
(1)
t
5
5
ns
t
CBPH
EHEL
t
t
CEW
Chip Enable Low to WAIT Valid
Clock Period
1
7.5
20
20
1
15
5
7.5
20
20
ns
ns
ns
ELTV
(2)
t
12.5
4.5
t
CLK
CSP
KHKH
t
t
Chip Enable Low to Clock High
ELKH
t
t
KHAX
KHBH
t
t
KHWH
t
Hold Time From Active Clock Edge
2
2
ns
HD
KHEH
t
KHLH
t
KHRL
t
t
Clock Rise Time
Clock Fall Time
R
t
1.8
9
2.0
11
ns
KHKL
F
t
t
t
KHTL
Clock High to WAIT Valid
Clock High to Clock Low
ns
ns
KHTV
KHKL
t
KP
4
3
5
3
t
t
t
AVKH
BLKH
Set-up Time to Active Clock Edge
WHKH
t
SP
ns
t
WLKH
t
t
CHKH
RHKH
(1)
t
Maximum Chip Enable Pulse Width
8
8
µs
t
CEM
ELEH
Note: 1. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every t . A refresh opportunity is
ELEH
satisfied by either of the following two conditions: E = V during Clock input K rising edge or E = V for longer than 15ns.
IH
IH
2. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as t
specifications are met.
ELKH
Figure 34. Power-Up AC Waveforms
E
tVCHEL
1.7V
VCC, VCCQ
Device Ready For Normal Operation
Device Initialization
AI06794
Table 19. Power-Up AC Characteristics
M69KB096AA
Symbol
Alt.
Parameter
70ns
85ns
Min
Unit
Min
Max
Max
t
t
Initialization delay
150
150
µs
VCHEL
PU
45/48
M69KB096AA
PART NUMBERING
Table 20. Ordering Information Scheme
Example:
M69KB096 A
A
70
C
W
8
Device Type
M69 = PSRAM
Mode
K =Tested Die
Operating Voltage
B = V = 1.7 to 1.95V, Burst, Address/Data Bus Standard x16
CC
Array Organization
096 = 64 Mbit (4Mb x16)
Option
A = 1 Chip Enable
Die Revision
A = Revision A
Speed Class
70 = 70ns
85 = 85ns
Maximum Clock Frequency
A= 66 MHz Max Clock Frequency in Burst Read Mode
C= 80MHz Max Clock Frequency in Burst Read Mode
Package
W = Unsawn Wafer
Operating Temperature
8 = –30 to 85 °C
The notation used for the device number is as shown in Table 20.. Not all combinations are necessarily
available. For a list of available options (speed, package, etc.) or for further information on any aspect of
this device, please contact your nearest STMicroelectronics Sales Office.
46/48
M69KB096AA
REVISION HISTORY
Table 21. Document Revision History
Date
Rev.
Revision Details
13-Oct-2004
0.1
First Issue.
I
I
current for Standard Leakage option added in FEATURES SUMMARY.
current for Standard Leakage option added in Table 13., DC Characteristics and test
SB
SB
conditions updated. I
current for Standard Leakage option added in Table
TCR
11-Feb-2005
0.2
14., Temperature Compensated Refresh Specifications and Conditions. I
current for
PAR
Standard Leakage option added in Table 15., Partial Array Refresh Specifications and
Conditions.
Standard Leakage option added in Table 20., Ordering Information Scheme.
Root Part Number changed to M69KB096AA.
104MHz maximum clock frequency and Low Leakage option removed.
Temperature range updated to –30°C to +85°C.
Clock Input (K). definition updated. Figure 3., Block Diagram modified.
Bus Modes Tables 2, 3 and Synchronous Burst Mode paragraph updated.
Output Impedance Bit (BCR5) renamed Driver Strength and definition updated.
R1 and R2 updated in Table 13., DC Characteristics and Refresh Specifications and
Conditions tables merged into Table 14..
Figures 15, 16, and 17 describing Asynchronous Read AC waveforms updated.
Figures 18, 19, 20, 21 and 22 describing Synchronous Read AC waveforms updated.
29-Apr-2005
1.0
Figures 23, 24, and 25, describing Asynchronous Write AC waveforms updated. t
and
AVWL
t
added in Table 17., Asynchronous Write AC Characteristics.
AVBL
Figures 28 and 29 added.
Figures 30, 31, and 32, describing Synchronous Write AC waveforms updated. Figure
32., Synchronous Burst Write Followed by Read AC Waveforms (4 Words) added. t
RHKH
and t
added in Table 18., Synchronous Burst Write AC Characteristics
KHRL
Table 21., Bond Pad Location and Identification modified to express the pad coordinates
from the center of the die.
, FEATURES SUMMARY, OPERATING MODES and Figure 5., Synchronous Burst Write
Mode (4-word burst) modified.
16-June-2005
18-Aug-2005
2.0
3.0
Updated Note 2 in Table 13., page 23, added notes to Table 14., page 24 and Table
17., page 40. Deleted Note 5 from Table 15., page 27.
Clock rate added in datasheet title.
Test conditions for I
Characteristics.
, I
, I
, I
, I
and I updated in Table 13., DC
12-Dec-2005
19-Jan-2006
4
5
CC1 CC1P CC2 CC3R CC3W SB
Section Wafer and die specifications removed.
47/48
M69KB096AA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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48/48
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