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M74HC175RM13TR [STMICROELECTRONICS]

QUAD D-TYPE FLIP FLOP WITH CLEAR; 四D型触发器与Clear
M74HC175RM13TR
型号： M74HC175RM13TR
厂家： ST    ST
描述：

QUAD D-TYPE FLIP FLOP WITH CLEAR
四D型触发器与Clear

触发器 锁存器 逻辑集成电路 光电二极管
文件： 总11页 (文件大小：428K)
中文：  中文翻译
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M74HC175  
QUAD D-TYPE FLIP FLOP WITH CLEAR  
■
■
■
■
■
■
■
HIGH SPEED :  
= 16 ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC175B1R  
M74HC175M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 175  
M74HC175RM13TR  
M74HC175TTR  
TSSOP  
DESCRIPTION  
The M74HC175 is an high speed CMOS HEX  
D-TYPE FLIP FLOP WITH CLEAR fabricated with  
silicon gate C MOS technology.  
These four flip-flops are controlled by a clock input  
(CLOCK) and a clear input (CLEAR). The  
information data applied to the D inputs (1D to 4D)  
are transferred to the outputs (1Q to 4Q and 1Q to  
4Q) on the positive-going edge of the clock pulse.  
The reset function is accomplished when the  
CLEAR input is low and all Q outputs are low  
regardless of other input conditions.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  
M74HC175  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
PIN DESCRIPTION  
PIN No  
SYMBOL  
NAME AND FUNCTION  
Asynchronous Master  
Reset (Active Low)  
1
CLEAR  
1Q to 4Q  
1Q to 4Q  
1D to 4D  
CLOCK  
2, 7, 10, 15  
3, 6, 11, 14  
4, 5, 12, 13  
9
Flip-Flop Outputs  
Complementary Flip-Flop  
Outputs  
Data Inputs  
Clock Input (LOW to  
HIGH, edge triggered)  
8
GND  
Vcc  
Ground (0V)  
16  
Positive Supply Voltage  
TRUTH TABLE  
INPUTS  
OUTPUTS  
FUNCTION  
CLEAR  
D
X
L
CLOCK  
Q
L
Q
H
H
L
X
H
L
H
H
X
H
L
H
Qn  
Qn  
NO CHANGE  
X : Don’t Care  
LOGIC DIAGRAM  
This logic diagram has not be used to estimate propagation delays  
2/11  
M74HC175  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
-0.5 to +7  
V
V
CC  
V
DC Input Voltage  
-0.5 to V + 0.5  
I
CC  
V
DC Output Voltage  
DC Input Diode Current  
DC Output Diode Current  
DC Output Current  
-0.5 to V + 0.5  
V
O
CC  
I
± 20  
± 20  
mA  
mA  
mA  
mA  
mW  
°C  
IK  
I
OK  
I
± 25  
O
I
or I  
DC V  
or Ground Current  
CC  
± 50  
CC  
GND  
P
Power Dissipation  
500(*)  
-65 to +150  
300  
D
T
Storage Temperature  
Lead Temperature (10 sec)  
stg  
T
°C  
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is  
not implied  
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Value  
Unit  
V
Supply Voltage  
2 to 6  
0 to V  
V
V
CC  
V
Input Voltage  
I
CC  
V
Output Voltage  
0 to V  
CC  
V
O
T
Operating Temperature  
Input Rise and Fall Time  
-55 to 125  
0 to 1000  
0 to 500  
0 to 400  
°C  
ns  
ns  
ns  
op  
V
V
V
= 2.0V  
= 4.5V  
= 6.0V  
CC  
CC  
CC  
t , t  
r
f
3/11  
M74HC175  
DC SPECIFICATIONS  
Test Condition  
Value  
T
= 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
V
High Level Input  
Voltage  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
IH  
V
V
V
Low Level Input  
Voltage  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
IL  
V
High Level Output  
Voltage  
I =-20 µA  
1.9  
4.4  
5.9  
2.0  
4.5  
6.0  
1.9  
4.4  
1.9  
4.4  
OH  
O
I =-20 µA  
4.5  
6.0  
4.5  
6.0  
2.0  
4.5  
6.0  
4.5  
6.0  
O
I =-20 µA  
5.9  
5.9  
V
V
O
I =-4.0 mA  
4.18 4.31  
4.13  
5.63  
4.10  
5.60  
O
I =-5.2 mA  
5.68  
5.8  
0.0  
0.0  
0.0  
O
V
Low Level Output  
Voltage  
I =20 µA  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
OL  
O
I =20 µA  
O
I =20 µA  
0.1  
0.1  
O
I =4.0 mA  
0.17 0.26  
0.18 0.26  
0.33  
0.33  
0.40  
0.40  
O
I =5.2 mA  
O
I
Input Leakage  
Current  
I
V = V  
or GND  
6.0  
6.0  
± 0.1  
± 1  
± 1  
µA  
µA  
I
CC  
CC  
I
Quiescent Supply  
Current  
CC  
V = V  
or GND  
4
40  
80  
I
4/11  
M74HC175  
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6ns)  
L
r
f
Test Condition  
Value  
-40 to 85°C -55 to 125°C Unit  
T
= 25°C  
Symbol  
Parameter  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
t
t
Output Transition  
Time  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
2.0  
4.5  
6.0  
30  
8
75  
15  
95  
19  
110  
22  
TLH THL  
ns  
ns  
7
13  
16  
19  
t
t
Propagation Delay  
Time  
60  
19  
16  
50  
16  
14  
13  
52  
61  
28  
7
150  
30  
190  
38  
225  
45  
PLH PHL  
(CLOCK - Q, Q)  
26  
32  
38  
t
t
Propagation Delay  
Time  
125  
25  
155  
31  
190  
38  
PLH PHL  
ns  
(CLEAR - Q, Q)  
21  
26  
32  
f
Maximum Clock  
Frequency  
6.2  
31  
37  
5
4.2  
21  
25  
MAX  
25  
30  
MHz  
ns  
t
t
Minimum Pulse  
Width (CLOCK)  
75  
15  
13  
75  
15  
13  
75  
15  
13  
0
95  
19  
16  
95  
19  
16  
95  
19  
16  
0
110  
22  
19  
110  
22  
19  
110  
22  
19  
0
W(H)  
W(L)  
W(L)  
6
t
Minimum Pulse  
Width (CLEAR)  
28  
7
ns  
6
t
t
Minimum Set-up  
Time  
28  
7
s
ns  
6
Minimum Hold  
Time  
h
0
0
0
ns  
0
0
0
t
Minimum Removal  
Time (CLEAR)  
5
5
5
REM  
5
5
5
ns  
5
5
5
CAPACITIVE CHARACTERISTICS  
Test Condition  
Value  
T
= 25°C  
Symbol  
Parameter  
-40 to 85°C -55 to 125°C Unit  
A
V
CC  
(V)  
Min. Typ. Max. Min. Max. Min. Max.  
C
Input Capacitance  
5.0  
5
10  
10  
10  
pF  
pF  
IN  
C
Power Dissipation  
Capacitance (note  
1)  
PD  
5.0  
47  
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without  
PD  
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I  
FLOP)  
= C x V x f + I /4 (per FLIP/  
CC(opr)  
PD CC IN CC  
5/11  
M74HC175  
TEST CIRCUIT  
C
R
= 50pF or equivalent (includes jig and probe capacitance)  
L
T
= Z  
of pulse generator (typically 50Ω)  
OUT  
WAVEFORM 1: PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CLOCK), SETUP AND  
HOLD TIME (D TO CLOCK) (f=1MHz; 50% duty cycle)  
6/11  
M74HC175  
WAVEFORM 2 :MINIMUM PULSE WIDTH (CLEAR) AND REMOVAL TIME ( CLEAR TO CLOCK)  
(f=1MHz; 50% duty cycle)  
WAVEFORM 3 : INPUT WAVEFORMS (f=1MHz; 50% duty cycle)  
7/11  
M74HC175  
Plastic DIP-16 (0.25) MECHANICAL DATA  
mm.  
TYP  
inch  
TYP.  
DIM.  
MIN.  
0.51  
0.77  
MAX.  
MIN.  
0.020  
0.030  
MAX.  
a1  
B
b
1.65  
0.065  
0.5  
0.020  
0.010  
b1  
D
E
e
0.25  
20  
0.787  
8.5  
2.54  
17.78  
0.335  
0.100  
0.700  
e3  
F
7.1  
5.1  
0.280  
0.201  
I
L
3.3  
0.130  
Z
1.27  
0.050  
P001C  
8/11  
M74HC175  
SO-16 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
1.75  
0.2  
MIN.  
MAX.  
0.068  
0.007  
0.064  
0.018  
0.010  
A
a1  
a2  
b
0.1  
0.003  
1.65  
0.46  
0.25  
0.35  
0.19  
0.013  
0.007  
b1  
C
0.5  
0.019  
c1  
D
45° (typ.)  
9.8  
5.8  
10  
0.385  
0.228  
0.393  
0.244  
E
6.2  
e
1.27  
8.89  
0.050  
0.350  
e3  
F
3.8  
4.6  
0.5  
4.0  
5.3  
0.149  
0.181  
0.019  
0.157  
0.208  
0.050  
0.024  
G
L
1.27  
0.62  
M
S
8° (max.)  
PO13H  
9/11  
M74HC175  
TSSOP16 MECHANICAL DATA  
mm.  
inch  
TYP.  
DIM.  
MIN.  
TYP  
MAX.  
1.2  
MIN.  
MAX.  
0.047  
0.006  
0.041  
0.012  
0.0089  
0.201  
0.260  
0.176  
A
A1  
A2  
b
0.05  
0.8  
0.15  
1.05  
0.30  
0.20  
5.1  
0.002  
0.031  
0.007  
0.004  
0.193  
0.244  
0.169  
0.004  
0.039  
1
0.19  
0.09  
4.9  
c
D
5
6.4  
0.197  
0.252  
E
6.2  
6.6  
E1  
e
4.3  
4.4  
4.48  
0.173  
0.65 BSC  
0.0256 BSC  
K
0°  
8°  
0°  
8°  
L
0.45  
0.60  
0.75  
0.018  
0.024  
0.030  
A2  
A
K
L
b
e
A1  
c
E
D
E1  
PIN 1 IDENTIFICATION  
1
0080338D  
10/11  
M74HC175  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the  
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from  
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications  
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information  
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or  
systems without express written approval of STMicroelectronics.  
© The ST logo is a registered trademark of STMicroelectronics  
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco  
Singapore - Spain - Sweden - Switzerland - United Kingdom  
© http://www.st.com  
11/11  

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