M74HC181M1R [STMICROELECTRONICS]
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR; 算术逻辑单元/函数发生器
| 型号： | M74HC181M1R |
| 厂家： | 
ST |
| 描述： | ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR |
| 文件： | 总13页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M74HC181
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
.
.
.
.
.
.
.
.
HIGH SPEED
tPD = 13 ns (TYP.) AT VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOH = IOL = 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
B1R
(Plastic Package)
M1R
(Micro Package)
VCC (OPR) = 2 V to 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS181
ORDER CODES :
M74HC181M1R
M74HC181B1R
DESCRIPTION
The 74HC181 is a high speed CMOS ARITHMETIC
LOGIC UNIT/FUNCTION GENERATOR fabricated
with silicon gate C2MOS technology. It has the same
highspeed performance ofLSTTL combined withtrue
CMOS low power consumption. These circuits per-
form 16 binary arithmetic operations on two 4-bit
words as shown in tables 1 and 2. These operations
are selected by the four function-select lines (S0, S1,
S2, S3) andinclude addition, subtraction, decrement,
and straight transfer. When performing arithmetic
manipulations, theinternal carries must be enabled by
applying a low-level voltage to the mode control input
(M). A full carry look-ahead scheme ismade available
in these devices for fast, simultaneous carry gener-
ationby means of two cascade-outputs (pins 15 and
17)for thefourbits in the package. Whenused in con-
junction with the M54HC182 or M74HC182, full carry
look-ahead circuits, high-speed arithmetic operations
can be performed. These circuits will accomodate ac-
tive-high oractive-low data, if the pin designations are
interpreted as shown below. Subtraction is accom-
plished by 1,s complement addition where the 1’s
complement ofthesubtrahend isgenerated internally.
The resultant output is1–B–1, which requires anend-
around or forced carry to produce A–B. The 181 can
also be utilized as a comparator. The A = B output is
internally decoded from the function outputs (F0, F1,
F2, F3) so that when two words of equal magnitude
are applied at the A and B inputs, itwill assume a high
level to indicated equality (A = B). The ALU should be
PIN CONNECTIONS (top view)
* Open drain Output Structure
October 1993
1/13
M74HC181
DESCRIPTION (continued)
in thesubtract mode withCn =Hwhen performing this
comparison. The A = B output is open-drain so that it
can be wire-AND connected to give a comparison for
more that four bits. The carry output (Cn + 4) canalso
be used to supply relative magnitude information.
Again, the ALU should be placed in the subtract mode
by placing thefunction select inputs S3, S2, S1, S0 at
L, H, H, L, respectively. These circuits have been de-
signed to not only incorporate all of the designer’s re-
quirements for arithmetic operations, but also to pro-
vide 16 possible functions of two Boolean variables
without the use of external circuitry. These logic func-
tionsare selected byuse ofthefour function-select in-
puts (S0, S1, S2, S3) with the mode-control input (M)
at a high level to disable the internal carry. All inputs
areequipped withprotectioncircuitsagainst staticdis-
charge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUITS
ONLY OUTPUT A = B
IEC LOGIC SYMBOLS
PIN DESCRIPTION
PIN No
SYMBOL
A0 to A3
B0 to B3
S0 to S3
Cn
NAME AND FUNCTION
Word A Inputs
2, 23, 21, 19
1, 22, 20, 18
Word B Inputs
6, 5, 4, 3
Function Select Inputs
Inv. Carry Input
7
8
M
Mode Control Input
Function Outputs
9, 10, 11, 13
F0 to F3
A = B
P
14
15
16
17
12
24
Comparator Output
Carry Propagate Output
Inv. Carry Output
Carry Generate Output
Ground (0V)
Cn + 4
G
GND
VCC
Positive Supply Voltage
PIN NUMBER
2
1
23 22 21 20 19 18
9
10 11 13
7
16
15 17
ACTIVE LOW DATA (Table 1) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 Cn Cn + 4
ACTIVE HIGH DATA (Table 1) A0 B0 A1 B1 A2 B2 A3 B3 F0 F1 F2 F3 Cn Cn + 4
P
X
G
Y
Input Cn
Output Cn + 4
Active LOW Data (Figure 1) Active HIGH Data (Figure 2)
H
H
L
H
L
A ≥ B
A < B
A > B
A ≤ B
A ≤ B
A > B
A < B
A ≥ B
H
L
L
2/13
M74HC181
TRUTH TABLE 1
Selection
ACTIVE LOW DATA
M = H Logic
Functions
M = L: Arithmetic Operations
S3
L
S2
L
S1
L
S0
L
Cn = L (no carry)
Cn = H (with carry)
F = A
F = A Minus 1
F = A
L
L
L
H
L
F = AB
F = A + B
F = 1
F = AB Minus 1
F = AB Minus 1
F = Minus 1 (2’s Compl)
F = A Plus (A + B)
F = AB Plus (A + B)
F = A Minus B Minus 1
F = A + B
F = AB
F = (AB)
F = Zero
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
F = A + B
F = B
F = A Plus (A + B) Plus 1
F = AB Plus (A + B) Plus 1
F = A Minus B
L
L
H
L
L
H
H
L
F = A
B
L
H
L
F = A + B
F = AB
F = (A + B) Plus 1
H
H
H
H
H
H
H
H
F = A Plus (A + B)
F = A Plus B
F = A Plus (A + B) Plus 1
F = A Plus B Plus 1
F = AB Plus (A + B) Plus 1
F = (A + B) Plus 1
L
L
H
L
F = A
F = B
B
L
H
H
L
F = AB Plus (A + B)
F = A + B
L
H
L
F = A + B
F = 0
H
H
H
H
F = A Plus A *
F = AB Plus A
F = AB Plus A
F = A
F = A Plus A Plus 1
F = AB Plus A Plus 1
F = AB Plus A Plus 1
F = A Plus 1
L
H
L
F = AB
F = AB
F = A
H
H
H
* Each bit is shifted to the next more significant position.
FIGURE 1
3/13
M74HC181
TRUTH TABLE 2
Selection
ACTIVE HIGH DATA
M = H Logic
Functions
M = L: Arithmetic Operations
S3
L
S2
L
S1
L
S0
L
Cn = H (no carry)
Cn = L (with carry)
F = A
F = A
F = A Plus 1
L
L
L
H
L
F = A + B
F = AB
F = 0
F = A + B
F = (A + B) Plus 1
F = (A + B) Plus 1
F = Zero
L
L
H
H
L
F = A + B
L
L
H
L
F = Minus 1 (2’s Compl)
F = A Plus (AB)
F = (A + B) Plus AB
F = A Minus B Minus 1
F = AB Minus 1
F = A Plus AB
F = A Plus B
L
H
H
H
H
L
F = AB
F = B
F = A Plus AB Plus 1
F = (A + B) Plus (AB) Plus 1
F = A Minus B
L
L
H
L
L
H
H
L
F = A
B
L
H
L
F = AB
F = AB
H
H
H
H
H
H
H
H
F = A + B
F = A Plus AB Plus 1
F = A Plus B Plus 1
F = (A + B) Plus AB Plus 1
F = AB
L
L
H
L
F = A
F = B
F = AB
F = 1
B
L
H
H
L
F = (A + B) Plus AB
F = AB Minus 1
F = A Plus A *
F = (A + B) Plus A
F = (A + B) Plus A
F = A Minus 1
L
H
L
H
H
H
H
F = A Plus A Plus 1
F = (A + B) Plus A Plus 1
F = (A + B) Plus A Plus 1
F = A
L
H
L
F = A + B
F = A + B
F = A
H
H
H
* Each bit is shifted to the next more significant position.
FIGURE 2
4/13
M74HC181
LOGIC DIAGRAM
5/13
M74HC181
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
V
IIK
DC Input Diode Current
DC Output Diode Current
DC Output Source Sink Current Per Output Pin
mA
mA
mA
mA
mW
oC
IOK
± 20
IO
± 25
ICC or IGND DC VCC or Ground Current
± 50
PD
Tstg
TL
Power Dissipation
500 (*)
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
oC
Absolute MaximumRatingsare those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2 to 6
Unit
V
Supply Voltage
Input Voltage
0 to VCC
0 to VCC
-40 to +85
0 to 1000
0 to 500
0 to 400
V
VO
Output Voltage
V
oC
Top
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
ns
6/13
M74HC181
DC SPECIFICATIONS
Test Conditions
VCC
(V)
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
-40 to 85 oC
Symbol
Parameter
Unit
VIH
High Level Input Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
V
V
VIL
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
VOH
High Level Output Voltage
(except A = B output)
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
VI =
VIH
or
IO=-20 µA
V
V
5.9
VIL
IO=-4.0 mA 4.18 4.31
4.13
5.63
IO=-5.2 mA 5.68
5.8
0.0
0.0
0.0
VOL
Low Level Output Voltage
0.1
0.1
0.1
0.1
0.1
0.1
0.33
0.33
±1
VI =
VIH
or
IO= 20 µA
VIL
IO= 4.0 mA
IO= 5.2 mA
0.17 0.26
0.18 0.26
±0.1
II
Input Leakage Current
6.0 VI = VCC or GND
6.0 VI = VCC or GND
µA
µA
ICC
Quiescent Supply Current
4
40
7/13
M74HC181
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Test Conditions
Value
TA = 25 oC
-40 to 85 oC
74HC
Symbol
Parameter
Unit
VCC
(V)
54HC and 74HC
Min. Typ. Max. Min. Max.
tTLH
tTHL
Output Transition Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
30
8
75
15
95
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
13
16
tPLH
tPHL
Propagation Delay Time
(1)
54
16
13
90
26
20
97
27
21
80
23
18
81
24
19
80
23
18
80
23
18
80
23
18
95
27
21
95
27
21
86
24
18
92
27
27
5
120
24
150
30
20
26
tPLH
tPHL
Propagation Delay Time
(2)
215
43
270
54
37
46
tPLH
tPHL
Propagation Delay Time
(3)
215
43
270
54
37
46
tPLH
tPHL
Propagation Delay Time
(4)
180
36
225
45
31
38
tPLH
tPHL
Propagation Delay Time
(5)
190
38
240
48
32
41
tPLH
tPHL
Propagation Delay Time
(6)
180
36
225
45
31
38
tPLH
tPHL
Propagation Delay Time
(7)
170
34
215
43
29
37
tPLH
tPHL
Propagation Delay Time
(8)
170
34
215
43
29
37
tPLH
tPHL
Propagation Delay Time
(9)
220
44
275
55
37
47
tPLH
tPHL
Propagation Delay Time
(10)
220
44
275
55
37
47
tPLH
tPHL
Propagation Delay Time
(11)
200
40
250
50
34
43
tPLZ
tPZL
Propagation Delay Time
(12)
210
42
265
53
RL = 1kΩ
36
45
CIN
Input Capacitance
10
10
pF
pF
CPD (*) Power Dissipation Capacitance
195
(*) CPD isdefined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the followingequation. ICC(opr) = CPD • VCC • fIN + ICC
8/13
M74HC181
PROPAGATION DELAY TIME TEST CONDITIONS
Test No
(1)
INPUT
Cn
OUTPUT
Test Conditions
Cn + 4
(2)
Any A or B
Any A or B
Cn
Cn + 4
M = GND, S0 = S3 = VCC, S1 = S2 GND (SUM mode)
M = GND, S0 = S3 = GND, S1 = S2 VCC (DIFF mode)
M = GND (SUM or DIFF mode)
(3)
Cn + 4
(4)
Any F
(5)
Any A or B
Any A or B
Any A or B
Any A or B
Ai or Bi
G
G
M = GND, S0 = S3 = VCC, S1 = S2 GND (SUM mode)
M = GND, S0 = S3 = GND, S1 = S2 VCC (DIFF mode)
M = GND, S0 = S3 = VCC, S1 = S2 GND (SUM mode)
M = GND, S0 = S3 = GND, S1 = S2 VCC (DIFF mode)
M = GND, S0 = S3 = VCC, S1 = S2 GND (SUM mode)
M = GND, S0 = S3 = GND, S1 = S2 VCC (DIFF mode)
M = VCC (Logic mode)
(6)
(7)
F
(8)
F
(9)
Fi
(10)
(11)
(12)
Ai or Bi
Fi
Ai or Bi
Fi
Any A or B
A = B
M = GND, S0 = S3 = GND, S1 = S2 VCC (DIFF mode)
SWITCHING CHARACTERISTICS TEST WAVEFORM
9/13
M74HC181
TEST CIRCUIT ICC (Opr.)
Input Condition :
A0, A1, A2, A3, S0, S3, Cn = VDD
B1, B2, B3, S1, S2, M = GND
INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHINGCHARACTERISTICS TEST.
10/13
M74HC181
Plastic DIP24 (0.25) MECHANICAL DATA
mm
inch
TYP.
0.025
0.018
DIM.
MIN.
0.23
15.2
TYP.
0.63
0.45
MAX.
MIN.
0.009
0.598
MAX.
a1
b
b1
b2
D
E
0.31
0.012
1.27
0.050
32.2
1.268
0.657
16.68
e
2.54
0.100
1.100
e3
F
27.94
14.1
0.555
I
4.445
3.3
0.175
0.130
L
P043A
11/13
M74HC181
SO24 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45° (typ.)
15.20
10.00
15.60
10.65
0.598
0.393
0.614
0.420
E
e
1.27
0.05
0.55
e3
F
13.97
7.40
0.50
7.60
1.27
0.291
0.19
0.299
0.050
L
S
8° (max.)
L
c1
b
e
s
e3
E
D
24
13
1
12
12/13
M74HC181
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
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13/13
相关型号：
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STMICROELECTR
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