M74HC40103F1R [STMICROELECTRONICS]
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS; 8 STAGE预置同步递减计数器
| 型号： | M74HC40103F1R |
| 厂家： | 
ST |
| 描述： | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| 文件： | 总14页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M54/74HC40102
M54/74HC40103
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
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.
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.
.
.
HIGH SPEED
fMAX = 40 MHz (TYP.) at VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
B1R
(Plastic Package)
F1R
(Ceramic Package)
WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
PIN AND FUNCTION COMPATIBLE WITH
40102B/40103B
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXXXF1R M74HCXXXXXM1R
M74HCXXXXXB1R M74HCXXXXX C1R
DESCRIPTION
PIN CONNECTIONS (top view)
The M54/74HC40102/40103 are highspeed CMOS
8-STAGE PRESETTABLE
SYNCHRONOUS
DOWN COUNTERS fabricated with silicon gate
C2MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while main-
taining the CMOS low power dissipation.
The HC40102, and HC40103 consist of an 8-stage
synchronous down counter with a single output
which is active when the internal count is zero. The
HC40102 is configured as two cascaded 4-bit BCD
counters, and the HC40103 contains a single 8-bit
binary counter. Each type has control inputs for en-
abling or disabling the clock, for clearing the counter
to its maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on each posi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETECT
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the J
input is clocked into the counter on the next positive
clock transition regardless of the state of the CI/CE
input.
NC =
No Internal
Connection
March 1993
1/14
M54/M74HC40102/40103
DESCRIPTION (Continued)
When the ASYNCHRONOUS PRESET-ENABLE
(APE)input is low, data at the J inputs isasynchron-
ously forced into the counter regardless of the state
of the SPE, CI/CE, or CLOCK inputs. J Inputs J0-J7
represent two 4-bit BCD words for the HC40102 and
a single 8-bit binary word for the HC40103. When
the CLEAR (CLR input is low, the counter is asyn-
chronously cleared to its maximum count (9910 for
the HC40102 and 25510 for the HC40103 regard-
less of the state of any other input. The precedence
relationship between control input is indicated in the
truth table. If all control inputs are high at the time of
zero count, the counters will jump to the maximum
count, giving a counting sequence of 100 pr 256
clockpulses long. The HC40102 and HC40103 may
be cascaded using the CI/CE input and the CO/ZD
output, in either a synchronous or ripple mode. All
inputs are equipped with protection circuits against
static discharge and transient excess voltage.
TRUTH TABLE
CONTROL INPUTS
MODE
FUNCTIONAL DESCRIPTION
CLEAR APE
SPE
CI/CE
H
H
H
H
COUNT INHIBIT
EVEN IF CLOCK IS GIVEN, NO COUNT IS
MADE
H
H
H
H
H
L
L
REGULAR COUNT
DOWN COUNT AT RISING EDGE OF CLOCK
X
SYNCHRONOUS PRESET
ASYNCRONOUS PRESET
CLEAR
DATA OF PI TERMINAL IS PRESET AT
RISING EDGE OF CLOCK
H
L
L
X
X
X
X
DATA PF PI TERMINAL IS
ASYNCHRONOUSLY PRESET TO CLOCK
X
COUNTER IS SET TO MAXIMUM COUNT
X: DON’T CARE - MAXIMUM COUNT:”99” FORHC40102AND ”255”: FOR HC40103
LOGIC DIAGRAM (HC40102)
2/14
M54/M74HC40102/40103
LOGIC DIAGRAM (HC40103)
TIMING CHART
3/14
M54/M74HC40102/40103
PIN DESCRIPTION
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK
CLock Input (LOW to
HIGH edge triggered)
2
CLEAR
Asynchronous Master
Reset Input (Active LOW)
3
CI/CE
Terminal Enable Input
Jam Inputs
4, 5, 6, 7, 10, J0 to J9
11, 12, 13
9
APE
CO/ZD
SPE
Asynchronous Preset
Enable Input (Active LOW)
14
15
Terminal Count Output
(Active LOW)
Synchronous Preset
Enable Input (Active LOW)
8
GND
VCC
Ground (0V)
16
Positive Supply Voltage
IEC LOGIC SYMBOLS
HC40102
HC40103
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
± 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
V
IIK
DC Input Diode Current
DC Output Diode Current
DC Output Source Sink Current Per Output Pin
mA
mA
mA
mA
mW
oC
IOK
± 20
IO
± 25
ICC or IGND DC VCC or Ground Current
± 50
PD
Tstg
TL
Power Dissipation
500 (*)
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
oC
Absolute MaximumRatingsare those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
4/14
M54/M74HC40102/40103
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2 to 6
Unit
V
Supply Voltage
Input Voltage
Output Voltage
0 to VCC
0 to VCC
V
VO
V
Top
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
oC
oC
tr, tf
Input Rise and Fall Time
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
0 to 1000
0 to 500
0 to 400
ns
DC SPECIFICATIONS
Test Conditions
VCC
Value
-40 to 85 oC -55 to 125 oC
74HC 54HC
TA = 25 oC
54HC and 74HC
Symbol
Parameter
Unit
(V)
Min. Typ. Max. Min. Max. Min. Max.
VIH
High Level Input
Voltage
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
VIL
Low Level Input
Voltage
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
VOH
High Level
Output Voltage
1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
1.9
4.4
VI =
VIH
or
IO=-20 µA
V
V
5.9
5.9
VIL
IO=-4.0 mA 4.18 4.31
4.13
5.63
4.10
5.60
IO=-5.2 mA 5.68
5.8
0.0
0.0
0.0
VOL
Low Level Output 2.0
Voltage
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VI =
VIH
or
IO= 20 µA
4.5
6.0
4.5
6.0
0.1
0.1
VIL
IO= 4.0 mA
IO= 5.2 mA
0.17 0.26
0.18 0.26
±0.1
0.33
0.33
±1
0.40
0.40
±1
II
Input Leakage
6.0
VI = VCC or GND
µA
µA
Current
ICC
Quiescent Supply 6.0 VI = VCC or GND
Current
4
40
80
5/14
M54/M74HC40102/40103
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Test Conditions
Value
TA = 25 oC
54HC and 74HC
-40 to 85 oC -55 to 125 oC
Symbol
Parameter
Unit
VCC
(V)
74HC
54HC
Min. Typ. Max. Min. Max. Min. Max.
tTLH
tTHL
Output Transition
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
30
8
75
15
95
19
110
22
ns
ns
ns
ns
ns
pF
7
13
16
19
tPLH
tPHL
Propagation
Delay Time
(CK - CO/ZD)
96
24
20
116
29
25
104
26
22
48
12
10
8
185
37
230
46
280
56
31
39
47
tPLH
tPHL
Propagation
Delay Time
(APE - CO/ZD)
225
45
280
56
340
68
38
48
57
tPLH
tPHL
Propagation
Delay Time
(CL - CO/ZD)
200
40
250
50
300
60
34
43
51
tPLH
tPHL
Propagation
Delay Time
(CI/CE - CO/ZD)
95
120
24
145
29
19
16
20
24
fMAX
Propagation
Delay Time
4
3
2.6
13
15
20
24
32
38
5
16
19
CIN
Input Capacitance
10
10
10
pF
pF
CPD (*) Power Dissipation
Capacitance
60
(*) CPD isdefined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the followingequation. ICC(opr) = CPD • VCC • fIN + ICC
TEST CIRCUIT ICC (Opr.)
INPUT TRANSITIONTIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICSTEST.
6/14
M54/M74HC40102/40103
FUNCTIONAL DESCRIPTION
The HC40102 and HC40103 are 8-stage preset-
table synchronous down counters. Carry Out/Zero
Detect (CO/ZD) is output at the ”L” level for the
period of 1 bit when the readout becomes ”0”. The
HC40102 adopts binary coded decimal notation,
making setting up to 99 counts possible. While the
HC40103adopts 8-bit binary counterand canset up
to 255 counts.
The contents of count jump to maximum count (99
for the HC40102 and 225 for the HC40103) if clock
is given when the readout is ”0”. Therefore, oper-
ation of 100-frequency division and that of 256-fre-
quency division are carried outfor the HC40102 and
HC40103, respectively, when clock input alone is
given without various kinds of preset operation.
PRESET OPERATION AND RESET OPERATION
COUNT OPERATION
When Clear (CLEAR) input is set to the ”L” level, the
readout is set to the maximum count independetly
of other inputs. When Asynchronous Preset Enable
(APE) input is set to the ”L” level, readouts given on
J0 to J7can be preset asynchronously to counter in-
dependently of inputs other than CLEAR input.
When Synchronous Preset Enable (SPE) is set to
the ”L” level, the readouts given on J0 to J7 can be
preset to counter synchronously with the rise of
clock.
At the ”H” level of control input of CLEAR, SPE and
APE, the counter carriers out down count operation
one byone attherise of pulsegiven toCLOCKinput.
Count operation can be inhibited by setting Carry
Input/Clock Enable CI/CE to the ”H” level.
CO/ZD is output at the ”L” level when the readout
becomes ”0” but is not output even if the readout
becomes ”0” when CI/CE is at the ”H” level, thus
maintaining the ”H” level.
As to these operation modes, refer to the truthtable.
Synchronous cascade operation can be carried out
by using CI/CE input and CO/ZD output.
Input
CLEAR APE SPE
Output
J
TE CLOCK
Qn + 1
L
X
L
X
X
X
L
X
L
X
X
X
X
X
X
L
X
X
X
L
L
H
L
H
H
H
H
H
H
H
L
H
L
_
H
H
H
H
H
▲_
_
L
H
X
X
X
▲_
H
_
__
L
_▼
Qn
_
H
H
▲_
Qn
__
Qn
H
X
7/14
M54/M74HC40102/40103
SWITCHING CHARACTERISTICS TEST WAVEFORM
WAVEFORM 1
WAVEFORM 2
WAVEFORM 3
WAVEFORM 4
WAVEFORM 5
WAVEFORM 6
(** F/F output is internal signal of IC)
8/14
M54/M74HC40102/40103
EXAMPLE OF TYPICAL APPLICATION
PROGRAMMABLE DIVIDE-BY-N COUNTER
fIN
N + 1
• fOUT
=
•Timing chart when N = ”3”
(J0, J1 = VCC, J2 – J7 = GND)
• HC40102... 1/2to 1/100 are dividable
• HC40103... 1/2to 1/256 are dividable
PARALLEL CARRY CASCADING
* Atsynchronous cascade connection, huzzerd occurs atC0 output after itssecond stage when digitplacechanges, due todelay arrival. Therefore,
take gate from HC32 or the like,notfrom C0 output at the rear stage directly.
PROGRAMMABLE TIMER
Note :The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the
above formula-1/fIN the above formula.
9/14
M54/M74HC40102/40103
Plastic DIP16 (0.25) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.51
0.77
TYP.
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
10/14
M54/M74HC40102/40103
Ceramic DIP16/1 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
20
MIN.
MAX.
0.787
0.276
A
B
7
D
E
3.3
0.130
0.700
0.38
0.015
e3
F
17.78
2.29
0.4
2.79
0.55
1.52
0.31
1.27
10.3
8.05
5.08
0.090
0.016
0.046
0.009
0.020
0.110
0.022
0.060
0.012
0.050
0.406
0.317
0.200
G
H
L
1.17
0.22
0.51
M
N
P
7.8
0.307
Q
P053D
11/14
M54/M74HC40102/40103
SO16 (Narrow) MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.004
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45° (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
8° (max.)
P013H
12/14
M54/M74HC40102/40103
PLCC20 MECHANICAL DATA
mm
inch
DIM.
MIN.
9.78
8.89
4.2
TYP.
MAX.
10.03
9.04
MIN.
0.385
0.350
0.165
TYP.
MAX.
0.395
0.356
0.180
A
B
D
4.57
d1
d2
E
2.54
0.56
0.100
0.022
7.37
8.38
0.290
0.330
0.004
e
1.27
5.08
0.38
0.050
0.200
0.015
e3
F
G
0.101
M
M1
1.27
1.14
0.050
0.045
P027A
13/14
M54/M74HC40102/40103
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
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14/14
相关型号：
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STMICROELECTR
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