M74HC651M1 [STMICROELECTRONICS]

HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, MICRO, PLASTIC, DIP-24;


型号：	M74HC651M1
厂家：	ST
描述：	HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, MICRO, PLASTIC, DIP-24 总线收发器
文件：	总12页 (文件大小：204K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M74HC651

M74HC652

HC651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)

HC652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)

HIGH SPEED

f_MAX= 73 MHz (TYP.) AT V_CC= 5V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_{CC (}MIN.)

OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

I_OH= I_OL= 6 mA (mIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

M1R

(Plastic Package)

(Micro Package)

ORDER CODES :

M74HCXXXM1R

M74HCXXXB1R

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS651/652

PIN CONNECTIONS (top view)

DESCRIPTION

M74HC651/652 are high speed CMOS OCTAL

BUS TRANSCEIVERS AND REGISTERS (3-

STATE), fabricated in silicon gate C²MOS technol-

ogy. They have the same high speed performance

of LSTTL combined with trueCMOS low power con-

sumption. These devices consist of bus transceiver

circuits, D-type flip-flops, and control circuitry ar-

ranged for multiplexed transmission of data directly

from the input bus or from the internal storage reg-

isters. Enable GABand GBA are provided to control

the transceiver functions.

Select AB and Select BA control pins are provided

to select whether real-time or stored data is trans-

fered. A low input level selects real-time data, and

a high selects stored data.

Data on the A or B bus, or both, can be stored in the

internal D flip-flops by low-to-high transitions at the

appropriate clock pins (CLOCK AB or CLOCK BA)

regardless oftheselect or enable control pins. When

select AB and select BA are in the real-time transfer

mode, it is also possible to store data without using

the internal D-type flip-flops by simultaneously en-

abling GAB and GBA. In this configuration each out-

put reinforces its input. Thus, when all other data

sources to the two sets of bus lines are at high im-

pedance, each set of bus lines will remain at its last

state. All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

GAB, GAB, CAB,

SAB, SBA, CBA

A, B

October 1993

1/12

M74HC651/652

LOGIC DIAGRAM (HC652)

Note : In case of M74HC652 output inverter marked * at A bus and B bus are eliminated.

TIMING CHART

2/12

M74HC651/652

TRUTH TABLE

HC652 (The truth table for HC651 is the same as this, but with the outputs inverted)

GAB GBA CAB CBA SAB SBA

FUNCTION

INPUTS

Both the A bus and the B bus are inputs

The output functions of the A and B bus are disabled

INPUTS

Both the A and B buz are used for inputs to the

internal flip-flops. Data at the bus will be stored on

low to high transition of the clock inputs

OUTPUTS INPUTS

The A bus are outputs and the B bus are inputs

The data at the B bus are displayed at the A bus

The data at the B bus ar displayed at the A bus.

The data of the B bus are stored to the internal

flip-flop on low to high transition of th clock pulse

The data stored to the internal flip-flop are dispayed

at the A bus

The data at the B bus are stored to the internal flip-

flop on low to high transition of the clock pulse. The

states of the internal flip-flops output directly to the

A bus

INPUTS OUTPUTS The A bus are inputs and the B bus are outputs

The data at the A bus are displayed at the B bus

The data at the A bus are displayed at the B bus.

The data of the A bus are stored to the internal flip-

flop on low to high transition of the clock pulse

The data stored to the internal flip-flops are

displayed at the B bus

the data at the A bus are stored to the internal flip-

flop on low to high transition of the clock pulse. The

states of the internal flip-flops output directly to the

B bus

OUTPUTS OUTPUTS Both the A bus and the B bus are outputs

The data stored to the internal flip-flops are

displayed at the A and B bus respectively

The output at the A bus are displayed at the B bus,

the output at the B bus are displayed at the A bus

respectively

: DON’T CARE

: HIGH IMPEDANCE

Qn : THE DATA STOREDTO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS

: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF

THE CLOCK INPUTS

3/12

M74HC651/652

PIN DESCRIPTION

PIN No

SYMBOL

CLOCK AB

SELECT AB

GAB

NAME AND FUNCTION

A to B Clock Input (LOW to HIGH, Edge-Trigged)

Select A to B Source Input

Direction Control Input

4, 5, 6, 7, 8, 9, 10, 11

A1 to A8

B1 to B8

GBA

A data Inputs/Outputs

20, 19, 18, 17, 16, 15, 14, 13

B Data Inputs/Outputs

Output Enable Input (Active LOW)

Select B to A Source Input

SELECT BA

CLOCK BA

GND

B to A Clock Input (LOW to HIGH, Edge-Triggered)

Ground (0V)

V_CC

Positive Supply Voltage

IEC LOGIC SYMBOLS

HC651

HC652

4/12

M74HC651/652

ABSOLUTE MAXIMUM RATINGS

Symbol

V_CC

V_I

Parameter

Value

Unit

Supply Voltage

-0.5 to +7

DC Input Voltage

-0.5 to V_CC+ 0.5

± 20

V_O

DC Output Voltage

I_IK

DC Input Diode Current

DC Output Diode Current

DC Output Source Sink Current Per Output Pin

^oC

I_OK

± 20

I_O

± 35

I_CCor I_GNDDC V_CCor Ground Current

± 70

P_D

T_stg

T_L

Power Dissipation

500 (*)

Storage Temperature

Lead Temperature (10 sec)

-65 to +150

300

^oC

Absolute MaximumRatingsare those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied.

(*) 500 mW: 65 ^oC derate to 300 mW by 10mW/^oC: 65 ^oC to 85 ^oC

RECOMMENDED OPERATING CONDITIONS

Symbol

V_CC

V_I

Parameter

Value

2 to 6

Unit

Supply Voltage

Input Voltage

0 to V_CC

-40 to +85

0 to 1000

0 to 500

0 to 400

V_O

Output Voltage

^oC

T_op

Operating Temperature:

t_r, t_f

Input Rise and Fall Time

V_CC= 2 V

V_CC= 4.5 V

V_CC= 6 V

5/12

M74HC651/652

DC SPECIFICATIONS

Test Conditions

V_CC

(V)

Value

T_A= 25 ^oC

Min. Typ. Max. Min. Max.

-40 to 85 ^oC

Symbol

Parameter

Unit

V_IH

High Level Input Voltage

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

2.0

4.5

6.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

V_IL

Low Level Input

Voltage

0.5

1.35

1.8

0.5

1.35

1.8

V_OH

High Level Output Voltage

1.9

4.4

5.9

2.0

4.5

6.0

1.9

4.4

V_I=

V_IH

I_O=-20 µA

5.9

V_IL

I_O=-6.0 mA 4.18 4.31

4.13

5.63

I_O=-7.8 mA 5.68

5.8

0.0

V_OL

Low Level Output Voltage

0.1

V_I=

V_IH

I_O= 20 µA

0.1

V_IL

I_O= 6.0 mA

I_O= 7.8 mA

0.17 0.26

0.18 0.26

±0.1

0.37

±1

I_I

Input Leakage Current

6.0 V_I= V_CCor GND

µA

I_OZ

3 State Output Off State Current

6.0

V_I= V_IHor V_IL

±0.5

±5.0

V_O= V_CCor GND

I_CC

Quiescent Supply Current

6.0 V_I= V_CCor GND

µA

AC ELECTRICAL CHARACTERISTICS (Input t_r= t_f= 6 ns)

Test Conditions

Value

T_A= 25 ^oC

-40 to 85 ^oC

Symbol

Parameter

Unit

V_CCC_L

(V) (pF)

Min. Typ. Max. Min. Max.

t_TLH

t_THL

Output Transition Time

2.0

4.5

6.0

2.0

t_PLH

t_PHL

Propagation Delay Time

(BUS - BUS)

116

150

190

4.5

6.0

2.0

150

4.5

190

240

6.0

2.0

t_PLH

t_PHL

Propagation Delay Time

(CLOCK - BUS)

210

265

4.5

6.0

2.0

250

315

150

4.5

6.0

6/12

M74HC651/652

AC ELECTRICAL CHARACTERISTICS (Continued)

Test Conditions

Value

T_A= 25 ^oC

-40 to 85 ^oC

Unit

Symbol

Parameter

V_CCC_L

(V) (pF)

Min. Typ. Max. Min. Max.

t_PLH

t_PHL

Propagation Delay Time

(SELECT - BUS)

2.0

170

215

4.5

6.0

2.0

210

265

150

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

t_PZL

t_PZH

3-State Output Enable Time

175

220

50 R_L= 1 KΩ

215

270

150 R_L= 1 KΩ

t_PLZ

t_PHZ

Output Disable Time

175

220

50 R_L= 1 KΩ

f_MAX

Maximum Clock Frequency

Minimum Clock Pulse Width

Minimum Set-up Time

Minimum Hold Time

4.8

MHz

t_W(H)

t_W(L)

t_s

t_h

C_IN

Input Capacitance

C_I/O

Bus Terminal Capacitance

C_PD(*) Power Dissipation Capacitance

for HC651

for HC652

(*) C_PDisdefined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.

(Refer to Test Circuit). Average operting current can be obtained by the followingequation. I_CC(opr) = C_PD• V_CC• f_IN+ I_CC/8 (per Channel)

7/12

M74HC651/652

SWITCHING CHARACTERISTICS TEST CIRCUIT AND WAVEFORM

WAVEFORM 1

WAVEFORM 2

WAVEFORM 3

WAVEFORM 5

WAVEFORM 4

GAB= ”L”

GBA = ”H”

8/12

M74HC651/652

TEST WAVEFORM I_CC(Opr.)

INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICSTEST.

9/12

M74HC651/652

Plastic DIP24 (0.25) MECHANICAL DATA

inch

TYP.

0.025

0.018

DIM.

MIN.

0.23

15.2

TYP.

0.63

0.45

MAX.

MIN.

0.009

0.598

MAX.

0.31

0.012

1.27

0.050

32.2

1.268

0.657

16.68

2.54

0.100

1.100

27.94

14.1

0.555

4.445

3.3

0.175

0.130

P043A

10/12

M74HC651/652

SO24 MECHANICAL DATA

inch

TYP.

DIM.

MIN.

TYP.

MAX.

2.65

0.20

2.45

0.49

0.32

MIN.

MAX.

0.104

0.007

0.096

0.019

0.012

0.10

0.004

0.35

0.23

0.013

0.009

0.50

0.020

45° (typ.)

15.20

10.00

15.60

10.65

0.598

0.393

0.614

0.420

1.27

0.05

0.55

13.97

7.40

0.50

7.60

1.27

0.291

0.19

0.299

0.050

8° (max.)

11/12

M74HC651/652

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronicsproductsare notauthorized foruse ascritical componentsin life support devices or systems without express

written approval of SGS-THOMSON Microelectonics.

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12/12

M74HC651M1 [STMICROELECTRONICS]

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